Display apparatus

Abstract

A display device according to an embodiment of the present specification may provide a display device comprising a display area, a non-display area surrounding the display area, a pixel disposed in the display area, and the non-display area including a driver IC, a gate driver, a low-potential power line, a high-potential power line, and a subframe control unit, wherein the subframe control unit is disposed between the pixel and the gate driver.

Description

Technology Field

[0001] The present specification relates to a gate driving circuit and a display device using the same, and more specifically, to a display device that prevents an unintended increase in output current by further configuring an additional transistor connected to the gate driving circuit. Background Technology

[0002] With the recent entry into the information age, the field of displays that visually represent electrical information signals has developed rapidly, and in response to this, various display apparatuses with excellent performance such as thinness, lightness, and low power consumption are being developed.

[0003] Specific examples of such display devices include Liquid Crystal Display Apparatus (LCD), Organic Light Emitting Display Apparatus (OLED), and Quantum Dot Display Apparatus.

[0004] A display device includes a pixel array on which an image is displayed and a panel driving circuit that drives the signal lines of the pixel array. The panel driving circuit includes a data driving circuit that supplies data signals to the data lines of the pixel array, a gate driving circuit (or scan driving circuit) that sequentially supplies gate pulses (or scan pulses) synchronized with the data signals to the gate lines (or scan lines) of the pixel array, a timing controller that controls the data driving circuit and the gate driving circuit, and the like.

[0005] Recently, technology in which gate driver circuits are embedded in display panels along with pixel arrays is being applied. The gate driver circuit embedded in the display panel is known as a "GIP (Gate In Panel) circuit." The GIP circuit includes a shift register formed in the bezel area of ​​the display panel. The shift register includes a plurality of dependently connected GIP elements. The GIP elements generate a gate output in response to a start pulse or a carry signal and shift that gate output according to the shift clock. Therefore, the shift register is supplied with a start pulse, shift clock, driving voltage, etc.

[0006] Recently, with further technological advancements, low-temperature polypropylene (LTPS) transistors and oxide transistors have been utilized as light-emitting driving transistors and switching transistors, respectively, to improve efficiency through low-frequency driving. While arranging these heterogeneous transistors together offers the advantage of significantly reducing power consumption during driving, leakage current occurs in the transistors in high-temperature environments, causing the output voltage from the gate driving unit to the pixel to rise.

[0007] Such an abnormal increase in output voltage can cause screen abnormalities when oxide transistors are driven at low speeds.

[0008] In order to solve the aforementioned problems, various methods have recently been sought to reduce the non-display area of ​​irregular display panels with built-in gate drivers. The problem to be solved

[0009] The present specification aims to prevent an abnormal increase in output voltage in a transistor due to stress under high temperature conditions in a display device with an integrated gate driver.

[0010] The problems described in this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0011] A display device according to an embodiment of the present specification includes a display area, a non-display area surrounding the display area, a pixel disposed in the display area, and the non-display area includes a driver IC, a gate driver, a low-potential power line, a high-potential power line, and a subframe control unit, and the subframe control unit may be disposed between the pixel and the gate driver.

[0012] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0013] The display device according to the embodiment of the present specification can provide a display device in which pixels in the display area operate normally by configuring a separate control unit at the output terminal of the gate driving unit to offset the increase in gate output caused by low-speed driving.

[0014] A display device according to an embodiment of the present specification can offset the output rise by turning on a subframe control unit when an output rise phenomenon occurs in a gate driver unit in which an oxide semiconductor is disposed for 1Hz low-speed driving, and outputting the gate low signal of the gate driver unit to the gate output terminal.

[0015] The effects of this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0016] Since the content of the invention described above regarding the problem to be solved, the means for solving the problem, and the effect does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the invention. Brief explanation of the drawing

[0017] FIG. 1 is a drawing showing the front of a display panel according to an embodiment of the present specification. Figure 2 is a cross-sectional view of the marked area cut along the cutting line I-I' of Figure 1. Figure 3a is a circuit diagram showing the circuit configuration of the gate driver. Figure 3b is a voltage-current graph showing the change in output of the transistor according to temperature. Figure 3c is a conceptual diagram showing the frame configuration according to the driving speed of the gate driver and the change in output of the gate driver at that time. FIG. 4a is a diagram showing the configuration of the display area and the non-display area in the embodiment viewed from the display panel of FIG. 1. FIG. 4b is a conceptual diagram showing the low-speed frame configuration of the gate driver in the embodiment of FIG. 4a and the change in output of the gate driver at that time. Specific details for implementing the invention

[0018] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0019] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0020] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0021] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0022] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0023] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0024] In describing the components of this specification, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by the terms. Where it is stated that a component is "connected," "combined," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that other components may be "interposed" between each component, or that each component may be "connected," "combined," or "joined" through other components.

[0025] In this specification, the term "display device" may include display devices in the narrow sense, such as a Liquid Crystal Module (LCM), an Organic Light-Emitting Module (OLED Module), and a Quantum Dot Module, which include a display panel and a driver for driving the display panel. Additionally, it may include set electronic devices or set devices or set apparatuses, such as equipment displays including complete products or final products such as notebook computers, televisions, computer monitors, automotive displays, or other forms of vehicles, as well as mobile electronic devices such as smartphones or electronic pads, which include LCMs, OLED modules, QD modules, etc.

[0026] Accordingly, the display device in this specification may include the display device itself in the narrow sense, such as an LCM, an OLED module, a QD module, etc., and even a set device that is an application product or end-consumer device including an LCM, an OLED module, a QD module, etc.

[0027] In addition, depending on the case, an LCM, OLED module, or QD module composed of a display panel and a driving unit may be referred to as a "display device" in the narrow sense, and an electronic device as a finished product including the LCM, OLED module, or QD module may be distinguished and referred to as a "set device." For example, a display device in the narrow sense includes a liquid crystal (LCD), organic light-emitting diode (OLED), or quantum dot display panel and a source PCB, which is a control unit for driving the display panel, and a set device may be a concept that further includes a set PCB, which is a set control unit electrically connected to the source PCB to control the entire set device.

[0028] The display panel used in this embodiment may be any type of display panel, such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a quantum dot (QD) display panel, and an electroluminescent display panel, and is not limited to a specific display panel capable of bezel bending using the flexible substrate for the organic light-emitting diode (OLED) display panel and the lower backplate support structure of this embodiment. Furthermore, the display panel used in the display device according to the embodiment of this specification is not limited to the shape or size of the display panel.

[0029] More specifically, when the display panel is an organic light-emitting diode (OLED) display panel, it may include a plurality of gate lines and data lines, and pixels (Pixel, PXL) formed in the intersection area of ​​the gate lines and data lines. It may also be configured to include an array comprising thin-film transistors, which are devices for selectively applying voltage to each pixel, an organic light-emitting diode (OLED) layer on the array, and an encapsulation substrate or encapsulation layer disposed on the array to cover the organic light-emitting diode layer. The encapsulation layer can protect the thin-film transistors and the organic light-emitting diode layer from external shocks and prevent moisture or oxygen from penetrating into the organic light-emitting diode layer. Furthermore, the layer formed on the array may include an inorganic light-emitting layer, for example, a nano-sized material layer or a quantum dot.

[0030] FIG. 1 illustrates an exemplary organic electroluminescent (OLED) display panel that may be integrated into display devices.

[0031] FIG. 1 is a plan view showing an exemplary display device that may be included in an electronic device.

[0032] Referring to FIG. 1, the display device (100) includes at least one active area, and an array of pixels is formed in the active area. One or more inactive areas may be arranged around the active area. That is, the inactive areas may be adjacent to one or more sides of the active area. In FIG. 1, the inactive areas surround a rectangular active area. However, the shape of the active area and the shape / arrangement of the inactive area adjacent to the active area are not limited to the example shown in FIG. 1. The active area and the inactive area may be shapes suitable for the design of an electronic device equipped with the display device (100). Exemplary shapes of the active area include a pentagon, a hexagon, a circle, an ellipse, etc.

[0033] Each pixel within the display area may be associated with a pixel circuit. The pixel circuit may include one or more switching transistors and one or more driving transistors on the substrate (101). Each pixel circuit may be electrically connected to a gate line and a data line to communicate with one or more driving circuits, such as a gate driver and a data driver, located in a non-display area. The pixel may include an organic light-emitting diode.

[0034] As illustrated in FIG. 1, the driving circuit may be implemented as a thin film transistor (TFT) in the non-display area. This driving circuit may be referred to as a gate-in panel (GIP). Additionally, some components, such as a data driver IC, may be mounted on a separate printed circuit board and combined with a connection interface (pad / bump, pin, etc.) placed in the non-display area using a circuit film such as a flexible printed circuit board (FPCB), chip-film (COF), or tape-carrier-package (TCP). The non-display area may be bent together with the connection interface so that the printed circuit (COF, PCB, etc.) can be located on the back of the display device (100).

[0035] The display device (100) may further include a power controller that supplies various voltages or currents to or controls the supply of pixel circuits, data drivers, gate drivers (GIPs), etc. Such a power controller is also called a Power Management Integrated Circuit (PMIC). Additionally, the display device (100) may also be provided with a voltage line that supplies a high-level voltage (VDD), a reference power voltage line (VSS, 210), and a reference voltage (VRFE) related to driving the pixel circuit, as illustrated in the example.

[0036] As the display device (100) is miniaturized, an oxide semiconductor advantageous for low-speed driving, which is efficient in power consumption, can be applied to the gate driving unit (GIP). The oxide semiconductor is not limited to the gate driving unit (GIP) and can also be used as a transistor for driving pixels in the display area. Low-speed driving and high-speed driving can be defined as a refresh rate of less than 60Hz, specifically 1Hz to 5Hz. High-speed driving can be defined as a refresh rate of 60Hz or higher, such as 120Hz to 240Hz.

[0037] Meanwhile, the display device (100) may further include various additional elements for generating various signals or driving organic light-emitting diodes within the display area. Additional elements for driving organic light-emitting diodes may include an inverter circuit, a multiplexer, an electrostatic discharge circuit, etc. The display device (100) may also include additional elements related to functions other than driving organic light-emitting diodes. For example, the display device (100) may include additional elements that provide touch detection functions, user authentication functions (e.g., fingerprint recognition), multi-level pressure detection functions, tactile feedback functions, etc.

[0038] The aforementioned additional elements may be located in the non-display area and / or in an external circuit connected to the connection interface.

[0039] The reference power voltage line (VSS) may be positioned to surround the display area (A / A) in the outer non-display area (I / A) of the display device (100). The reason for this positioning is to ensure that the reference power is supplied to the cathode electrodes of all organic light-emitting diodes placed in the display area (A / A) at the shortest possible distance, thereby minimizing electrical resistance and making it easier to supply power.

[0040] FIG. 2 is a cross-sectional view showing the cutting line I-I' in the display area (A / A) of the display device. In the display device (100), thin-film transistors (102, 104, 106, 108), organic light-emitting diodes (112, 114, 116), and various functional layers are located on a substrate (101).

[0041] The substrate (101) may be a glass or plastic substrate. In the case of a plastic substrate, a polyimide-based or polycarbonate-based material may be used to provide flexibility. In particular, polyimide is widely used as a plastic substrate because it can be applied to high-temperature processes and is a material that can be coated.

[0042] The buffer layer (130) is a functional layer for protecting electrodes / wires from impurities, such as alkali ions, leaking from the substrate (101) or the underlying layers. The buffer layer may be composed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. The buffer layer (130) may include a multi-buffer (131) and / or an active buffer (132). The multi-buffer (131) may be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx), and may delay the diffusion of moisture and / or oxygen that has penetrated into the substrate (101). The active buffer (132) protects the semiconductor layer (102) of the transistor and performs the function of blocking various types of defects introduced from the substrate (101). The active buffer (132) may be formed of amorphous silicon (a-Si), etc.

[0043] The thin-film transistor may be in a form in which a semiconductor layer (102), a gate insulating film (103), a gate electrode (104), an interlayer insulating film (105), and source and drain electrodes (106, 108) are sequentially arranged. The semiconductor layer (102) is located on the buffer layer (130). The semiconductor layer (102) may be made of polysilicon (p-Si), in which case a certain region may be doped with impurities. Additionally, the semiconductor layer (102) may be made of amorphous silicon (a-Si) or various organic semiconductor materials such as pentacene. Furthermore, the semiconductor layer (102) may be made of oxide. The gate insulating film (103) may be formed of an insulating inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), and may also be formed of an insulating organic material. The gate electrode (104) can be formed from various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof.

[0044] The interlayer insulating film (105) may be formed from an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), and may also be formed from an insulating organic material. A contact hole in which the source and drain regions are exposed may be formed by the selective removal of the interlayer insulating film (105) and the gate insulating film (103).

[0045] Source and drain electrodes (106, 108) are formed in a single layer or multilayer shape using an electrode material on an interlayer insulating film (105). If necessary, a passivation layer composed of an inorganic insulating material may cover the source and drain electrodes (106, 108).

[0046] A first flattening layer (107-1) may be positioned on a thin film transistor. The first flattening layer (107-1) protects the thin film transistor and flattens the upper surface thereof. The first flattening layer (107-1) may be configured in various forms and may be formed from one or more of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, and a polyphenylene sulfide resin, but is not limited thereto.

[0047] Various metal layers serving as wires / electrodes may be disposed on the upper portion of the first flattening layer (107-1).

[0048] The second flattening layer (107-2) is located on top of the first flattening layer (107-1). The reason there are two flattening layers is that as the display device (100) evolves to high resolution, the number of various signal wires increases. Consequently, it is difficult to place all wires on a single layer while securing the minimum spacing, so an additional layer is created. Due to this additional layer (second flattening layer), there is room for wire placement, making it easier to design the wire / electrode placement. Additionally, if a dielectric material is used for the flattening layers (107-1, 107-2), the flattening layers (107-1, 107-2) can also be utilized to form capacitance between metal layers.

[0049] The organic light-emitting device may be in the form in which an anode electrode (112), an organic light-emitting layer (114), and a cathode electrode (116) are sequentially arranged. That is, the organic light-emitting device may be composed of an anode electrode (112) formed on a planarization layer (107), an organic light-emitting layer (114) located on the anode electrode (112), and a cathode electrode (116) located on the organic light-emitting layer (114).

[0050] The anode electrode (112) can be electrically connected to the drain electrode (108D) of the driving thin-film transistor through the connecting electrode (108-2). If the organic light-emitting display device (100) is a top emission type, the anode electrode (112) can be made of an opaque conductive material with high reflectivity. For example, the anode electrode (112) can be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof. The connecting electrode (108-2) can be made of the same material as the source and drain electrodes (106, 108).

[0051] The bank (110) is formed in the remaining area excluding the light-emitting region. Accordingly, the bank (110) has a bank hole that exposes an anode electrode (112) corresponding to the light-emitting region. The bank (110) may be made of an inorganic insulating material such as silicon nitride film (SiNx) or silicon oxide film (SiOx), or an organic insulating material such as BCB, acrylic resin, or imide resin.

[0052] An organic light-emitting layer (114) is positioned on an anode electrode (112) exposed by a bank (110). The organic light-emitting layer (114) may include a light-emitting layer, an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, etc.

[0053] A cathode electrode (116) is positioned on an organic light-emitting layer (114). When the display device (100) is of the top emission type, the cathode electrode (116) is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), thereby emitting light generated in the organic light-emitting layer (114) to the top of the cathode electrode (116).

[0054] An encapsulation layer (120) is positioned on the cathode electrode (116). The encapsulation layer (120) prevents the penetration of oxygen and moisture from the outside to prevent oxidation of the light-emitting material and the electrode material. When an organic light-emitting device is exposed to moisture or oxygen, pixel shrinkage, in which the light-emitting area is reduced, may occur, or dark spots may appear within the light-emitting area. The encapsulation layer may be composed of an inorganic film made of glass, metal, aluminum oxide (AlOx), or silicon (Si)-based materials, or it may have a structure in which organic and inorganic films are alternately stacked. The inorganic film serves to block the penetration of moisture or oxygen, and the organic film serves to flatten the surface of the inorganic film. The reason for forming the encapsulation layer as multiple thin film layers is to make the movement path of moisture or oxygen longer and more complex compared to a single layer, thereby making it difficult for moisture / oxygen to penetrate to the organic light-emitting device.

[0055] Specifically, the encapsulation layer (120) may include a first inorganic insulating film (121), an organic insulating film (122), and a second inorganic insulating film (123), and the first inorganic insulating film (121), the organic insulating film (122), and the second inorganic insulating film (123) may be arranged sequentially.

[0056] A barrier film (140) is positioned on the encapsulation layer (120) to encapsulate the entire substrate (101) containing an organic light-emitting element. The barrier film (140) may be a phase difference film or an optically isotropic film. If the barrier film has optically isotropic properties, it transmits incident light incident on the barrier film without phase delay. Additionally, an organic film or an inorganic film may be further positioned on the upper or lower surface of the barrier film. The organic film or inorganic film formed on the upper or lower surface of the barrier film serves to block the penetration of external moisture or oxygen.

[0057] An adhesive layer (145) may be positioned between the barrier film (140) and the encapsulation layer (120). The adhesive layer (145) bonds the encapsulation layer (120) and the barrier film (140). The adhesive layer (145) may be a heat-curing or natural-curing adhesive. For example, the adhesive layer (145) may be composed of a material such as B-PSA (Barrier pressure sensitive adhesive). A touch panel (film), a polarizing film, an upper surface cover, etc., may also be positioned on the barrier film (140).

[0058] Figure 3a illustrates the configuration of a gate driving unit applied to a display device.

[0059] Referring to FIG. 3a, the gate driver (GIP) outputs an output signal (SN(n)) of the gate high voltage (VGH) while node Q2 is deactivated to the gate high voltage (VGH) and node QB is activated to the gate low voltage (VGL). Subsequently, the gate driver (GIP) outputs an output signal (SN(n)) of the gate low voltage (VGL) while node Q2 is activated to the gate low voltage (VGL) and node QB is deactivated to the gate high voltage (VGH). In other words, the gate driver (GIP) outputs an output signal (SN(n)) of the gate low voltage (VGL) from the time node Q is bootstrapped, synchronized with the timing when node Q2 is activated.

[0060] To this end, the gate driving unit (G1P) may include a Q2 control unit, a QB control unit, an output unit, and a first stabilization unit.

[0061] The Q2 control unit can be implemented with transistor T3. Transistor T3 activates node Q2 by applying a start signal (VST) of gate low voltage (VGL) to node Q2 according to a clock signal (CLK). The gate electrode of transistor T3 is connected to the input terminal of the clock signal (CLK), and the first electrode and the second electrode of transistor T3 are connected to the input terminal of the start signal (VST) and node Q2, respectively.

[0062] The QB control unit activates node QB opposite to node Q2 based on the clock signal (CLK), start signal (VST), and the potential of node Q2. The QB control unit can be implemented with capacitor C_ON, transistor T5, transistor T4, transistor T6, and capacitor CB.

[0063] Capacitor C_ON is connected between the input terminal of the clock signal (CLK) and node Q1. Transistor T5 supplies the clock signal (CLK) to node QB according to the potential of node Q1. The gate electrode of transistor T5 is connected to node Q1, and the first and second electrodes of transistor T5 are connected to the input terminal of the clock signal (CLK) and node QB, respectively. Transistor T4 supplies the gate high voltage (VGH) to node Q1 according to the start signal (VST). The gate electrode of transistor T4 is connected to the input terminal of the start signal (VST), and the first and second electrodes of transistor T4 are connected to node Q1 and the input terminal of the gate high voltage (VGH), respectively. With this configuration, the potential of node Q1 changes in synchronization with the clock signal (CLK) while the start signal (VST) is maintained at the gate high voltage (VGH). In addition, the potential of node Q1 becomes the gate high voltage (VGH) while the start signal (VST) is maintained at the gate low voltage (VGL).

[0064] Transistor T6 supplies a gate high voltage (VGH) to node QB according to the potential of node Q2. The gate electrode of transistor T6 is connected to node Q2, and the first and second electrodes of transistor T6 are connected to the input terminals of node QB and the gate high voltage (VGH), respectively. Capacitor CB is connected between node QB and the gate high voltage (VGH) to stabilize the potential of node QB.

[0065] The output section includes a pull-down transistor T1, a pull-up transistor T2, and a capacitor CQ.

[0066] Transistor T1 supplies an output signal (SN(n)) at gate low voltage (VGL) to the output node from the time node Q is bootstrapped, synchronized with the timing when node Q2 is activated. The gate electrode of transistor T1 is connected to node Q, and the first and second electrodes of transistor T1 are connected to the input terminal of gate low voltage (VGL) and the output node, respectively. Capacitor CQ is connected between node Q and the output node. Capacitor CQ serves to bootstrap node Q by reflecting the potential change of the output node to the potential of node Q when the output signal (SN(n)) changes from gate high voltage (VGH) to gate low voltage (VGL). Transistor T2 supplies an output signal (SN(n)) at gate high voltage (VGH) to the output node while node QB is activated prior to node Q2. The gate electrode of transistor T2 is connected to node QB, and the first and second electrodes of transistor T2 are connected to the output node and the input terminal of the gate high voltage (VGH), respectively.

[0067] The first stabilization unit can be implemented as a transistor TA. The gate electrode of the transistor TA is connected to the input terminal of the gate low voltage (VGL), and the first and second electrodes of the transistor TA are connected to node Q2 and node Q, respectively. The channel current between the first and second electrodes of the transistor TA becomes zero when node Q is bootstrapped. In other words, the transistor TA is turned off when node Q is bootstrapped, thereby severing the electrical connection between node Q2 and node Q. Meanwhile, the transistor TA remains turned on while node Q is not bootstrapped.

[0068] Transistor TA remains turned on and turns off only when node Q is bootstrapped, thereby blocking the current flow between node Q2 and node Q. Therefore, when node Q is bootstrapped, the potential of node Q2 differs from the potential of node Q. Since the potential of node Q2 does not change even if the potential of node Q changes at the moment of bootstrapping, transistors T3 and T6 connected to node Q2 are not overloaded at that moment. If transistor TA were absent, the drain-source voltage (Vds) of transistor T3 and the gate-source voltage (Vgs) of transistor T6 could increase above a threshold due to bootstrapping; if this overload persists, device failure, known as breakdown, may occur. Transistor TA prevents transistors T3 and T6 connected to node Q2 from breaking down at the moment of node Q's bootstrapping.

[0069] In the case of transistor T2 in Fig. 3a, the drain-source voltage (VGH-VGL) is large when the potential of the output node maintains the gate low voltage (VGL), and if this condition persists for a long time, it is prone to degradation. If leakage current flows through transistor T2 due to degradation, a normal output signal (SN(n)) cannot be output.

[0070] FIG. 3b is a graph illustrating the change in output of a transistor at room temperature and high temperature related to FIG. 3a. Referring to FIG. 3b, the voltage and output current according to the temperature of the transistor can be observed. The x-axis of the graph represents the gate-source voltage (Vgs). At approximately -2V or lower, there is no difference in output current values ​​between room temperature and high temperature, but as it reverses to positive at approximately -1V, a difference in output current values ​​may occur. Referring to FIG. 3b, it can be seen that when the gate-source voltage (Vgs) is 0V, a difference in output current values ​​occurs between the transistor at room temperature and the transistor at high temperature, and the output current at high temperature is greater. When the display device (100) is at a high temperature, the leakage current of the gate driver may increase.

[0071] Figure 3c shows the frame diagram during high-speed driving and low-speed driving, and the output of the gate driving unit during low-speed driving.

[0072] The display device (100) can be applied by combining high-speed and low-speed driving, and can enjoy the effect of reducing power consumption through low-speed driving. On the other hand, referring to FIG. 3c, when driving at high speed of 120Hz, the main frame can be refreshed in about 8.3ms to operate normally. At this time, the output voltage of the gate driver (GIP) can be about -9v. On the other hand, when driving at low speed of 1Hz, since it must be refreshed once every second, the sub-frame section after about 8.3ms, when the main frame is output, must hold the output value of the main frame, and as the holding time increases, a phenomenon may occur in which the output value of the gate driver (GIP) rises. The gate driver (GIP) can be output at a voltage of about -7v or higher during the sub-frame section.

[0073] By combining Figures 3a to 3c, the potential of the Q2 node rises due to leakage current through the path from transistor T3 to transistor T1 and the Q node in the configuration diagram of the gate driver of Figure 3a, and when the output of transistor T1 decreases, a phenomenon in which leakage current is output through transistor T2 can easily occur at high temperatures.

[0074] FIG. 4a is a drawing illustrating the display device of FIG. 1 with features related to an embodiment of the present invention. Referring to FIG. 4a, a driver IC (200) may be disposed on the upper side of a substrate (101), and a pad for a low potential power supply (VSS) and a pad for a high potential power supply (VDD) may be disposed on the left and right sides of the driver IC. Pads for signals controlling a gate driver (GIP) may be disposed in the area of ​​the driver IC (200). Specifically, pads for a clock signal (CLK), a start signal (VST), a gate high voltage (VGH), and a gate low voltage (VGL) may be disposed. Wires extending from the pads for the clock signal (CLK), the start signal (VST), the gate high voltage (VGH), and the gate low voltage (VGL) are connected to the gate driver (GIP) so that light emission signals and scan signals required for the pixel circuit of the display area (A / A) can be generated at the gate driver (GIP).

[0075] Referring to FIG. 4a, for an embodiment of the present specification, a subframe control pad (SFC) for a subframe control unit (300) may be further disposed in the area of ​​the driver IC (200). The subframe control unit (300) may be disposed between the gate driver (GIP) and the pixel (PXL) of the display area (A / A). The gate electrode of the subframe control unit (300) may be connected to the subframe control pad (SFC), and the source electrode may be connected to the gate low signal (VGL). The drain electrode of the subframe control unit (300) may be connected to the wiring output from the gate driver (GIP) toward the pixel (PXL) of the display area (A / A). A signal may be added from the drive IC (200) for the subframe control unit (300) to output a signal to the subframe control pad (SFC) at the time when the main frame ends and the subframe begins, thereby turning on the subframe control unit (300). When the subframe control unit (300) is turned on, the voltage of the gate low voltage (VGL) can be applied as the output signal of the gate driver (GIP). In the case of the gate low voltage (VGL), a voltage of approximately -9V is always applied. When the gate low voltage (VGL) is applied to the output signal of the gate driver (GIP) through the turned-on subframe control unit (300), the increase in the subframe section output of the gate driver (GIP) can be offset.

[0076] FIG. 4b is a graph showing the output value of the gate driver (GIP) in the embodiment of FIG. 4a.

[0077] Referring to FIG. 4b, the subframe control unit (300) can be turned on at the start of the subframe section where the output of the gate driver (GIP) must be held after the mainframe section of 8.3ms in low-speed driving of 1Hz. When the subframe control unit (300) is turned on from the turn-off state, -9v of the gate low voltage (VGL) is applied to the output terminal of the gate driver (GIP), which can offset the rise in the output of the gate driver (GIP) in FIG. 3c. This prevents screen abnormalities caused by abnormal output of the gate driver (GIP).

[0078] A display device according to an embodiment of the present specification includes a Liquid Crystal Display device (LCD), a Field Emission Display device (FED), an Organic Light Emitting Display Device (OLED), and a Quantum Dot Display Device.

[0079] The display device according to the embodiments of the present specification may also include a set electronic device apparatus or a set device or set apparatus, such as a laptop computer, television, computer monitor, automotive display apparatus or other forms of vehicle that are complete products or final products including an LCM, an OLED module, etc., an equipment display apparatus including an automotive display apparatus or other forms of a vehicle, a mobile electronic device apparatus such as a smartphone or an electronic pad.

[0080] A display device according to an embodiment of the present specification may be described as follows.

[0081] A display device according to an embodiment of the present specification includes a display area and a non-display area surrounding the display area, a pixel disposed in the display area and a driver IC disposed in the non-display area, a gate driver, a low-potential power line, a high-potential power line, and a subframe control unit, wherein the subframe control unit may be disposed between the pixel and the gate driver unit.

[0082] In the display device according to the embodiment of the present specification, the driver IC may include a subframe control pad connected to the gate electrode of the subframe control unit.

[0083] A display device according to an embodiment of the present specification includes a gate low voltage pad and a gate high voltage pad connected to a gate driving unit, and the gate low voltage pad can be connected to a source electrode of a subframe control unit.

[0084] In the display device according to the embodiment of the present specification, the gate low voltage may be -9V.

[0085] A display device according to an embodiment of the present specification may include an oxide transistor in the gate driving portion.

[0086] In the display device according to the embodiment of the present specification, the drain electrode of the subframe control unit and the output terminal of the gate driving unit are electrically connected, and the output terminal of the gate driving unit may be connected to a pixel.

[0087] In the display device according to the embodiment of the present specification, the gate driving unit can be driven at a low speed of 1 Hz.

[0088] In the display device according to the embodiment of the present specification, the subframe control unit may be in a turn-off state during the mainframe period of the pixel and in a turn-on state during the subframe period of the pixel.

[0089] In the display device according to the embodiment of the present specification, when the subframe control unit is in a turned-on state, the drain of the subframe control unit can output an output voltage of approximately -9V.

[0090] A display device according to an embodiment of the present specification includes a display area, a non-display area surrounding the display area, a pixel disposed in the display area, and a driver IC disposed in the non-display area, a gate driver, a low-potential power line, a high-potential power line, and a subframe control unit, and the gate driver can perform low-speed driving.

[0091] In the display device according to the embodiment of the present specification, the gate driving part may include an oxide semiconductor.

[0092] In the display device according to the embodiment of the present specification, the subframe control unit may be disposed between the pixel and the gate driving unit.

[0093] In the display device according to the embodiment of the present specification, the driver IC may include a subframe control pad connected to the gate electrode of the subframe control unit.

[0094] The features, structures, effects, etc. described in the examples of the present application described above are included in at least one example of the present application and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of the present application may be combined or modified and implemented in other examples by a person skilled in the art to which the present application pertains. Accordingly, details regarding such combinations and modifications should be interpreted as being included within the scope of the present application.

[0095] It will be obvious to those skilled in the art that the present application described above is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical aspects of the present application. Therefore, the scope of the present application is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present application. Explanation of the symbols

[0096] 101 : Substrate 102: Semiconductor layer 103 : Gate insulating film 104: Gate electrode 105 : Interlayer insulation film 106: Source electrode 107-1 : First leveling layer 107-2 : Second leveling layer 108: Drain electrode 108-1 : Power Wiring 108-2: First metal layer 110 : Bank 112: Anode electrode 114: Organic light-emitting layer 116: Cathode electrode 120 : Bag layer 121 : First inorganic insulating film 122 : Organic insulating film 123 : Second inorganic insulating film 130 : Buffer layer 131 : Multibuffer 132 : Active buffer 140 : Barrier film 145 : Adhesive layer 200: Driver IC 300 : Subframe control unit VDD : Classic Warfare Power Wiring VSS: Low potential power wiring GIP: Gate driver A / A : Display area

Claims

Claim 1 A display device comprising: a substrate including a display area and a non-display area surrounding the display area; a driver IC disposed on the substrate; a gate driver disposed on the substrate; a low-potential power pad disposed on the left and right sides of the driver IC; a high-potential power pad disposed on the left and right sides of the driver IC; a low-potential power wiring disposed on the substrate and surrounding at least three sides of the display area; and a high-potential power wiring disposed on the substrate, at least a portion of which is arranged parallel to the low-potential power wiring. Claim 2 A display device according to claim 1, wherein the gate driving unit comprises: a transistor T1 electrically connected between an input terminal of a gate low voltage and an output node, comprising a gate electrode electrically connected to node Q; a transistor T2 electrically connected between an input terminal of a gate high voltage and the output node, comprising a gate electrode electrically connected to node QB; a transistor T3 electrically connected between an input terminal of a start signal and node Q, comprising a gate electrode electrically connected to an input terminal of a clock signal; and a transistor TA electrically connected between the transistor T3 and the transistor T1. Claim 3 In paragraph 2, the gate driving unit further comprises: a capacitor CQ electrically connected between the node Q and the output node; a capacitor CB electrically connected between the input terminal of the gate high voltage and the gate electrode of the transistor T2; a transistor T4 electrically connected to the input terminal of the gate high voltage; a transistor T5 electrically connected between the input terminal of the clock signal and the transistor T2; and a transistor T6 electrically connected between the input terminal of the gate high voltage and the transistor T2. Claim 4 A display device according to paragraph 3, further comprising a capacitor C_ON electrically connected between the input terminal of the clock signal and the transistor T4. Claim 5 A display device according to claim 1, further comprising a reference power voltage line disposed on the substrate and disposed parallel to the high potential power wiring. Claim 6 A display device according to claim 1, further comprising a clock signal line disposed on the outer side of the gate driving unit. Claim 7 A display device according to claim 1, further comprising a start signal line disposed on the outer side of the gate driving unit. Claim 8 A display device according to claim 1, further comprising a clock signal pad disposed on the left and right sides of the area of ​​the driver IC, a start signal pad disposed on the left and right sides of the area of ​​the driver IC, a gate high voltage pad disposed on the left and right sides of the area of ​​the driver IC, and a gate low voltage pad disposed on the left and right sides of the area of ​​the driver IC. Claim 9 A display device according to claim 1, wherein the low-potential power wiring is positioned to the left and right of the driver IC, and the high-potential power wiring is positioned to the left, right, and bottom of the driver IC. Claim 10 A display device according to paragraph 2, wherein the clock signal is applied to the gate electrode of the transistor T2 and the start signal is applied to the gate electrode of the transistor T1. Claim 11 In paragraph 3, the transistor T4 is a display device connected between the input terminal of the gate high voltage and the input terminal of the clock signal. Claim 12 In claim 3, the gate driver comprises: a Q2 control unit including the transistor T3 that activates node Q2 in response to the clock signal; a QB control unit including the transistor T5, the transistor T4, the transistor T6, and the capacitor CB that activates node QB in response to the clock signal in opposition to node Q2; an output unit including the transistor T1 which is a pull-down element, the transistor T2 which is a pull-up element, and the capacitor CQ; and a stabilization unit including the transistor TA which blocks the electrical connection between node Q2 and node Q when node Q is bootstrapped. Claim 13 A display device according to paragraph 3, wherein the first electrode of the transistor T3 is connected to the input terminal of the start signal, the second electrode of the transistor T3 is connected to the first electrode of the transistor TA, and the second electrode of the transistor TA is connected to the gate electrode of the transistor T1. Claim 14 A display device according to claim 1, wherein the high-potential power line is positioned closer to the driver IC than the low-potential power line on the left and right sides of the driver IC, respectively. Claim 15 A display device according to claim 1, wherein the gate driving unit comprises an oxide transistor. Claim 16 A display device according to claim 1, further comprising a pixel circuit including an oxide transistor on the substrate. Claim 17 In claim 1, the gate driving unit is driven at a refresh rate of less than 60Hz, a display device. Claim 18 In claim 6, the display device wherein the clock signal line is positioned closer to the display area than the low-potential power line, respectively, on the left and right sides of the driver IC. Claim 19 In claim 7, the display device wherein the start signal line is positioned closer to the display area than the low potential power line, respectively, on the left and right sides of the driver IC. Claim 20 A display device according to claim 1, further comprising: a gate high voltage wiring disposed inwardly from the gate driving unit; and a gate low voltage wiring disposed inwardly from the gate driving unit, wherein the gate high voltage wiring and the gate low voltage wiring are disposed closer to a display area than the low potential power wiring, respectively, on the left and right sides of the driver IC.

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