Semiconductor device and method of fabricating thereof

Abstract

The present invention provides a semiconductor device capable of improving performance and reliability. The semiconductor device comprises an active pattern extending in a first direction; a gate structure extending in a second direction different from the first direction on the active pattern and including a gate insulating film and a gate filling film; a gate spacer extending in a second direction on a sidewall of the gate structure; a gate shield insulating pattern disposed on a sidewall of the gate spacer, covering an upper surface of the gate insulating film and including an insulating material; and a gate capping pattern on the gate structure covering an upper surface of the gate filling film.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor device capable of improving performance and reliability.

[0005] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device that can improve performance and reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] One aspect of a semiconductor device of the present invention for solving the above problem comprises an active pattern extending in a first direction; a gate structure extending in a second direction different from the first direction on the active pattern and including a gate insulating film and a gate filling film; a gate spacer extending in a second direction on a sidewall of the gate structure; a gate shield insulating pattern disposed on a sidewall of the gate spacer, covering the upper surface of the gate insulating film and including an insulating material; and a gate capping pattern on the gate structure covering the upper surface of the gate filling film.

[0008] Another aspect of the semiconductor device of the present invention for solving the above problem comprises: a first gate structure extending in a first direction in a first region of a substrate and including a first gate insulating film and a first gate filling film; a second gate structure extending in a second direction in a second region of a substrate and including a second gate insulating film and a second gate filling film; a first gate spacer extending in a first direction on a sidewall of the first gate structure; a second gate spacer extending in a second direction on a sidewall of the second gate structure; a gate shield insulating pattern disposed on a sidewall of the first gate spacer, covering the upper surface of the first gate insulating film and including an insulating material; a first gate capping pattern covering the upper surface of the first gate filling film on the first gate structure; and a second gate capping pattern covering the upper surface of the second gate structure on the second gate structure, wherein the width in a third direction perpendicular to the first direction of the first gate structure is smaller than the width in a fourth direction perpendicular to the second direction of the second gate structure.

[0009] Another aspect of the semiconductor device of the present invention for solving the above problem comprises: an active pattern including a fin-shaped pattern in a first direction and a sheet pattern on the fin-shaped pattern; a gate structure extending in a second direction different from the first direction on the active pattern and including a gate insulating film and a gate filling film; a gate spacer extending in a second direction on a sidewall of the gate structure; a gate shield insulating pattern disposed on a part of the sidewall of the gate spacer, covering the upper surface of the gate insulating film and including an insulating material; and a gate capping pattern on the gate structure covering the upper surface of the gate filling film and not in contact with the upper surface of the gate insulating film, wherein, with respect to the upper surface of the sheet pattern, the upper surface of the gate insulating film is lower than the upper surface of the gate filling film.

[0010] Another aspect of the semiconductor device of the present invention for solving the above problem comprises a gate structure including an active pattern extended in a first direction, a gate liner pattern and a gate top pattern extending in a second direction different from the first direction on the active pattern, wherein the gate liner pattern includes a gate insulating film and a lower conductive liner, and the gate top pattern includes an upper conductive liner and a gate filling film, a gate spacer extended in a second direction on a side wall of the gate structure, and a gate capping pattern covering the upper surface of the gate filling film on the gate structure, wherein the upper surface of the gate liner pattern includes an inclined surface, the upper surface of the gate top pattern has a concave shape, the upper surface of the gate liner pattern has a first step, and the upper surface of the gate top pattern has a second step greater than the first step.

[0011] One aspect of the method for manufacturing a semiconductor device according to the present invention for solving the above other problems comprises forming a gate trench defined by a gate spacer that intersects the active pattern on an active pattern, sequentially forming a free gate insulating film and a lower gate conductive film along the sidewall and bottom surface of the gate trench, forming a sacrificial pattern that fills a portion of the gate trench on the lower gate conductive film, removing the free gate insulating film and the lower gate conductive film protruding above the upper surface of the sacrificial pattern to form a gate insulating film and a lower conductive liner, forming a gate shield insulating pattern extended along the sidewall of the gate trench on the upper surface of the gate insulating film and the upper surface of the lower conductive liner, and after removing the sacrificial pattern, forming a free gate filling film that fills the gate trench on the lower conductive liner and the gate shield insulating pattern, removing a portion of the free gate filling film to form a gate filling film, and forming a gate capping pattern on the gate filling film.

[0012] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0013] FIG. 1 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 2 to 4 are cross-sectional views taken along A-A, B-B, and C-C of FIG. 1. Figure 5 is an enlarged view of section P of Figure 2. Figure 6 is an enlarged view of section Q of Figure 3. FIGS. 7 to 11 are drawings for illustrating semiconductor devices according to several embodiments. FIGS. 12 to 14 are drawings for explaining a semiconductor device according to some embodiments. FIGS. 15 to 19 are drawings for explaining a semiconductor device according to some embodiments. FIG. 20 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 21 to 24 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 25 to 27 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 28 to 30 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 31 to 46 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0014] In the drawings relating to semiconductor devices according to some embodiments, a fin-type transistor (FinFET) including a channel region having a fin-shaped pattern, a transistor including a nanowire or a nanosheet are illustrated as examples, but are not limited thereto. The technical concept of the present invention can be applied to transistors based on two-dimensional materials (2D material based FETs) and heterostructures thereof.

[0015] Additionally, a semiconductor device according to some embodiments may include a tunneling FET or a three-dimensional (3D) transistor. A semiconductor device according to some embodiments may include a bipolar junction transistor, a horizontal dual diffusion transistor (LDMOS), etc.

[0016] FIG. 1 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 2 through 4 are cross-sectional views taken along A-A, B-B, and C-C of FIG. 1. FIG. 5 is an enlarged view of section P of FIG. 2. FIG. 6 is an enlarged view of section Q of FIG. 3.

[0017] Referring to FIGS. 1 to 6, a semiconductor device according to some embodiments may include a first active pattern (AP1), a second active pattern (AP2), a first connection gate structure (50), and a gate shield insulation pattern (160).

[0018] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0019] A first active pattern (AP1) and a second active pattern (AP2) may be disposed on a substrate (100). The first active pattern (AP1) and the second active pattern (AP2) may each be extended in a second direction (D2). The first active pattern (AP1) and the second active pattern (AP2) may be adjacent to each other in a first direction (D1). The first active pattern (AP1) and the second active pattern (AP2) may be spaced apart in the first direction (D1). For example, the first direction (D1) is a direction that intersects the second direction (D2).

[0020] For example, the first active pattern (AP1) may be a region where a PMOS is formed, and the second active pattern (AP2) may be a region where an NMOS is formed. The first active pattern (AP1) may include a channel region of the PMOS, and the second active pattern (AP2) may include a channel region of the NMOS.

[0021] For example, the first active pattern (AP1) and the second active pattern (AP2) may be active regions included in a logic region. The first active pattern (AP1) and the second active pattern (AP2) may be active regions included in a single standard cell.

[0022] As another example, the first active pattern (AP1) and the second active pattern (AP2) may be active regions included in the SRAM region. The first active pattern (AP1) may be a region where the pull-up transistor of the SRAM is formed, and the second active pattern (AP2) may be a region where the pull-down transistor or pass transistor of the SRAM is formed, but is not limited thereto.

[0023] The first active pattern (AP1) may include a first lower pattern (BP1) and a plurality of first sheet patterns (NS1). The second active pattern (AP2) may include a second lower pattern (BP2) and a plurality of second sheet patterns (NS2).

[0024] The first lower pattern (BP1) and the second lower pattern (BP2) may each protrude from the substrate (100). The first lower pattern (BP1) and the second lower pattern (BP2) may each be extended in a second direction (D2). The first lower pattern (BP1) and the second lower pattern (BP2) may each have a pin-shaped pattern.

[0025] The first lower pattern (BP1) may be spaced apart from the second lower pattern (BP2) in a first direction (D1). The first lower pattern (BP1) and the second lower pattern (BP2) may be separated by a pin trench (FT) extending in a second direction (D2).

[0026] A plurality of first sheet patterns (NS1) may be placed on a first lower pattern (BP1). A plurality of first sheet patterns (NS1) may be spaced apart from the first lower pattern (BP1) in a third direction (D3).

[0027] A plurality of second sheet patterns (NS2) may be placed on the second lower pattern (BP2). A plurality of second sheet patterns (NS2) may be spaced apart from the second lower pattern (BP2) in a third direction (D3).

[0028] Each first sheet pattern (NS1) can be sequentially arranged in a third direction (D3). Each first sheet pattern (NS1) can be spaced apart in a third direction (D3). Each second sheet pattern (NS2) can be sequentially arranged in a third direction (D3). Each second sheet pattern (NS2) can be spaced apart in a third direction (D3). Here, the third direction (D3) may be a direction orthogonal to the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be the thickness direction of the substrate (100). The first direction (D1) may be a direction orthogonal to the second direction (D2).

[0029] Although the first sheet pattern (NS1) and the second sheet pattern (NS2) are depicted as being arranged in three places in the third direction (D3), this is for convenience of explanation only and is not limited thereto.

[0030] Each of the first sub-pattern (BP1) and the second sub-pattern (BP2) may be formed by etching a portion of the substrate (100) or may include an epitaxial layer grown from the substrate (100). Each of the first sub-pattern (BP1) and the second sub-pattern (BP2) may include silicon or germanium, which are elemental semiconductor materials. Additionally, each of the first sub-pattern (BP1) and the second sub-pattern (BP2) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0031] Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with a Group IV element.

[0032] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0033] Each first sheet pattern (NS1) may include one of an elemental semiconductor material such as silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Each second sheet pattern (NS2) may include one of an elemental semiconductor material such as silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor.

[0034] The width of the first sheet pattern (NS1) in the first direction (D1) may increase or decrease in proportion to the width of the first lower pattern (BP1) in the first direction (D1). The width of the second sheet pattern (NS2) in the first direction (D1) may increase or decrease in proportion to the width of the second lower pattern (BP2) in the first direction (D1).

[0035] A first field insulating film (105) can be formed on a substrate (100). The first field insulating film (105) can fill at least a portion of the pin trench (FT).

[0036] The first field insulating film (105) may be disposed on a substrate (100) between the first active pattern (AP1) and the second active pattern (AP2). The first field insulating film (105) may be in direct contact with the first active pattern (AP1) and the second active pattern (AP2).

[0037] The fact that the first field insulating film (105) is in direct contact with the first active pattern (AP1) and the second active pattern (BP2) may mean that there is no active pattern used as a channel region of the transistor interposed between the first active pattern (AP1) and the second active pattern (BP2). The first field insulating film (105) may be placed between the first lower pattern (BP1) and the second lower pattern (BP2). The first field insulating film (105) may be in direct contact with the first lower pattern (BP1) and the second lower pattern (BP2).

[0038] For example, the first field insulating film (105) may cover the entire sidewall of the first lower pattern (BP1) defining the pin trench (FT) and the sidewall of the second lower pattern (BP2). Unlike what is illustrated, in another example, the first field insulating film (105) may cover a portion of the sidewall of the first lower pattern (BP1) defining the pin trench (FT) and / or a portion of the sidewall of the second lower pattern (BP2). For example, a portion of the first lower pattern (BP1) and / or a portion of the second lower pattern (BP2) may protrude in a third direction (D3) above the upper surface of the first field insulating film (105). Each first sheet pattern (NS1) and each second sheet pattern (NS2) are positioned higher than the upper surface of the first field insulating film (105).

[0039] The first field insulating film (105) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. The first field insulating film (105) is depicted as a single film but is not limited thereto. Unlike what is depicted, the first field insulating film (105) may include a field liner extending along the sidewalls and bottom surface of the fin trench (FT), and a field filling film on the field liner.

[0040] A first connection gate structure (50) may be formed on a substrate (100). The first connection gate structure (50) may be disposed on a first field insulating film (105). The first connection gate structure (50) may intersect with a first active pattern (AP1), a second active pattern (AP2), and the first field insulating film (105). The first connection gate structure (50) may be extended in a first direction (D1).

[0041] The first connection gate structure (50) can intersect with the first lower pattern (BP1) and the second lower pattern (BP2). The first connection gate structure (50) can wrap each of the first sheet pattern (NS1) and each of the second sheet pattern (NS2).

[0042] The first connected gate structure (50) may include a first gate structure (120) and a second gate structure (220). For example, the first gate structure (120) may be a p-type gate structure and the second gate structure (220) may be an n-type gate structure. In a semiconductor device according to some embodiments, the first gate structure (120) and the second gate structure (220) may come into contact with each other, specifically, they may come into direct contact.

[0043] A first gate structure (120) may be formed on a first active pattern (AP1). The first gate structure (120) may intersect with the first active pattern (AP1). The first gate structure (120) may include a p-type gate electrode.

[0044] The first gate structure (120) can intersect with the first lower pattern (BP1). The first gate structure (120) can wrap each first sheet pattern (NS1).

[0045] A second gate structure (220) may be formed on a second active pattern (AP2). The second gate structure (220) may intersect with the second active pattern (AP2). The second gate structure (220) may include an n-type gate electrode.

[0046] The second gate structure (220) can intersect with the second lower pattern (BP2). The second gate structure (220) can wrap each second sheet pattern (NS2).

[0047] A first p-type transistor (10p) may be defined in the region where the first gate structure (120) and the first active pattern (AP1) intersect, and a first n-type transistor (10n) may be defined in the region where the second gate structure (220) and the second active pattern (AP2) intersect.

[0048] Since the first gate structure (120) extends over the first field insulating film (105), the first gate structure (120) overlaps with the first active pattern (AP1) as well as a portion of the first field insulating film (105). Since the second gate structure (220) extends over the first field insulating film (105), the second gate structure (220) overlaps with the second active pattern (AP2) as well as a portion of the first field insulating film (105). The boundary between the first gate structure (120) and the second gate structure (220) may be located on the upper surface of the first field insulating film (105).

[0049] The first connection gate structure (50) may include a first connection gate insulating film (130, 230), a first lower conductive liner (121), a first connection upper conductive liner (122, 222), and a first connection gate filling film (123, 223).

[0050] For example, the first gate structure (120) may include a first gate insulating film (130), a first lower conductive liner (121), a first upper conductive liner (122), and a first gate filling film (123). The first lower conductive liner (121) and the first upper conductive liner (122) may be disposed between the first gate insulating film (130) and the first gate filling film (123). The second gate structure (220) may include a second gate insulating film (230), a second upper conductive liner (222), and a second gate filling film (223). The second upper conductive liner (222) may be disposed between the second gate insulating film (230) and the second gate filling film (223).

[0051] The first gate insulating film (130) may be placed on the first active pattern (AP1). The first gate insulating film (130) may extend along the upper surface of the first field insulating film (105) and the upper surface of the first lower pattern (BP1). The first gate insulating film (130) may wrap around each first sheet pattern (NS1). The first gate insulating film (130) may be placed along the perimeter of each first sheet pattern (NS1).

[0052] The second gate insulating film (230) may be placed on the second active pattern (AP2). The second gate insulating film (230) may extend along the upper surface of the first field insulating film (105) and the upper surface of the second lower pattern (BP2). The second gate insulating film (230) may wrap around each second sheet pattern (NS2). The second gate insulating film (230) may be placed along the perimeter of each second sheet pattern (NS2). The first gate insulating film (130) and the second gate insulating film (230) may be in direct contact on the upper surface of the first field insulating film (105). The first gate insulating film (130) and the second gate insulating film (230) are formed at the same level. Here, "same level" means formed by the same manufacturing process. The first gate insulating film (130) and the second gate insulating film (230) may be placed across the first active pattern (AP1) and the second active pattern (AP2). The boundary between the first gate insulating film (130) and the second gate insulating film (230) may not be distinct.

[0053] The first gate insulating film (130) and the second gate insulating film (230) may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0054] In FIGS. 2 to 4, the first gate insulating film (130) and the second gate insulating film (230) are depicted as single films, but are not limited thereto. The first gate insulating film (130) and the second gate insulating film (230) may be multiple films including an interface film and a high dielectric constant insulating film on the interface film.

[0055] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the first and second gate insulating films (130, 230) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0056] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0057] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0058] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0059] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0060] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0061] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0062] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0063] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0064] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0065] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0066] For example, the first and second gate insulating films (130, 230) may include a single ferroelectric material film. For another example, the first and second gate insulating films (130, 230) may include a plurality of ferroelectric material films spaced apart from each other. The first and second gate insulating films (130, 230) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0067] A first lower conductive liner (121) may be placed on a first active pattern (AP1). A first lower conductive liner (121) may be formed on a first gate insulating film (130). A first lower conductive liner (121) may be placed on a connecting gate insulating film (130, 230) on the first active pattern (AP1). A first lower conductive liner (121) may wrap around each first sheet pattern (NS1). A first lower conductive liner (121) may be placed along the perimeter of each first sheet pattern (NS1).

[0068] The first lower conductive liner (121) can completely fill the space between the first lower pattern (BP1) and the first sheet pattern (NS1), and the space between adjacent first sheet patterns (NS1). For example, when there is a first lower sheet pattern (NS1) and a first upper sheet pattern (NS1) immediately adjacent in the third direction (D3), the first lower conductive liner (121) can completely fill the space between the upper surface of the first lower sheet pattern (NS1) facing in the third direction (D3) and the lower surface of the first upper sheet pattern (NS1).

[0069] The first lower conductive liner (121) may not be placed on the second active pattern (AP2). The first lower conductive liner (121) may not extend to the second active pattern (AP2). The first lower conductive liner (121) may not be formed on the second gate insulating film (230). The first lower conductive liner (121) may not be placed on the first connecting insulating film (130, 230) on the second active pattern (AP2). The first lower conductive liner (121) may not wrap around each second sheet pattern (NS2). The first lower conductive liner (121) may not be formed along the perimeter of each second sheet pattern (NS2).

[0070] The first lower conductive liner (121) may include one end of the first lower conductive liner (121) located on the upper surface of the first field insulating film (105) between the first active pattern (AP1) and the second active pattern (AP2). The first lower conductive liner (121) may define a step on the upper surface of the first field insulating film (105) between the first active pattern (AP1) and the second active pattern (AP2).

[0071] In a semiconductor device according to some embodiments, the first gate structure (120) includes a first lower conductive liner (121), and the second gate structure (220) may not include the first lower conductive liner (121). When the first gate structure (120) and the second gate structure (220) are in direct contact, the first gate structure (120) and the second gate structure (220) may be distinguished based on the first lower conductive liner (121).

[0072] The interface between the first gate structure (120) and the second gate structure (220) may be located at one end of the first lower conductive liner (121). The step defined by the first lower conductive liner (121) may be located at the interface between the first gate structure (120) and the second gate structure (220).

[0073] The first lower conductive liner (121) may be, for example, a p-type work function film that controls the work function. The first lower conductive liner (121) may include, for example, at least one of TiN, TiAlN, TaC, TaN, TiSiN, TaSiN, and TaCN. In a semiconductor device according to some embodiments, the first lower conductive liner (121) may include TiN or TiAlN.

[0074] The first upper conductive liner (122) may be disposed on the first active pattern (AP1). The first upper conductive liner (122) may be formed on the first lower conductive liner (121).

[0075] When the first lower conductive liner (121) completely fills the space between the first lower pattern (BP1) and the first sheet pattern (NS1), and the space between adjacent first sheet patterns (NS1), the first upper conductive liner (122) may extend along the outer profile of the first lower conductive liner (121). The first upper conductive liner (122) may not be formed in the space between the first lower pattern (BP1) and the first sheet pattern (NS1), and in the space between adjacent first sheet patterns (NS1). The first upper conductive liner (122) may not be formed along the perimeter of each first sheet pattern (NS1).

[0076] The second upper conductive liner (222) can be placed on the second active pattern (AP2). The second upper conductive liner (222) can be in direct contact with the first upper conductive liner (122).

[0077] A second upper conductive liner (222) may be formed on the second gate insulating film (230). The second upper conductive liner (222) may wrap around each second sheet pattern (NS2). The second upper conductive liner (222) may be positioned along the perimeter of each second sheet pattern (NS2).

[0078] The second upper conductive liner (222) can completely fill the space between the second lower pattern (BP2) and the second sheet pattern (NS2), and the space between adjacent second sheet patterns (NS2). For example, when there is a second lower sheet pattern (NS2) and a second upper sheet pattern (NS2) immediately adjacent in the third direction (D3), the second upper conductive liner (222) can completely fill the space between the upper surface of the second lower sheet pattern (NS2) facing in the third direction (D3) and the lower surface of the second upper sheet pattern (NS2).

[0079] The first connecting upper conductive liner (122, 222) may be placed on the first lower conductive liner (121). For example, the first connecting upper conductive liner (122, 222) may be in direct contact with the first lower conductive liner (121). The first connecting upper conductive liner (122, 222) may be placed across the first active pattern (AP1) and the second active pattern (AP2).

[0080] Since the first lower conductive liner (121) is disposed between the first upper conductive liner (122) and the first gate insulating film (130), the first upper conductive liner (122) may not come into contact with the first gate insulating film (130).

[0081] In a semiconductor device according to some embodiments, the second upper conductive liner (222) may be in direct contact with the second gate insulating film (230) formed on the second active pattern (AP2). The second upper conductive liner (222) may be in direct contact with the second gate insulating film (230) surrounding the perimeter of the second sheet pattern (NS2).

[0082] The first connecting upper conductive liner (122, 222) may be, for example, an n-type work function film that controls the work function. The first connecting upper conductive liner (122, 222) may include, for example, one of TiAl, TiAlC, TaAl, or TaAlC. The first upper conductive liner (122) and the second upper conductive liner (222) may be formed at the same level. In a semiconductor device according to some embodiments, the first connecting upper conductive liner (122, 222) may include TiAl or TiAlC.

[0083] The first connection gate filling film (123, 223) may be disposed on the first connection upper conductive liner (122, 222). The first connection gate filling film (123, 223) may be disposed across the first active pattern (AP1) and the second active pattern (AP2). The first gate filling film (123) may be disposed on the first active pattern (AP1). The second gate filling film (223) may be disposed on the second active pattern (AP2).

[0084] The first gate filling film (123, 223) may include, for example, at least one of tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), ruthenium (Ru), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), titanium (Ti), and titanium nitride (TiN). The first gate filling film (123) and the second gate filling film (223) may be formed at the same level.

[0085] The first gate filling film (123) and the second gate filling film (223) are depicted as single films, but are not limited thereto. Of course, the first gate filling film (123) and the second gate filling film (223) may each have a structure in which a plurality of conductive films are stacked.

[0086] The first epitaxial pattern (150) may be placed on the first lower pattern (BP1). The first epitaxial pattern (150) may be placed on at least one side of the first gate structure (120). The first epitaxial pattern (150) may be connected to the first sheet pattern (NS1).

[0087] The second epitaxial pattern (250) may be placed on the second lower pattern (BP2). The second epitaxial pattern (250) may be placed on at least one side of the second gate structure (220). The second epitaxial pattern (250) may be connected to the second sheet pattern (NS2).

[0088] The first epitaxial pattern (150) may be included in the source / drain of a first p-type transistor (10p) using the first sheet pattern (NS1) as the channel region. The second epitaxial pattern (250) may be included in the source / drain of a first n-type transistor (10n) using the second sheet pattern (NS2) as the channel region.

[0089] The first gate spacer (140) may be disposed on the side wall of the first connection gate structure (50). The first gate spacer (140) may be disposed on the side wall of the first gate structure (120) and the side wall of the second gate structure (220).

[0090] The first gate spacer (140) may be extended in a first direction (D1). The first connecting gate structure (50) may include a long sidewall extended in the first direction (D1) and a short sidewall extended in a second direction (D2). The first gate spacer (140) may be extended along the long sidewall of the first connecting gate structure (50). The first gate spacer (140) may not be placed on the short sidewall of the first connecting gate structure (50).

[0091] In FIG. 3, the first gate spacer (140) disposed on the second lower pattern (BP2) may include an outer spacer (141) and an inner spacer (142). The inner spacer (142) may be disposed between the second sheet pattern (NS2) adjacent in the third direction (D3). In FIG. 2, the first gate spacer (140) disposed on the first lower pattern (BP1) may not include the inner spacer (142) and may include only the outer spacer (141).

[0092] Unlike what is illustrated, for example, the first gate spacer (140) placed on the first lower pattern (BP1) and the first gate spacer (140) placed on the second lower pattern (BP2) may both include an outer spacer (141) and an inner spacer (142). Unlike what is illustrated, for another example, the first gate spacer (140) placed on the first lower pattern (BP1) and the first gate spacer (140) placed on the second lower pattern (BP2) may both not include an inner spacer (142) and may include only an outer spacer (141).

[0093] The outer spacer (141) and the inner spacer (142) may each include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0094] A pair of gate cutting structures (GCS) can be placed on a substrate (100). The gate cutting structures (GCS) can be placed on a first field insulating film (105).

[0095] Gate cutting structures (GCS) may be spaced apart in a first direction (D1). A first active pattern (AP1) and a second active pattern (AP2) may be placed between gate cutting structures (GCS) adjacent in the first direction (D1). For example, a first lower pattern (BP1) and a second lower pattern (BP2) may be placed between gate cutting structures (GCS) adjacent in the first direction (D1).

[0096] A first connecting gate structure (50) may be positioned between adjacent gate cutting structures (GCS) in a first direction (D1). The gate cutting structures (GCS) may separate the gate structures adjacent in the first direction (D1). The sidewall of the first connecting gate structure (50) may face the sidewall of the gate cutting structure (GCS).

[0097] In a semiconductor device according to some embodiments, a first gate insulating film (130), a first lower conductive liner (121), and a first upper conductive liner (122) may extend along the sidewall of a gate cutting structure (GCS). A second gate insulating film (230) and a second upper conductive liner (222) may extend along the sidewall of a gate cutting structure (GCS).

[0098] For example, the gate cutting structure (GCS) can be placed along the boundary of a standard cell. For example, the gate cutting structure (GCS) can be a standard cell isolation structure. As another example, the gate cutting structure (GCS) can be placed within an SRAM region and can be a gate isolation structure.

[0099] The gate cutting structure (GCS) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbon (SiOC), aluminum oxide (AlO), and combinations thereof. The gate cutting structure (GCS) is depicted as a single film, but is not limited thereto.

[0100] The first gate capping pattern (145) may be placed on the first connection gate structure (50). The first gate capping pattern (145) may be placed on the first gate structure (120) and the second gate structure (220). The first gate capping pattern (145) may cover the upper surface (123_US) of the first gate filling film and the upper surface (223_US) of the second gate filling film. For example, the upper surface (145_US) of the first gate capping pattern may be placed in the same plane as the upper surface of the interlayer insulating film (190) and the upper surface of the gate cutting structure (GCS).

[0101] The first gate capping pattern (145) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonate (SiOC), silicon oxycarbonite (SiOCN) and combinations thereof.

[0102] The gate shield insulation pattern (160) may be placed on the first connection gate structure (50). The gate shield insulation pattern (160) may be placed on the first gate structure (120) and the second gate structure (220).

[0103] The gate shield insulation pattern (160) may be disposed on the sidewall of the first gate spacer (140). The gate shield insulation pattern (160) may be disposed on the sidewall of the gate cutting structure (GCS). The gate shield insulation pattern (160) may extend along a portion of the sidewall of the first gate spacer (140) and a portion of the sidewall of the gate cutting structure (GCS). In a semiconductor device according to some embodiments, the gate shield insulation pattern (160) may be disposed between the first gate spacer (140) and the first gate capping pattern (145), and between the gate cutting structure (GCS) and the first gate capping pattern (145). In a planar view, the gate shield insulation pattern (160) may have a closed loop shape.

[0104] The gate shield insulation pattern (160) may include a first sidewall (160_SW1) and a second sidewall (160_SW2) that are opposite to each other. The first sidewall (160_SW1) of the gate shield insulation pattern may face the first gate capping pattern (145). On the other hand, the first sidewall (160_SW1) of the gate shield insulation pattern may face the long sidewall of the first connecting gate structure (50) and the short sidewall of the first connecting gate structure (50). The second sidewall (160_SW2) of the gate shield insulation pattern may face the first gate spacer (140) and the gate cutting structure (GCS).

[0105] The gate shield insulation pattern (160) may extend to the upper surface (145_US) of the first gate capping pattern. In a semiconductor device according to some embodiments, the first gate capping pattern (145) does not cover the upper surface (160_US) of the gate shield insulation pattern. For example, the upper surface (160_US) of the gate shield insulation pattern may lie in the same plane as the upper surface (145_US) of the first gate capping pattern.

[0106] The gate shield insulation pattern (160) includes an insulating material. The gate shield insulation pattern (160) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOCN), and combinations thereof.

[0107] In FIGS. 4 to 6, the gate shield insulation pattern (160) may cover the upper surface (130_US) of the first gate insulating film and the upper surface (230_US) of the second gate insulating film. The gate shield insulation pattern (160) may cover at least a portion of the upper surface (121_US) of the first lower conductive liner. The gate shield insulation pattern (160) may come into contact with the upper surface (130_US) of the first gate insulating film, the upper surface (230_US) of the second gate insulating film, and the upper surface (121_US) of the first lower conductive liner.

[0108] For example, the gate shield insulation pattern (160) may cover a portion of the upper surface (121_US) of the first lower conductive liner. The thickness (t1) of the gate shield insulation pattern (160) may be smaller than the sum of the thickness (t21) of the first gate insulating film (130) and the thickness (t22) of the first lower conductive liner (121).

[0109] Unlike what is depicted, the gate shield insulation pattern (160) may not cover the upper surface (121_US) of the first lower conductive liner. The bottom surface (160_BS) of the gate shield insulation pattern may not come into contact with the upper surface (121_US) of the first lower conductive liner.

[0110] Since the gate shield insulation pattern (160) covers the upper surface (130_US) of the first gate insulating film and the upper surface (230_US) of the second gate insulating film, the first gate capping pattern (145) may not come into contact with the first gate insulating film (130) and the second gate insulating film (230).

[0111] The first gate insulating film (130) may not extend along the boundary between the gate shield insulating pattern (160) and the first gate spacer (140). The first gate insulating film (130) may not extend along the boundary between the gate shield insulating pattern (160) and the gate cutting structure (GCS). Alternatively, the gate shield insulating pattern (160) may not be placed between the first gate insulating film (130) and the first gate spacer (140), and between the first gate insulating film (130) and the gate insulating structure (GCS). The gate shield insulating pattern (160) may not be placed between the second gate insulating film (230) and the first gate spacer (140), and between the second gate insulating film (230) and the gate insulating structure (GCS).

[0112] The first upper conductive liner (122) may extend along the first sidewall (160_SW1) of the gate shield insulation pattern. The first upper conductive liner (122) may be positioned between the gate shield insulation pattern (160) and the first gate filling film (123). A portion of the first upper conductive liner (122) may extend between the gate shield insulation pattern (160) and the first gate filling film (123). The first upper conductive liner (122) may extend to the upper surface (123_US) of the first gate filling film. The first upper conductive liner (122) may be in contact with the first sidewall (160_SW1) of the gate shield insulation pattern.

[0113] The second upper conductive liner (222) may extend along the first sidewall (160_SW1) of the gate shield insulation pattern and the bottom surface (160_BS) of the gate shield insulation pattern. The second upper conductive liner (222) may extend to the upper surface (223_US) of the second gate filling film. The second upper conductive liner (222) may contact the first sidewall (160_SW1) of the gate shield insulation pattern.

[0114] The first gate capping pattern (145) can cover the upper surface (123_US) of the first gate filling film, the upper surface (223_US) of the second gate filling film, the upper surface (122_US) of the first upper conductive liner, and the upper surface (222_US) of the second upper conductive liner. For example, the first gate capping pattern (145) can come into contact with the first gate filling film (123), the second gate filling film (223), the first upper conductive liner (122), and the second upper conductive liner (222).

[0115] In FIGS. 5 and 6, the upper surface (130_US) of the first gate insulating film, the upper surface (121_US) of the first lower conductive liner, the upper surface (122_US) of the first upper conductive liner, the upper surface (230_US) of the second gate insulating film, and the upper surface (222_US) of the second upper conductive liner may include an inclined surface. The upper surface (123_US) of the first gate filling film and the upper surface (223_US) of the second gate filling film may each have a concave shape.

[0116] In a semiconductor device according to some embodiments, the first gate insulating film (130) and the first lower conductive liner (121) of the first gate structure (120) may be defined as a gate liner pattern. The gate shield insulating pattern (160) may cover at least a portion of the upper surface (130_US, 121_US) of the gate liner pattern. The first upper conductive liner (122) and the first gate filling film (123) of the first gate structure (120) may be defined as a gate upper pattern. The second gate structure (220) may also be defined similarly to the first gate structure (120).

[0117] For example, the upper surface of the gate liner pattern of the first gate structure (120) may include an inclined surface. The upper surface of the gate upper pattern of the first gate structure (120) may have a concave shape.

[0118] For example, with respect to the upper surface (NS1_US) of the first active pattern, the upper surface (130_US) of the first gate insulating film and the upper surface (121_US) of the first lower conductive liner are lower than the upper surface (123_US) of the first gate filling film and the upper surface (122_US) of the first upper conductive liner. For example, if the first active pattern (AP1) includes the first sheet pattern (NS1), the upper surface (NS1_US) of the first active pattern may be the upper surface of the sheet pattern positioned at the top of the first sheet pattern (NS1). With respect to the upper surface (NS2_US) of the second active pattern, the upper surface (230_US) of the second gate insulating film is lower than the upper surface (223_US) of the second gate filling film and the upper surface (222_US) of the second upper conductive liner.

[0119] The gate shield insulation pattern (160) may cover at least a portion of the upper surface (121_US) of the first lower conductive liner. That is, with respect to the upper surface (NS1_US) of the first active pattern, the upper surface (130_US) of the first gate insulating film and the upper surface (230_US) of the second gate insulating film may be lower than the bottom surface (160_BS) of the gate shield insulation pattern.

[0120] In FIG. 5, the height (H11) from the upper surface (NS1_US) of the first active pattern to the upper surface (130_US) of the first gate insulating film is smaller than the height (H14) from the upper surface (NS1_US) of the first active pattern to the upper surface (123_US) of the first gate filling film and the height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner. The height (H11) from the upper surface (NS1_US) of the first active pattern to the upper surface (130_US) of the first gate insulating film is larger than the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner. The height (H14) from the upper surface (NS1_US) of the first active pattern to the upper surface (123_US) of the first gate filling film is smaller than the height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner. Here, "height of the upper surface" may mean the height from the upper surface of the active pattern to the lowest part of the upper surface. Although not shown, the height relationship within the first gate structure (120) in FIG. 5 can, of course, also be applied to the second gate structure (220) shown in FIG. 6.

[0121] The upper surface (130_US, 121_US) of the gate liner pattern of the first gate structure (120) may have a first step (SP1). The upper surface (122_US, 123_US) of the gate upper pattern of the first gate structure (120) may have a second step (SP2). The upper surface (123_US) of the first gate filling film may have a third step (SP3). Here, "step of the upper surface" may be the height difference between the highest part of the upper surface and the lowest part of the upper surface with respect to the upper surface of the active pattern.

[0122] The step (SP1) of the upper surface (130_US, 121_US) of the gate liner pattern is smaller than the step (SP2) of the upper surface (122_US, 123_US) of the gate upper pattern. For example, the step (SP1) of the upper surface (130_US, 121_US) of the gate liner pattern may be smaller than the step (SP3) of the upper surface (123_US) of the first gate filling film. For another example, the step (SP1) of the upper surface (130_US, 121_US) of the gate liner pattern may be the same as the step (SP3) of the upper surface (123_US) of the first gate filling film. For yet another example, the step (SP1) of the upper surface (130_US, 121_US) of the gate liner pattern may be larger than the step (SP3) of the upper surface (123_US) of the first gate filling film.

[0123] Unlike what is illustrated, for example, the step (SP1) of the upper surface (130_US, 121_US) of the gate liner pattern may be the same as the step (SP2) of the upper surface (122_US, 123_US) of the gate upper pattern. For another example, the step (SP1) of the upper surface (130_US, 121_US) of the gate liner pattern may be greater than the step (SP2) of the upper surface (122_US, 123_US) of the gate upper pattern.

[0124] A first source / drain contact (180) may be disposed on the first epitaxial pattern (150). A first silicide film (155) may be further disposed between the first source / drain contact (180) and the first epitaxial pattern (150).

[0125] A second source / drain contact (280) may be disposed on the second epitaxial pattern (250). A second silicide film (255) may be further disposed between the second source / drain contact (280) and the second epitaxial pattern (250).

[0126] The first source / drain contact (180) and the second source / drain contact (280) each comprise a conductive material and may include, for example, at least one of a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, and a conductive semiconductor material. Although the first source / drain contact (180) and the second source / drain contact (280) are each depicted as having a single film, this is for convenience of explanation only and is not limited thereto. As an example, the first source / drain contact (180) and the second source / drain contact (280) may include a contact barrier film and a contact filling film that fills the space defined by the contact barrier film. As another example, the first source / drain contact (180) and the second source / drain contact (280) may include only a contact filling film without a contact barrier film. The first silicide film (155) and the second silicide film (255) may each include, for example, a metal silicide material.

[0127] By lowering the height of the first gate structure (120) and the second gate structure (220) in the portion adjacent to the source / drain contact (180, 280), the gate shield insulation pattern (160) can prevent a short circuit between the source / drain contact (180, 280) and the gate structure (120, 220). Additionally, by lowering the height of the first gate structure (120) and the second gate structure (220) in the portion adjacent to the source / drain contact (180, 280), the capacitance between the source / drain contact (180, 280) and the gate structure (120, 220) can be reduced.

[0128] The interlayer insulating film (190) can be placed on the first epitaxial pattern (150) and the second epitaxial pattern (250). Each of the interlayer insulating films (190) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (Flowable Oxide), TOSZ (Tonen SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, or a combination thereof, but is not limited thereto.

[0129] Although not shown, a wiring line extending in a second direction (D2) along the gate cutting structure (GCS) can be placed on the gate cutting structure (GCS).

[0130] FIGS. 7 to 11 are drawings for explaining semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 to 6. For reference, FIGS. 7 to 11 are enlarged views of section P of FIG. 2. Through FIGS. 7 to 11, the enlarged view related to section Q of FIG. 3 can be easily inferred.

[0131] Referring to FIGS. 7 and FIGS. 8, in a semiconductor device according to some embodiments, the gate shield insulating pattern (160) can cover the entire upper surface (121_US) of the first lower conductive liner.

[0132] In FIG. 7, the thickness (t1) of the gate shield insulation pattern (160) may be equal to the sum of the thickness (t21) of the first gate insulation film (130) and the thickness (t22) of the first lower conductive liner (121).

[0133] In FIG. 8, the thickness (t1) of the gate shield insulation pattern (160) may be greater than the sum of the thickness (t21) of the first gate insulation film (130) and the thickness (t22) of the first lower conductive liner (121). At this time, the first upper conductive liner (122) may cover a portion of the bottom surface (160_BS) of the gate shield insulation pattern.

[0134] Referring to FIG. 9, in a semiconductor device according to some embodiments, the upper surface (130_US) of the first gate insulating film and the upper surface (121_US) of the first lower conductive liner may be flat with respect to the upper surface (NS1_US) of the first active pattern.

[0135] The upper surface (122_US) of the first upper conductive liner and the upper surface (123_US) of the first gate filling film may be flat with respect to the upper surface (NS1_US) of the first active pattern.

[0136] Unlike what is depicted, the upper surface (122_US) of the first upper conductive liner includes an inclined surface, and the upper surface (123_US) of the first gate filling film may have a concave shape.

[0137] Referring to FIG. 10, in a semiconductor device according to some embodiments, the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner may be the same as the height (H14) from the upper surface (NS1_US) of the first active pattern to the upper surface (123_US) of the first gate filling film.

[0138] The height (H11) from the upper surface (NS1_US) of the first active pattern to the upper surface (130_US) of the first gate insulating film is greater than the height (H14) from the upper surface (NS1_US) of the first active pattern to the upper surface (123_US) of the first gate filling film. The height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner is greater than the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner.

[0139] Referring to FIG. 11, in a semiconductor device according to some embodiments, the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner is greater than the height (H14) from the upper surface (NS1_US) of the first active pattern to the upper surface (123_US) of the first gate filling film.

[0140] For example, the height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner may be greater than the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner. For another example, the height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner may be equal to the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner. As another example, the height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner may be smaller than the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner.

[0141] FIGS. 12 to 14 are drawings for explaining semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 1 to 6.

[0142] Referring to FIGS. 12 to 14, in a semiconductor device according to some embodiments, a first gate capping pattern (145) may cover the upper surface (160_US) of a gate shield insulating pattern. The first gate capping pattern (145) may come into contact with the upper surface (160_US) of the gate shield insulating pattern.

[0143] The gate shield insulation pattern (160) does not extend to the upper surface (145_US) of the first gate capping pattern. The upper surface (160_US) of the gate shield insulation pattern is lower than the upper surface (145_US) of the first gate capping pattern.

[0144] The first gate capping pattern (145) can cover the upper surface of the first gate spacer (140).

[0145] During the process of manufacturing the first connection gate structure (50), a portion of the gate shield insulation pattern (160) and a portion of the first gate spacer (140) may be etched so that the upper surface (160_US) of the gate shield insulation pattern may be lowered. Afterward, the first gate capping pattern (145) may cover the upper surface (160_US) of the etched gate shield insulation pattern.

[0146] FIGS. 15 to 19 are drawings for illustrating semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 1 to 6.

[0147] Referring to FIGS. 15 to 19, in a semiconductor device according to some embodiments, the upper surface (122_US) of the first upper conductive liner may be lower than the bottom surface (160_BS) of the gate shield insulating pattern with respect to the upper surface (NS1_US) of the first active pattern. The upper surface (222_US) of the second upper conductive liner may be lower than the bottom surface (160_BS) of the gate shield insulating pattern with respect to the upper surface (NS2_US) of the second active pattern.

[0148] The first upper conductive liner (122) does not extend along the first sidewall (160_SW1) of the gate shield insulation pattern. The second upper conductive liner (222) does not extend along the first sidewall (160_SW1) of the gate shield insulation pattern. The first upper conductive liner (122) and the second upper conductive liner (222) do not cover the first sidewall (160_SW1) of the gate shield insulation pattern.

[0149] The first upper conductive liner (122) is not positioned between the gate shield insulation pattern (160) and the first gate filling film (123). The first gate filling film (123) may come into contact with the first sidewall (160_SW1) of the gate shield insulation pattern. The first upper conductive liner (122) does not extend to the upper surface (123_US) of the first gate filling film.

[0150] The second upper conductive liner (222) is not positioned between the gate shield insulation pattern (160) and the second gate filling film (223). The second gate filling film (223) may come into contact with the first sidewall (160_SW1) of the gate shield insulation pattern. The second upper conductive liner (222) does not extend to the upper surface (223_US) of the second gate filling film.

[0151] The first gate capping pattern (145) is in contact with the first gate filling film (123) and the second gate filling film (223), but is not in contact with the first upper conductive liner (122) and the second upper conductive liner (222).

[0152] In a semiconductor device according to some embodiments, the first gate insulating film (130), the first lower conductive liner (121), and the first upper conductive liner (122) of the first gate structure (120) may be defined as a gate liner pattern. The gate shield insulating pattern (160) may cover at least a portion of the upper surface (130_US, 121_US, 122_US) of the gate liner pattern. The first gate filling film (123) of the first gate structure (120) may be defined as a gate upper pattern. The second gate structure (220) may also be defined similarly to the first gate structure (120).

[0153] With respect to the upper surface (NS1_US) of the first active pattern, the upper surface (130_US) of the first gate insulating film, the upper surface (121_US) of the first lower conductive liner, and the upper surface (122_US) of the first upper conductive liner are lower than the upper surface (123_US) of the first gate filling film. With respect to the upper surface (NS2_US) of the second active pattern, the upper surface (230_US) of the second gate insulating film and the upper surface (222_US) of the second upper conductive liner are lower than the upper surface (223_US) of the second gate filling film.

[0154] In FIG. 18, the height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner is smaller than the height (H14) from the upper surface (NS1_US) of the first active pattern to the upper surface (123_US) of the first gate filling film. The height (H13) from the upper surface (NS1_US) of the first active pattern to the upper surface (122_US) of the first upper conductive liner is smaller than the height (H12) from the upper surface (NS1_US) of the first active pattern to the upper surface (121_US) of the first lower conductive liner. Although not shown, the height relationship within the first gate structure (120) in FIG. 18 can, of course, also be applied to the second gate structure (220) shown in FIG. 19.

[0155] FIG. 20 is a drawing for illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 6.

[0156] Referring to FIG. 20, in a semiconductor device according to some embodiments, the first gate insulating film (130), the first lower conductive liner (121), and the first upper conductive liner (122) do not extend along the sidewall of the gate cutting structure (GCS). The second gate insulating film (230) and the second upper conductive liner (222) do not extend along the sidewall of the gate cutting structure (GCS).

[0157] The gate shield insulation pattern (160) is not placed between the gate cutting structure (GCS) and the first gate capping pattern (145). Meanwhile, the gate shield insulation pattern (160) is placed between the first gate spacer (140) and the first gate capping pattern (145). In a planar view, the gate shield insulation pattern (160) may have a line shape that is spaced apart in the second direction (D2) and extended in the first direction (D1).

[0158] FIGS. 21 to 24 are drawings for illustrating semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 1 to 6.

[0159] Referring to FIGS. 21 to 24, in a semiconductor device according to some embodiments, a first gate capping pattern (145) may come into contact with a first gate insulating film (130), a second gate insulating film (230), and a first lower conductive liner (121).

[0160] In other words, the first gate capping pattern (145) can cover the upper surface of the first gate insulating film (130_US in FIG. 5), the upper surface of the second gate insulating film (230_US in FIG. 6), and the first lower conductive liner (121_US in FIG. 5). That is, the first gate capping pattern (145) can cover at least a portion of the upper surfaces (130_US, 121_US) of the gate liner pattern.

[0161] The first gate capping pattern (145) may include a horizontal portion (145H) and a vertical portion (145V). The horizontal portion (145H) of the first gate capping pattern may cover the upper surface of the first gate filling film (123) and the upper surface of the second gate filling film (223). The vertical portion (145V) of the first gate capping pattern may extend between the first gate spacer (140) and the first upper conductive liner (122). The vertical portion (145V) of the first gate capping pattern may extend between the first gate spacer (140) and the second upper conductive liner (222). The vertical portion (145V) of the first gate capping pattern may extend between the gate cutting structure (GCS) and the first upper conductive liner (122).

[0162] In FIG. 23, the space between the gate cutting structure (GCS) and the first upper conductive liner (122) can be entirely filled by the first gate capping pattern (145).

[0163] In FIG. 24, the vertical portion (145V) of the first gate capping pattern may include an air gap (AG). Although not illustrated, the vertical portion (145V) of the first gate capping pattern between the first gate spacer (140) and the first upper conductive liner (122) may include an air gap (AG). The vertical portion (145V) of the first gate capping pattern between the first gate spacer (140) and the second upper conductive liner (222) may include an air gap (AG).

[0164] FIGS. 25 to 27 are drawings for explaining semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 1 to 6.

[0165] Referring to FIGS. 25 to 27, in a semiconductor device according to some embodiments, the second gate structure (220) may further include a second lower conductive liner (221) disposed between the second gate insulating film (230) and the second upper conductive liner (222). Additionally, the first active pattern (AP1) and the second active pattern (AP2) may be pin-shaped patterns protruding from the substrate (100).

[0166] A portion of the first active pattern (AP1) and a portion of the second active pattern (AP2) may protrude above the upper surface of the first field insulating film (105).

[0167] The first connection gate structure (50) may cover a portion of the first active pattern (AP1) and a portion of the second active pattern (AP2) that protrude above the upper surface of the first field insulating film (105). For example, a deep trench (DT) deeper than a pin trench (FT) may be placed between the first active pattern (AP1) and the second active pattern (AP2).

[0168] Unlike what is described, for example, a deep trench (DT) may not be formed between the first active pattern (AP1) and the second active pattern (AP2). As another example, a dummy pin pattern may be disposed between the first active pattern (AP1) and the second active pattern (AP2), the upper surface of which is covered by the first field insulating film (105).

[0169] Although it has been illustrated that a first active pattern (AP1) and a second active pattern (AP2) are placed within an active area defined by a deep trench (DT), this is for convenience of explanation only and is not limited thereto.

[0170] A second lower conductive liner (221) may be disposed on a second active pattern (AP2). A second lower conductive liner (221) may be formed on a second gate insulating film (230). A second lower conductive liner (121) may be disposed along the profile of a second active pattern (AP2) disposed above the upper surface of a first field insulating film (105).

[0171] The second lower conductive liner (221) may be in direct contact with the upper surface of the first lower conductive liner (121) and the first field insulating film (105). For example, the thickness (t31) of the first lower conductive liner (121) may be greater than the thickness (t32) of the second lower conductive liner (221). A step shape may be formed at the boundary between the second lower conductive liner (221) and the first lower conductive liner (121). The step defined between the second lower conductive liner (221) and the first lower conductive liner (121) may be located at the boundary surface between the first gate structure (120) and the second gate structure (220).

[0172] The second lower conductive liner (221) contains the same material as the first lower conductive liner (121).

[0173] In FIG. 27, the gate shield insulation pattern (160) may be placed on the upper surface of lower conductive liners (121, 221) of different thicknesses. Alternatively, the thickness (t31) of the first lower conductive liner (121) and the thickness (t32) of the second lower conductive liner (221) are different, but the thickness (t1) of the gate shield insulation pattern (160) on the upper surface of the first lower conductive liner (121) is the same as the thickness (t1) of the gate shield insulation pattern (160) on the upper surface of the second lower conductive liner (221).

[0174] FIGS. 28 to 30 are drawings for illustrating a semiconductor device according to some embodiments. For reference, FIG. 28 is a layout drawing for illustrating a semiconductor device according to some embodiments. FIGS. 29 and FIGS. 30 are cross-sectional views taken along D-D and E-E of FIG. 28.

[0175] The first active pattern (AP1), the second active pattern (AP2), and the first connection gate structure (50) illustrated in the first region (I) of FIG. 28 may be substantially the same as those described using FIG. 1 through 27. Additionally, the cross-sectional view taken along A-A and C-C of FIG. 16 may be substantially the same as one of the drawings described in FIG. 2 through 27. Accordingly, the following description focuses on the second region (II) of FIG. 28 and FIG. 29 and FIG. 30.

[0176] In addition, although a cross-sectional view cut in the fifth direction (D5) in the fourth active pattern (AP4) of FIG. 28 is not shown, it is obvious that a person skilled in the art of the present invention can infer the cross-sectional view through the contents shown in FIG. 2 to FIG. 27.

[0177] Referring to FIG. 28 and FIG. 30, a semiconductor device according to some embodiments may include a first active pattern (AP1), a second active pattern (AP2), and a first connection gate structure (50) disposed in a first region (I), and a third active pattern (AP3), a fourth active pattern (AP4), and a second connection gate structure (60) disposed in a second region (II).

[0178] The substrate (100) may include a first region (I) and a second region (II). The first region (I) and the second region (II) may each be one of a logic region, an SRAM region, and an I / O region. For example, the first region (I) and the second region (II) may be the same region. For another example, the first region (I) and the second region (II) may be different regions.

[0179] The third active pattern (AP3) and the fourth active pattern (AP4) may be disposed on the substrate (100). The third active pattern (AP3) and the fourth active pattern (AP4) may each be extended in a fifth direction (D5). The third active pattern (AP3) and the fourth active pattern (AP4) may be adjacent to each other in a fourth direction (D4). The third active pattern (AP3) may be an area where a PMOS is formed, and the fourth active pattern (AP4) may be an area where an NMOS is formed.

[0180] The third active pattern (AP3) may include a third lower pattern (BP3) and a plurality of third sheet patterns (NS3). The fourth active pattern (AP4) may include a fourth lower pattern (BP4) and a plurality of fourth sheet patterns (NS4). The third lower pattern (BP3) may be spaced apart from the fourth lower pattern (BP4) in a fourth direction (D4). The third lower pattern (BP3) and the fourth lower pattern (BP4) may be separated by a pin trench (FT) extending in a fifth direction (D5).

[0181] A plurality of third sheet patterns (NS3) may be placed on the third lower pattern (BP3). A plurality of third sheet patterns (NS3) may be spaced apart from the third lower pattern (BP3) in a third direction (D3). A plurality of fourth sheet patterns (NS4) may be placed on the fourth lower pattern (BP4). A plurality of fourth sheet patterns (NS4) may be spaced apart from the fourth lower pattern (BP4) in a third direction (D3).

[0182] A second field insulating film (106) may be formed on a substrate (100). The second field insulating film (106) may be disposed on the substrate (100) between a third active pattern (AP3) and a fourth active pattern (AP4). The second field insulating film (106) may be disposed between a third lower pattern (BP3) and a fourth lower pattern (BP4). The second field insulating film (106) may cover the sidewalls of the third lower pattern (BP3) and the sidewalls of the fourth lower pattern (BP4). The second field insulating film (106) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0183] A second connection gate structure (60) may be formed on a substrate (100). The second connection gate structure (60) may be disposed on a second field insulating film (106). The second connection gate structure (60) may intersect with a third active pattern (AP3), a fourth active pattern (AP4), and the second field insulating film (106). The second connection gate structure (60) may be extended in a fourth direction (D4). The fourth direction (D4) may be a direction orthogonal to the fifth direction (D5).

[0184] The second connecting gate structure (60) can intersect with the third lower pattern (BP3) and the fourth lower pattern (BP4). The second connecting gate structure (60) can wrap each of the third sheet pattern (NS3) and each of the fourth sheet pattern (NS4).

[0185] For example, the width (W2) in the fifth direction (D5) of the second connection gate structure (60) is larger than the width (W1) in the second direction (D2) of the first connection gate structure (50).

[0186] The second connection gate structure (60) may include a third gate structure (320) and a fourth gate structure (420). The third gate structure (320) may be a p-type gate structure, and the fourth gate structure (420) may be an n-type gate structure.

[0187] A third gate structure (320) may be formed on a third active pattern (AP3). The third gate structure (320) may intersect with the third active pattern (AP3). The third gate structure (320) may intersect with a third lower pattern (BP3). The third gate structure (320) may wrap around each third sheet pattern (NS3).

[0188] A fourth gate structure (420) may be formed on a fourth active pattern (AP4). The fourth gate structure (420) may intersect with the fourth active pattern (AP4). The fourth gate structure (420) may intersect with a fourth lower pattern (BP4). The fourth gate structure (420) may wrap around each of the fourth sheet patterns (NS4).

[0189] A second p-type transistor (20p) may be defined in the region where the third gate structure (320) and the third active pattern (AP3) intersect, and a second n-type transistor (20n) may be defined in the region where the fourth gate structure (420) and the fourth active pattern (AP4) intersect.

[0190] The second connection gate structure (60) may include a second connection gate insulating film (330, 430), a third lower conductive liner (321), a second connection upper conductive liner (322, 422), and a second connection gate filling film (323, 423).

[0191] The third gate structure (320) may include a third gate insulating film (330), a third lower conductive liner (321), a third upper conductive liner (322), and a third gate filling film (323). The fourth gate structure (420) may include a fourth gate insulating film (430), a fourth upper conductive liner (422), and a fourth gate filling film (423).

[0192] Since the third gate structure (320) and the fourth gate structure (420) may be substantially identical to the description of the first gate structure (120) and the second gate structure (220) described using FIGS. 1 to 6, the overlapping parts are omitted.

[0193] The third epitaxial pattern (350) may be placed on the third lower pattern (BP3). Although not shown, an epitaxial pattern may also be placed on the fourth lower pattern (BP4).

[0194] The second gate spacer (340) may be disposed on the side wall of the second connecting gate structure (60). The second gate spacer (340) may extend along the long side wall of the second connecting gate structure (60).

[0195] The second gate capping pattern (345) may be placed on the second connection gate structure (60). The second gate capping pattern (345) may completely cover the upper surface (320_US) of the third gate structure. The upper surface (345_US) of the second gate capping pattern may be placed in the same plane as the upper surface of the interlayer insulating film (190) and the upper surface of the gate cutting structure (GCS).

[0196] The upper surface (320_US) of the third gate structure may include the upper surface of the third gate insulating film (330), the upper surface of the third lower conductive liner (321), the upper surface of the third upper conductive liner (322), and the upper surface of the third gate filling film (323). For example, the upper surface (320_US) of the third gate structure may have a concave shape. With respect to the upper surface of the third active pattern (AP3), the upper surface of the third gate insulating film (330) may be higher than the upper surface of the third lower conductive liner (321). The upper surface of the third lower conductive liner (321) may be higher than the upper surface of the third upper conductive liner (322). The upper surface of the third upper conductive liner (322) may be higher than the upper surface of the third gate filling film (323).

[0197] For example, the second gate capping pattern (345) may come into contact with the upper surface of the third gate insulating film (330), the upper surface of the third lower conductive liner (321), the upper surface of the third upper conductive liner (322), and the upper surface of the third gate filling film (323).

[0198] The details regarding the upper surface of the fourth gate structure (420) may be substantially the same as the details regarding the upper surface (320_US) of the third gate structure, so they are omitted below.

[0199] FIGS. 31 to 46 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments.

[0200] For reference, FIGS. 31, 33, 35, 37, 39, 41, 43, and 45 are intermediate drawings cut along A-A of FIG. 1. FIGS. 32, 34, 36, 38, 40, 42, 44, and 46 are intermediate drawings cut along C-C of FIG. 1.

[0201] Referring to FIGS. 31 and 32, a gate trench (50t) intersecting the first active pattern (AP1) and the second active pattern (AP2) can be formed on the substrate (100).

[0202] The gate trench (50t) can be defined by the first gate spacer (140).

[0203] While forming the gate trench (50t), a first active pattern (AP1) and a second active pattern (AP2) may be formed. More specifically, while forming the gate trench (50t), a first sheet pattern (NS1) spaced apart from the first lower pattern (BP1) and a second sheet pattern (NS2) spaced apart from the second lower pattern (BP2) may be formed.

[0204] Referring to FIGS. 33 and 34, the pre-gate insulating film (130p) and the lower gate conductive film (121p) can be formed sequentially along the sidewalls and bottom surfaces of the gate trench (50t).

[0205] The free gate insulating film (130p) may extend along the upper surface of the first field insulating film (105), the upper surface of the first lower pattern (BP1), and the upper surface of the second lower pattern (BP2). The free gate insulating film (130p) may be formed along the perimeter of the first sheet pattern (NS1) and the perimeter of the second sheet pattern (NS2).

[0206] A lower gate conductive film (121p) can be formed on a free gate insulating film (130p). The lower gate conductive film (121p) can completely fill the space between the first lower pattern (BP1) and the first sheet pattern (NS1), and the space between adjacent first sheet patterns (NS1). Additionally, the lower gate conductive film (121p) can completely fill the space between the second lower pattern (BP2) and the second sheet pattern (NS2), and the space between adjacent second sheet patterns (NS2).

[0207] Referring to FIGS. 35 and 36, a sacrificial pattern (70) can be formed on the lower gate conductive film (121p).

[0208] The sacrifice pattern (70) can fill a portion of the gate trench (50t). The sacrifice pattern (70) may include, for example, an ACL (Amorphous Carbon Layer), a SOH (Spin On Hardmask), or a photoresist (PR), but is not limited thereto.

[0209] Referring to FIGS. 37 and 38, a free gate insulating film (130p) and a lower gate conductive film (121p) protruding above the upper surface of the sacrifice pattern (70) can be removed using a sacrifice pattern (70).

[0210] Through this, a first gate insulating film (130), a second gate insulating film (230), a first lower conductive liner (121), and a second lower conductive liner (221) can be formed within the gate trench (50t).

[0211] The upper surface of the first gate insulating film (130) and the upper surface of the first lower conductive liner (121) may include an inclined surface. The upper surface of the second gate insulating film (230) and the upper surface of the second lower conductive liner (221) may include an inclined surface.

[0212] Referring to FIGS. 39 to 42, a gate shield insulating pattern (160) may be formed on the upper surface (130_US) of the first gate insulating film and the upper surface (121_US) of the first lower conductive liner. The gate shield insulating pattern (160) may be formed on the upper surface (230_US) of the second gate insulating film and the upper surface (221_US) of the second lower conductive liner.

[0213] The gate shield insulation pattern (160) may extend along the sidewall of the gate trench (50t). The gate shield insulation pattern (160) may be formed on a portion of the sidewall of the first gate spacer (140) and a portion of the sidewall of the gate cutting structure (GCS).

[0214] Next, the sacrifice pattern (70) within the gate trench (50t) can be removed.

[0215] Although not shown, after removing the sacrifice pattern (70), a mask pattern can be formed to fill part of the gate trench (50t). The mask pattern overlaps the first active pattern (AP1) in the third direction (D3) but does not overlap the second active pattern (AP2) in the third direction (D3). The mask pattern covers the first lower conductive liner (121) but does not cover the second lower conductive liner (221).

[0216] By using a mask pattern, the second lower conductive liner (221) can be removed.

[0217] Next, the mask pattern can be removed.

[0218] Referring to FIGS. 43 and 44, an upper gate conductive film (122p) and a pre-gate filling film (123p) may be formed on the first lower conductive liner (121) and the gate shield insulating pattern (160).

[0219] The upper gate conductive film (122p) may extend along the first lower conductive liner (121) and the second gate insulating film (230). The upper gate conductive film (122p) extends along the sidewall of the gate shield insulating pattern (160). The upper gate conductive film (122p) covers the sidewall of the gate shield insulating pattern (160).

[0220] A pre-gate filling film (123p) can be formed on an upper gate conductive film (122p). The pre-gate filling film (123p) can fill the gate trench (50t).

[0221] Referring to FIGS. 45 and 46, a portion of the free gate filling film (123p) and the upper gate conductive film (122p) can be removed to form a first upper conductive liner (122), a second upper conductive liner (222), a first gate filling film (123), and a second gate filling film (223).

[0222] Next, referring to FIGS. 2 to 4, a first gate capping pattern (145) can be formed on the first gate filling film (123) and the second gate filling film (223).

[0223] The first gate capping pattern (145) can fill the remaining gate trench (50t) after the first connecting gate structure (50) is formed.

[0224] Unlike what is described, the gate shielding insulation pattern (160) may be removed before the first gate capping pattern (145) is removed. In this case, the first gate capping pattern (145) may also fill the space where the gate shielding insulation pattern (160) was removed. When the gate shielding insulation pattern (160) is removed, the gate shielding insulation pattern (160) may comprise silicon oxide or a low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0225] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0226] 100: Substrate 105: Field insulating film BP: Lower pattern NS: Sheet pattern 50, 60, 120, 220: Gate structure 160: Gate shielding insulation pattern

Claims

Claim 1 A semiconductor device comprising: an active pattern extending in a first direction; a gate structure extending in a second direction different from the first direction on the active pattern and including a gate insulating film and a gate filling film; a gate spacer extending in the second direction on a sidewall of the gate structure; a gate shield insulating pattern disposed on a sidewall of the gate spacer, covering an upper surface of the gate insulating film and including an insulating material; and a gate capping pattern covering an upper surface of the gate filling film on the gate structure, wherein the gate structure further comprises a conductive liner disposed between the gate filling film and the gate insulating film, and the conductive liner extending along a bottom surface of the gate shield insulating pattern and a sidewall of the gate shield insulating pattern. Claim 2 A semiconductor device according to claim 1, wherein the conductive liner comprises a lower conductive liner disposed between the gate filling film and the gate insulating film, and the gate shield insulating pattern covers at least a portion of the upper surface of the lower conductive liner. Claim 3 A semiconductor device according to claim 2, wherein the thickness of the gate shield insulating pattern is smaller than the sum of the thickness of the gate insulating film and the thickness of the lower conductive liner. Claim 4 A semiconductor device according to claim 2, wherein the thickness of the gate shield insulating pattern is equal to the sum of the thickness of the gate insulating film and the thickness of the lower conductive liner. Claim 5 In claim 2, the conductive liner further comprises an upper conductive liner disposed between the lower conductive liner and the gate filling film, and a portion of the upper conductive liner extends between the gate filling film and the gate shield insulating pattern. Claim 6 delete Claim 7 delete Claim 8 A semiconductor device according to claim 1, wherein, based on the upper surface of the active pattern, the upper surface of the gate insulating film is lower than the upper surface of the gate filling film. Claim 9 A semiconductor device according to claim 1, wherein the gate capping pattern covers the upper surface of the gate shield insulating pattern. Claim 10 A semiconductor device according to claim 1, wherein the gate shield insulation pattern is not disposed between the gate insulating film and the gate spacer. Claim 11 In claim 1, the active pattern is a semiconductor device including a pin-shaped pattern. Claim 12 A semiconductor device according to claim 11, wherein the active pattern further comprises a sheet pattern spaced apart from the pin-shaped pattern on the pin-shaped pattern. Claim 13 A first gate structure extending in a first direction in a first region of a substrate and comprising a first gate insulating film and a first gate filling film; a second gate structure extending in a second direction in a second region of the substrate and comprising a second gate insulating film and a second gate filling film; a first gate spacer extending in the first direction on a sidewall of the first gate structure; a second gate spacer extending in the second direction on a sidewall of the second gate structure; a gate shield insulating pattern disposed on a sidewall of the first gate spacer, covering the upper surface of the first gate insulating film and comprising an insulating material; and a first gate capping pattern on the first gate structure covering the upper surface of the first gate filling film. A semiconductor device comprising, on the second gate structure, a second gate capping pattern covering the upper surface of the second gate structure, wherein the first gate capping pattern does not contact the first gate insulating film, the second gate capping pattern contacts the second gate insulating film, and the width in a third direction perpendicular to the first direction of the first gate structure is smaller than the width in a fourth direction perpendicular to the second direction of the second gate structure. Claim 14 delete Claim 15 A semiconductor device according to claim 13, wherein the first gate structure further comprises a conductive liner disposed between the first gate filling film and the first gate insulating film, and the gate shield insulating pattern covers at least a portion of the upper surface of the conductive liner. Claim 16 A semiconductor device comprising: an active pattern including a pin-shaped pattern in a first direction and a sheet pattern on the pin-shaped pattern; a gate structure including a gate insulating film and a gate filling film, extending in a second direction different from the first direction on the active pattern; a gate spacer extending in the second direction on a sidewall of the gate structure; a gate shield insulating pattern disposed on a part of the sidewall of the gate spacer, covering the upper surface of the gate insulating film and including an insulating material; and a gate capping pattern on the gate structure covering the upper surface of the gate filling film and non-contacting with the upper surface of the gate insulating film, wherein the gate structure further comprises a conductive liner disposed between the gate filling film and the gate insulating film, the conductive liner extending along the bottom surface of the gate shield insulating pattern and the sidewall of the gate shield insulating pattern, and, with respect to the upper surface of the sheet pattern, the upper surface of the gate insulating film is lower than the upper surface of the gate filling film. Claim 17 In claim 16, the semiconductor device wherein the gate shield insulating pattern covers at least a portion of the upper surface of the conductive liner. Claim 18 delete Claim 19 A semiconductor device comprising: an active pattern extending in a first direction; a gate structure extending in a second direction different from the first direction on the active pattern, and including a gate liner pattern and a gate top pattern, wherein the gate liner pattern includes a gate insulating film and a lower conductive liner, and the gate top pattern includes an upper conductive liner and a gate filling film; a gate spacer extending in the second direction on a sidewall of the gate structure; and a gate capping pattern covering the upper surface of the gate filling film on the gate structure, wherein the upper surface of the gate liner pattern includes an inclined surface, the upper surface of the gate top pattern has a concave shape, the upper surface of the gate liner pattern has a first step, and the upper surface of the gate top pattern has a second step greater than the first step. Claim 20 A method for manufacturing a semiconductor device comprising: forming a gate trench defined by a gate spacer that intersects the active pattern on an active pattern; sequentially forming a free gate insulating film and a lower gate conductive film along the sidewall and bottom surface of the gate trench; forming a sacrificial pattern that fills a portion of the gate trench on the lower gate conductive film; removing the free gate insulating film and the lower gate conductive film that protrude above the upper surface of the sacrificial pattern to form a gate insulating film and a lower conductive liner; forming a gate shield insulating pattern extended along the sidewall of the gate trench on the upper surface of the gate insulating film and the upper surface of the lower conductive liner; after removing the sacrificial pattern, forming a free gate filling film that fills the gate trench on the lower conductive liner and the gate shield insulating pattern; removing a portion of the free gate filling film to form a gate filling film; and forming a gate capping pattern on the gate filling film.

Images