Pixel and display apparatus having the same

Abstract

A pixel includes a light-emitting element, a driving switching element, a first compensation switching element, and a second compensation switching element. The driving switching element applies a driving current to the light-emitting element. The first compensation switching element and the second compensation switching element are disposed between the control electrode and the output electrode of the driving switching element. The first compensation switching element and the second compensation switching element are connected in series with each other. The driving switching element is a P-type transistor. The first compensation switching element is an N-type transistor. The second compensation switching element is a P-type transistor.

Description

Technology Field

[0001] The present invention relates to a pixel and a display device including the same, and more specifically, to a pixel and a display device including the same that reduces power consumption and improves display quality. Background Technology

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver that provides a gate signal to the plurality of gate lines, a data driver that provides a data voltage to the data lines, an emission driver that provides an emission signal to the emission lines, and a driving control unit that controls the gate driver, the data driver, and the emission driver.

[0003] When the image displayed on the display panel is a still image or when the display panel operates in an always-on mode, the driving frequency of the display panel can be reduced to reduce power consumption.

[0004] If the driving frequency of the above display panel is reduced, the display quality of the display panel may deteriorate due to current leakage. In addition, in conventional pixel structures, the charging of the polyimide layer causes the electric field to concentrate in the active region of the driving transistor, thereby changing the device characteristics of the driving transistor. Consequently, there is a problem in which photonic afterimages occur in specific areas of the display panel due to these changes in the device characteristics of the driving transistor. The problem to be solved

[0005] The objective of the present invention is to provide a pixel capable of reducing the power consumption of a display panel and improving display quality.

[0006] Another objective of the present invention is to provide a display device including the pixel. means of solving the problem

[0007] A pixel according to one embodiment for realizing the purpose of the present invention described above includes a light-emitting element, a driving switching element, a first compensation switching element, and a second compensation switching element. The driving switching element applies a driving current to the light-emitting element. The first compensation switching element and the second compensation switching element are disposed between the control electrode and the output electrode of the driving switching element. The first compensation switching element and the second compensation switching element are connected in series with each other. The driving switching element is a P-type transistor. The first compensation switching element is an N-type transistor. The second compensation switching element is a P-type transistor.

[0008] In one embodiment of the present invention, the pixel may further include an initialization switching element that applies an initialization voltage to a connection node between the first compensation switching element and the second compensation switching element.

[0009] In one embodiment of the present invention, the pixel comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fourth node; a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a first power supply voltage is applied, and an output electrode connected to the second node; and a control electrode to which the emission signal is applied, and to the third node It may include a sixth pixel switching element comprising an input electrode connected to and an output electrode connected to the anode electrode of the light-emitting element, a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element, a seventh pixel switching element comprising a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node, and the light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied. The driving switching element may be the first pixel switching element. The first compensation switching element may be the third-1 pixel switching element. The second compensation switching element may be the third-2 pixel switching element.

[0010] In one embodiment of the present invention, the first pixel switching element, the second pixel switching element, the third-2 pixel switching element, the fourth pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element may be P-type transistors. The third-1 pixel switching element may be an N-type transistor.

[0011] In one embodiment of the present invention, during a first interval, the emission signal may have an inactive level, the data initialization gate signal may have an active level, the data writing gate signal may have an inactive level, and the compensation gate signal may have an active level. During a second interval following the first interval, the emission signal may have an inactive level, the data initialization gate signal may have an inactive level, the data writing gate signal may have an active level, and the compensation gate signal may have an active level.

[0012] In one embodiment of the present invention, the active level of the emission signal may be a low level, the active level of the data initialization gate signal may be a low level, the active level of the data writing gate signal may be a low level, and the active level of the compensation gate signal may be a high level.

[0013] In one embodiment of the present invention, the light-emitting element initialization gate signal may have the same phase as the data writing gate signal.

[0014] In one embodiment of the present invention, during a second section continuous with the second section, during a third section, the emission signal may have an inactive level, the data initialization gate signal may have an inactive level, the data writing gate signal may have an inactive level, and the light-emitting element initialization gate signal may have an active level.

[0015] In one embodiment of the present invention, the light-emitting element initialization gate signal may have the same phase as the data initialization gate signal.

[0016] In one embodiment of the present invention, the active region of the driving transistor may be disposed on the same layer as the active region of the second compensation transistor. The active region of the driving transistor may be disposed on a different layer from the active region of the first compensation transistor.

[0017] In one embodiment of the present invention, the pixel may include a first active layer, a first gate insulating layer disposed on the first active layer, a first gate metal layer disposed on the first gate insulating layer, a second gate insulating layer disposed on the first gate metal layer, a second gate metal layer disposed on the second gate insulating layer, a first interlayer insulating layer disposed on the second gate metal layer, a second active layer disposed on the first interlayer insulating layer, a third gate insulating layer disposed on the second active layer, a third gate metal layer disposed on the third gate insulating layer, and a second interlayer insulating layer disposed on the third gate metal layer. The active region of the driving transistor and the active region of the second compensation transistor may be disposed on the first active layer. The active region of the first compensation transistor may be disposed on the second active layer.

[0018] In one embodiment of the present invention, the first gate metal layer and the second gate metal layer may be disposed in a region that overlaps with the active region of the driving transistor.

[0019] In one embodiment of the present invention, the first compensation transistor may include a gate electrode, a drain electrode, a source electrode, and a bottom gate electrode that overlaps with the gate electrode.

[0020] In one embodiment of the present invention, the pixel may include a first active layer, a first gate insulating layer disposed on the first active layer, a first gate metal layer disposed on the first gate insulating layer, a second gate insulating layer disposed on the first gate metal layer, a second gate metal layer disposed on the second gate insulating layer, a first interlayer insulating layer disposed on the second gate metal layer, a second active layer disposed on the first interlayer insulating layer, a third gate insulating layer disposed on the second active layer, a third gate metal layer disposed on the third gate insulating layer, and a second interlayer insulating layer disposed on the third gate metal layer. The gate electrode of the first compensation transistor may be formed on the third gate metal layer, and the bottom gate electrode of the first compensation transistor may be formed on the second gate metal layer.

[0021] In one embodiment of the present invention, the driving transistor may include a first gate electrode, a drain electrode, a source electrode, and a second gate electrode.

[0022] A display device according to one embodiment for realizing the purpose of the present invention described above includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes a pixel. The gate driver provides a gate signal to the pixel. The data driver provides a data voltage to the pixel. The emission driver provides an emission signal to the pixel. The pixel includes a light-emitting element, a driving switching element that applies a driving current to the light-emitting element, and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other. The driving switching element is a P-type transistor. The first compensation switching element is an N-type transistor. The second compensation switching element is a P-type transistor.

[0023] In one embodiment of the present invention, the pixel may further include an initialization switching element that applies an initialization voltage to a connection node between the first compensation switching element and the second compensation switching element.

[0024] In one embodiment of the present invention, the pixel comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fourth node; a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a first power supply voltage is applied, and an output electrode connected to the second node; a control electrode to which the emission signal is applied; and the third It may include a sixth pixel switching element comprising an input electrode connected to a node and an output electrode connected to the anode electrode of the light-emitting element; a control electrode to which a light-emitting element initialization gate signal is applied; a seventh pixel switching element comprising an input electrode to which a second initialization voltage is applied and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied. The driving switching element may be the first pixel switching element. The first compensation switching element may be the third-1 pixel switching element.The above second compensation switching element may be the above third-2 pixel switching element.

[0025] In one embodiment of the present invention, the first pixel switching element, the second pixel switching element, the third-2 pixel switching element, the fourth pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element may be P-type transistors.

[0026] The above 3-1 pixel switching element may be an N-type transistor. Effects of the invention

[0027] According to such a pixel and a display device including the same, when the image displayed on the display panel is a still image or when the display panel operates in an always-on display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0028] By configuring the first compensation switching element above as an N-type transistor, current leakage during low-frequency driving can be prevented, thereby improving the display quality of the display panel in low-frequency driving mode.

[0029] In addition, by configuring the second compensation switching element adjacent to the driving switching element as a P-type transistor, it is possible to prevent the electric field from concentrating in the active region of the driving transistor due to the charging of the polyimide layer. Therefore, it is possible to prevent photonic afterimages from occurring in specific regions of the display panel due to changes in the characteristics of the driving transistor. As a result, the display quality of the display panel can be improved.

[0030] In addition, since the number of N-type transistors can be reduced in a pixel structure that includes both the N-type transistor and the P-type transistor, the resolution characteristics of the pixel can be improved, and high-frequency characteristics can be improved in high-speed driving mode. Furthermore, the yield of the display device can be further improved. Brief explanation of the drawing

[0031] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a circuit diagram showing the pixels of the display panel of Figure 1. Figure 3 is a timing diagram showing input signals applied to the pixels of Figure 2. FIG. 4a is a timing diagram showing signals applied to the pixels of the display panel of FIG. 2 in low-frequency driving mode. FIG. 4b is a timing diagram showing signals applied to the pixels of the display panel of FIG. 2 in normal driving mode. Figure 5a is a circuit diagram showing current leakage when a high-gradation image is displayed on the pixels of Figure 2. Figure 5b is a circuit diagram showing current leakage when a low-gradation image is displayed on the pixels of Figure 2. Figure 6a is a conceptual diagram showing the electric field applied to the driving transistor of the comparative example. Figure 6b is a conceptual diagram showing the electric field applied to the driving transistor of Figure 2. FIG. 7 is a cross-sectional view showing the first pixel switching element, the third-1 pixel switching element, and the third-2 pixel switching element of the pixel of FIG. 2. FIG. 8 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view showing the first pixel switching element, the third-1 pixel switching element, and the third-2 pixel switching element of the pixel of FIG. 8. FIG. 10 is a timing diagram showing input signals applied to a pixel of a display panel of a display device according to one embodiment of the present invention. FIG. 11 is a timing diagram showing input signals applied to a pixel of a display panel of a display device according to one embodiment of the present invention. FIG. 12 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention. Specific details for implementing the invention

[0032] Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

[0033] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0034] Referring to FIG. 1, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0035] The above display panel (100) includes a display portion for displaying an image and a peripheral portion arranged adjacent to the display portion.

[0036] The display panel (100) comprises a plurality of gate lines (GWL, GCL, GIL, GBL), a plurality of data lines (DL), a plurality of emission lines (EL), and a plurality of pixels electrically connected to each of the gate lines (GWL, GCL, GIL, GBL), the data lines (DL), and the emission lines (EL). The gate lines (GWL, GCL, GIL, GBL) extend in a first direction (D1), the data lines (DL) extend in a second direction (D2) that intersects the first direction (D1), and the emission lines (EL) extend in the first direction (D1).

[0037] The drive control unit (200) receives input image data (IMG) and an input control signal (CONT) from an external device. For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal (CONT) may include a master clock signal and a data enable signal. The input control signal (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.

[0038] The above driving control unit (200) generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0039] The above drive control unit (200) generates the first control signal (CONT1) to control the operation of the gate drive unit (300) based on the input control signal (CONT) and outputs it to the gate drive unit (300). The first control signal (CONT1) may include a vertical start signal and a gate clock signal.

[0040] The above drive control unit (200) generates the second control signal (CONT2) to control the operation of the data drive unit (500) based on the input control signal (CONT) and outputs it to the data drive unit (500). The second control signal (CONT2) may include a horizontal start signal and a load signal.

[0041] The above drive control unit (200) generates a data signal (DATA) based on the input image data (IMG). The above drive control unit (200) outputs the data signal (DATA) to the data drive unit (500).

[0042] The above driving control unit (200) generates the third control signal (CONT3) to control the operation of the gamma reference voltage generation unit (400) based on the input control signal (CONT) and outputs it to the gamma reference voltage generation unit (400).

[0043] The above drive control unit (200) generates the fourth control signal (CONT4) to control the operation of the emission drive unit (600) based on the input control signal (CONT) and outputs it to the emission drive unit (600).

[0044] The gate driving unit (300) generates gate signals for driving the gate lines (GWL, GCL, GIL, GBL) in response to the first control signal (CONT1) received from the driving control unit (200). The gate driving unit (300) can output the gate signals to the gate lines (GWL, GCL, GIL, GBL).

[0045] The gamma reference voltage generation unit (400) generates a gamma reference voltage (VGREF) in response to the third control signal (CONT3) received from the driving control unit (200). The gamma reference voltage generation unit (400) provides the gamma reference voltage (VGREF) to the data driving unit (500). The gamma reference voltage (VGREF) has a value corresponding to each data signal (DATA).

[0046] For example, the gamma reference voltage generation unit (400) may be placed within the drive control unit (200) or within the data drive unit (500).

[0047] The data driving unit (500) receives the second control signal (CONT2) and the data signal (DATA) from the driving control unit (200), and receives the gamma reference voltage (VGREF) from the gamma reference voltage generation unit (400). The data driving unit (500) converts the data signal (DATA) into an analog data voltage using the gamma reference voltage (VGREF). The data driving unit (500) outputs the data voltage to the data line (DL).

[0048] The emission driving unit (600) generates emission signals to drive the emission lines (EL) in response to the fourth control signal (CONT4) received from the driving control unit (200). The emission driving unit (600) can output the emission signals to the emission lines (EL).

[0049] In FIG. 1, for convenience of explanation, the gate driving unit (300) is shown as being positioned on the first side of the display panel (100) and the emission driving unit (600) is shown as being positioned on the second side of the display panel (100), but the present invention is not limited thereto. For example, both the gate driving unit (300) and the emission driving unit (600) may be positioned on the first side of the display panel (100). For example, the gate driving unit (300) and the emission driving unit (600) may be formed integrally.

[0050] FIG. 2 is a circuit diagram showing a pixel of the display panel (100) of FIG. 1. FIG. 3 is a timing diagram showing input signals applied to the pixel of FIG. 2.

[0051] Referring to FIGS. 1 to 3, the display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0052] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0053] In this embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin-film transistor. For example, the first type of switching element may be a low-temperature polysilicon (LTPS) thin-film transistor. For example, the second type of switching element may be an oxide thin-film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0054] The pixel may include a light-emitting element (EE), a driving switching element (e.g., T1) that applies a driving current to the light-emitting element (EE), a first compensation switching element (e.g., T3-1) and a second compensation switching element (e.g., T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (e.g., T1) and are connected in series with each other.

[0055] Here, the driving switching element (e.g., T1) may be a P-type transistor, the first compensation switching element (e.g., T3-1) may be an N-type transistor, and the second compensation switching element (e.g., T3-2) may be a P-type transistor.

[0056] The pixel may further include an initialization switching element (e.g., T4) that applies an initialization voltage (e.g., VI1) to a connection node (e.g., N4) between the first compensation switching element (e.g., T3-1) and the second compensation switching element (e.g., T3-2).

[0057] More specifically, the pixel may include first, second, third-1, third-2, fourth, fifth, sixth, and seventh pixel switching elements (T1, T2, T3-1, T3-2, T4, T5, T6, and T7), a storage capacitor (CST), and the light-emitting element (EE).

[0058] The first pixel switching element (T1) includes a control electrode connected to a first node (N1), an input electrode connected to a second node (N2), and an output electrode connected to a third node (N3). The first pixel switching element (T1) may be the driving switching element.

[0059] For example, the first pixel switching element (T1) may be a polysilicon thin-film transistor. The first pixel switching element (T1) may be a P-type thin-film transistor. The control electrode of the first pixel switching element (T1) may be a gate electrode, the input electrode of the first pixel switching element (T1) may be a source electrode, and the output electrode of the first pixel switching element (T1) may be a drain electrode.

[0060] The second pixel switching element (T2) includes a control electrode to which the data write gate signal (GW) is applied, an input electrode to which the data voltage (VDATA) is applied, and an output electrode connected to the second node (N2).

[0061] For example, the second pixel switching element (T2) may be a polysilicon thin-film transistor. The second pixel switching element (T2) may be a P-type thin-film transistor. The control electrode of the second pixel switching element (T2) may be a gate electrode, the input electrode of the second pixel switching element (T2) may be a source electrode, and the output electrode of the second pixel switching element (T2) may be a drain electrode.

[0062] The above 3-1 pixel switching element (T3-1) includes a control electrode to which the compensation gate signal (GC) is applied, an input electrode connected to the first node (N1), and an output electrode connected to the fourth node (N4). The above 3-1 pixel switching element (T3-1) may be the first compensation switching element.

[0063] For example, the third-1 pixel switching element (T3-1) may be an oxide thin-film transistor. The third-1 pixel switching element (T3) may be an N-type thin-film transistor. The control electrode of the third-1 pixel switching element (T3-1) may be a gate electrode, the input electrode of the third pixel switching element (T3-1) may be a source electrode, and the output electrode of the third pixel switching element (T3-1) may be a drain electrode.

[0064] The above third-2 pixel switching element (T3-2) includes a control electrode to which the data write gate signal (GW) is applied, an input electrode connected to the fourth node (N4), and an output electrode connected to the third node (N3). The above third-2 pixel switching element (T3-2) may be the second compensation switching element.

[0065] For example, the third-2 pixel switching element (T3-2) may be an oxide thin-film transistor. The third-2 pixel switching element (T3-2) may be an N-type thin-film transistor. The control electrode of the third-2 pixel switching element (T3-2) may be a gate electrode, the input electrode of the third-2 pixel switching element (T3-2) may be a source electrode, and the output electrode of the third-2 pixel switching element (T3-2) may be a drain electrode.

[0066] The fourth pixel switching element (T4) includes a control electrode to which the data initialization gate signal (GI) is applied, an input electrode to which the initialization voltage (VI1) is applied, and an output electrode connected to the fourth node (N4). The fourth pixel switching element (T3-1) may be the initialization switching element.

[0067] For example, the fourth pixel switching element (T4) may be a polysilicon thin-film transistor. The fourth pixel switching element (T4) may be a P-type thin-film transistor. The control electrode of the fourth pixel switching element (T4) may be a gate electrode, the input electrode of the fourth pixel switching element (T4) may be a source electrode, and the output electrode of the fourth pixel switching element (T4) may be a drain electrode.

[0068] The fifth pixel switching element (T5) includes a control electrode to which the emission signal (EM) is applied, an input electrode to which the first power supply voltage (ELVDD) is applied, and an output electrode connected to the second node (N2).

[0069] For example, the fifth pixel switching element (T5) may be a polysilicon thin-film transistor. The fifth pixel switching element (T5) may be a P-type thin-film transistor. The control electrode of the fifth pixel switching element (T5) may be a gate electrode, the input electrode of the fifth pixel switching element (T5) may be a source electrode, and the output electrode of the fifth pixel switching element (T5) may be a drain electrode.

[0070] The sixth pixel switching element (T6) includes a control electrode to which the emission signal (EM) is applied, an input electrode connected to the third node (N3), and an output electrode connected to the anode electrode of the light-emitting element (EE).

[0071] For example, the sixth pixel switching element (T6) may be a polysilicon thin-film transistor. The sixth pixel switching element (T6) may be a P-type thin-film transistor. The control electrode of the sixth pixel switching element (T6) may be a gate electrode, the input electrode of the sixth pixel switching element (T6) may be a source electrode, and the output electrode of the sixth pixel switching element (T6) may be a drain electrode.

[0072] The seventh pixel switching element (T7) includes a control electrode to which the light-emitting element initialization gate signal (GB) is applied, an input electrode to which a second initialization voltage (VI2) is applied, and an output electrode connected to the anode electrode of the organic light-emitting element. In this embodiment, the case in which the second initialization voltage (VI2) is applied to the input electrode of the seventh pixel switching element (T7) is exemplified, but the present invention is not limited thereto. Depending on the embodiment, the initialization voltage (VI1) may be applied to the input electrode of the seventh pixel switching element (T7).

[0073] For example, the seventh pixel switching element (T7) may be a polysilicon thin-film transistor. The seventh pixel switching element (T7) may be a P-type thin-film transistor. The control electrode of the seventh pixel switching element (T7) may be a gate electrode, the input electrode of the seventh pixel switching element (T7) may be a source electrode, and the output electrode of the seventh pixel switching element (T7) may be a drain electrode.

[0074] The storage capacitor (CST) includes a first electrode to which the first power supply voltage (ELVDD) is applied and a second electrode connected to the first node (N1).

[0075] The light-emitting element (EE) includes the anode electrode and the cathode electrode to which the second power supply voltage (ELVSS) is applied.

[0076] Referring to FIG. 3, during the first interval (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an active level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an active level.

[0077] During the second section (DU2) following the first section (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an active level, and the compensation gate signal (GC) may have an active level.

[0078] In this embodiment, the light-emitting element initialization gate signal (GB) may have the same phase as the data write gate signal (GW).

[0079] For example, the active level of the emission signal (EM) may be a low level, and the inactive level may be a high level. The active level of the data initialization gate signal (GI) may be a low level, and the inactive level may be a high level. The active level of the data write gate signal (GW) may be a low level, and the inactive level may be a high level. The active level of the light-emitting element initialization gate signal (GB) may be a low level, and the inactive level may be a high level. The active level of the compensation gate signal may be a high level, and the inactive level may be a low level. Since the emission signal (EM), the data initialization gate signal (GI), the data write gate signal (GW), and the light-emitting element initialization gate signal (GB) are control signals for a P-type transistor, they may have a low level active level. On the other hand, since the compensation gate signal (GC) is a control signal for an N-type transistor, it may have a high level active level.

[0080] During the first interval (DU1), the first node (N1) and the storage capacitor (CST) are initialized by the data initialization gate signal (GI) and the compensation gate signal (GC). During the second interval (DU2), the threshold voltage (|VTH|) of the first pixel switching element (T1) is compensated by the data write gate signal (GW) and the compensation gate signal (GC), and the data voltage (VDATA) compensated by the threshold voltage (|VTH|) is written to the first node (N1). During the second interval (DU2), the anode electrode of the light-emitting element (EE) is initialized by the light-emitting element initialization gate signal (GB). During the third interval (DU3), the light-emitting element (EE) emits light by the emission signal (EM), and the display panel (100) displays an image.

[0081] In this embodiment, the off-period of the emission signal (EM) is exemplified as the first and second periods (DU1, DU2), but the present invention is not limited thereto. The off-period of the emission signal (EM) may include the data writing period (DU2), and the off-period of the emission signal (EM) may be longer than the first and second periods (DU1, DU2).

[0082] In the first section (DU1), the data initialization gate signal (GI) and the compensation gate signal (GC) may have an activation level. When the data initialization gate signal (GI) has the activation level, the fourth pixel switching element (T4) is turned on, and when the compensation gate signal (GC) has the activation level, the third-1 pixel switching element (T3-1) is turned on, so that the initialization voltage (VI1) can be applied to the first node (N1).

[0083] In the second section (DU2), the data write gate signal (GW) and the compensation gate signal (GC) may have an active level. When the data write gate signal (GW) and the compensation gate signal (GC) have an active level, the second pixel switching element (T2), the third-1 pixel switching element (T3-1), and the third-2 pixel switching element (T3-2) are turned on. Additionally, the first pixel switching element (T1) is also turned on by the initialization voltage (VI1).

[0084] Along the path formed by the turned-on first, second, third-1 and third-2 pixel switching elements (T1, T2, T3-1, T3-2), a voltage is set at the first node (N1) that is the data voltage (VDATA) minus the threshold voltage (|VTH|) of the first pixel switching element (T1).

[0085] Additionally, in the second section (DU2), the light-emitting element initialization gate signal (GB) may have an activation level. When the light-emitting element initialization gate signal (GB) has the activation level, the seventh pixel switching element (T7) is turned on, and the second initialization voltage (VI2) may be applied to the anode electrode of the light-emitting element (EE).

[0086] In the third section (DU3), the emission signal (EM) may have an activation level. When the emission signal (EM) has the activation level, the fifth pixel switching element (T5) and the sixth pixel switching element (T6) are turned on. Additionally, the first pixel switching element (T1) is also turned on by the data voltage (VDATA).

[0087] The driving current can drive the light-emitting element (EE) by flowing in the order of the fifth pixel switching element (T5), the first pixel switching element (T1), and the sixth pixel switching element (T6). The intensity of the driving current can be determined by the level of the data voltage (VDATA). The brightness of the light-emitting element (EE) can be determined by the intensity of the driving current. The driving current (ISD) flowing along the path formed from the input electrode to the output electrode of the first pixel switching element (T1) can be expressed as shown in Equation 1 below.

[0088] [Formula 1]

[0089]

[0090] In Equation 1, u is the mobility of the first pixel switching element (T1), Cox is the capacitance per unit area of ​​the first pixel switching element (T1), W / L represents the ratio of the width to the length of the first pixel switching element (T1), VSG represents the voltage between the input electrode (N2) and the control electrode (N1) of the first pixel switching element (T1), and |VTH| represents the threshold voltage of the first pixel switching element (T1).

[0091] The voltage (VG) of the first node (N1), in which the threshold voltage (|VTH|) is compensated in the second section (DU2), can be expressed as Equation 2.

[0092] [Equation 2]

[0093]

[0094] When the light-emitting element (EE) emits light in the third section (DU3), the driving voltage (VOV) and the driving current (ISD) can be expressed by the following Equations 3 and 4. In Equation 3, VS is the voltage of the second node (N2).

[0095] [Equation 3]

[0096]

[0097] [Equation 4]

[0098]

[0099] Since the threshold voltage (|VTH|) is compensated in the second section (DU2), when the light-emitting element (EE) emits light in the third section (DU3), the driving current (ISD) can be determined independently of the threshold voltage (|VTH|) component of the first pixel switching element (T1).

[0100] In this embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in an always-on mode, the driving frequency of the display panel (100) may be reduced to reduce power consumption. If all of the switching elements of the display panel (100) are polysilicon, flicker may occur due to leakage current of the switching elements in a low-frequency driving mode. Therefore, some of the switching elements of the pixels may be composed of oxide thin-film transistors. In this embodiment, the third-1 pixel switching element (T3-1) may be the oxide thin-film transistor. The first pixel switching element (T1), the second pixel switching element (T2), the third-2 pixel switching element (T3-2), the fourth pixel switching element (T4), the fifth pixel switching element (T5), the sixth pixel switching element (T6), and the seventh pixel switching element (T7) may be polysilicon thin-film transistors.

[0101] FIG. 4a is a timing diagram showing signals applied to pixels of the display panel (100) of FIG. 2 in low-frequency driving mode. FIG. 4b is a timing diagram showing signals applied to pixels of the display panel (100) of FIG. 2 in normal driving mode.

[0102] Referring to FIGS. 1 to 4b, the display panel (100) can be driven in a first mode and a second mode. In the first mode, the display panel driver drives the pixel switching elements of the display panel (100) at a low-frequency driving frequency, and in the second mode, the display panel driver drives the pixel switching elements of the display panel (100) at a high-frequency driving frequency. The first mode may be a low-frequency driving mode, and the second mode may be a general driving mode.

[0103] For example, in the first mode, all pixel switching elements may be driven at a low-frequency driving frequency. Alternatively, in the first mode, some pixel switching elements may be driven at a low-frequency driving frequency.

[0104] The above display panel driving unit (e.g., driving control unit (200)) can analyze the input image. The above display panel driving unit can determine whether the input image is a video or a still image.

[0105] When the input image is a video, the display panel (100) can be driven in the general driving mode. When the input image is a still image, the display panel (100) can be driven in the low-frequency driving mode. Additionally, when the display panel operates in the always-on mode, the display panel (100) can be driven in the low-frequency driving mode.

[0106] FIG. 4a shows the signals of the low-frequency driving mode. In the low-frequency driving mode, the emission signal (EM), the data initialization gate signal (GI), the data writing gate signal (GW), the light-emitting element initialization gate signal (GB), and the compensation gate signal (GC) can all be driven at a low-frequency driving frequency.

[0107] For example, in FIG. 4a, the high-frequency driving frequency may be 60 Hz and the low-frequency driving frequency may be 1 Hz. In this case, in the low-frequency driving mode, a write operation (WRITE) may be performed in only one frame per second, and a hold operation (HOLD) may be performed in the remaining 59 frames.

[0108] For example, if the low-frequency driving frequency is 10Hz, in the low-frequency driving mode, write operations (WRITE) can be performed on only 10 frames per second, and hold operations (HOLD) can be performed on the remaining 50 frames.

[0109] For example, if the low-frequency driving frequency is 30Hz, in the low-frequency driving mode, write operations (WRITE) can be performed only on 30 frames per second, and hold operations (HOLD) can be performed on the remaining 30 frames.

[0110] FIG. 4b shows the signals of the general driving mode. In the general driving mode, the emission signal (EM), the data initialization gate signal (GI), the data writing gate signal (GW), the light-emitting element initialization gate signal (GB), and the compensation gate signal (GC) can all be driven at a high-frequency driving frequency.

[0111] For example, in FIG. 4b, the high-frequency driving frequency may be 60 Hz. In the general driving mode, a write operation (WRITE) can be performed in every frame.

[0112] FIG. 5a is a circuit diagram showing current leakage when a high-gradation image is displayed on the pixel of FIG. 2. FIG. 5b is a circuit diagram showing current leakage when a low-gradation image is displayed on the pixel of FIG. 2.

[0113] Referring to FIGS. 1 to 5b, the pixel is disposed between the control electrode and the output electrode of the driving switching element (T1) and includes the first compensation switching element (T3-1) and the second compensation switching element (T3-2) connected in series with each other. The first compensation switching element (T3-1) may be an N-type transistor, and the second compensation switching element (T3-2) may be a P-type transistor.

[0114] FIG. 5a illustrates a case where a high-gradation image is displayed on a pixel. When a high-gradation image is displayed on the pixel, the gate voltage of the driving transistor (T1) is relatively low, so the current path is formed from the output electrode of the driving transistor (T1) toward the control electrode of the driving transistor (T1). Since the second compensation switching element (T3-2) is a P-type transistor, the current leakage is large, but since the first compensation switching element (T3-1) is an N-type transistor, the current leakage is small. Since the current leakage in the first compensation switching element (T3-1) is small, the level of the gate voltage of the driving transistor (T1) hardly decreases. Therefore, even if the pixel is driven at a low-frequency driving frequency, the current leakage is prevented, and the display quality of the display panel (100) can be prevented from deteriorating.

[0115] FIG. 5b illustrates a case where a low-gradation image is displayed on a pixel. When a low-gradation image is displayed on the pixel, the gate voltage of the driving transistor (T1) is relatively high, so the current path is formed from the control electrode of the driving transistor (T1) toward the output electrode of the driving transistor (T1). Since the second compensation switching element (T3-2) is a P-type transistor, the current leakage is large, but since the first compensation switching element (T3-1) is an N-type transistor, the current leakage is small. Since the current leakage is small in the first compensation switching element (T3-1), the level of the gate voltage of the driving transistor (T1) is hardly reduced in this case as well. Therefore, even if the pixel is driven at a low-frequency driving frequency, the current leakage is prevented, and the display quality of the display panel (100) can be prevented from deteriorating.

[0116] FIG. 6a is a conceptual diagram showing the electric field applied to the driving transistor of the comparative example. FIG. 6b is a conceptual diagram showing the electric field applied to the driving transistor of FIG. 2.

[0117] FIG. 6a illustrates a case where a compensation transistor placed adjacent to the output electrode of the driving transistor (T1) is formed as an N-type transistor. Here, the compensation transistor can receive a compensation gate signal (GC).

[0118] The pixel (P) of the above display panel (100) has a much longer luminous section compared to the non-luminous section.

[0119] In the case of FIG. 6a, the emission signal (EM) has an active level (ON, e.g. -8V) during the light-emitting period of the pixel (P), and the compensation gate signal (GC) has an inactive level (OFF, e.g. -8V). Since the compensation transistor is an N-type transistor, the inactive level of the compensation gate signal (GC) may be a low level (e.g. -8V).

[0120] An electric field is formed in the polyimide layer (PI) by the emission signal (EM) and the compensation gate signal (GC) in the light-emitting portion of the pixel (P), and the electric field is formed in the driving transistor (T1) through the buffer layer (BF) as shown in FIG. 6a. In FIG. 6a, since the electric field is concentrated in the driving transistor (T1), the device characteristics of the driving transistor (T1) may change due to the electric field. In addition, a problem may occur in which a photonic afterimage occurs in a specific area of ​​the display panel (100) due to the change in the device characteristics of the driving transistor (T1).

[0121] FIG. 6b illustrates a case where a second compensation transistor (T3-2) positioned adjacent to the output electrode of the driving transistor (T1) is formed as a P-type transistor. Here, as shown in FIG. 2, the second compensation transistor (T3-2) can receive a data write gate signal (GW).

[0122] In the case of FIG. 6b, the emission signal (EM) has an active level (ON, e.g. -8V) during the light-emitting period of the pixel (P), and the data write gate signal (GW) has an inactive level (OFF, e.g. +8V). Since the second compensation transistor is a P-type transistor, the inactive level of the data write gate signal (GW) may be a high level (e.g. +8V).

[0123] An electric field is formed in the polyimide layer (PI) by the emission signal (EM) and the data writing gate signal (GW) in the light-emitting portion of the pixel (P), and the electric field is formed in the driving transistor (T1) through the buffer layer (BF) as shown in FIG. 6b. In FIG. 6b, since the electric field is not concentrated in the driving transistor (T1), it is possible to prevent the device characteristics of the driving transistor (T1) from changing due to the electric field. In addition, since the change in the device characteristics of the driving transistor (T1) is prevented, it is also possible to prevent photonic afterimages from occurring in a specific area of ​​the display panel (100).

[0124] FIG. 7 is a cross-sectional view showing the first pixel switching element (T1), the third-1 pixel switching element (T3-1), and the third-2 pixel switching element (T3-2) of the pixel of FIG. 2.

[0125] Referring to FIGS. 1 to 7, the pixel may include a first active layer (AC1), a first gate insulating layer (GI1) disposed on the first active layer (AC1), a first gate metal layer (GATE1) disposed on the first gate insulating layer (GI1), a second gate insulating layer (GI2) disposed on the first gate metal layer (GATE1), a second gate metal layer (GATE2) disposed on the second gate insulating layer (GI2), a first interlayer insulating layer (ILD1) disposed on the second gate metal layer (GATE2), a second active layer (AC2) disposed on the first interlayer insulating layer (ILD1), a third gate insulating layer (GI3) disposed on the second active layer (AC2), a third gate metal layer (GATE3) disposed on the third gate insulating layer (GI3), and a second interlayer insulating layer (ILD2) disposed on the third gate metal layer (GATE3). A first source-drain metal layer (SD1) may be formed on the second interlayer insulating layer (ILD2). The first source-drain metal layer (SD1) may contact the doping layer (P+) of the first active layer (AC1) through a contact hole. Additionally, the first source-drain metal layer (SD1) may contact the doping layer of the second active layer (AC2) through a contact hole.

[0126] The active region (CH1) of the driving transistor (T1) may be placed on the same layer as the active region (CH3-2) of the second compensation transistor (T3-2). The active region (CH1) of the driving transistor (T1) may be placed on a different layer from the active region (CH3-1) of the first compensation transistor (T3-1).

[0127] In this embodiment, the active region (CH1) of the driving transistor (T1) and the active region (CH3-2) of the second compensation transistor (T3-2) may be placed in the first active layer (AC1). The active region (CH3-1) of the first compensation transistor (T3-1) may be placed in the second active layer (AC2).

[0128] The first gate metal layer (GATE1) and the second gate metal layer (GATE2) may be overlapped and disposed in an area overlapping with the active region (CH1) of the driving transistor (T1), and the first gate metal layer (GATE1) and the second gate metal layer (GATE2) overlapped and disposed in an area overlapping with the active region (CH1) may form the storage capacitor (CST).

[0129] The pixel may further include a buffer layer (BF2, BF1) disposed below the first active layer (AC1). According to an embodiment, the buffer layer (BF2, BF1) may be omitted or may include two or more different layers. The pixel may further include a substrate (BR) disposed below the buffer layer (BF2, BF1). For example, the substrate (BR) may include a polyimide layer and a barrier layer.

[0130] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0131] The first compensation switching element (T3-1) above is configured as an N-type transistor to prevent current leakage during low-frequency driving, thereby improving the display quality of the display panel (100) in low-frequency driving mode.

[0132] In addition, by configuring the second compensation switching element (T3-2) adjacent to the driving switching element (T1) as a P-type transistor, it is possible to prevent the electric field from concentrating in the active region of the driving transistor (T1) due to the charging of the polyimide layer (PI). Therefore, it is possible to prevent photonic afterimages from occurring in a specific region of the display panel (100) due to changes in the characteristics of the driving transistor (T1). As a result, the display quality of the display panel (100) can be improved.

[0133] In addition, since the number of N-type transistors can be reduced in a pixel structure that includes both the N-type transistor and the P-type transistor, the resolution characteristics of the pixel can be improved, and high-frequency characteristics can be improved in high-speed driving mode. Furthermore, the yield of the display device can be further improved.

[0134] FIG. 8 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention. FIG. 9 is a cross-sectional view showing a first pixel switching element, a third-1 pixel switching element, and a third-2 pixel switching element of the pixel of FIG. 8.

[0135] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 7 except for the structure of the pixels, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0136] Referring to FIGS. 1, FIGS. 3 to 6b, FIGS. 8, and FIGS. 9, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0137] The above display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0138] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0139] The pixel may include a light-emitting element (EE), a driving switching element (e.g., T1) that applies a driving current to the light-emitting element (EE), a first compensation switching element (e.g., T3-1) and a second compensation switching element (e.g., T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (e.g., T1) and are connected in series with each other.

[0140] Here, the driving switching element (e.g., T1) may be a P-type transistor, the first compensation switching element (e.g., T3-1) may be an N-type transistor, and the second compensation switching element (e.g., T3-2) may be a P-type transistor.

[0141] In this embodiment, the first compensation transistor (T3-1) includes a gate electrode, a drain electrode, a source electrode, and a bottom gate electrode that overlaps with the gate electrode. The compensation gate signal (GC) can be applied in common to the gate electrode and the bottom gate electrode.

[0142] Since the first compensation transistor (T3-1) further includes the bottom gate electrode (BML), the device characteristics and reliability of the first compensation transistor (T3-1) can be further improved. For example, since the first compensation transistor (T3-1) further includes the bottom gate electrode (BML), device degradation caused by a shift in the threshold voltage of the first compensation transistor (T3-1) can be prevented.

[0143] The pixel may include a first active layer (AC1), a first gate insulating layer (GI1) disposed on the first active layer (AC1), a first gate metal layer (GATE1) disposed on the first gate insulating layer (GI1), a second gate insulating layer (GI2) disposed on the first gate metal layer (GATE1), a second gate metal layer (GATE2) disposed on the second gate insulating layer (GI2), a first interlayer insulating layer (ILD1) disposed on the second gate metal layer (GATE2), a second active layer (AC2) disposed on the first interlayer insulating layer (ILD1), a third gate insulating layer (GI3) disposed on the second active layer (AC2), a third gate metal layer (GATE3) disposed on the third gate insulating layer (GI3), and a second interlayer insulating layer (ILD2) disposed on the third gate metal layer (GATE3).

[0144] The active region (CH1) of the driving transistor (T1) may be placed on the same layer as the active region (CH3-2) of the second compensation transistor (T3-2). The active region (CH1) of the driving transistor (T1) may be placed on a different layer from the active region (CH3-1) of the first compensation transistor (T3-1).

[0145] In this embodiment, the gate electrode of the first compensation transistor (T3-1) is formed on the third gate metal layer (GATE3), and the bottom gate electrode (BML) of the first compensation transistor (T3-1) can be formed on the second gate metal layer (GATE2).

[0146] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0147] The first compensation switching element (T3-1) above is configured as an N-type transistor to prevent current leakage during low-frequency driving, thereby improving the display quality of the display panel (100) in low-frequency driving mode.

[0148] In addition, by configuring the second compensation switching element (T3-2) adjacent to the driving switching element (T1) as a P-type transistor, it is possible to prevent the electric field from concentrating in the active region of the driving transistor (T1) due to the charging of the polyimide layer (PI). Therefore, it is possible to prevent photonic afterimages from occurring in a specific region of the display panel (100) due to changes in the characteristics of the driving transistor (T1). As a result, the display quality of the display panel (100) can be improved.

[0149] In addition, since the number of N-type transistors can be reduced in a pixel structure that includes both the N-type transistor and the P-type transistor, the resolution characteristics of the pixel can be improved, and high-frequency characteristics can be improved in high-speed driving mode. Furthermore, the yield of the display device can be further improved.

[0150] FIG. 10 is a timing diagram showing input signals applied to a pixel of a display panel of a display device according to one embodiment of the present invention.

[0151] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 7 except for the input signal applied to the pixel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0152] Referring to FIGS. 1, FIGS. 2, FIGS. 5a to 6b and FIG. 10, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0153] The above display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0154] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0155] The pixel may include a light-emitting element (EE), a driving switching element (e.g., T1) that applies a driving current to the light-emitting element (EE), a first compensation switching element (e.g., T3-1) and a second compensation switching element (e.g., T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (e.g., T1) and are connected in series with each other.

[0156] Referring to FIG. 10, during the first interval (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an active level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an active level.

[0157] During the second section (DU2) following the first section (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an active level, and the compensation gate signal (GC) may have an active level.

[0158] In this embodiment, during the third section (DU3) following the second section (DU2), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data writing gate signal (GW) may have an inactive level, and the light-emitting element initialization gate signal (GB) may have an active level.

[0159] For example, the active level of the emission signal (EM) may be a low level, and the inactive level may be a high level. The active level of the data initialization gate signal (GI) may be a low level, and the inactive level may be a high level. The active level of the data write gate signal (GW) may be a low level, and the inactive level may be a high level. The active level of the light-emitting element initialization gate signal (GB) may be a low level, and the inactive level may be a high level. The active level of the compensation gate signal may be a high level, and the inactive level may be a low level. Since the emission signal (EM), the data initialization gate signal (GI), the data write gate signal (GW), and the light-emitting element initialization gate signal (GB) are control signals for a P-type transistor, they may have a low level active level. On the other hand, since the compensation gate signal (GC) is a control signal for an N-type transistor, it may have a high level active level.

[0160] During the first interval (DU1), the first node (N1) and the storage capacitor (CST) are initialized by the data initialization gate signal (GI) and the compensation gate signal (GC). During the second interval (DU2), the threshold voltage (|VTH|) of the first pixel switching element (T1) is compensated by the data write gate signal (GW) and the compensation gate signal (GC), and the data voltage (VDATA) compensated by the threshold voltage (|VTH|) is written to the first node (N1). During the third interval (DU3), the anode electrode of the light-emitting element (EE) is initialized by the light-emitting element initialization gate signal (GB). During the fourth interval (DU4), the light-emitting element (EE) emits light by the emission signal (EM), and the display panel (100) displays an image.

[0161] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0162] The first compensation switching element (T3-1) above is configured as an N-type transistor to prevent current leakage during low-frequency driving, thereby improving the display quality of the display panel (100) in low-frequency driving mode.

[0163] In addition, by configuring the second compensation switching element (T3-2) adjacent to the driving switching element (T1) as a P-type transistor, it is possible to prevent the electric field from concentrating in the active region of the driving transistor (T1) due to the charging of the polyimide layer (PI). Therefore, it is possible to prevent photonic afterimages from occurring in a specific region of the display panel (100) due to changes in the characteristics of the driving transistor (T1). As a result, the display quality of the display panel (100) can be improved.

[0164] FIG. 11 is a timing diagram showing input signals applied to a pixel of a display panel of a display device according to one embodiment of the present invention.

[0165] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 7 except for the input signal applied to the pixel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0166] Referring to FIGS. 1, FIGS. 2, FIGS. 5a to 6b and FIG. 11, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0167] The above display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0168] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0169] The pixel may include a light-emitting element (EE), a driving switching element (e.g., T1) that applies a driving current to the light-emitting element (EE), a first compensation switching element (e.g., T3-1) and a second compensation switching element (e.g., T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (e.g., T1) and are connected in series with each other.

[0170] Referring to FIG. 11, during the first interval (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an active level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an active level.

[0171] During the second section (DU2) following the first section (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an active level, and the compensation gate signal (GC) may have an active level.

[0172] In this embodiment, the light-emitting element initialization gate signal (GB) may have the same phase as the data initialization gate signal (GI).

[0173] During the first interval (DU1), the first node (N1) and the storage capacitor (CST) are initialized by the data initialization gate signal (GI) and the compensation gate signal (GC). During the first interval (DU1), the anode electrode of the light-emitting element (EE) is initialized by the light-emitting element initialization gate signal (GB). During the second interval (DU2), the threshold voltage (|VTH|) of the first pixel switching element (T1) is compensated by the data write gate signal (GW) and the compensation gate signal (GC), and the data voltage (VDATA) compensated by the threshold voltage (|VTH|) is written to the first node (N1). During the third interval (DU3), the light-emitting element (EE) emits light by the emission signal (EM), and the display panel (100) displays an image.

[0174] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0175] The first compensation switching element (T3-1) above is configured as an N-type transistor to prevent current leakage during low-frequency driving, thereby improving the display quality of the display panel (100) in low-frequency driving mode.

[0176] In addition, by configuring the second compensation switching element (T3-2) adjacent to the driving switching element (T1) as a P-type transistor, it is possible to prevent the electric field from concentrating in the active region of the driving transistor (T1) due to the charging of the polyimide layer (PI). Therefore, it is possible to prevent photonic afterimages from occurring in a specific region of the display panel (100) due to changes in the characteristics of the driving transistor (T1). As a result, the display quality of the display panel (100) can be improved.

[0177] FIG. 12 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention.

[0178] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 7 except for the structure of the pixels, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0179] Referring to FIGS. 1, FIGS. 3 to 6b and FIG. 12, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0180] The above display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0181] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0182] The pixel may include a light-emitting element (EE), a driving switching element (e.g., T1) that applies a driving current to the light-emitting element (EE), a first compensation switching element (e.g., T3-1) and a second compensation switching element (e.g., T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (e.g., T1) and are connected in series with each other.

[0183] Here, the driving switching element (e.g., T1) may be a P-type transistor, the first compensation switching element (e.g., T3-1) may be an N-type transistor, and the second compensation switching element (e.g., T3-2) may be a P-type transistor.

[0184] In this embodiment, the driving transistor (T1) may include a first gate electrode, a drain electrode, a source electrode, and a second gate electrode. The first gate electrode and the second gate electrode may be commonly connected to the first node (N1).

[0185] When the driving transistor (T1) includes the first gate electrode and the second gate electrode, the afterimage phenomenon can be further prevented.

[0186] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0187] The first compensation switching element (T3-1) above is configured as an N-type transistor to prevent current leakage during low-frequency driving, thereby improving the display quality of the display panel (100) in low-frequency driving mode.

[0188] In addition, by configuring the second compensation switching element (T3-2) adjacent to the driving switching element (T1) as a P-type transistor, it is possible to prevent the electric field from concentrating in the active region of the driving transistor (T1) due to the charging of the polyimide layer (PI). Therefore, it is possible to prevent photonic afterimages from occurring in a specific region of the display panel (100) due to changes in the characteristics of the driving transistor (T1). As a result, the display quality of the display panel (100) can be improved.

[0189] In addition, since the number of N-type transistors can be reduced in a pixel structure that includes both the N-type transistor and the P-type transistor, the resolution characteristics of the pixel can be improved, and high-frequency characteristics can be improved in high-speed driving mode. Furthermore, the yield of the display device can be further improved. Industrial applicability

[0190] According to the display device of the present invention described above, the display quality of the display panel can be improved while reducing the power consumption of the display device.

[0191] Although the invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0192] 100: Display panel 200: Drive control unit 300: Gate driver 400: Gamma reference voltage generator 500: Data driver 600: Emission driver

Claims

Claim 1 A pixel comprising: a light-emitting element; a driving switching element that applies a driving current to the light-emitting element; a first compensation switching element and a second compensation switching element disposed between the control electrode and the output electrode of the driving switching element and connected in series with each other, wherein the second compensation switching element is directly connected to the driving switching element, wherein the driving switching element is a P-type transistor, the first compensation switching element is an N-type transistor, and the second compensation switching element is a P-type transistor, wherein the active region of the driving switching element is disposed on the same layer as the active region of the second compensation switching element, and the active region of the driving switching element is disposed on a different layer from the active region of the first compensation switching element. Claim 2 A pixel according to claim 1, further comprising an initialization switching element that applies an initialization voltage to a connection node between the first compensation switching element and the second compensation switching element. Claim 3 In claim 1, the pixel comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fourth node; a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a first power supply voltage is applied, and an output electrode connected to the second node; and a control electrode to which the emission signal is applied, and connected to the third node A pixel comprising: a sixth pixel switching element including an input electrode and an output electrode connected to the anode electrode of the light-emitting element; a seventh pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element including the anode electrode and a cathode electrode to which the second power supply voltage is applied, wherein the driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element is the third-2 pixel switching element. Claim 4 A pixel according to claim 3, wherein the first pixel switching element, the second pixel switching element, the third-2 pixel switching element, the fourth pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element are P-type transistors, and the third-1 pixel switching element is an N-type transistor. Claim 5 A pixel according to claim 3, wherein the first pixel switching element, the second pixel switching element, the third-2 pixel switching element, the fourth pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element are polysilicon transistors, and the third-1 pixel switching element is an oxide transistor. Claim 6 A pixel according to claim 3, wherein during a first interval, the emission signal has an inactive level, the data initialization gate signal has an active level, the data write gate signal has an inactive level, and the compensation gate signal has an active level, and during a second interval continuous with the first interval, the emission signal has an inactive level, the data initialization gate signal has an inactive level, the data write gate signal has an active level, and the compensation gate signal has an active level. Claim 7 A pixel according to claim 6, characterized in that the active level of the emission signal is a low level, the active level of the data initialization gate signal is a low level, the active level of the data write gate signal is a low level, and the active level of the compensation gate signal is a high level. Claim 8 A pixel according to claim 6, characterized in that the light-emitting element initialization gate signal has the same phase as the data write gate signal. Claim 9 A pixel according to claim 6, characterized in that during a third section consecutive to the second section, the emission signal has an inactive level, the data initialization gate signal has an inactive level, the data writing gate signal has an inactive level, and the light-emitting element initialization gate signal has an active level. Claim 10 A pixel according to claim 6, characterized in that the light-emitting element initialization gate signal has the same phase as the data initialization gate signal. Claim 11 delete Claim 12 In claim 1, the pixel comprises: a first active layer; a first gate insulating layer disposed on the first active layer; a first gate metal layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate metal layer; a second gate metal layer disposed on the second gate insulating layer; a first interlayer insulating layer disposed on the second gate metal layer; a second active layer disposed on the first interlayer insulating layer; a third gate insulating layer disposed on the second active layer; a third gate metal layer disposed on the third gate insulating layer; and a second interlayer insulating layer disposed on the third gate metal layer, wherein the active region of the driving switching element and the active region of the second compensation switching element are disposed on the first active layer, and the active region of the first compensation switching element is disposed on the second active layer. Claim 13 A pixel according to claim 12, characterized in that the first gate metal layer and the second gate metal layer are disposed in an area overlapping with the active area of ​​the driving switching element. Claim 14 A pixel according to claim 1, wherein the first compensation switching element comprises a gate electrode, a drain electrode, a source electrode, and a bottom gate electrode that overlaps with the gate electrode. Claim 15 A light-emitting element; a driving switching element that applies a driving current to the light-emitting element; a first compensation switching element and a second compensation switching element disposed between the control electrode and the output electrode of the driving switching element and connected in series with each other, comprising a first active layer; a first gate insulating layer disposed on the first active layer; a first gate metal layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate metal layer; a second gate metal layer disposed on the second gate insulating layer; a first interlayer insulating layer disposed on the second gate metal layer; a second active layer disposed on the first interlayer insulating layer; a third gate insulating layer disposed on the second active layer; and a third gate metal layer disposed on the third gate insulating layer. A pixel comprising a second interlayer insulating layer disposed on the third gate metal layer, wherein the driving switching element is a P-type transistor, the first compensation switching element is an N-type transistor, the second compensation switching element is a P-type transistor, the first compensation switching element includes a gate electrode, a drain electrode, a source electrode, and a bottom gate electrode that overlaps with the gate electrode, wherein the gate electrode of the first compensation switching element is formed on the third gate metal layer and the bottom gate electrode of the first compensation switching element is formed on the second gate metal layer, wherein a first portion of the first gate metal layer and a first portion of the second gate metal layer are disposed overlappingly in an area that overlaps with the active region of the driving switching element, and a second portion of the first gate metal layer is disposed in an area that overlaps with the active region of the second compensation switching element. Claim 16 A pixel according to claim 1, wherein the driving switching element comprises a first gate electrode, a drain electrode, a source electrode, and a second gate electrode. Claim 17 A display device comprising: a display panel including a pixel; a gate driver providing a gate signal to the pixel; a data driver providing a data voltage to the pixel; and an emission driver providing an emission signal to the pixel, wherein the pixel includes a light-emitting element; a driving switching element applying a driving current to the light-emitting element; and a first compensation switching element and a second compensation switching element disposed between a control electrode and an output electrode of the driving switching element and connected in series with each other, wherein the second compensation switching element is directly connected to the driving switching element, wherein the driving switching element is a P-type transistor, the first compensation switching element is an N-type transistor, and the second compensation switching element is a P-type transistor, wherein the active region of the driving switching element is disposed on the same layer as the active region of the second compensation switching element, and the active region of the driving switching element is disposed on a different layer from the active region of the first compensation switching element. Claim 18 A display device according to claim 17, wherein the pixel further comprises an initialization switching element that applies an initialization voltage to a connection node between the first compensation switching element and the second compensation switching element. Claim 19 In claim 17, the pixel comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fourth node; a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a first power supply voltage is applied, and an output electrode connected to the second node; and a control electrode to which the emission signal is applied, and A display device comprising: a sixth pixel switching element including an input electrode connected to a third node and an output electrode connected to an anode electrode of the light-emitting element; a seventh pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element including the anode electrode and a cathode electrode to which the second power supply voltage is applied, wherein the driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element is the third-2 pixel switching element. Claim 20 A display device according to claim 19, wherein the first pixel switching element, the second pixel switching element, the third-2 pixel switching element, the fourth pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element are P-type transistors, and the third-1 pixel switching element is an N-type transistor.

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