Structures with doped semiconductor layers and methods and systems for forming same

Abstract

A method and system for depositing a material such as a doped semiconductor material are disclosed. An exemplary method comprises the steps of: providing a substrate; forming a first doped semiconductor layer disposed on the substrate; and forming a second doped semiconductor layer disposed on the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and the second doped semiconductor layer comprises the first dopant. A structure and an element formed using the present method, and a system for carrying out the present method are also disclosed.

Description

Technology Field

[0001] The present disclosure relates to a method and system suitable for forming an electronic device structure in general. More specifically, the present disclosure relates to a method and system that can be used to form a structure including a doped semiconductor layer. Background Technology

[0002] For example, the scaling of semiconductor devices, such as complementary metal-oxide semiconductor (CMOS) devices, has led to significant improvements in the speed and density of integrated circuits. However, conventional device scaling technologies face major challenges at the future technological crossroads.

[0003] One approach to improving semiconductor device performance is to enhance carrier mobility by utilizing strain-induced effects, which in turn improves the transistor driving current. For example, it has been shown that hole mobility can be significantly improved in p-channel group IV semiconductor transistors using stressor sites, such as those used in the source and drain regions of the transistor.

[0004] Furthermore, a reduction in contact resistance for active sites of a semiconductor device structure may be desirable when continuously improving the device at future technological crossroads. For example, in the case of a CMOS device structure, the contact resistance may include the electrical resistance between one or more active (e.g., stressor) sites, such as the source and drain sites of a transistor structure, and the contact structure. In the case of an n-type MOS device, the stressor site is a significantly doped site, namely, approximately 5 x 10⁻⁶ doped with phosphorus or arsenic. 20 cm -3It may include a region having a carrier density. High doping levels achievable in the stressor region of an n-type MOS device can lower the contact resistivity to less than 0.3 mΩ-cm. However, for p-type MOS devices, boron is used as a typical dopant. In some cases, boron may have relatively low solubility in semiconductor materials, and consequently, it may be difficult to obtain a high concentration of p-type dopant and consequently low contact resistance for the semiconductor material.

[0005] For example, attempts to lower the contact resistance of silicon germanium films involve growing a SiGe layer with a high boron concentration. However, high boron concentrations are difficult to achieve as the Ge:Si ratio increases, due to the low boron solubility in germanium; therefore, attempts to simply increase the boron concentration of the silicon germanium film have generally not been sufficient to reduce the contact resistivity of the silicon germanium layer to the desired value.

[0006] Further attempts to reduce contact resistance for silicon germanium and similar films include the addition of other dopants (where a first dopant (e.g., boron) may be dissolved) and high-temperature annealing processes. These techniques can be problematic because using relatively high temperatures during the annealing process can cause one or more of the dopants to cluster on the surface of the doped semiconductor film.

[0007] In addition, in some applications, it may be desirable to selectively deposit semiconductor materials (e.g., significantly doped group IV semiconductor materials) using a first dopant (e.g., boron) and a second dopant (e.g., gallium, aluminum, or indium). However, such technology may not have been well developed so far.

[0008] Accordingly, an improved method and system for depositing doped semiconductor materials are desirable. Structures and devices formed using said method and / or system are also desirable.

[0009] Any discussion, including problems and solutions stated in this section, is incorporated into this disclosure solely for the purpose of providing context for the present disclosure. Any or all information in such discussion should not be construed as having been known at the time the present invention was made or otherwise constitutes the prior art.

[0010] Various embodiments of the present disclosure relate to a method for forming a structure, a structure and an element formed using such method, and an apparatus for performing said method and / or forming said structure and / or element. While the ways in which various embodiments of the present disclosure solve the problems of the prior methods and systems are discussed in more detail below, generally, various embodiments of the present disclosure provide an improved method for forming a doped semiconductor layer exhibiting a relatively low contact resistance. Additionally, or alternatively, the doped semiconductor layer may be formed at a relatively low temperature without using an annealing step to improve the contact resistance of the doped semiconductor layer. Furthermore, an example of the doped semiconductor layer may be placed on a first portion of the substrate surface with respect to a second portion of the substrate surface.

[0011] According to an exemplary embodiment of the present disclosure, a method for forming a structure is disclosed. The exemplary method comprises the steps of providing a substrate in a reaction chamber, forming a first doped semiconductor layer disposed on the substrate, and forming a second doped semiconductor layer disposed on the first doped semiconductor layer. The first doped semiconductor layer may comprise a first dopant and a second dopant. The second doped semiconductor layer may comprise the first dopant. The first doped semiconductor layer may comprise, for example, a p-type or n-type doped Group IV semiconductor material. The second doped semiconductor layer may comprise, for example, a p-type or n-type doped Group IV semiconductor material. The exemplary method may include the step of etching the first doped semiconductor layer material and the second doped semiconductor layer material. The etching may be performed using a halide-containing gas such as hydrogen chloride, chlorine, etc. The exemplary method may include the step of forming a cap layer disposed on the second doped semiconductor layer. In such cases, the etching step may include the step of etching the cap layer material. The cap layer may include a semiconductor material, such as a group IV semiconductor, for example, and a dopant, such as a first dopant and / or a second dopant. As described in more detail below, various steps of the exemplary method described herein may be performed, for example, in the same reaction chamber of the same cluster tool or in different reaction chambers. The first doped semiconductor layer, the second doped semiconductor layer, and / or the cap layer may be formed on a first portion of the surface of the substrate with respect to a second portion of the substrate. The first portion of the surface of the substrate may include a single-crystal semiconductor, such as single-crystal silicon, for example, n-type single-crystal Czochralski silicon, for example, n-type single-crystal float zone silicon, for example, p-type single-crystal Czochralski silicon, or p-type single-crystal float zone silicon.A second portion of the surface of the substrate may include a dielectric, such as silicon oxide, a high-dielectric dielectric, or a low-dielectric dielectric. Exemplary high-dielectric dielectrics include hafnium oxide, zirconium oxide, and aluminum oxide. Exemplary low-dielectric dielectrics include SiOC, SiOCN, SiN, SiNC, BN, etc.

[0012] According to a further exemplary embodiment of the present disclosure, a structure is formed using the method described herein. The structure may comprise a substrate having a first doped semiconductor layer disposed on a substrate and a second doped semiconductor layer disposed on the first doped semiconductor layer. An exemplary structure may further comprise a cap layer.

[0013] According to additional embodiments of the present disclosure, a device or a part thereof may be formed using the method and / or structure described herein. The device may comprise a substrate, a first doped semiconductor layer, a second doped semiconductor layer, and a conductive layer placed over the second doped semiconductor layer. The first doped semiconductor layer and / or the second doped semiconductor layer may be used to form a source or drain portion of a device such as a field-effect transistor (FET) (e.g., FinFET).

[0014] According to additional examples of the present disclosure, a system for performing and / or performing the method described herein or forming a structure, an element, or a part thereof is disclosed.

[0015] A method for forming a structure is further described herein, the method comprising: providing a substrate in a reaction chamber; forming a first doped semiconductor layer disposed on the substrate; and forming a second doped semiconductor layer disposed on the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and the second doped semiconductor layer comprises the first dopant.

[0016] In some embodiments, the first dopant includes a first p-type dopant.

[0017] In some embodiments, the first p-type dopant is selected from one or more of B, Al, Ga, and In.

[0018] In some embodiments, the second dopant includes a second p-type dopant.

[0019] In some embodiments, the second p-type dopant is selected from one or more of B, Al, Ga, and In.

[0020] In some embodiments, the first dopant includes boron and the second dopant includes gallium.

[0021] In some embodiments, the method further includes the step of forming a cap layer placed on top of a second doped semiconductor layer.

[0022] In some embodiments, the cap layer includes a semiconductor material.

[0023] In some embodiments, the cap layer includes a cap dopant.

[0024] In some embodiments, the cap dopant includes a p-type dopant.

[0025] In some embodiments, the p-type dopant comprises one or more of B, Al, Ga, and In.

[0026] In some embodiments, the first doped semiconductor layer is optionally formed on a first portion of the surface of the substrate.

[0027] In some embodiments, a second doped semiconductor layer is optionally formed to be placed on a first portion of the surface of the substrate.

[0028] A structure formed according to the method described herein is further described herein.

[0029] In some embodiments, the first doped semiconductor layer is about 1x10 17 atomic / cm 3to about 5x10 21 atomic / cm 3 , approximately 1x10 17 atomic / cm 3 to about 3x10 21 atomic / cm 3 , approximately 1x10 18 atomic / cm 3 to about 2x10 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 1x10 21 atomic / cm 3 , 1x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 2.5x10 20 atomic / cm 3 Excess, or 5x10 20 atomic / cm 3 Includes an excess or more carriers.

[0030] In some embodiments, the first doped semiconductor layer is about 1x10 17 atomic / cm 3 to about 5x10 21 atomic / cm 3 , approximately 1x10 17 atomic / cm 3 to about 3x10 21 atomic / cm 3 , approximately 1x10 18 atomic / cm 3 to about 2x10 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 1x10 21 atomic / cm 3 , 1x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 2.5x10 20 atomic / cm 3 Excess, or 5x10 20 atomic / cm 3 It contains excess boron.

[0031] In some embodiments, the first doped semiconductor layer comprises about 10 atomic% to about 90 atomic%, about 30 atomic% to about 70 atomic%, or about 40 atomic% to about 50 atomic% of silicon.

[0032] In some embodiments, the first doped semiconductor layer comprises about 10 atomic% to about 90 atomic%, about 65 atomic% to about 30 atomic%, or about 60 atomic% to about 50 atomic% of germanium.

[0033] In some embodiments, the first doped semiconductor layer is about 0 to about 5 x 10 21 atomic / cm 3 , about 0 or more to about 3x10 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 9x10 20 atomic / cm 3 , or about 1x10 19 atomic / cm 3 to about 9x10 19 atomic / cm 3 , or 1x10 20 atomic / cm 3 It contains excess gallium.

[0034] In some embodiments, the thickness of the first doped semiconductor layer is greater than 0 or about 1 nm to about 50 nm, about 2 nm to about 20 nm, or about 3 nm to about 10 nm.

[0035] In some embodiments, the thickness of the second doped semiconductor layer is about 1 nm to about 50 nm, about 2 nm to about 20 nm, or about 3 nm to about 10 nm.

[0036] In some embodiments, the second doped semiconductor layer is about 1x10 17 atomic / cm 3 to about 5x10 21 atomic / cm 3 , approximately 1x1017 atomic / cm 3 to about 3x10 21 atomic / cm 3 , approximately 1x10 18 atomic / cm 3 to about 2x10 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 1x10 21 atomic / cm 3 , 1x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 2.5x10 20 atomic / cm 3 Excess, or 5x10 20 atomic / cm 3 Includes excess carrier.

[0037] In some embodiments, the second doped semiconductor layer is about 1x10 17 atomic / cm 3 to about 5x10 21 atomic / cm 3 , approximately 1x10 17 atomic / cm 3 to about 3x10 21 atomic / cm 3 , approximately 1x10 18 atomic / cm 3 to about 2x10 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 1x10 21 atomic / cm 3 , 1x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 2.5x10 20 atomic / cm 3 Excess, or 5x10 20 atomic / cm 3 It contains excess boron.

[0038] In some embodiments, the second doped semiconductor layer comprises about 10 atomic% to about 90 atomic%, about 30 atomic% to about 70 atomic%, or about 40 atomic% to about 50 atomic% of silicon.

[0039] In some embodiments, the second doped semiconductor layer comprises about 10 atomic% to about 90 atomic%, about 65 atomic% to about 30 atomic%, or about 60 atomic% to about 50 atomic% of germanium.

[0040] In some embodiments, the concentration of the second dopant in the first doped semiconductor layer is higher near the top surface compared to the first doped semiconductor layer bulk material.

[0041] In some embodiments, the concentration of carbon in the first doped semiconductor layer is lower near the top surface compared to the first doped semiconductor layer bulk material.

[0042] In some embodiments, the carbon concentration at a distance of ±10 nm, ±5 nm, or ±3 nm from the interface of the first doped semiconductor layer / second doped semiconductor layer is 1x10 21 atomic / cm 3 Less than, 1x10 20 atomic / cm 3 Less than, 1x10 19 atomic / cm 3 Less than, 5x10 18 atomic / cm 3 Less than, 1x10 18 atomic / cm 3 Less than, 5x10 17 atomic / cm 3 Less than, 1x10 17 atomic / cm 3 Less than, or 5x10 16 atomic / cm 3 It is less than.

[0043] In some embodiments, the gallium concentration at a distance of ±10 nm, ±5 nm, or ±3 nm from the interface of the first doped semiconductor layer / second doped semiconductor layer is 1x10 20 atomic / cm 3Less than, 1x10 19 atomic / cm 3 Less than, 5x10 18 atomic / cm 3 Less than, 1x10 18 atomic / cm 3 Less than, 5x10 17 atomic / cm 3 Less than, 1x10 17 atomic / cm 3 Less than, or 5x10 16 atomic / cm 3 It is less than.

[0044] In some embodiments, the concentration of carbon at a distance of less than 10 nm, 5 nm, or 3 nm, or 1 to 10 nm, 1 to 5 nm, or 1 to 3 nm from the top of the second doped semiconductor interface is 1x10 21 atomic / cm 3 Less than, 1x10 20 atomic / cm 3 Less than, 5x10 19 atomic / cm 3 Less than, 1x10 19 atomic / cm 3 Less than, 5x10 18 atomic / cm 3 Less than or equal to 1x10 18 atomic / cm 3 It is less than.

[0045] In some embodiments, the concentration of gallium at a distance of less than 5 nm, less than 3 nm, or less than 2 nm, or 1 to 5 nm, or 1 to 3 nm from the top of the second doped semiconductor interface is 1 x 10⁻⁶ 18 atomic / cm 3 Excess, 1x10 19 atomic / cm 3 Excess, 5x10 18 atomic / cm 3 Excess, 5x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 5x10 20 atomic / cm 3 Excess, or 1x10 21 atomic / cm3 It is an excess.

[0046] An element formed according to any method described herein and / or formed using any of any structure described herein is further described herein.

[0047] In some embodiments, the element includes a source portion formed according to the method described herein.

[0048] In some embodiments, the element includes a drain portion formed according to the method described herein.

[0049] In some embodiments, the method further includes the step of forming a conductive layer placed on top of a second doped semiconductor layer.

[0050] A system configured to perform the method described herein and / or to form the structure described herein is further described herein.

[0051] A system is further described herein comprising: one or more reaction chambers; a gas injection system fluidly coupled to at least one of the one or more reaction chambers; a first gas source; a second gas source; a third gas source; an exhaust source; and a controller configured to control the gas flow through the gas injection system to form a first doped semiconductor layer placed on the surface of a substrate, a second doped semiconductor layer placed on the first doped semiconductor layer, and a cap layer on the second doped semiconductor layer.

[0052] In some embodiments, the controller is configured to perform the step of etching the first doped semiconductor layer and the second doped semiconductor layer placed on the second surface within the one or more reaction chambers.

[0053] These and other embodiments will be readily apparent to those skilled in the art from the following detailed description of specific embodiments with reference to the accompanying drawings. The present invention is not limited to any specific embodiments disclosed. Brief explanation of the drawing

[0054] A more complete understanding of the embodiments of the present disclosure can be obtained by referring to the detailed description of the invention and the claims in conjunction with the following exemplary drawings. FIG. 1 illustrates a method according to various exemplary embodiments of the present disclosure. FIGS. 2 and FIGS. 3 show a structure according to an exemplary embodiment of the present disclosure. FIG. 4 illustrates another method according to an exemplary embodiment of the present disclosure. FIGS. 5 to 10 show a structure according to an exemplary embodiment of the present disclosure. FIG. 11 shows a part of an element according to an exemplary embodiment of the present disclosure. FIG. 12 shows a reactor system according to an exemplary additional embodiment of the present disclosure. FIG. 13 shows secondary ion mass spectrometry (SIMS) measurement results illustrating advantageous characteristics of some embodiments of the method according to the present disclosure. It will be understood that the elements of the drawings are depicted in a simplified and clear manner and are not necessarily drawn to scale. For example, to aid in understanding the embodiments illustrated in this disclosure, the dimensions of some components in the drawings may be exaggerated compared to other components. Specific details for implementing the invention

[0055] The description of exemplary embodiments of methods, structures, elements, and systems provided below is merely illustrative and intended only for illustrative purposes, and is not intended to limit the scope or claims of this disclosure. Furthermore, citing multiple embodiments describing features is not intended to exclude other embodiments having additional features or other embodiments including other combinations of specified features. For example, various embodiments are presented as exemplary embodiments and may be referenced in the dependent claims. Unless otherwise noted, exemplary embodiments or their components may be combined or applied separately.

[0056] As described in more detail below, various embodiments of the present disclosure provide a method for forming a doped semiconductor layer on the surface of a substrate. An exemplary method may be used to form source and / or drain regions of a semiconductor device, for example, which exhibit relatively high mobility and relatively low contact resistance while maintaining the structure and composition of the deposited layer. For example, the method described herein may include the step of forming a first doped semiconductor layer disposed on the surface of a substrate, and the step of forming a second doped semiconductor layer disposed on the first doped semiconductor. As described in more detail below, one or more of the forming steps may be optionally disposed on the first region or on the material with respect to a second region of the material.

[0057] In the present disclosure, “gas” may include materials that are gases, vaporized solids, and / or vaporized liquids at normal temperature and pressure (NTP), and may consist of a single gas or a mixture of gases depending on the context. Gases other than process gases, i.e., gases introduced without passing through gas distribution assemblies, multi-port injection systems, other gas distribution devices, etc., may be used, for example, to seal the reaction space and may include sealing gases such as rare gases. In some cases, the term “precursor” may refer to a compound that participates in a chemical reaction to produce another compound, and in particular, a compound that constitutes the membrane matrix or the main framework of the membrane; the term “reactant” may be used interchangeably with the term “precursor.” The term “inert gas” may refer to a gas that does not participate in a chemical reaction and / or does not become part of the membrane matrix to a significant extent. Exemplary inert (e.g., carrier) gases include He, Ar, H2, N2, and any combination thereof.

[0058] As used herein, the term “substrate” may refer to any underlying material or materials that can be used to form, or upon which an element, circuit, or film can be formed. The substrate may comprise a bulk material such as silicon (e.g., single-crystal silicon), other Group IV materials such as germanium, or other semiconductor materials such as Group II-VI or Group III-V, and may comprise one or more layers placed on or beneath the bulk material. Additionally, the substrate may comprise various features, such as indentations, protrusions, etc., formed within or on at least a portion of the layers of the substrate. As described in more detail below, the surface of the substrate may comprise two or more regions, wherein each of the two or more regions comprises a different material and / or a material having a different crystalline structure.

[0059] As used herein, the term “epitaxy layer” may refer to a substantially single-crystalline layer on a substantially single-crystalline substrate or layer placed underneath.

[0060] As used herein, the term “chemical vapor deposition” may refer to any process in which a substrate is exposed to one or more volatile precursors that react and / or decompose on the surface of the substrate to produce a desired deposition.

[0061] As used herein, the term "silicon germanium" refers to a semiconductor material comprising silicon and / or germanium, Si 1-x Ge x (1 ≥ x ≥ 0, or 0.2 ≥ x ≥ 0.8, or 0.4 ≥ x ≥ 0.6) or materials including silicon and germanium having a composition as described herein may be referred to.

[0062] As used herein, the terms “film” and / or “layer” may refer to any continuous or discontinuous structure and material, such as a material deposited by the method disclosed herein. For example, the film and / or layer may comprise a two-dimensional material, a three-dimensional material, nanoparticles, or even a partial or whole molecular layer or a partial or whole atomic layer or an atomic and / or molecular cluster. The film or layer may comprise a material or layer having pinholes, which may be at least partially continuous.

[0063] As used herein, the term "single-crystalline" may refer to materials including crystalline materials that are substantially single crystals, i.e., exhibit long-range alignment. However, it should be understood that while "single-crystalline" materials merely exhibit long-range alignment, they are not perfect single crystals and may also contain various defects, stacking faults, atomic substitutions, etc.

[0064] As used herein, the term “non-crystalline” may refer to a material that does not contain a substantial single crystal, that is, a material that exhibits short-range alignment or has no alignment at all in its crystal structure. “Non-crystalline” materials may include polycrystalline materials that may exhibit short-range alignment and amorphous materials that have no alignment in their crystal structure.

[0065] As used herein, the “structure” may include a substrate as described herein. The structure may include one or more layers disposed on the substrate, such as one or more layers formed according to the method described herein.

[0066] As used herein, the term "Group IV semiconductor" may refer to a semiconductor material comprising at least one of carbon (C), silicon (Si), germanium (Ge), tin (Sn), or an alloy thereof.

[0067] As used herein, the terms “Group IIIA dopant precursor” or “p-type dopant precursor” may refer to a dopant precursor comprising at least one of boron (B), aluminum (Al), gallium (Ga), or indium (In). Similarly, a p-type dopant may comprise one or more of B, Al, Ga, and In.

[0068] As used herein, the terms "Group V dopant precursor" or "n-type dopant precursor" may refer to a dopant precursor comprising at least one of phosphorus (P), arsenic (As), and antimony (Sb). Similarly, an n-type dopant may comprise one or more of P, As, and Sb.

[0069] Additionally, in this disclosure, any two numeric values ​​of a variable may constitute an executable range of said variable, and any indicated range may include or exclude endpoints. Additionally, any value of the indicated variable may refer to an exact value or an approximate value (whether indicated as "approximately"), may include an equivalent, and may refer to an average, median, representative, majority, etc. Also, in this disclosure, the terms "comprising," "consisting of," and "having" independently refer to "ordinarily or approximately comprising," "comprising," "essentially made of," or "made of" in some embodiments. In this disclosure, any defined meaning does not necessarily exclude the ordinary and conventional meaning in some embodiments.

[0070] Now, returning to the drawings, FIG. 1 illustrates a method (100) according to an exemplary embodiment of the present disclosure. FIG. 2 and FIG. 3 illustrate structures (200 and 300) that can correspond to steps of the method (100).

[0071] The method (100) includes the steps of providing a substrate within a reaction chamber (102), forming a first doped semiconductor layer (104), and forming a second doped semiconductor layer (106). Additionally, steps (104 and 106) may be repeated as desired.

[0072] During step (102), a substrate (e.g., substrate (202)) is provided within a reaction chamber as described herein. As a non-limiting example, the reaction chamber used during step (102) may include a reaction chamber of a chemical vapor deposition system. However, it is also considered that other reaction chambers and alternative chemical vapor deposition systems may be used to carry out embodiments of the present disclosure. The reaction chamber may be a standalone reaction chamber or part of a cluster tool.

[0073] Step (102) may include heating a substrate in a reaction chamber to a desired deposition temperature. In some embodiments of the present disclosure, step (102) includes heating the substrate to a temperature of approximately 1100°C or less, approximately 700°C or less, approximately 650°C or less, approximately 600°C or less, approximately 550°C or less, approximately 500°C or less, approximately 450°C or less, or even approximately 400°C or less, or even approximately 300°C or less, or even approximately 250°C or less. For example, in some embodiments of the present disclosure, the step of heating the substrate to a deposition temperature may include heating the substrate to about 400°C to about 1100°C or about 400°C to about 700°C. For example, in some embodiments of the present disclosure, the step of heating the substrate to a deposition temperature may include the step of heating the substrate to a temperature of about 290°C to about 400°C.

[0074] In addition to controlling the substrate temperature, the pressure within the reaction chamber may also be controlled. For example, in some embodiments of the present disclosure, the pressure within the reaction chamber during step (102) may be less than 760 Torr, or less than 350 Torr, or less than 100 Torr, or less than 50 Torr, or less than 25 Torr, or even less than 10 Torr. In some embodiments, the pressure within the reaction chamber may be 10 Torr to 760 Torr, 10 Torr to 200 Torr, or 10 Torr to 100 Torr.

[0075] During step (104), a first doped semiconductor layer (204) is formed on the substrate (202). The first doped semiconductor layer (204) may be formed as a (e.g., single)crystalline material placed on at least a portion of the substrate (202). Thus, at least a portion of the surface (206) of the first doped semiconductor layer (204) may be single-crystalline and may function as a template for an additional epitaxial layer.

[0076] The first doped semiconductor layer (204) may include a group IV semiconductor material. Exemplary group IV semiconductors include silicon (e.g., n-type doped Si), silicon germanium (SiGe) (e.g., p-type doped SiGe), germanium (e.g., p-type doped Ge), and germanium tin (e.g., p-type doped GeSn).

[0077] According to various embodiments of the present disclosure, the first doped semiconductor layer (204) comprises a first dopant and a second dopant. According to aspects of these embodiments, the first dopant and the second dopant are of the same type (n-type or p-type). Exemplary dopants include, for example, a Group IIIA metal as a p-type dopant and a Group V dopant as an n-type dopant.

[0078] During step (104), one or more Group IV precursors and one or more Group IIIA and / or Group V dopant precursors flow into the reaction chamber through one or more gas injectors, such as a multi-port injector (MPI) containing multiple individual port injectors to provide a gas mixture into the reaction chamber. Various combinations of precursors are supplied to one or more individual port injectors to finely adjust the concentration profile as desired. When depositing the film, to mitigate reactions with some dopants, such as gallium, within the film, the precursors (e.g., all precursors) may preferably be free of halides (e.g., chlorine). That is, the chemical formula of the precursor or its components may not contain Cl or other halides.

[0079] In some embodiments, a single Group IV precursor may be used during the deposition process, for example, when the Group IV semiconductor to be deposited comprises silicon (Si) or germanium (Ge). In some embodiments, two or more Group IV precursors may be used during the deposition process, for example, when the Group IV semiconductor to be deposited comprises silicon germanium, silicon germanium carbide (Si 1-x-y Ge x C y ), Germanium tin (Ge 1-x Sn x ), germanium silicon tin (Ge 1-x-y Si x Sn y ), germanium silicon tin carbide (Ge 1-x-y Si x Sn y C x ), silicon tin (Si 1-x Sn x ), silicon tin carbide (Si 1-x-y Sn x C y ), or silicon carbide (Si 1-x C x In the case of including a group IV semiconductor alloy that includes but is not limited to ), two or more group IV precursors may be used.

[0080] An exemplary silicon precursor (for, for example, for the deposition of a silicon-containing first doped semiconductor layer) is silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), pentasilane (Si5H 12 It may comprise one or more hydrogenated silicon precursors selected from ), methylsilane (CH3-SiH3), or other suitable silicon-containing precursors. Advantageously, the silicon precursor does not contain chlorine. Advantageously, the silicon precursor does not contain a halide.

[0081] An exemplary germanium precursor (for, for example, for the deposition of a first doped semiconductor layer containing germanium) may include at least one of germane (GeH4), digermaine (Ge2H6), trigermaine (Ge3H8), or lowmylsilane (GeH6Si) or other suitable germanium-containing precursors.

[0082] An exemplary tin precursor (for example, for the deposition of a first doped semiconductor layer containing tin) may include tin tetrachloride (SnCl4), SiH4, tin tetrachloride (SnD4), and other suitable tin-containing precursors.

[0083] The p-type (e.g., first) dopant precursor may comprise, for example, at least one of diborane (B2H6) or deuterium-diborane (B2D6), or one or more borohydrides. Exemplary borohydrides include gallium borohydride (Ga(BH4)3), aluminum borohydride (Al(BH)4)3), and indium borohydride (In(BH)4)3). In an alternative embodiment of the present disclosure, the p-type dopant precursor is of formula Y x M(BH4) 3-x It may include a borohydride having (Y is independently selected from hydrogen, deuterium, chlorine, bromine, and iodine; M is a Group IIIA metal independently selected from gallium, aluminum, and indium; and x is an integer from 0 to 2).

[0084] In some embodiments of the present disclosure, the p-type dopant precursor is of the general formula R x M(BH4) 3-x It comprises one or more organic borohydrides having (wherein R is independently selected from CH3, C2H5, C6H5, CF3SO3 and NH2, M is a Group IIIA metal independently selected from gallium, aluminum and indium; and x is an integer from 1 to 3).

[0085] In some embodiments of the present disclosure, the p-type dopant precursor is of the general formula Zx MY 3-x (Z is independently selected from hydrogen, deuterium, chlorine, bromine, and iodine; M is a Group IIIA metal independently selected from gallium, aluminum, and indium; Y is a halide independently selected from chlorine, bromine, and iodine; and x is an integer from 0 to 3). In some embodiments of the present disclosure, the halide dopant may comprise a dimeric structure, so the method has the formula (Z x MY 3-x The method may include the step of selecting a halide to include a halide having )2 (wherein Z is independently selected from hydrogen, deuterium, chlorine, bromine, and iodine; M is a Group IIIA metal independently selected from gallium, aluminum, and indium; Y is a halide independently selected from chlorine, bromine, and iodine; and x is an integer from 0 to 3).

[0086] In some embodiments of the present disclosure, the p-type dopant precursor may comprise one or more organic halides, and general formula R x MY 3-x The method may further include the step of selecting one or more organic halides to comprise an organic halide having (wherein R is independently selected from CH3, C2H5, C6H5, CF3SO3, and NH2; M is a Group IIIA metal independently selected from gallium, aluminum, and indium; Y is a halide independently selected from chlorine, bromine, and iodine; and x is an integer from 0 to 3).

[0087] Selecting a Group IIIA dopant precursor containing an organic component may be more advantageous for depositing a Group IV semiconductor. For example, incorporating carbon into a Group IV semiconductor may further increase the deformation in the Group IV semiconductor being deposited. Therefore, in some embodiments of the present disclosure, the step of exposing a substrate to at least one Group IIIA precursor further comprises the step of exposing the substrate to at least one of an organic borohydride or an organic halide. In other embodiments, the step of exposing the substrate to at least one of an organic borohydride or an organic halide further comprises the step of incorporating carbon into a first doped semiconductor layer, wherein the atomic percentage (atomic%) in the first doped semiconductor layer is, for example, greater than approximately 0.5 atomic%.

[0088] In some embodiments of the present disclosure, it may be advantageous to deposit a first and / or second doped semiconductor layer without substantially incorporating carbon into the deposited semiconductor layer. However, since organometallic dopant precursors may contain organic components, i.e., carbon-containing components, it may be difficult to minimize carbon incorporation into the first doped semiconductor layer when using metal-organic dopant precursors. However, the method of the present disclosure may selectively deposit a first doped semiconductor layer using an organometallic or other precursor dopant without substantial carbon incorporation into the semiconductor layer. As a non-limiting exemplary embodiment, the deposition method (e.g., optionally) may include the step of depositing a layer containing germanium (Ge) that is substantially carbon-free.

[0089] In some embodiments of the present disclosure, two or more dopant species may be incorporated into the first doped semiconductor layer (204) using a single dopant precursor. For example, in some embodiments, step (104) includes exposing a substrate to one or more Group IIIA dopant precursors, such as borohydride or organic borohydride and / or other Group IIIA precursors. In embodiments using borohydride or organic borohydride, the dopant precursor may include boron (B) in addition to an additional (e.g., second) Group IIIA dopant (e.g., gallium, aluminum, or indium). Thus, using borohydride or organic borohydride includes incorporating the first dopant and the additional (second) dopant into the first doped semiconductor layer. This method may be used to further increase the dopant concentration in the Group IV semiconductor without correspondingly degrading the crystal quality of the Group IV semiconductor.

[0090] The precursor for the second dopant may include, for example, at least one Group IIIA organometallic dopant precursor and / or a Group V precursor. In some cases, it may be preferable to use a halogen-free Group IIIA precursor for the first and / or second dopant source.

[0091] In some embodiments, the second dopant precursor may comprise at least one metal-organic compound selected from a gallium dopant, an aluminum dopant, and / or an indium dopant. The gallium dopant precursor may comprise, for example, a gallium alkyl. The gallium dopant precursor may comprise, for example, trimethylgallium (TMG) or triethylgallium (TEG), tritertiarybutylgallium (TTBGa), tri-isopropylgallium (TiPGa), gallium trichlorine (GaCl3), Ga(BH4)3, diethylpotassium chloride (DeGaCl), RGaCl2, GaR3, GaH x(Here, R may be a linear or branched alkyl group, e.g., ethyl, butyl, or propyl group) may be included. The aluminum dopant precursor may include at least one of trimethylaluminum (TMA) or triethylaluminum (TEA). The indium dopant precursor may include at least one of trimethylindium (TMI), triethylindium (TEI), cyclopentadienylindium (InCp), di-isopropylmethylindium (DIPMeIn), or ethyldimethylindium (EDMIn).

[0092] In some embodiments, the gallium dopant precursor is, for example, trimethylgallium (TMG) or triethylgallium (TEG), tritertiarybutylgallium (TTBGa), tri-isopropylgallium (TiPGa), Ga(BH4)3, GaR3, GaH x (Here, R may be a linear or branched alkyl group, e.g., ethyl, butyl, or propyl group) may include at least one of these.

[0093] In some embodiments, the p-type dopant precursor may be provided in a diluted form, and the diluted form may contain approximately 0.1% to approximately 100% of the dopant precursor in the carrier gas.

[0094] The n-type dopant precursor may include, for example, at least one of phosphine and acin. In some embodiments, the n-type dopant precursor may be provided in a diluted form, and the diluted form may contain approximately 1% to approximately 5% of the dopant precursor in the carrier gas.

[0095] The thickness of the first doped semiconductor layer (204) formed during step (104) may be greater than 0 (zero), or about 1 nm to about 50 nm, about 2 nm to about 20 nm, or about 3 nm to about 10 nm. The first doped semiconductor layer (204) (e.g., doped Si 1-x Ge xThe concentration of one or more p-type dopants (e.g., boron) in ) is approximately 1 x 10⁻⁶ 17 atomic / cm 3 to about 5x10 21 atomic / cm 3 , approximately 1x10 17 atomic / cm 3 to about 3x10 21 atomic / cm 3 , approximately 1x10 18 atomic / cm 3 to about 2x10 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 1x10 21 atomic / cm 3 , 1x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 2.5x10 20 atomic / cm 3 Excess, or 5x10 20 atomic / cm 3 It may exceed. The concentration of the second p-type dopant (e.g., aluminum, gallium, or indium) is about 0 or 0 to about 3 x 10⁻⁶. 21 atomic / cm 3 , approximately 8x10 18 atomic / cm 3 to about 9x10 20 atomic / cm 3 , or about 1x10 19 atomic / cm 3 to about 9x10 19 atomic / cm 3 , or 1x10 20 atomic / cm 3 It may exceed.

[0096] In the case of a silicon germanium layer, the first doped semiconductor layer (204) may contain about 10% to about 90%, or about 30% to about 70%, or about 40% to about 50% silicon, and / or about 10% to about 90%, or about 65% to about 30%, or about 60% to about 50% germanium. In some embodiments, the germanium (and / or other component) content within the first doped semiconductor layer (204) may not be constant, but rather may vary so that the germanium content (and / or other component) may have a gradient composition within the first doped semiconductor layer (204).

[0097] During step (106), a second doped semiconductor layer (302) is epitaxy formed on a first doped semiconductor layer (204) on at least a portion of the substrate (202) as shown in FIG. 3. The second doped semiconductor layer (302) may comprise a semiconductor material (e.g., Group IV) and a first dopant (e.g., the same first dopant in the first doped semiconductor layer or a first dopant of the same type).

[0098] A structure having desired characteristics can be formed by forming (e.g., growing) a first doped semiconductor layer (204) containing the first dopant and the second dopant before forming (e.g., growing) a second doped semiconductor layer (302) containing the first dopant. For example, the second dopant can diffuse to the top and / or carbon can be trapped in the layer (204), thereby providing desired characteristics such as low contact resistance. Additionally, the heavier atomic mass of the second dopant (e.g., Ga) compared to the first dopant (e.g., B) may be desirable for the formation of shallow junctions by minimizing channeling effects. For example, by forming SiGe:B:Ga prior to the SiGe:B layer, Ga can diffuse to the surface of the SiGe:B layer, and C can be trapped inside the original SiGe:B:Ga layer. By utilizing this, the amount of carbon on the surface of the SiGe:B layer can be reduced. In some embodiments, the carbon concentration within a distance of ±10 nm, ±5 nm, or ±3 nm at the interface of the first doped semiconductor layer / second doped semiconductor layer (e.g., SiGe:B:Ga / SiGe:B) is 5x10 21 atomic / cm 3 Less than, 1x10 21 atomic / cm 3 Less than, 1x10 20 atomic / cm 3 Less than, 1x10 19 atomic / cm 3 Less than, 5x10 18 atomic / cm 3 Less than, 1x10 18 atomic / cm 3 Less than, 5x10 17 atomic / cm 3 Less than, 1x10 17 atomic / cm 3 Less than or 5x10 16 atomic / cm 3It is less than. In some embodiments, the Ga concentration within a distance of ±10 nm, ±5 nm, or ±3 nm at the interface of the first doped semiconductor layer / second doped semiconductor (e.g., SiGe:B:Ga / SiGe:B) is 1x10 20 atomic / cm 3 Less than, 1x10 19 atomic / cm 3 Less than, 5x10 18 atomic / cm 3 Less than, 1x10 18 atomic / cm 3 Less than, 5x10 17 atomic / cm 3 Less than, 1x10 17 atomic / cm 3 Less than, or 5x10 16 atomic / cm 3 It is less than. In some embodiments, the carbon concentration within a distance of less than 10 nm, 5 nm, or 3 nm from the second doped semiconductor layer (e.g., SiGe:B)-top interface, or within 1 to 10 nm, 1 to 5 nm, or 1 to 3 nm, is 5x10 21 atomic / cm 3 Less than, 1x10 21 atomic / cm 3 Less than, 1x10 20 atomic / cm 3 Less than, 5x10 19 atomic / cm 3 Less than, 1x10 19 atomic / cm 3 Less than, 5x10 18 atomic / cm 3 Less than or equal to 1x10 18 atomic / cm 3 It is less than. In some embodiments, the Ga concentration within a distance of less than 5 nm, less than 3 nm, or less than 2 nm, or within 1 to 5 nm, or within 1 to 3 nm from the second doped semiconductor layer (e.g., SiGe:B) is 1x10 18 atomic / cm 3 Excess, 5x10 18 atomic / cm 3 Excess, 1x10 19 atomic / cm 3Excess, 5x10 19 atomic / cm 3 Excess, 1x10 20 atomic / cm 3 Excess, 5x10 20 atomic / cm 3 Excess, or 1x10 21 atomic / cm 3 It is an excess.

[0099] The concentration of the first dopant in the second doped semiconductor layer (302) is approximately 1x10 17 atomic / cm 3 to about 5x10 21 atomic / cm 3 , or about 1x10 17 atomic / cm 3 to about 3x10 21 atomic / cm 3 , or about 1x10 18 atomic / cm 3 to about 2x10 21 atomic / cm 3 , or about 8x10 18 atomic / cm 3 to about 1x10 21 atomic / cm 3 or 1x10 19 atomic / cm 3 Excess dopant or 1x10 20 Carrier / cm 3 Excess, or 2.5x10 20 Carrier / cm 3 Excess, or even 5x10 20 Carrier / cm 3 The range may be greater than. Additionally, as a specific example, the second doped semiconductor layer may comprise about 10% to about 90%, or about 30% to about 70%, or about 40% to about 50% silicon, or about 10% to about 90%, or about 65% to about 30%, or about 60% to about 50% germanium. The thickness of the second doped semiconductor layer (302) may be about 1 nm to about 50 nm, about 2 nm to 20 nm, or about 3 nm to 10 nm.

[0100] The semiconductor material (e.g., group IV) for step (106) and the precursor for the first dopant may be the same or similar as those described above in relation to step (104).

[0101] Step (106) may be performed in the same reaction chamber used during Step (104). Alternatively, Step (106) may be performed in a different reaction chamber, such as the reaction chamber used during Step (104) or another reaction chamber in the same cluster tool as another reactor system. The pressure and / or temperature within the reaction chamber for Step (106) may be the same as or similar to the pressure and / or temperature associated with Step (104).

[0102] Secondary-ion mass spectrometry (SIMS) data for a SiGe:B:Ga / SiGe:B laminate formed according to method (100) confirms that carbon atoms in the SiGe:B:Ga layer appear to remain in the original SiGe:B:Ga layer (layer (204)), and gallium in the layer (204) is segregated toward the upper surface of the layer (302), thereby providing a structure having relatively low contact resistance.

[0103] As discussed in more detail below, the exemplary method may also include the step of forming a cap layer. According to some embodiments of the present disclosure, one or more of the first doped semiconductor layer, the second doped semiconductor layer, and the cap layer may be optionally formed over one portion of the substrate (e.g., containing a first material or having a first (e.g., crystalline) structure) with respect to another portion (e.g., containing a second material or having a second (e.g., amorphous) structure).

[0104] As described herein, the selective deposition process may include a greater amount of material remaining on the first surface relative to the second surface. For example, the selective process may have a greater and / or greater amount of the first doped semiconductor layer remaining in the first region compared to any first doped semiconductor layer remaining in the second region, or a greater amount of the second doped semiconductor layer remaining in the first region compared to any second doped semiconductor layer remaining in the second region. In some embodiments of the present disclosure, the selectivity of the deposition process may be expressed as the ratio of the material formed on the first surface (or within the first region) to the combined amount of material formed on the first and second surfaces (or regions). For example, if 10 nm of the first doped semiconductor layer remains in the first region and 1 nm of the first doped semiconductor layer remains in the second region, the selective deposition process will be considered to have a selectivity of 91%. In some embodiments, the selectivity of the method disclosed herein may be greater than about 80%, greater than about 90%, greater than about 95%, 99.5%, 98%, greater than 99%, or even greater than about 100%.

[0105] FIG. 4 illustrates a method (400) for selectively forming one or more of a first doped semiconductor layer, a second doped semiconductor layer, and a cap layer according to an exemplary embodiment of the present disclosure. FIG. 5 through 10 illustrate a substrate (500) and a structure (600, 700, 800, 900, and 1000) that may correspond to the steps of the method (400).

[0106] The method (400) includes the steps of providing a substrate in a reaction chamber (402), forming a first doped semiconductor layer (404), forming a second doped semiconductor layer (406), forming a cap layer (408), and etching (410).

[0107] Except that the method (400) includes a cap layer forming step (408) and an etching step (410), the method (400) may be the same or similar to the method (100). Steps (402 to 406) may be the same or similar to the steps (102 to 106) described above. For example, the steps may be performed in the same type of reaction chamber, at the same or similar temperature, and at the same or similar pressure, and / or using one or more of the same precursors (e.g., all of them).

[0108] Referring to FIGS. 4 and 5, the substrate (or structure) (500) provided during step (402) may include a first region (506) comprising a first material (e.g., a (single)crystalline bulk material (502)) and a second region (508) comprising a second material (e.g., a non-single-crystalline material (504)). The first region (506) may include a single-crystalline surface (510), and the second region (508) may include a non-single-crystalline surface (512), such as a polycrystalline surface or an amorphous surface. The single-crystalline surface (510) may include a semiconductor material, for example, one or more group IV semiconductor materials, such as silicon (Si), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), and germanium (Ge). The non-crystalline surface (512) may include dielectric materials such as, for example, oxides, oxynitrides, nitrides, oxycarbides, or oxycarbonitrides, and may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and mixtures thereof, such as SiOC, SiOCN, SiON.

[0109] During step (404), as shown in FIG. 6, a first doped semiconductor layer (602) may be optionally deposited on top of a first material (e.g., bulk material (502)) in a first region (506) on top of a second material (e.g., non-monocrystalline material (504)) in a second region (508). The first doped semiconductor layer (602) may be formed as a (e.g., monocrystalline) material placed on top of the first region / surface (e.g., region (506) / surface (210)). Thus, the surface (606) of the first doped semiconductor layer (602) may be monocrystalline and may function as a template for an additional epitaxial layer.

[0110] As further illustrated in FIG. 6, a structure (600) comprising a first doped semiconductor layer (602) optionally formed in a first region (506) may include some components (604) of the first doped semiconductor material formed in a second region (508)—e.g., nuclei and / or clusters. In this case, an etching process, which is described in more detail below, may be used to remove the components (604). In other cases, the nucleation delay of the first doped semiconductor layer may be sufficiently high on the second / non-monocrystalline surface (512) relative to the first surface (510) so that the components (604) are not formed. In this case, the etching step may not be desirable. As a specific example, the nucleation delay may be about 2 nm or more, 5 nm or more, 10 nm or more.

[0111] The first doped semiconductor layer (602) may include any material described above in relation to the first doped semiconductor layer (204). For example, the first doped semiconductor layer (602) may include a group IV semiconductor material including a first dopant and a second dopant as described above. The thickness and / or composition of the first doped semiconductor layer (602) may be the same as or similar to the thickness and / or composition of the first doped semiconductor layer (204).

[0112] During step (406), a second doped semiconductor layer (702) is optionally formed (e.g., epitaxy) on the first doped semiconductor layer (602) as shown in FIG. 7. The second doped semiconductor layer (702) may comprise any material described above in association with the second doped semiconductor layer (302). For example, the second doped semiconductor layer (702) may comprise a group IV semiconductor material including the first dopant as described above. The thickness and / or composition of the second doped semiconductor layer (702) may be the same as or similar to the thickness and / or composition of the second doped semiconductor layer (302).

[0113] The structure (700) may include a component (704) of the first and / or second doped semiconductor material formed in the second region (508)—for example, a nucleus and / or cluster. In this case, an etching process, which is described in more detail below, may be used to remove the component (704). In other cases, the nucleation delay of the second doped semiconductor layer may be sufficiently high in region (508) relative to region (506) so that the component (704) is not formed. As a specific example, the nucleation delay may be about 10 nm or more.

[0114] During step (408), a cap layer (802) is optionally (e.g., epitaxy) formed on the second doped semiconductor layer (702) as shown in FIG. 8. The cap layer (802) may comprise, for example, a single element group IV semiconductor that can be doped. The dopant in the layer (802) may have the same type of dopant or the same dopant as the first dopant in the layer (602) and / or layer (702). The structure (800) may comprise a component (804) of the first and / or second doped semiconductor material and / or cap material formed in the second region (508)—e.g., a nucleus and / or cluster. In this case, an etching process, which is described in more detail below, may be used to remove the component (804). In other cases, the nucleation delay of the cap layer may be sufficiently high in region (508) relative to region (506) so that the component (804) is not formed.

[0115] The use of the cap layer (802) can reduce and stop any second dopant (e.g., Al, Ga, or In) segregation. To illustrate a specific example, the SiGe:B / SiGe:B:Ga epitaxial layer can be kept intact and the original features and properties can be maintained by using the cap layer (802) as a sacrificial layer. Thus, it is possible to have a similar film process that can be used for optional SiGe:B:Ga or S / D applications.

[0116] The cap layer (802) may comprise, for example, single-crystalline silicon, and the cap layer may be doped with, for example, a p-type dopant. Suitable p-type dopants include boron and gallium. In some embodiments, the cap layer may be doped with boron and gallium. Thus, the cap layer may be grown using a silicon precursor and optionally using a boron precursor and / or a gallium precursor. Suitable silicon precursors include silanes such as SiH4 and Si2H6. Suitable boron precursors include boranes such as B2H6. Suitable gallium precursors include organometallic gallium precursors, for example, gallium alkyls, such as triethylgallium.

[0117] During step (410), any material deposited in region (508) during one or more steps (404 to 408) may be removed by etching. A cap layer (802) may be used to protect layer (702) during step (410). For example, both the material of the first region (506) (e.g., single-crystalline semiconductor) and the material of the second region (508) (e.g., non-monocrystalline) may be exposed to an etchant gas. The etchant may remove more of the (e.g., non-monocrystalline) component (804) of the second region (508) than the material of the first region (506) (e.g., single-crystalline semiconductor, e.g., cap layer (802)) to form a structure (900). Additionally, less material may be deposited in the second region (508) compared to the region (506).

[0118] As shown in FIG. 9, a portion (902) of the cap layer (802) may be retained even after all or substantially all of any material deposited on the region (508) has been removed. The remainder of the cap layer (802) may form silicide, for example, when a metal contact is formed on the second deposited semiconductor layer. The etching step (410) may selectively continue to remove all or substantially all of the cap layer (802), as shown in FIG. 10. This may be useful, for example, when using a metal contact that does not form silicide. The step (410) may also be used to refresh the second material for subsequent processing.

[0119] The etchant gas used during step (410) may include, for example, a halogen-containing gas or a halide gas—for example, at least one of chlorine (Cl2) or hydrogen chloride or (HCl).

[0120] Step (410) may be performed in the same reaction chamber used during Step (404 and / or 406). Alternatively, Step (410) may be performed in a different reaction chamber, such as a different reaction chamber in a cluster tool that is the same (or different) as the reaction chamber used during Step (404 and / or 406). The pressure and / or temperature within the reaction chamber for Step (410) may be the same or similar to the pressure and / or temperature associated with Step (404 and / or 406). One or more of Steps (404 to 410) may be repeated as desired.

[0121] In some embodiments, the second doped semiconductor layer may be a germanium layer. Advantageously, the second doped semiconductor layer may be a p-type doped germanium layer. Boron and / or gallium may be used as dopants. Advantageously, the germanium layer is doped with boron and gallium. Thus, the second doped semiconductor layer may be grown in a process using a germanium precursor and optionally a boron precursor and / or a gallium precursor. Suitable germanium precursors include germane, such as germane (GeH4), digermaine (Ge2H6), and trigermaine (Ge3H8). Alternatively, a precursor comprising germanium, silicon, and hydrogen, such as lowylsilane (GeH6Si), may be used as a germanium precursor. Suitable boron precursors include borohydrides such as diborane or deuterium-diborane. The gallium precursor may comprise a gallium alkyl, such as, for example, trimethylgallium (TMG), triethylgallium (TEG), tri-isopropylgallium (TiPGa), or tritertiarybutylgallium (TTBGa). Alternatively, the gallium precursor may comprise a gallium halide, such as gallium chloride (GaCl3). Alternatively, the gallium precursor may comprise two alkyl ligands and one halide ligand, such as diethylgallium chloride (DeGaGl). Alternatively, the gallium precursor may comprise a gallium borohydride, such as Ga(BH4)3. In some embodiments, the first precursor is GaH3. In some embodiments, the gallium precursor is selected from R2GaCl, RGaCl2, and GaR3 (where R is ethyl, butyl, or propyl). In some embodiments, this doped germanium layer, used as a second doped semiconductor layer, is at least 1 x 10⁻⁶ 17 atomic / cm 3 Up to 5x10 21 atomic / cm 3 , or at least 1x10 18 atomic / cm 3 Up to 2x10 21 atomic / cm 3, or at least 8x10 18 atomic / cm 3 Up to 1x10 21 atomic / cm 3 , or at least 1x10 19 atomic / cm 3 Dopant or up to 1x10 20 atomic / cm 3 , or 2.5x10 20 atomic / cm 3 Excess, or even 5x10 20 atomic / cm 3 It may contain boron in excess concentrations. In some embodiments, this doped germanium layer is up to 3x10 21 atomic / cm 3 , or at least 8x10 18 atomic / cm 3 Up to 9x10 20 atomic / cm 3 , or at least 1x10 19 atomic / cm 3 Up to 9x10 19 atomic / cm 3 or at least 1x10 20 atomic / cm 3 Gallium may be included at a concentration of . In some embodiments, the so-called doped germanium layer may be grown at a temperature of at least 250°C to a maximum of 800°C, or at least 300°C to a maximum of 450°C. In some embodiments, the so-called doped germanium layer may be grown at a pressure of at least 10 Torr to a maximum of 760 Torr.

[0122] FIG. 11 shows a portion of a device (1100) according to an additional example of the present disclosure. The portion of the device (1100) includes a substrate (1102), a first doped semiconductor layer (1104), a second doped semiconductor layer (1106), and a conductive layer (1108).

[0123] The substrate (1102) may be any substrate material described herein or may include the same. For example, the substrate (1102) may be identical to the substrate (202) and / or the substrate (502).

[0124] The first doped semiconductor layer (1104) may be identical or similar to the first doped semiconductor layer (204 or 602) described above. Similarly, the second doped semiconductor layer (1106) may be identical or similar to the second doped semiconductor layer (302 or 702) described above. The first doped semiconductor layer (1104) and / or the second doped semiconductor layer (1106) may be used to form the source or drain portion of a field-effect transistor (FET), such as a FinFET or other FET device. The use of the first doped semiconductor layer (1104) may reduce the contact resistance between the conductive layer (1108) and the underlying doped semiconductor layer.

[0125] The conductive layer (1108) may include, for example, a metal, such as titanium, nickel, cobalt, nickel-platinum alloy, etc. As a specific example, the contact resistance of a gallium-doped p-type silicon germanium (e.g., SiGe:B:Ga) layer (1106) is 10 without annealing. -9 Ω·cm 2 to about 5x10 -10 Ω·cm 2 , about 5x10 -10 Ω·cm 2 to about 2x10 -10 Ω·cm 2 , or about 2x10 -10 Ω·cm 2 to about 1 x 10 -10 Ω·cm 2 It may be less than

[0126] FIG. 12 illustrates a system (1200) according to an exemplary additional embodiment of the present disclosure. The system (1200) may be used to perform and / or perform a method as described herein or to form a structure or element as described herein.

[0127] In the illustrated example, the system (1200) comprises an optional substrate handling system (1202), one or more reaction chambers (1204), a gas injection system (1206), and an optional wall (1208) disposed between the reaction chamber(s) (1204) and the substrate handling system (1202). The system (1200) may also include a first gas source (1210), a second gas source (1212), a third gas source (1214), a fourth gas source (1216), an exhaust source (1226), and a controller (1228).

[0128] Although shown as four gas sources (1210 to 1216), the system (1200) may include any suitable number of gas sources. Each of the gas sources (1210 to 1216) may include, for example, a precursor gas, such as a precursor (e.g., Group IV, p-type dopant precursor, and / or n-type dopant precursor) as described above, and may include a mixture of such precursors and / or a mixture of one or more precursors together with a carrier gas, such as hydrogen, nitrogen, argon, helium, etc. Additionally or alternatively, one or another of the gas sources (1210 to 1216) may include an etchant, such as a halide, such as hydrogen chloride and / or a chlorine-containing gas such as chlorine. Gas supply sources (1210 to 1216) can be connected to the reaction chamber (1204) through lines (1218 to 1224), each of which may include a flow controller, a valve, a heater, etc.

[0129] The system (1200) may include an appropriate number of reaction chambers (1204) and a substrate handling system (1202). Additionally, one or more reaction chambers (1204) may be cross-flow cold-wall epitaxy reaction chambers or may include such.

[0130] The vacuum source (1226) may include one or more vacuum pumps.

[0131] The controller (1228) may be configured to perform various functions and / or steps described herein. For example, the controller (1228) may be configured to control the flow of gas into a gas injection system to form a first doped semiconductor layer placed on a substrate and to form a second doped semiconductor layer placed on the first doped semiconductor layer as described above. The controller (1228) may include one or more microprocessors, memory elements, and / or switching elements to perform various functions. Although shown as a single unit, the controller (1228) may alternatively include a number of devices. For example, the controller (1228) may be used to control the flow of gas (e.g., by monitoring and / or controlling the flow rate of precursors and / or other gases from sources (1210 to 1216) or by controlling valves, motors, heaters, etc.). Additionally, if the system (1200) includes two or more reaction chambers, the two or more reaction chambers may be coupled to the same / shared controller.

[0132] During the operation of the reactor system (1200), a substrate, such as a semiconductor wafer (not shown), is transferred, for example, from a substrate handling system (1202) to a reaction chamber (1204). Once the substrate(s) are transferred to the reaction chamber (1204), one or more gases from gas sources (1210 to 1216), such as a precursor, a dopant, a carrier gas, an etchant, and / or a purge gas, are introduced into the reaction chamber (1204) through a gas injection system (1206). The gas injection system (1206) can be used to meter and control the gas flow rate of one or more gases (e.g., from one or more gas sources (1210 to 1216)) during substrate processing, and to provide the desired flow of these gases to various locations within the reaction chamber (1204).

[0133] FIG. 13 shows secondary ion mass spectrometry (SIMS) measurement results illustrating advantageous characteristics of some embodiments of the method according to the present disclosure. In particular, SIMS measurements were performed on a sample comprising a first doped semiconductor layer grown on an n-type single-crystal silicon substrate, but other substrates, such as a p-type single-crystal silicon substrate, may also be used. A second doped semiconductor layer was grown on the first doped semiconductor layer. The first doped semiconductor layer was grown using a gallium precursor, a boron precursor, a silicon precursor, and a germanium precursor. Thus, in these embodiments, B is used as the first dopant, and Ga is used as the second dopant during the growth of the first semiconductor layer. The second doped semiconductor layer was grown using a boron precursor, a silicon precursor, and a germanium precursor. Thus, in these exemplary embodiments, both the first and second doped semiconductor layers are p-type silicon germanium. The results of FIG. 13 were based on a process using the following precursors and process conditions during the growth of the first doped semiconductor layer and during the growth of the second doped semiconductor layer: the substrate was maintained at a pressure of at least 30 tor to a maximum of 50 tor, particularly 40 tor, at a temperature of at least 450°C to a maximum of 550°C, particularly 500°C, as measured by a pyrometer suspended above the wafer in the reaction chamber. Silane, particularly SiH4, was used as the silicon precursor. Germaine, particularly GeH4, was used as the germanium precursor. Borohydride, particularly B2H6, was used as the boron precursor. During the growth of the first doped semiconductor layer, a gallium precursor was additionally provided to the reaction chamber. In the process according to the present embodiment, gallium alkyl, particularly triethylgallium, was used as the gallium precursor.In the SIMS measurement embodiment shown in FIG. 13, the following flow rates were used, but other flow rates may also be used as desired to achieve different layer compositions: a flow rate of SiH4 of at least 30 sccm to a maximum of 120 sccm, particularly 60 sccm was used; a flow rate of GeH4 of at least 170 sccm to a maximum of 650 sccm, particularly 330 sccm was used; a flow rate of B2H6 of at least 2 sccm to a maximum of 10 sccm, particularly 5 sccm was used; and a flow rate of triethylgallium of at least 3 sccm to a maximum of 12 sccm, particularly 3 sccm was used. The SIMS measurement in FIG. 13 indicates that the gallium concentration increases toward the surface of the doped semiconductor layer (i.e., toward a depth of 0 nm). Unless the present invention is bound by any particular theory or mode of operation, this is believed to be caused by gallium surface segregation. This effect is advantageously utilized in the present method to achieve a high surface gallium concentration, which can consequently result in low contact resistance of the metal contact formed on the second doped semiconductor layer. SIMS measurements show a carbon concentration exhibiting a peak located at the first doped semiconductor layer (in this case, SiGe:B:Ga). This carbon peak is caused by carbon terminated in the first doped semiconductor layer from the organometallic gallium precursor used. During the growth of the second doped semiconductor layer, no gallium precursor or other carbon-containing precursor is used in these embodiments so that the second doped semiconductor layer is substantially carbon-free. Thus, by using this specific order of the first doped semiconductor layer and the second doped semiconductor layer, a high gallium surface concentration and a low carbon surface concentration can be obtained, which can result in excellent contact resistance. Note that FIG. 13 indicates an apparent increase in carbon concentration toward the surface of the second doped semiconductor layer (C clearly increases from a depth of 30 nm to a depth of 0 nm).This is the knock-on effect, a defect caused by carbon adsorption on the sample surface, and it is noted that the carbon concentration does not actually increase toward the sample surface.

[0134] The exemplary embodiments of the present disclosure described above do not limit the scope of the invention, because these embodiments are merely examples of embodiments of the invention, which are defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the invention. Certainly, various modifications of the invention, such as alternative useful combinations of the described elements, in addition to those shown and described herein, may be apparent from the description to those skilled in the art. Such modifications and embodiments are also intended to be within the scope of the appended claims.

Claims

Claim 1 A system comprising: one or more reaction chambers; a gas injection system fluidly coupled to at least one of the one or more reaction chambers; a first gas source; a second gas source; a third gas source; an exhaust source; and a controller, wherein the controller is configured to control the flow of gas into the gas injection system to form a first doped semiconductor layer disposed on the surface of a substrate, a second doped semiconductor layer disposed on the first doped semiconductor layer, and a cap layer disposed on the second doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and the second doped semiconductor layer comprises the first dopant; wherein the first doped semiconductor layer is optionally formed on a first portion of the surface of the substrate; and wherein the second doped semiconductor layer is optionally formed on the first doped semiconductor layer, and the concentration of carbon is greater in the first doped semiconductor layer than in the second doped semiconductor layer. Claim 2 A system according to claim 1, wherein the controller is configured to perform the step of etching the first doped semiconductor layer and the second doped semiconductor layer placed on the second surface within the one or more reaction chambers. Claim 3 A system according to claim 1, further comprising a substrate handling system. Claim 4 In paragraph 3, the system further comprises a wall between the substrate handling system and the one or more reaction chambers. Claim 5 A system according to claim 1, further comprising a fourth gas supply source. Claim 6 A system according to claim 1, wherein one or more reaction chambers comprise a cross-flow cold-wall epitaxy reaction chamber. Claim 7 A system according to claim 1, comprising two or more reaction chambers, wherein the two or more reaction chambers are coupled to the controller. Claim 8 A system according to claim 1, wherein the first gas source comprises a chlorine-free precursor. Claim 9 In paragraph 8, the system, wherein the second gas supply source comprises a first dopant. Claim 10 In claim 9, the system comprises a first dopant including a first p-type dopant. Claim 11 In claim 9, the system, wherein the third gas supply source comprises a second dopant. Claim 12 In paragraph 11, the system comprises a second dopant including a second p-type dopant. Claim 13 In paragraph 11, the system wherein the second dopant comprises gallium, aluminum, or indium. Claim 14 A system according to claim 13, wherein the first dopant comprises boron and the second dopant comprises gallium. Claim 15 A system according to claim 1, wherein the first doped semiconductor layer comprises p-type silicon germanium. Claim 16 In claim 15, the system wherein the second doped semiconductor layer comprises p-type silicon germanium. Claim 17 A system according to claim 1, wherein the cap layer comprises at least one of silicon and germanium. Claim 18 A system according to claim 17, wherein the cap layer further comprises a p-type dopant selected from boron and gallium. Claim 19 A system according to claim 1, wherein the step of forming the first doped semiconductor layer comprises the step of providing a silicon precursor, a germanium precursor, a boron precursor, and a gallium precursor to the reaction chamber.

Images