Semiconductor package

Abstract

The semiconductor package of the present invention comprises a connecting substrate having a cavity inside, a third semiconductor chip disposed between the connecting substrates, a first semiconductor chip and a second semiconductor chip located above the third semiconductor chip and connected to each other by the third semiconductor chip, and a molding film covering the third semiconductor chip and the first and second semiconductor chips. The third semiconductor chip is characterized by including a plurality of first bumps exposed on the molding film to be connected to the first and second semiconductor chips.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting the semiconductor chip onto a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the recent advancement of the electronics industry, semiconductor packages are evolving in various directions with the goals of miniaturization, weight reduction, and manufacturing cost reduction. Furthermore, as their applications expand to include high-capacity storage devices, a wide variety of semiconductor packages are emerging. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a semiconductor package with improved reliability.

[0004] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A semiconductor package according to the present invention comprises a connecting substrate having a cavity inside, a third semiconductor chip disposed between the connecting substrates, a first semiconductor chip and a second semiconductor chip located above the third semiconductor chip and connected to each other by the third semiconductor chip, and a molding film covering the third semiconductor chip and the first and second semiconductor chips.

[0006] The third semiconductor chip is characterized by including a plurality of first bumps exposed on the molding film to be connected to the first and second semiconductor chips.

[0007] A semiconductor package according to the present invention comprises a connecting substrate having a cavity inside, a third semiconductor chip disposed within the cavity, a first semiconductor chip and a second semiconductor chip located above the third semiconductor chip and connected to each other by the third semiconductor chip, and a molding film covering the third semiconductor chip and the first and second semiconductor chips.

[0008] The third semiconductor chip comprises a plurality of first bumps exposed on the molding film to be connected to the first and second semiconductor chips, and the connecting substrate comprises a plurality of second bumps exposed on the molding film to be connected to the first and second semiconductor chips.

[0009] A semiconductor package according to the present invention comprises a connecting substrate having a cavity inside, a third semiconductor chip disposed in the cavity, a molding film interposed between the third semiconductor chip and the connecting substrate and surrounding the upper surface of the third semiconductor chip and the connecting substrate, a first semiconductor chip mounted close to one side of the connecting substrate on the molding film and connected to the connecting substrate and the third semiconductor chip, and a second semiconductor chip mounted close to the other side of the connecting substrate on the molding film and connected to the connecting substrate and the third semiconductor chip.

[0010] The third semiconductor chip comprises a plurality of first bumps protruding from its upper surface and connected to the lower surface of the first and second semiconductor chips, and a first anti-oxidation layer covering the surface of the first bumps, and the connecting substrate comprises a plurality of second bumps protruding from its upper surface and connected to the lower surface of the first or second semiconductor chip, and a second anti-oxidation layer covering the surface of the second bumps, wherein the third semiconductor chip has the same thickness as the connecting substrate, the first bumps and the second bumps have the same vertical length, the diameter of the first bumps is 10μm to 40μm, and the diameter of the second bumps is 50μm to 100μm. Effects of the invention

[0011] According to the present invention, a third semiconductor chip acts as a bridge interposer, and by directly connecting the third semiconductor chip to the first and second semiconductor chips through bumps, electrical connection between the first and second semiconductor chips can be performed more stably and quickly.

[0012] In addition, by connecting the first and second semiconductor chips to each other through the third semiconductor chip, the process of forming a separate rewiring substrate for connecting the first and second semiconductor chips can be omitted, thereby reducing the manufacturing cost of the semiconductor package. Brief explanation of the drawing

[0013] FIG. 1 is a plan view for illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a drawing for explaining a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. FIGS. 3 to 11 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention. Specific details for implementing the invention

[0014] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0015] FIG. 1 is a plan view for explaining a semiconductor package according to embodiments of the present invention, FIG. 2 is a cross-sectional view along I-I' of FIG. 1 for explaining a semiconductor package according to embodiments of the present invention, FIG. 3 is an enlarged view showing the “A” portion of FIG. 2.

[0016] Referring to FIGS. 1 and 2, the semiconductor package (1) includes a connection substrate (100), a third semiconductor chip (300), a first semiconductor chip (CH1), a second semiconductor chip (CH2), a molding film (400), a redistribution substrate (500), a solder resist layer (600), and a plurality of external connection terminals (700).

[0017] The connection board (100) may be a printed circuit board (PCB). The connection board (100) may have a cavity (CV) formed therein.

[0018] The third semiconductor chip (300) may be placed in the hollow (CV) of the connecting substrate (100). In this specification, the third semiconductor chip (300) may also be referred to as a 'bridge interposer'. The connecting substrate (100) has a first thickness (t1) on one side of the third semiconductor chip (300) and a second thickness (t2) on the other side of the third semiconductor chip (300). The first thickness (t1) and the second thickness (t2) are the same. The third semiconductor chip (300) may have a thickness similar to or the same as that of the connecting substrate (100). The thickness (t3) of the third semiconductor chip (300) may be formed to be the same as the first thickness (t1) and the second thickness (t2). The thickness of the third semiconductor chip (300) is preferably 100 μm to 300 μm, and may be, for example, 200 μm.

[0019] The third semiconductor chip (300) may be a chip or an interposer substrate that includes a predetermined circuit pattern for electrical connection between the first semiconductor chip (CH1) and the second semiconductor chip (CH2) mounted on the upper side. Additionally, the third semiconductor chip (300) may serve to connect the first semiconductor chip (CH1) and the second semiconductor chip (CH2) to the rewiring substrate (500). The third semiconductor chip (300) may include a third semiconductor substrate (SB) and a third interlayer insulating film (IL) disposed thereon. A wiring layer (330) may be disposed within the third interlayer insulating film (IL). The third semiconductor chip (300) may include a plurality of through-vias (340) that penetrate a portion of the third semiconductor substrate (SB) and the third interlayer insulating film (IL) and are connected to the wiring layer (330).

[0020] The first semiconductor chip (CH1) and the second semiconductor chip (CH2) may each be one selected from among memory device chips such as flash memory chips, DRAM chips, SRAM chips, EEPROM chips, PRAM chips, MRAM chips, ReRAM chips, HBM (high bandwidth memory) chips, HMC (hybrid memory cubic) chips, etc., and MEMS (microelectromechanical system) device chips. The first semiconductor chip (CH1) and the second semiconductor chip (CH2) may each include chip pads (CP) disposed on their lower portions. Internal connection members (CM) are each bonded to the chip pads (CP). The internal connection members (CM) may be, for example, conductive bumps, conductive pillars, and / or solder balls.

[0021] The third semiconductor chip (300) can be directly connected to the first semiconductor chip (CH1) and the second semiconductor chip (CH2). The third semiconductor chip (300) may include a plurality of first bumps (310) protruding from its upper surface to be connected to the first and second semiconductor chips (CH1, CH2). The first bumps (310) are connected to internal connecting members (CM).

[0022] Each of the plurality of first bumps (310) may have a pillar shape. The first bump (310) may contain copper (Cu). The diameter (d1) of the first bump (310) may be 10 μm to 40 μm. A first oxidation-preventing layer (350) may be formed on the surface of the first bump (310). The first oxidation-preventing layer (350) may contain nickel and gold. The first oxidation-preventing layer (350) may be an electroless nickel-gold plating layer. The first oxidation-preventing layer (350) may prevent oxidation of the first bump (310). The first oxidation-preventing layer (350) may be in contact with internal connecting members (CM).

[0023] The first oxidation-preventing layer (350) may include a nickel plating layer and a gold plating layer. The first oxidation-preventing layer (350) may have a multi-layer structure. The first oxidation-preventing layer (350) may be in a form where the nickel plating layer surrounds the gold plating layer.

[0024] The first oxidation-preventing layer (350) has excellent adhesion so that a plurality of first bumps (310) can be stably connected to the first and second semiconductor chips (CH1, CH2), and at the same time, has excellent conductivity so that a plurality of first bumps (310) can be effectively electrically connected to the first and second semiconductor chips (CH1, CH2).

[0025] The third semiconductor chip (300) may further include a plurality of upper chip pads (321) and a plurality of lower chip pads (322). A plurality of upper chip pads (321) may be formed on the upper surface of the third semiconductor chip (300), and a plurality of lower chip pads (322) may be formed on the lower surface of the third semiconductor chip (300). A plurality of upper chip pads (321) and a plurality of lower chip pads (322) may have a flat shape. A plurality of first bumps (310) described above may be located on the upper surface of a plurality of upper chip pads (321). A plurality of upper chip pads (321) may correspond to a plurality of first bumps (310). A plurality of lower chip pads (322) may be connected to a redistribution board (500) described later.

[0026] The molding film (400) can cover the third semiconductor chip (300) and the first and second semiconductor chips (CH1, CH2). The molding film (400) can cover the space between the third semiconductor chip (300) and the first semiconductor chip (CH1), and the space between the third semiconductor chip (300) and the second semiconductor chip (CH2).

[0027] Additionally, the molding film (400) can cover the upper surface of the third semiconductor chip (300) and the connecting substrate (100). However, the molding film (400) can cover the upper surface of the third semiconductor chip (300) such that a portion of the plurality of first bumps (310) is exposed on the molding film (400). The lower end of the first oxidation-preventing layer (350) is in contact with the upper surface of the molding film (400).

[0028] The molding film (400) may include an insulating polymer, for example, an epoxy molding compound (EMC).

[0029] The first semiconductor chip (CH1) and the second semiconductor chip (CH2) can be mounted on the molding film (400). The first semiconductor chip (CH1) can be mounted on the molding film (400) so as to overlap one side of the third semiconductor chip (300), and the second semiconductor chip (CH2) can be mounted on the molding film (400) so as to overlap the other side of the third semiconductor chip (300).

[0030] The connecting substrate (100) may include a plurality of second bumps (210) protruding from its upper surface. The plurality of second bumps (210) may be exposed to the upper surface of the molding film (400) and connected to the first and second semiconductor chips (CH1, CH2).

[0031] A portion of the second bump (210) protruding from the upper surface of the connecting substrate (100) may be connected to the first semiconductor chip (CH1), and another portion of the second bump (210) protruding from the upper surface of the connecting substrate (100) may be connected to the second semiconductor chip (CH2).

[0032] Each of the plurality of second bumps (210) may have a pillar shape. The second bumps (210) may contain copper (Cu). The diameter (d2) of the second bump (210) is larger than the diameter (d1) of the first bump (310). Preferably, the diameter (d2) of the second bump (210) may be 50 μm to 100 μm. A second anti-oxidation layer (250) may be formed on the surface of the second bump (210), similar to the first bump (310). The second anti-oxidation layer (250) can prevent oxidation of the second bump (210).

[0033] The second oxidation-preventing layer (250) may include nickel and gold. The second oxidation-preventing layer (250) may be an electroless nickel-gold plating layer. The second oxidation-preventing layer (250) may prevent oxidation of the second bump (210). The second oxidation-preventing layer (250) may be in contact with internal connecting members (CM). The bottom of the second oxidation-preventing layer (250) is in contact with the upper surface of the molding film (400).

[0034] As previously explained, since the third semiconductor chip (300) and the connecting substrate (100) have the same thickness, the vertical lengths (V1, V2) of the plurality of first bumps (310) of the third semiconductor chip (300) and the plurality of second bumps (210) of each connecting substrate (100) can be formed identically so that the semiconductor chips described later can be mounted on the third semiconductor chip (300) and the connecting substrate (100). The vertical length (V1) of the first bump (310) and the vertical length (V2) of the second bump (210) may be 10 μm to 20 μm.

[0035] The second anti-oxidation layer (250) has excellent adhesion so that a plurality of second bumps (210) can be stably connected to the first and second semiconductor chips (CH1, CH2), and at the same time, has excellent conductivity so that signal transmission to each of the first semiconductor chip (CH1) and the second semiconductor chip (CH2) can be effectively performed through the connecting substrate (100).

[0036] The connecting substrate (100) may further include a conductive pillar (230) penetrating the interior. The length of the conductive pillar (230) penetrating the interior of the connecting substrate (100) may be formed to be equal to the thickness of the connecting substrate (100). That is, the conductive pillar (230) may have a shape extending from the lower surface to the upper surface of the connecting substrate (100).

[0037] Each of the conductive pillars (230) can be connected to each of the second bumps (210) formed on the upper part. Each of the conductive pillars (230) may contain a metal such as copper, tin, lead, silver, aluminum, gold, or nickel.

[0038] The connecting substrate (100) may further include an upper substrate pad (221) and a lower substrate pad (222). The upper substrate pad (221) may be located on the upper side of the conductive pillar (230), and the lower substrate pad (222) may be located on the lower side of the conductive pillar (230). The upper substrate pad (221) and the lower substrate pad (222) may have a flat shape. The upper substrate pad (221) of the connecting substrate (100) may be provided to have the same thickness as the upper chip pad (321) of the third semiconductor chip (300), and the lower substrate pad (222) of the connecting substrate (100) may be provided to have the same thickness as the lower chip pad (322) of the third semiconductor chip (300).

[0039] The upper substrate pad (221) can be connected to the second bump (210) located on the upper side. In this case, as described above, a portion of the second bump (210) may be exposed to the upper side of the molding film (400), and thus can be connected to the first or second semiconductor chip (CH1, CH2) on the upper side.

[0040] The lower substrate pad (222) can be connected to the rewiring substrate (500) described later, which is located at the bottom.

[0041] Meanwhile, some of the multiple first bumps (310) of the third semiconductor chip (300) may be connected to the first semiconductor chip (CH1) and some may be connected to the second semiconductor chip (CH2).

[0042] A plurality of first bumps (310) and a plurality of second bumps (210) are connected to a first semiconductor chip (CH1) and a second semiconductor chip (CH2) mounted on the upper part of a molding film (400), thereby connecting the first and second semiconductor chips (CH1, CH2) to a third semiconductor chip (300) and a connecting substrate (100), while simultaneously supporting the first semiconductor chip (CH1) and the second semiconductor chip (CH2). At this time, the upper surface of the plurality of first bumps (310) and the upper surface of the plurality of second bumps (210) may be located on the same line. As the thickness of the third semiconductor chip (300) is formed to be similar to or equal to the thickness of the connecting substrate (100), the plurality of first bumps (310) do not need to be formed longer than the second bumps (210). The thickness of the third semiconductor chip (300) is preferably 100 μm to 300 μm, and for example, preferably 200 μm.

[0043] Inside the third semiconductor chip (300), a wiring layer (330) may be formed to connect the first and second semiconductor chips (CH1, CH2) by connecting a plurality of first bumps (310). The wiring layer (330) may include a plurality of wiring patterns (331). The wiring patterns (331) may be connected to upper pads (311) connected to the first bumps (310) on the upper surface of the third semiconductor chip (300). For example, as illustrated, when wiring patterns (331a) are connected to two upper pads (311), the wiring layer (330) can be connected to the first bumps (310) provided on the upper surface of each of the two upper pads (311). In other words, the wiring layer (330) is simultaneously connected to the first bump (310) connected to the first semiconductor chip (CH1) and the first bump (310) connected to the second semiconductor chip (CH2) among the plurality of first bumps (310), thereby enabling the first semiconductor chip (CH1) and the second semiconductor chip (CH2) to be connected.

[0044] In addition, a plurality of through-silicon vias (TSV: through-silicon via, 340) may be formed inside the third semiconductor chip (300) so as to be connected to the wiring layer (330) and provided below the wiring layer (330). The plurality of through-silicon vias (340) may be spaced apart from each other. The plurality of through-silicon vias (340) may extend in a direction perpendicular to the longitudinal direction of the third semiconductor chip (300).

[0045] Each side of a plurality of through-vias (340) may be surrounded by an insulating layer (341). The insulating layer (341) may be formed of an oxide film or a nitride film. For example, the insulating layer (341) may be formed of a silicon oxide film (SiO2) or a silicon nitride film (SiNx). By surrounding the sides of the through-vias (340), the insulating layer (341) can electrically insulate the plurality of through-vias (340) from each other from the third semiconductor substrate (SB).

[0046] As illustrated, the wiring layer (330) may include a wiring structure (S1) that connects one of a plurality of first bumps (310) and one of a plurality of through vias (340). By being connected to the first bump (310) by the wiring structure (S1), the through via (340) can transmit a signal generated from the first or second semiconductor chips (CH1, CH2) connected to the first bump (310) to the outside, or transmit a signal generated from the outside to the first or second semiconductor chip (CH1, CH2) connected to the first bump (310). In this case, by transmitting the signal through the through via (340) inside the third semiconductor chip (300), the signal can be transmitted more stably and quickly.

[0047] Meanwhile, the redistribution board (500) may be provided below the connection board (100) and the third semiconductor chip (300). The redistribution board (500) may be connected to a plurality of conductive pillars (230) and a plurality of through vias (340). The redistribution board (500) may include a redistribution insulating layer (510) and a plurality of redistribution patterns (520) formed within the redistribution insulating layer.

[0048] In this embodiment, the redistribution insulating layer (510) has a single layer, but may also be formed as a plurality of stacked layers. The number of stacked redistribution insulating layers (510) is not limited to that illustrated and can be varied in many ways. The redistribution insulating layer (510) may include an insulating polymer or a photoimageable dielectric (PID). For example, the photoimageable polymer may include at least one of photoimageable polyimide, polybenzoxazole (PBO), phenol-based polymer, or benzocyclobutene-based polymer.

[0049] A redistribution pattern (520) may be placed on a redistribution insulating layer (510). A plurality of redistribution patterns (520) may be provided. The redistribution pattern (520) may include via portions (VP) and pad portions (PP). The sides of the via portions (VP) may be sloped. The via portions (VP) may have a width that narrows from bottom to top. The redistribution patterns (520) may include a metal such as, for example, copper (Cu), aluminum (Al), gold (Au), nickel (Ni), or titanium (Ti).

[0050] A solder resist layer (600) may be provided below the redistribution board (500). The solder resist layer (600) covers the lower surface of the redistribution board (500), but may expose at least a portion of the lower surface of the redistribution board (500). A plurality of external connection terminals (700) may be provided on the lower surface of the redistribution board (500) exposed by the solder resist layer (600).

[0051] Each external connection terminal (700) may include at least one of a solder ball, a conductive bump, and a conductive pillar. The solder ball may include Sn or SnAg.

[0053] In this embodiment, the first and second semiconductor chips (CH1, CH2) can be electrically connected to external connection terminals (700) through the connection substrate (100) and the third semiconductor chip (300), so that it is possible to receive a signal from the outside or send a signal to the outside through the external connection terminals (700).

[0055] FIGS. 3 to 11 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention. Hereinafter, content that overlaps with what has been previously described is omitted.

[0056] Referring to FIG. 3, a connection substrate (100) and a third semiconductor chip (300) may be provided on a carrier substrate (50). The connection substrate (100) may include a cavity (CV). The third semiconductor chip (300) may be placed in the cavity (CV) of the connection substrate (100).

[0057] The carrier substrate (50) may include, for example, a polymer. As an example, the carrier substrate (50) may include an adhesive tape, and accordingly, the connecting substrate (100) and the third semiconductor chip (300) may be attached to the carrier substrate (50).

[0058] The third semiconductor chip (300) may include a plurality of first bumps (310) protruding from its upper surface. A plurality of upper chip pads (321) may be formed on the upper surface of the third semiconductor chip (300), and a plurality of first bumps (310) may be formed on the upper surface of each of the plurality of upper chip pads (321).

[0059] The third semiconductor chip (300) may include a wiring layer (330) connected to a plurality of first bumps (310) within it. The wiring layer (330) may include a plurality of wiring patterns (331). Additionally, the third semiconductor chip (300) may include a plurality of through-vias (340) connected to the wiring layer (330) within it. A plurality of lower chip pads (322) connected to each of the plurality of through-vias (340) may be formed on the lower surface of the third semiconductor chip (300). Each of the plurality of through-vias (340) may have its upper side connected to the wiring pattern (331) of the wiring layer (330) and its lower side connected to the lower chip pad (322).

[0060] A connecting substrate (100) may include a plurality of second bumps (210) protruding from its upper surface. A plurality of upper substrate pads (221) may be formed on the upper surface of the connecting substrate (100), and a plurality of second bumps (210) may be formed on the upper surface of each of the plurality of upper substrate pads (221). A plurality of lower substrate pads (222) may be formed on the lower surface of the connecting substrate (100).

[0061] The connecting substrate (100) may include a plurality of conductive pillars (230) penetrating the interior thereof. The plurality of conductive pillars (230) may extend from the lower surface to the upper surface of the connecting substrate (100). An upper substrate pad (221) may be located on the upper surface of each conductive pillar (230), and a lower substrate pad (222) may be located on the lower surface of each conductive pillar.

[0062] Referring to FIG. 4, a molding film (400) may be formed on a carrier substrate (50). The molding film (400) may cover the upper surface of the carrier substrate (50), the third semiconductor chip (300), and the connecting substrate (100). The molding film (400) may cover the space between the third semiconductor chip (300) and the connecting substrate (100), the upper surface of the third semiconductor chip (300), and the upper surface of the connecting substrate (100). The molding film (400) may cover a plurality of first bumps (310) and a plurality of second bumps (210).

[0063] Referring to FIG. 5, the carrier substrate (50) can be flipped over so that the lower surface of the third semiconductor chip (300) and the lower surface of the connecting substrate (100) face upward. Afterward, the carrier substrate (50) can be removed.

[0064] The carrier substrate (50) is removed so that lower conductive pads (222) adjacent to the lower surface of each connecting substrate (100) and lower pads adjacent to the lower surface of the third semiconductor chip (300) can be exposed.

[0065] Referring to FIG. 6, a redistribution insulating layer may be formed on the lower surface of each connecting substrate (100) and on the lower surface of the third semiconductor chip (300). The redistribution substrate (500) may cover the lower surface of each connecting substrate (100) and the lower surface of the third semiconductor chip (300).

[0066] A redistribution insulating layer may be patterned to form a plurality of holes within the redistribution insulating layer. The holes may expose the lower conductive pads (222) of each connecting substrate (100) and the lower pad of the third semiconductor chip (300). Patterning the redistribution insulating layer may be performed by an exposure process and a development process.

[0067] Referring to FIG. 7, redistribution patterns (520) may be formed on a redistribution insulating layer. For example, forming the redistribution pattern (520) may include forming a seed layer on the redistribution insulating layer, forming a conductive film by performing an electroplating process using the seed layer as an electrode, and patterning the seed film and the conductive film. The conductive film may include a metal such as copper (Cu). The redistribution pattern (520) may include a wiring portion provided within a hole and a via portion provided on the redistribution insulating layer.

[0068] Thus, a redistribution board (500) can be formed on the lower surface of each connecting board (100) and on the lower surface of the third semiconductor chip (300).

[0069] Referring to FIG. 8, a solder resist layer (600) covering the lower surface of a redistribution board (500) may be formed. The solder resist layer (600) may be formed to expose at least a portion of the lower surface of the redistribution board (500). That is, the solder resist layer (600) may be formed to expose the redistribution patterns (520) of the redistribution board (500). The solder resist layer (600) may be formed by applying a solder resist material to cover the lower surface of the redistribution board (500) and then etching it so that at least a portion of the redistribution board (500) is exposed.

[0070] Referring to FIG. 9, external connection terminals (700) may be formed on the lower surface of the redistribution board (500) exposed by the solder resist layer (600).

[0071] Referring to FIG. 10, the carrier substrate (50) can be flipped over again so that the lower surface of the third semiconductor chip (300) and the lower surface of the connecting substrate (100) face downward.

[0072] A grinding process may be performed on the molding film (400) so that the molding film (400) can be flattened. A grinding process may be performed on the molding film (400) so that the upper surface of a plurality of first bumps (310) and the upper surface of a plurality of second bumps (320) may be exposed.

[0073] Referring to FIG. 11, a portion of the molding film (400) can be removed through an etching process so that a plurality of first bumps (310) and a plurality of second bumps (210) are exposed on the upper surface of the molding film (400). Afterward, an electroless nickel-gold plating process can be performed on the surface of the exposed plurality of first bumps (310) and a plurality of second bumps (210).

[0074] First, an electroless nickel plating layer can be formed by contacting a nickel plating solution to the surface of each of the plurality of first bumps (310) and the plurality of second bumps (210), and then a gold plating layer can be formed by contacting a gold plating solution to the nickel plating layer to form a gold plating layer. As the surface of each of the plurality of first bumps (310) and the plurality of second bumps (210) is covered by the oxidation prevention layer (250, 350), oxidation of the plurality of first bumps (310) and the plurality of second bumps (210) can be prevented.

[0075] Referring again to FIG. 2, a first semiconductor chip (CH1) and a second semiconductor chip (CH2) can be mounted on a plurality of first bumps (310) and a plurality of second bumps (210). That is, the first semiconductor chip (CH1) can be mounted on the first bump (310) of the third semiconductor chip (300) and the second bump (210) of the adjacent connecting substrate (100), and the second semiconductor chip (CH2) can be mounted on the first bump (310) of the third semiconductor chip (300) and the second bump (210) of the adjacent connecting substrate (100).

[0076] The first semiconductor chip (CH1) and the second semiconductor chip (CH2) may each include chip pads (CP) disposed at the bottom thereof and internal connecting members (CM) bonded to each of the chip pads (CP). The first bump (310) and the second bump (210) may be connected to the internal connecting members (CM).

[0077] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor package comprising: a connecting substrate having a cavity inside; a third semiconductor chip disposed between the connecting substrates; a first semiconductor chip and a second semiconductor chip located above the third semiconductor chip and connected to each other by the third semiconductor chip; and a molding film covering the third semiconductor chip and the first and second semiconductor chips, wherein the third semiconductor chip includes a plurality of first bumps exposed on the molding film to be connected to the first and second semiconductor chips, a part of the connecting substrate is connected to the first semiconductor chip and another part of the connecting substrate is connected to the second semiconductor chip, and the connecting substrate includes a conductive pillar penetrating the interior of the connecting substrate; and a plurality of second bumps formed on the upper surface of the conductive pillars to be exposed above the molding film and connected to the first or second semiconductor chip. Claim 2 In claim 1, the third semiconductor chip is a semiconductor package having the same thickness as the connecting substrate. Claim 3 A semiconductor package according to claim 2, wherein the thickness of the third semiconductor chip is 100μm to 300μm. Claim 4 A semiconductor package according to claim 1, wherein the first bump has a pillar shape and the diameter of the first bump is 10 μm to 40 μm. Claim 5 A semiconductor package according to claim 4, further comprising an anti-oxidation layer covering the surface of the first bump. Claim 6 In claim 1, the third semiconductor chip is connected to the plurality of first bumps to connect the first and second semiconductor chips, and the semiconductor package includes a wiring layer including a plurality of wirings. Claim 7 In claim 6, the third semiconductor chip comprises: a semiconductor package further including a plurality of through-vias provided below the wiring layer to be connected to the wiring layer, some of which transmit a signal to the first semiconductor chip and other parts of which transmit a signal to the second semiconductor chip. Claim 8 A semiconductor package according to claim 7, further comprising: a rewiring substrate provided below the connection substrate and the third semiconductor chip and connected to the through via; a solder resist layer covering the lower surface of the rewiring substrate, but exposing at least a portion of the lower surface of the rewiring substrate; and a plurality of external connection terminals provided on the lower surface of the rewiring substrate exposed by the solder resist layer. Claim 9 delete Claim 10 In claim 1, the first bump and the second bump are semiconductor packages having the same vertical length.

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