Dram cache system and operating method of the same

Abstract

A DRAM cache system and a method of operation thereof are disclosed. A method of operation of a DRAM cache system according to one disclosed embodiment is a method of operation of a DRAM cache system comprising a front-end module including a Translation Lookaside Buffer (TLB) and a Page Table Entry (PTE) and a back-end module, wherein in the front-end module, when there is a TLB miss for a memory request, the PTE is examined and, if there is a tag miss, a miss handler is called; and through the miss handler, a tag update corresponding to the memory request is performed and a cache fill command is offloaded to the back-end module.

Description

Technology Field

[0001] An embodiment of the present invention relates to a DRAM cache system and a method of operating the same. Background Technology

[0002] As new applications increasingly demand larger memory bandwidth and capacity, heterogeneous memory systems combine high-bandwidth on-package DRAM (Dynamic Random Access Memory) with large-capacity off-package memory. Furthermore, heterogeneous memory systems design on-package DRAM as a cache, and DRAM cache (DC) designs are classified into two categories: hardware-based and OS-managed methods.

[0003] Figure 1 is a schematic diagram illustrating the operation of a typical hardware-based DRAM cache. Referring to Figure 1, the hardware-based DRAM cache offloads the handling of misses for memory requests to the MSHR (Miss Status / Information Holding Register), thereby allowing it to process subsequent memory requests without waiting for a preceding miss to be completed. In other words, the hardware-based DRAM cache performs a non-blocking miss handling function.

[0004] In addition, the hardware-based method can minimize effective miss latency because the controller of the DRAM cache can send a response to the last-level cache as soon as the requested memory block arrives from off-package memory without waiting for the entire cache.

[0005] However, since hardware-based (HW-based) DRAM caches store metadata (e.g., tags, valid bits, dirty bits, etc.) in on-package DRAM, accessing metadata results in additional bandwidth consumption in the on-package DRAM, which increases the valid cycle time of DRAM cache access and causes performance degradation.

[0006] Figure 2 is a schematic diagram illustrating the operation of a typical OS-managed DRAM cache. Referring to Figure 2, the OS-managed DRAM cache exposes the on-package DRAM to the OS and stores data in page units. Here, the Page Table Entry (PTE) stores a tag (i.e., cache frame number) and searches for it in the Translation Lookaside Buffer (TLB), allowing the OS-managed caching mechanism to be used without modifying the memory controller. Since the OS-managed method can directly obtain the cache address (CA) upon a TLB hit, the bandwidth of the on-package DRAM is not wasted on metadata transmission, thereby providing ideal DRAM Cache (DC) access time.

[0007] However, OS management systems implement a blocking cache in that applications are interrupted while the OS handles DRAM Cache (DC) misses. In other words, application interruption is inevitable in OS management methods because the OS performs a cache fill upon a DC miss to guarantee a data hit upon a tag hit. Since OS management methods use coupled tag-data management where a tag hit guarantees a data hit, the tag is updated only after the cache fill is completed, resulting in a delay.

[0008] Therefore, a method is required to rapidly update tags without interrupting the application, without generating additional bandwidth in the on-package DRAM due to metadata transmission in the event of a tag miss. The problem to be solved

[0009] The present invention aims to provide a DRAM cache system capable of minimizing delay time in the event of a tag miss and a method of operating the same.

[0010] Meanwhile, the technical problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0011] A DRAM cache system according to one disclosed embodiment is a DRAM cache system comprising a front-end module and a back-end module, wherein the front-end module may be configured to perform non-blocking miss processing through a decoupled tag-data management method.

[0012] The above front-end module includes a Translation Lookaside Buffer (TLB) and a Page Table Entry (PTE), and when there is a TLB miss for a memory request, it checks the PTE; if there is a tag miss, it calls a miss handler, performs a tag update corresponding to the memory request through the miss handler, and can offload a cache fill command to the back-end module.

[0013] The above front-end module further includes a page descriptor comprising a physical page descriptor and a cache page descriptor, wherein the physical page descriptor includes two additional bits, a cache (cached: C) and a non-cacheable (non-cacheable: NC), wherein the cache (cached: C) bit is a bit indicating whether the corresponding page is cached in a DRAM cache, and the non-cacheable (non-cacheable: NC) bit is a bit indicating whether the corresponding page is cacheable, and the cache (cached: C) and non-cacheable (non-cacheable: NC) bits may be added to an unused field of the PTE (Page Table Entry).

[0014] The above front-end module can determine a tag hit or a tag miss through the cache bit and the non-cache bit added to the unused field of the PTE during the PTE check.

[0015] The above front-end module further includes a background removal daemon that pre-removes cache frames from a DRAM cache, and the background removal daemon can offload write-back commands to the back-end module if the pre-removed pages are dirty.

[0016] The back-end module may include an interface that receives the cache fill command or the write-store command from the front-end module.

[0017] The above interface is a register and may be composed of fields for a State bit, a Type bit, a PFN (Physical Frame Number) bit, a CFN (Cache Frame Number) bit, and an Offset bit.

[0018] The status bit indicates whether the interface is in use, the type bit specifies the command type of the cache fill command or the write-store command, the PFN bit stores the PFN (Physical Frame Number) corresponding to the cache fill command or the write-store command, and the CFN bit can store the CFN (Cache Frame Number) corresponding to the cache fill command or the write-store command.

[0019] The back-end module may allocate one or more PCSHRs (Page Copy Status / Information Holding Registers) to process the command when the interface receives the cache fill command or the write save command from the front-end module.

[0020] The back-end module may further include a comparator that compares the CFN (Cache Frame Number) included in the cache access with the CFN of the PCSHR when a cache access is received.

[0021] The above comparator may, if the comparison result shows that there is a CFN tag corresponding to a cache access in the PCSHR, consider the cache access as a data miss and create a sub-block in the PCSHR to handle the data miss.

[0022] The above comparator may consider the cache access as a data hit if, as a result of the comparison, there is no CFN tag corresponding to the cache access in the PCSHR.

[0023] A method of operation of a DRAM cache system according to a disclosed embodiment is a method of operation of a DRAM cache system comprising a front-end module including a Translation Lookaside Buffer (TLB) and a Page Table Entry (PTE) and a back-end module, wherein the front-end module checks the PTE when there is a TLB miss for a memory request and, if there is a tag miss, calls a miss handler; and performs a tag update corresponding to the memory request through the miss handler and offloads a cache fill command to the back-end module.

[0024] The above front-end module further includes a page descriptor including a physical page descriptor and a cache page descriptor, wherein the physical page descriptor includes two additional bits, a cache (cached: C) and a non-cacheable (non-cacheable: NC), wherein the cache (cached: C) bit is a bit indicating whether the corresponding page is cached in a DRAM cache, and the non-cacheable (non-cacheable: NC) bit is a bit indicating whether the corresponding page is cacheable, and the step of performing the tag update may include the step of adding the cache (cached: C) and non-cacheable (non-cacheable: NC) bits to an unused field of the PTE (Page Table Entry).

[0025] The method of operation of the above DRAM cache system may further include the step of receiving the cache fill command through an interface that is a register in the back-end module.

[0026] The above interface is composed of a field including a State bit, a Type bit, a PFN (Physical Frame Number) bit, and a CFN (Cache Frame Number) bit, wherein the State bit indicates whether the interface is in use, the Type bit specifies the command type of the cache fill command, the PFN bit stores the PFN (Physical Frame Number) corresponding to the cache fill command, and the CFN bit stores the CFN (Cache Frame Number) corresponding to the cache fill command.

[0027] The method of operation of the above DRAM cache system may further include the step of allocating one or more PCSHRs (Page Copy Status / Information Holding Registers) to process the cache fill command when the interface receives the cache fill command in the back-end module.

[0028] The method of operation of the above DRAM cache system may further include a step of determining whether the cache access is a data miss or a data hit by comparing the CFN (Cache Frame Number) included in the cache access with the CFN of the PCSHR when a cache access is received in the back-end module. Effects of the invention

[0029] According to one aspect of the disclosed invention, by performing separate tag data management in a DRAM cache system, data loss in the event of a DRAM tag miss can be resolved while minimizing the overall latency.

[0030] In addition, according to an embodiment of the present invention, by performing efficient data management through separated tag data management in a DRAM cache system, performance such as increased data processing speed or reduced required memory capacity can be improved compared to a conventional cache system.

[0031] Meanwhile, the effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present invention belongs from the description below. Brief explanation of the drawing

[0032] Figure 1 is a schematic diagram showing the operation of a typical hardware-based (HW-based) DRAM cache. Figure 2 is a schematic diagram showing the operation of a typical OS-managed DRAM cache. FIG. 3 is a diagram showing a DRAM cache system according to one embodiment of the present invention. FIG. 4 is a diagram illustrating page management using PTE and page descriptors in one embodiment of the present invention. FIG. 5 is a diagram showing the state in which a front-end module manages a cache frame in one embodiment of the present invention. FIG. 6 is a diagram illustrating the configuration and operation of a back-end module according to an embodiment of the present invention. Figure 7 is a diagram comparing the latency of the existing hardware-based and OS management (Blocking OS-manage) and the DRAM management system of the present invention (indicated as NOMAD in the drawing). Specific details for implementing the invention

[0033] Throughout the specification, the same reference numerals refer to the same components. This specification does not describe all elements of the embodiments, and general content in the art to which the disclosed invention belongs or content that overlaps between embodiments is omitted. The term "~module" as used in this specification may be implemented in software or hardware, and depending on the embodiments, multiple "~modules" may be implemented as a single component, or a single "~module" may include multiple components. The functions provided by the "~module" may be performed separately by multiple components or integrated with other additional components. The "~module" in this specification is not limited to software or hardware and may be configured to reside in an addressable storage medium or configured to run one or more processors.

[0034] Furthermore, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. A singular expression includes a plural expression unless the context clearly indicates an exception. Identification codes for each step are used for convenience of explanation and do not describe the order of the steps; the steps may be performed differently from the specified order unless the context clearly indicates a specific order.

[0035] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be interpreted as being limited to the embodiments below. These embodiments are provided to more fully explain the present invention to those with average knowledge in the art. Accordingly, the shapes of the elements in the drawings have been exaggerated to emphasize clearer explanations.

[0036] The configuration of the invention to clarify the solution to the problem to be solved by the present invention is described in detail with reference to the attached drawings based on preferred embodiments of the present invention. In assigning reference numbers to the components of the drawings, the same reference number is assigned to identical components even if they are located in different drawings, and it is noted in advance that components of other drawings may be cited if necessary when describing the drawings.

[0037] In the disclosed embodiment, to enable a non-blocking OS-managed DARM cache, a decoupled tag-data management method is proposed instead of a coupled tag-data management method. In the disclosed embodiment, the decoupled tag-data management method can control tags and data through different procedures. In this case, when a tag miss occurs, only the tag is updated and the interrupted application is immediately resumed, thereby significantly reducing the waiting time associated with handling the miss.

[0038] FIG. 3 is a diagram showing a DRAM cache system according to one embodiment of the present invention.

[0039] Referring to FIG. 3, the DRAM cache system (100) may include a front-end module (102) and a back-end module (104).

[0040] The front-end module (102) can be implemented based on an OS management method. However, the front-end module (102) can perform non-blocking miss processing through a decoupled tag-data management method.

[0041] Because the decoupled tag-data management method according to the disclosed embodiment controls the tag and data through different procedures, a tag hit does not necessarily guarantee a data hit in the DRAM cache.

[0042] In one embodiment, in the event of a tag miss, the front-end module (102) can offload a cache fill command to the back-end module (104) while updating only the tag and immediately resuming the interrupted application. To do this, the back-end module (104) must check for data in all DRAM cache accesses, but non-blocking miss processing is possible and the waiting time due to miss processing can be reduced.

[0043] Specifically, the front-end module (102) can manage tags of the DRAM cache using a Translation Lookaside Buffer (TLB) (111) and a Page Table Entry (PTE) (113).

[0044] When a memory request containing a virtual address is received from the processor, the front-end module (102) can check if there is an address translation corresponding to the memory request in the TLB (111).

[0045] TLB (111) can convert the Virtual Page Number (VPN) into a Physical Frame Number (PFN) and return it when there is an address translation corresponding to a memory request, and this is called a TLB hit.

[0046] If there is no address translation corresponding to the memory request in the TLB (111), the front-end module (102) checks the PTE (113), which is called a TLB miss. If, upon checking the PTE (113), there is a physical page (a page in the physical address space) mapped to a virtual page (a page in the virtual address space), the front-end module (102) can pass the physical page mapped to the virtual page to the TLB (111), which is called a tag hit.

[0047] On the other hand, if the PTE (113) checks and finds that there is no physical page mapped to the virtual page (i.e., a tag miss), the front-end module (102) can call the miss handler (115). At this time, the front-end module (102) can call the miss handler (115) through an OS routine, and the execution of the application is temporarily paused.

[0048] The miss handler (115) can update the tag of the DRAM cache by replacing the Physical Frame Number (PFN) of the PTE (113) with the Cache Frame Number (CFN) that serves as the tag of the new cache frame. At this time, the mapping information between the Physical Frame Number (PFN) and the Cache Frame Number (CFN) can be stored in the Page Descriptor (117). At the same time, the miss handler (115) can offload the cache fill command to the back-end module (104). Then, the front-end module (102) can immediately resume the execution of the application.

[0049] That is, in the disclosed embodiment, when a tag miss occurs, the front-end module (102) calls the miss handler (115) to update the tag, and then offloads the cache fill command to the back-end module (104) so ​​that the application can be resumed immediately without interruption.

[0050] Meanwhile, the front-end module (102) can manage page frames using the PTE (113) and page descriptor (117). In the disclosed embodiment, the PTE (113) and page descriptor (117) may have extended functions in addition to the functions of the existing PTE and page descriptor.

[0051] FIG. 4 is a diagram showing page management using PTE (113) and page descriptor (117) in one embodiment of the present invention.

[0052] Referring to FIG. 4, the page descriptor (117) may include a physical page descriptor (117a) and a cache page descriptor (117b). Here, the physical page descriptor (117a) may be extended through two additional bits: cached (C) and non-cacheable (NC).

[0053] The cache (C) bit may be a bit indicating whether the page is cached in the DRAM cache. The non-cache (NC) bit may be a bit indicating whether the page is cacheable. Since the two bits added in the physical page descriptor (117a) are used to determine tag misses (i.e. cacheable but not cached) during address translation, they are also added to the unused field of the PTE (113).

[0054] The added cache (C) bit and non-cache (NC) bit of the physical page descriptor (117a) allow the front-end module (102) to update the tag directly, thereby reducing latency. The front-end module (102) can determine a tag hit or a tag miss through the added cache (C) bit and non-cache (NC) bit in the unused field of the PTE (113).

[0055] Additionally, in the cache page descriptor (117b), the Valid (V) bit indicates the validity of the cache frame mapping, and the Dirty-in-Cache (DC) bit indicates whether write storage to off-package memory is required for the cache frame upon removal. Here, the DC bit is also stored in the PTE (113).

[0056] The cache page descriptor (117b) also includes the PFN of the physical frame mapped to the cache frame, and the TLB directory can be used to avoid TLB shootdown by tracking whether the cache frame information resides in the TLB (111).

[0057] When the front-end module (102) calls the miss handler (115) (i.e., in the case of a tag miss), the miss handler (115) may first check the cache page descriptor (117b) of the cache frame pointed to by the head of the available queue for validity check.

[0058] The miss handler (115) can send a cash-fill command to the back-end module (104) when an available cache frame is found. Then, the front-end module (102) stores the original PFN in the PFN field of the cache page descriptor (117b), and the PTE (113) can update the new CFN and the cache (cached: C) bit. That is, the PFN (Physical Frame Number) of the PTE (113) can be replaced with the CFN (Cache Frame Number) that serves as the tag for the new cache frame. After that, the front-end module (102) can resolve the tag miss and resume the application even if the data of the new cache frame is still unavailable.

[0059] Additionally, the front-end module (102) may also include a background removal daemon (119) that removes cache frames from the DRAM cache in advance. In this case, if the removed pages are dirty, the background removal daemon (119) may offload write-back commands to the back-end module (104).

[0060] In one embodiment, the front-end module (102) may utilize a First-In, First-Out (FIFO) policy and use a circular free queue to manage cache frames.

[0061] FIG. 5 is a diagram showing the state in which a front-end module (102) manages a cache frame in one embodiment of the present invention.

[0062] Referring to FIG. 5, the cache frame is allocated from the head upon request by the miss handler (15) and can be removed from the tail by the background removal daemon (119).

[0063] The miss handler (15) tracks the number of available cache frames to set the eviction flag, which can be handled by the background eviction daemon (119).

[0064] That is, the background removal daemon (119) can be called when the miss handler (15) sets the removal flag. The background removal daemon (119) can perform cache frame reclamation in a FIFO (First-In, First-Out) manner. At this time, to avoid frequent calls to the background removal daemon (119), a series of cache frames can be removed in advance at once.

[0065] The background removal daemon (119) can skip cache frames in which address translation information remains in the TLB (111) by referring to the TLB directory field of the Cache Page Descriptor (CPD) to avoid TLB shootdown. Additionally, the background removal daemon (119) can pass a write-save command to the back-end module (104) by checking whether a write-save is required through the Dirty-in-Cache (DC) bit of the CPD.

[0066] The back-end module (104) can be implemented on a hardware basis. However, the back-end module (104) is different from the existing hardware-based DRAM cache in that it is controlled by software through the interface (121) and performs cache-fill and write-back using the PCSHR (Page Copy Status / Information Holding Register) (123).

[0067] The back end module (104) can simultaneously execute cache fill and write store commands of the PCSHR (123) and progressively update the corresponding page copy status. Here, the back end module (104) does not need to perform additional work to obtain the cache address because it initiates a memory request with a valid cache address by referencing the TLB (111).

[0068] However, in the disclosed embodiment, separate tag data management is performed, so a TLB hit does not guarantee the existence of the corresponding page data. Accordingly, the back-end module (104) can query PCSHR (123) to see if there is a tag corresponding to the cache access following the TLB hit. Here, if there is a tag corresponding to the cache access, the cache access is considered a data miss, and if there is no tag corresponding to the cache access, this means that the entire page data has already been fetched into the on-package DRAM, so it can be considered a data hit.

[0069] FIG. 6 is a diagram illustrating the configuration and operation of a back-end module (104) according to an embodiment of the present invention.

[0070] Referring to FIG. 6, the interface (121) can receive a cache fill command or a write-store command from the front-end module (102). In one embodiment, the interface (121) may be a memory-mapped device register.

[0071] The interface (121) may be composed of fields such as a State (S) bit, a Type (T) bit, a PFN bit, a CFN bit, and an Offset bit.

[0072] Here, the status (S) bit may indicate whether the interface is in use. The front-end module (102) can send commands only when the interface (121) is in an idle state.

[0073] The Type (T) bit can specify the command type of a cache fill command or a write-save command. The PFN bit can store the Page Frame Number (PFN) corresponding to the cache fill command or the write-save command.

[0074] The CFN bit can store the CFN (Cache Frame Number) corresponding to a cache fill command or a write-save command.

[0075] When the back end module (104) receives a cache fill command or a write save command from the front end module (102), it may assign one or more PCSHRs (123) to process the command. In one embodiment, the back end module (104) may assign multiple PCSHRs (123) to process multiple page copy commands simultaneously.

[0076] PCSHR (123) may be composed of fields such as a Valid (V) bit, Type (T) bit, PFN bit, CFN bit, Priority (P) bit, Prioritized sub-block Index (PI) bit, Read-issued (R) bit, in-Buffer (B) bit, and partial-Write (W) bit.

[0077] Here, the valid (V) bit may indicate whether the corresponding PCSHR (123) is valid.

[0078] The Type (T) bit can specify the command type for a cache fill command or a write-store command.

[0079] The PFN bit can store the Page Frame Number (PFN) corresponding to a cache fill command or a write / save command.

[0080] The CFN bit can store the CFN (Cache Frame Number) corresponding to a cache fill command or a write-save command.

[0081] The type (T) bit, PFN bit, and CFN bit can be received from the interface (121).

[0082] The priority (P) bit indicates whether there is a priority subblock, and the priority subblock index (PI) bit may indicate the index of the priority subblock. When a cache fill command is executed, the priority (P) bit is set, and the priority subblock index (PI) bit can be inferred from the offset bit of the interface (121).

[0083] The Read / Write (R) bit, In-Buffer (B) bit, and Partial Write (W) bit can be used to track the state of a subblock.

[0084] The Read Issue (R) bit and Partial Write (W) bit can indicate whether a read and write transfer of a subblock has been issued, respectively.

[0085] The in-buffer (B) bit may indicate the subblock data currently available in the copy buffer while the page is being transferred.

[0086] When a cache access is received, the back-end module (104) can determine whether there is a tag (CFN tag) corresponding to the cache access by comparing the CFN included in the cache access with the CFN of the PCSHR (123) through a comparator (125). To do this, the comparator (125) can be connected to the CFN bit of each PCSHR (123).

[0087] That is, since the disclosed embodiment manages separate tag data, it must be possible to resolve data omissions in the back-end module (104). To this end, for every cache access, it can check whether there is a corresponding tag through a comparator (125).

[0088] As a result of comparison by the comparator (125), if there is a CFN tag corresponding to cache access in the PCSHR (123), the cache access may be considered a data miss. In this case, the back end module (104) may create a sub-block (or may be referred to as a sub-entry) to handle the data miss in the PCSHR (123) that has a CFN tag corresponding to cache access.

[0089] Data-missed cache accesses may be held in a pending subblock. Cache accesses held in a pending subblock may be handled differently depending on the type of cache access (i.e., read or write) and the state of the corresponding subblock.

[0090] As a result of comparison by the comparator (125), if there is no CFN tag corresponding to cache access in PCSHR (123), this means that the entire page data has already been fetched into the on-package DRAM, so it is considered a data hit and the entire page data becomes available in the DRAM cache.

[0091] FIG. 7 is a diagram comparing the latency of a conventional hardware-based and OS-managed (Blocking OS-manage) system with that of the DRAM management system of the present invention (indicated as NOMAD in the diagram). FIG. 7 (a) is a diagram comparing the latency for a TLB hit and a tag hit, and FIG. 7 (b) is a diagram comparing the latency for a TLB miss and a tag miss.

[0092] Referring to FIG. 7(a), it can be seen that the embodiment of the present invention (NOMAD) has a reduced latency compared to the hardware-based method and a very slight increase compared to the OS management method. That is, since the embodiment of the present invention (NOMAD) compares whether there is a corresponding tag in the back-end module (104) for every cache access, the latency for comparison is added compared to the OS management method, but it can be seen that a very short latency is added.

[0093] Referring to FIG. 7(b), it can be seen that the embodiment of the present invention (NOMAD) reduces latency compared to a hardware-based method and significantly reduces latency compared to an OS management method. That is, unlike the existing OS management method, the embodiment of the present invention (NOMAD) performs non-blocking miss processing through a decoupled tag-data management method, so the latency caused by miss processing can be significantly reduced compared to the existing OS management method.

[0094] And, when both the delay times of Fig. 7(a) and Fig. 7(b) are taken into account, it can be seen that the embodiment of the present invention (NOMAD) reduces the total delay time compared to the existing hardware method and OS management method.

[0095] The above detailed description is illustrative of the present invention. Furthermore, the foregoing describes preferred embodiments of the present invention, and the present invention may be used in various other combinations, modifications, and environments. That is, modifications or alterations are possible within the scope of the concept of the invention disclosed herein, the scope equivalent to the disclosed content, and / or the scope of the art or knowledge. The described embodiments describe the best state for implementing the technical concept of the present invention, and various modifications required for specific fields of application and uses of the present invention are possible. Accordingly, the above detailed description of the invention is not intended to limit the present invention to the disclosed embodiments. Additionally, the appended claims should be interpreted as including other embodiments. Explanation of the symbols

[0096] 100: DRAM cache system 102: Front-end module 104: Backend Module 111: Translation Lookaside Buffer (TLB) 113: PTE(Page Table Entry) 115: Miss Handler 117: Page descriptor 117a: Physical page descriptor 117b: Cache page descriptor 119: Background removal daemon 121: Interface 123: PCSHR (Page Copy Status / information Holding Register) 125: Comparator

Claims

Claim 1 A DRAM cache system comprising a front-end module and a back-end module, wherein the front-end module comprises a Translation Lookaside Buffer (TLB) and a Page Table Entry (PTE), and upon a TLB miss for a memory request, examines the PTE and, if it is a tag miss, calls a miss handler, performs a tag update corresponding to the memory request through the miss handler, and offloads a cache fill command to the back-end module, and further comprises a page descriptor comprising a Physical Page Descriptor and a Cache Page Descriptor, wherein the Physical Page Descriptor comprises two additional bits, a cached (C) and a non-cacheable (NC), wherein the cache bit is a bit indicating whether the corresponding page is cached in the DRAM cache, and the non-cache bit is a bit indicating whether the corresponding page is cacheable, and wherein the cache bit and the non-cache bit are added to an unused field of the Page Table Entry (PTE). Claim 2 delete Claim 3 delete Claim 4 A DRAM cache system according to claim 1, wherein the front-end module determines a tag hit or a tag miss through the cache bit and the non-cache bit added to the unused field of the PTE when examining the PTE. Claim 5 A DRAM cache system comprising a front-end module and a back-end module, wherein the front-end module includes a Translation Lookaside Buffer (TLB) and a Page Table Entry (PTE), and when there is a TLB miss for a memory request, it checks the PTE and, if there is a tag miss, calls a miss handler, performs a tag update corresponding to the memory request through the miss handler, and offloads a cache fill command to the back-end module, and the front-end module further includes a background removal daemon that removes cache frames in advance from the DRAM cache, and the background removal daemon offloads a write-back command to the back-end module when the previously removed pages are dirty. Claim 6 Claim 5, wherein the back-end module comprises an interface for receiving the cache fill command or the write-store command from the front-end module, in a DRAM cache system. Claim 7 A DRAM cache system according to claim 6, wherein the interface is a register and comprises fields of a State bit, a Type bit, a PFN (Physical Frame Number) bit, a CFN (Cache Frame Number) bit, and an Offset bit. Claim 8 A DRAM cache system according to claim 7, wherein the status bit indicates whether the interface is in use, the type bit specifies the command type of the cache fill command or the write-store command, the PFN bit stores a PFN (Physical Frame Number) corresponding to the cache fill command or the write-store command, and the CFN bit stores a CFN (Cache Frame Number) corresponding to the cache fill command or the write-store command. Claim 9 A DRAM cache system according to claim 8, wherein the back-end module allocates one or more PCSHRs (Page Copy Status / Information Holding Registers) to process the command when the interface receives the cache fill command or the write-store command from the front-end module. Claim 10 A DRAM cache system according to claim 9, wherein the back-end module further comprises a comparator that compares a CFN (Cache Frame Number) included in the cache access with a CFN of the PCSHR when a cache access is received. Claim 11 A DRAM cache system according to claim 10, wherein the comparator, when comparing the CFN of the PCSHR, determines that if there is a CFN tag corresponding to a cache access in the PCSHR, the cache access is considered a data miss and a sub-block is created in the corresponding PCSHR to process the data miss. Claim 12 A DRAM cache system according to claim 10, wherein the comparator considers the cache access to be a data hit if, as a result of comparing the CFN of the PCSHR, there is no CFN tag corresponding to the cache access in the PCSHR. Claim 13 A method of operation of a DRAM cache system comprising a front-end module including a Translation Lookaside Buffer (TLB) and a Page Table Entry (PTE) and a back-end module, wherein in the front-end module, when there is a TLB miss for a memory request, the PTE is examined and, if there is a tag miss, a miss handler is called; A method of operation of a DRAM cache system, comprising the step of performing a tag update corresponding to the memory request through the miss handler and offloading a cache fill command to the back end module, wherein the front end module further comprises a page descriptor including a physical page descriptor and a cache page descriptor, wherein the physical page descriptor comprises two additional bits, a cache (cached: C) and a non-cacheable (non-cacheable: NC), wherein the cache (cached: C) bit is a bit indicating whether the corresponding page is cached in the DRAM cache, and the non-cacheable (non-cacheable: NC) bit is a bit indicating whether the corresponding page is cacheable, and the step of performing the tag update includes the step of adding the cache (cached: C) and non-cacheable (non-cacheable: NC) bits to an unused field of the Page Table Entry (PTE). Claim 14 delete Claim 15 The method of operation of the DRAM cache system according to claim 13 further comprises the step of receiving the cache fill command through an interface that is a register in the back-end module. Claim 16 A method of operation of a DRAM cache system according to claim 15, wherein the interface comprises a field including a State bit, a Type bit, a Physical Frame Number (PFN) bit, and a Cache Frame Number (CFN) bit, wherein the State bit indicates whether the interface is in use, the Type bit specifies the command type of the cache fill command, the PFN bit stores a Physical Frame Number (PFN) corresponding to the cache fill command, and the CFN bit stores a Cache Frame Number (CFN) corresponding to the cache fill command. Claim 17 A method of operation of a DRAM cache system according to claim 16, wherein the method of operation of the DRAM cache system further comprises the step of, in the back-end module, allocating one or more PCSHRs (Page Copy Status / Information Holding Registers) to process the cache fill command when the interface receives the cache fill command. Claim 18 The method of operation of the DRAM cache system according to claim 17 further comprises the step of, when a cache access is received in the back-end module, comparing the CFN (Cache Frame Number) included in the cache access with the CFN of the PCSHR to determine whether the cache access is a data miss or a data hit.

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