Delay measurement circuit for sequential logic cell and integrated circuit including the same

Abstract

A delay measurement circuit is implemented to measure the delay of a sequential logic cell comprising a plurality of serially connected flip-flops, and operates based on a data signal and a clock signal, and includes a data selection circuit and a first output circuit. The data selection circuit outputs a selection data signal provided to the sequential logic cell based on the data signal. The first output circuit generates a first output signal generated from the sequential logic cell based on the data signal, the selection data signal, and the clock signal, and a second output signal representing the delay of the sequential logic cell based on the clock signal.

Description

Technology Field

[0001] The present invention relates to a semiconductor integrated circuit, and more specifically, to a delay measurement circuit for measuring the delay of a sequential logic cell, and an integrated circuit including said delay measurement circuit. Background Technology

[0002] Recently, as the integration density and capacity of semiconductor integrated circuits have increased, the variability of characteristics within a single semiconductor chip is becoming increasingly prominent. Consequently, to manufacture high-quality semiconductor devices, it is becoming increasingly necessary to accurately determine the characteristics of the semiconductor chip based on data extracted from it.

[0003] Previously, to identify the characteristics of semiconductor chips and analyze silicon trends, promise cells were embedded in the chips, and data extracted from the promise cells was utilized. However, since the promise cells were combinational logic cells composed solely of combinational logic components such as inverters, NAND gates, and NOR gates, there was a problem in that it was difficult to determine the characteristics of sequential logic cells, which include clock-based sequential logic. The problem to be solved

[0004] One objective of the present invention is to provide a delay measurement circuit capable of effectively verifying alternating current (AC) characteristics and correlations by performing delay measurements of sequential logic cells.

[0005] One objective of the present invention is to provide an integrated circuit comprising the delay measurement circuit. means of solving the problem

[0006] To achieve the above objective, a delay measurement circuit according to embodiments of the present invention is implemented to measure the delay of a sequential logic cell comprising a plurality of serially connected flip-flops, which operates based on a data signal and a clock signal, and includes a data selection circuit and a first output circuit. The data selection circuit outputs a selection data signal provided to the sequential logic cell based on the data signal. The first output circuit generates a first output signal generated from the sequential logic cell based on the data signal, the selection data signal, and the clock signal, and a second output signal representing the delay of the sequential logic cell based on the clock signal.

[0007] To achieve the above objective, an integrated circuit according to embodiments of the present invention includes an internal circuit and a test circuit. The test circuit is formed independently of the internal circuit and is a circuit for verifying the characteristics of the internal circuit, and includes a sequential logic cell and a delay measurement circuit. The sequential logic cell operates based on a data signal and a clock signal and includes a plurality of flip-flops connected in series. The delay measurement circuit measures the delay of the sequential logic cell and includes a data selection circuit and a first output circuit. The data selection circuit outputs a selection data signal provided to the sequential logic cell based on the data signal. The first output circuit generates a first output signal generated from the sequential logic cell based on the data signal, the selection data signal, and the clock signal, and generates a second output signal representing the delay of the sequential logic cell based on the clock signal. Effects of the invention

[0008] In the delay measurement circuit and integrated circuit according to the embodiments of the present invention as described above, the characteristics (i.e., delay) of a sequential logic cell operating based on a clock can be implemented. Specifically, a sequential logic cell is formed by serially connecting a plurality of flip-flops, and by repeating the same flip-flops multiple times to generate a pulse configured to a measurable level and measuring it, fine AC characteristics and correlations can be effectively verified. Accordingly, the characteristics of the integrated circuit can be identified, and MHC compatibility can be verified by supplementing the characteristics of sequential logic to MHC analysis, which was previously limited to combinational logic. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a delay measurement circuit and a test circuit including the same according to embodiments of the present invention. Figure 2 is a block diagram showing a specific example of the delay measurement circuit of Figure 1 and a test circuit including the same. Figures 3, 4, and 5 are drawings for explaining the operation of the delay measurement circuit of Figure 2. FIG. 6 is a block diagram showing a delay measurement circuit and a test circuit including the same according to embodiments of the present invention. FIG. 7 is a block diagram showing a specific example of the delay measurement circuit of FIG. 6 and a test circuit including it. FIG. 8 is a block diagram showing an integrated circuit including a delay measurement circuit according to embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions of identical components are omitted.

[0011] FIG. 1 is a block diagram showing a delay measurement circuit and a test circuit including the same according to embodiments of the present invention.

[0012] Referring to FIG. 1, the test circuit (10) may include a sequential logic cell (100) and a delay measurement circuit (200).

[0013] As described below with reference to FIG. 8, the test circuit (10) may be included in an integrated circuit (e.g., a semiconductor integrated circuit, a semiconductor device and / or a semiconductor chip). The test circuit (10) can be used to determine the characteristics of the integrated circuit (e.g., the amount of delay occurring in the integrated circuit, the AC (alternating current) characteristics of the integrated circuit, correlation, MHC compatibility, etc.).

[0014] The sequential logic cell (100) may be implemented to include sequential logic that operates based on a clock. For example, the sequential logic cell (100) may include a plurality of serially connected flip-flops (FF) that operate based on a data signal (DAT) and a clock signal (CLK). An exemplary structure of the sequential logic cell (100) will be described later with reference to FIG. 2.

[0015] The delay measurement circuit (200) can measure the delay of the sequential logic cell (100) (i.e., the delay caused by the sequential logic cell (100)). The delay measurement circuit (200) may include a data selection circuit (210) and a first output circuit (230).

[0016] The data selection circuit (210) can generate a selection data signal (SDAT) provided to the sequential logic cell (100) based on the data signal (DAT). For example, depending on the operating mode of the delay measurement circuit (200), the data signal (DAT) or an inverted data signal in which the data signal (DAT) is inverted may be output as the selection data signal (SDAT). An exemplary structure of the data selection circuit (210) will be described later with reference to FIG. 2.

[0017] The first output circuit (230) can generate a second output signal (DOUT) representing the delay of the sequential logic cell (100) based on a first output signal (QN) and a clock signal (CLK) output from the sequential logic cell (100). The first output signal (QN) can be generated from the sequential logic cell (100) based on a data signal (DAT), a selected data signal (SDAT), and a clock signal (CLK). For example, the first output circuit (230) may include at least one logic gate. An exemplary structure of the first output circuit (230) will be described later with reference to FIG. 2.

[0018] In the manufacturing process of semiconductor integrated circuits, Model & Hardware correlation verification is performed. Previously, promise cells were installed in semiconductor integrated circuits, and characteristics were identified and silicon trends analyzed based on data extracted from the promise cells. For example, a promise cell can be a ring oscillator type cell composed of a combinational logic chain, such as an inverter, NAND gate, or NOR gate. However, since such promise cells are composed solely of combinational logic, they cannot represent sequential logic cells that operate based on a clock, and MHC verification for sequential logic cells is required for more accurate correlation verification.

[0019] The aforementioned silicon trend analysis may be a procedure to verify process corner conditions such as SS and FF. As the process becomes more precise and fine, the characteristics of the device converge to zero, and if a separate device is added for measurement, the added device may result in values ​​that are more distorted than the original data. Accordingly, there is a need for a device capable of measuring and analyzing characteristic data while minimizing distortion during measurement.

[0020] The delay measurement circuit (200) according to embodiments of the present invention can be implemented to measure the characteristics (i.e., delay) of a sequential logic cell (100) that operates based on a clock. Specifically, a sequential logic cell (100) is formed by serially connecting a plurality of flip-flops (FF), and by repeating the same flip-flops multiple times to generate a pulse configured to a measurable level and measuring it, fine AC characteristics and correlations can be effectively verified. Accordingly, the characteristics of an integrated circuit including a test circuit (10) can be identified, and MHC compatibility can be verified by supplementing the characteristics of sequential logic in MHC analysis, which is limited to conventional combinational logic.

[0021] Figure 2 is a block diagram showing a specific example of the delay measurement circuit of Figure 1 and a test circuit including the same.

[0022] Referring to FIG. 2, the test circuit (10a) may include a sequential logic cell (100a), a data selection circuit (210a), and a first output circuit (230a). The data selection circuit (210a) and the first output circuit (230a) may form a delay measurement circuit (e.g., 200 of FIG. 1) according to embodiments of the present invention.

[0023] The sequential logic cell (100a) may correspond to the sequential logic cell (100) of FIG. 1. The sequential logic cell (100a) may include first to N (N is a natural number greater than or equal to 3) flip-flops (FF1, FF2, FF3, ..., FF(N-1), FFN) (110, 120, 130, 140, 150).

[0024] The first to Nth flip-flops (110, 120, 130, 140, 150) may correspond to a plurality of flip-flops (FF) of FIG. 1. Each of the first to Nth flip-flops (110, 120, 130, 140, 150) may include a data input terminal (D), a clock input terminal (CK), and an output terminal (Q). The first to Nth flip-flops (110, 120, 130, 140, 150) may be flip-flops of the same type having the same structure and operating characteristics.

[0025] The first to Nth flip-flops (110, 120, 130, 140, 150) can be arranged sequentially and connected in series. Specifically, the first to Nth flip-flops (110, 120, 130, 140, 150) can be connected in series by connecting the output terminal (Q) of the flip-flop placed at the front end to the clock input terminal (CK) of the flip-flop placed at the back end (i.e., FF output to next FF clock). In other words, the clock input terminal (CK) of the Kth flip-flop (K is a natural number between 2 and N) can be connected to the output terminal (Q) of the (K-1)th flip-flop.

[0026] Additionally, a data signal (DAT) is applied to the data input terminal (D) of the first to (N-1) flip-flops (110, 120, 130, 140), and a selection data signal (SDAT) output from the data selection circuit (210a) can be applied to the data input terminal (D) of the Nth flip-flop (150).

[0027] The connection and operation of the first to Nth flip-flops (110, 120, 130, 140, 150) are described in more detail as follows.

[0028] A data signal (DAT) can be applied to the data input terminal (D) of the first flip-flop (110) placed at the very front, and a clock signal (CLK) can be applied to the clock input terminal (CK). The first flip-flop (110) can generate a first flip-flop signal (Q1) based on the data signal (DAT) and the clock signal (CLK), and can output the first flip-flop signal (Q1) through the output terminal (Q).

[0029] A data signal (DAT) can be applied to the data input terminal (D) of the second flip-flop (120) placed at the rear end of the first flip-flop (110), and a first flip-flop signal (Q1) output from the first flip-flop (110) can be applied to the clock input terminal (CK). That is, the clock input terminal (CK) of the second flip-flop (120) can be connected to the output terminal (Q) of the first flip-flop (110). The second flip-flop (120) can generate a second flip-flop signal (Q2) based on the data signal (DAT) and the first flip-flop signal (Q1), and can output the second flip-flop signal (Q2) through the output terminal (Q).

[0030] A data signal (DAT) can be applied to the data input terminal (D) of a third flip-flop (130) placed after the second flip-flop (120), and a second flip-flop signal (Q2) output from the second flip-flop (120) can be applied to the clock input terminal (CK). That is, the clock input terminal (CK) of the third flip-flop (130) can be connected to the output terminal (Q) of the second flip-flop (120). The third flip-flop (130) can generate a third flip-flop signal (Q3) based on the data signal (DAT) and the second flip-flop signal (Q2), and can output the third flip-flop signal (Q3) through the output terminal (Q). The third flip-flop signal (Q3) can be applied to the clock input terminal (CK) of a fourth flip-flop (not shown) placed after the third flip-flop (130).

[0031] Similarly, a data signal (DAT) may be applied to the data input terminal (D) of the (N-1) flip-flop (140) placed in front of the (N-1) flip-flop (150), and a (N-2) flip-flop signal (not shown) output from the (N-2) flip-flop (not shown) placed in front of the (N-1) flip-flop (140) may be applied to the clock input terminal (CK). That is, the clock input terminal (CK) of the (N-1) flip-flop (140) may be connected to the output terminal (Q) of the (N-2) flip-flop. The (N-1) flip-flop (140) can generate a (N-1) flip-flop signal (Q(N-1)) based on the data signal (DAT) and the (N-2) flip-flop signal, and can output the (N-1) flip-flop signal (Q(N-1)) through the output terminal (Q).

[0032] A selection data signal (SDAT) output from a data selection circuit (210a) can be applied to the data input terminal (D) of the Nth flip-flop (150), which is placed at the rear end and is placed after the Nth (N-1) flip-flop (140), and a Nth flip-flop signal (Q(N-1)) output from the Nth (N-1) flip-flop (140) can be applied to the clock input terminal (CK). That is, the clock input terminal (CK) of the Nth flip-flop (150) can be connected to the output terminal (Q) of the Nth flip-flop (140). The Nth flip-flop (150) can generate an Nth flip-flop signal (QN) based on the selection data signal (SDAT) and the Nth flip-flop signal (Q(N-1)), and can output the Nth flip-flop signal (QN) through the output terminal (Q). The Nth flip-flop signal (QN) can correspond to the first output signal (QN) output from the sequential logic cell (100a). That is, the first output signal (QN) can be provided from the output terminal (Q) of the Nth flip-flop (150).

[0033] As described above, by serially connecting the first to Nth flip-flops (110, 120, 130, 140, 150) by connecting the output terminal (Q) of the flip-flop placed at the front end and the clock input terminal (CK) of the flip-flop placed at the rear end, the delay of the sequential logic cell (100a) (i.e., the delay caused by the sequential logic cell (100a)) can correspond to the delay from the clock input terminal (CK) to the output terminal (Q) of each of the first to Nth flip-flops (110, 120, 130, 140, 150) (i.e., CK-to-Q or CK2Q delay).

[0034] As described above, by arranging N flip-flops of the same type in series and implementing the input signal to repeat the same flip-flops N times, a pulse configured to a measurable level can be generated.

[0035] The data selection circuit (210a) may correspond to the data selection circuit (210) of FIG. 1. The data selection circuit (210a) may include an inverter (211) and a multiplexer (213).

[0036] The inverter (211) can invert the data signal (DAT) to generate an inverted data signal ( / DAT). The multiplexer (213) can output either the data signal (DAT) or the inverted data signal ( / DAT) as a selected data signal (SDAT) based on a selection signal (DSEL). For example, the multiplexer (213) may be implemented to include at least one switch.

[0037] In one embodiment, the delay measurement circuit may operate in different operating modes. The data selection circuit (210a) may output one of a data signal (DAT) and an inverted data signal ( / DAT) as a selected data signal (SDAT) depending on the operating mode, and the selection signal (DSEL) for selecting one of the data signal (DAT) and the inverted data signal ( / DAT) may be referred to as an operating mode selection signal or a mode selection signal.

[0038] Specifically, the above operating mode may include a first measurement mode and a second measurement mode. The first measurement mode may represent an operating mode for measuring a first delay of a sequential logic cell (100a) that occurs when a data signal (DAT) transitions from a first logic level to a second logic level. The second measurement mode may represent an operating mode for measuring a second delay of a sequential logic cell (100a) that occurs when a data signal (DAT) transitions from the second logic level to the first logic level. For example, the first logic level may be a logic low level, and the second logic level may be a logic high level. In this case, the first delay of the sequential logic cell (100a) may represent a delay that occurs when transitioning from the logic low level to the logic high level, i.e., a low-to-high delay, and the second delay of the sequential logic cell (100a) may represent a delay that occurs when transitioning from the logic high level to the logic low level, i.e., a high-to-low delay.

[0039] In one embodiment, in the first measurement mode, the data selection circuit (210a) may output a data signal (DAT) as a selection data signal (SDAT) and provide it to the sequential logic cell (100a) (i.e., the Nth flip-flop (150)). In the second measurement mode, the data selection circuit (210a) may output an inverted data signal ( / DAT) as a selection data signal (SDAT) and provide it to the sequential logic cell (100a) (i.e., the Nth flip-flop (150)). In other words, in the first measurement mode, the first delay (i.e., low-to-high delay) of the sequential logic cell (100a) can be measured using the data signal (DAT), and in the second measurement mode, the second delay (i.e., high-to-low delay) of the sequential logic cell (100a) can be measured using the inverted data signal ( / DAT).

[0040] In actual implementation, the characteristics of low-to-high type data and high-to-low type data may not be identical and may differ. In this case, when measuring using only one of the two types of data described above, it may be difficult to accurately measure the characteristics of both types of data. Therefore, in order to measure the characteristics of both types of data (i.e., low-to-high and high-to-low type data), a data selection circuit (210a) including an inverter (211) and a multiplexer (213) can be implemented to enable data selection.

[0041] The first output circuit (230a) may correspond to the first output circuit (230) of FIG. 1. The first output circuit (230a) may include an XOR gate (231). The XOR gate (231) may generate a second output signal (DOUT) by performing an XOR operation on the first output signal (QN) and the clock signal (CLK).

[0042] Figures 3, 4, and 5 are drawings for explaining the operation of the delay measurement circuit of Figure 2.

[0043] Referring to FIG. 3, the operation of measuring the first delay of the sequential logic cell (100a) in the first measurement mode is illustrated.

[0044] At time t11, the data signal (DAT) may transition from the first logic level to the second logic level. For example, as described above, the first logic level may be a logic low level, and the second logic level may be a logic high level. The first delay of the sequential logic cell (100a) measured in the first measurement mode may correspond to a delay that occurs when transitioning from the logic low level to the logic high level, i.e., a low-to-high delay.

[0045] At time t12, the clock signal (CLK) may transition from the first logic level to the second logic level, and a rising edge of the clock signal (CLK) may occur. For example, each of the first to Nth flip-flops (110, 120, 130, 140, 150) may operate based on the rising edge of the signal input to the clock input terminal (CK).

[0046] A clock signal (CLK) can be input to the clock input terminal (CK) of the first flip-flop (110), and a data signal (DAT) having the second logic level can be input to the data input terminal (D). The first flip-flop signal (Q1) generated by the first flip-flop (110) and output from the output terminal (Q) of the first flip-flop (110) can transition from the first logic level to the second logic level after a first delay time (D1) has elapsed from time t12, when the rising edge of the clock signal (CLK) occurs (i.e., a rising edge can occur).

[0047] The second flip-flop (120) may have a first flip-flop signal (Q1) input to its clock input terminal (CK) and a data signal (DAT) having the second logic level input to its data input terminal (D). The second flip-flop signal (Q2), generated by the second flip-flop (120) and output from the output terminal (Q) of the second flip-flop (120), may transition from the first logic level to the second logic level after a first delay time (D1) has elapsed from the point in time when the rising edge of the first flip-flop signal (Q1) occurs (i.e., the rising edge may occur).

[0048] The third flip-flop (130) may have a second flip-flop signal (Q2) input to its clock input terminal (CK) and a data signal (DAT) having the second logic level input to its data input terminal (D). The third flip-flop signal (Q3) generated by the third flip-flop (130) and output from the output terminal (Q) of the third flip-flop (130) may transition from the first logic level to the second logic level after a first delay time (D1) has elapsed from the point in time when the rising edge of the second flip-flop signal (Q2) occurs (i.e., the rising edge may occur).

[0049] Similarly, the (N-1) flip-flop (140) may receive the (N-2) flip-flop signal output from the preceding (N-2) flip-flop at the clock input terminal (CK), and may receive the data signal (DAT) having the second logic level at the data input terminal (D). The (N-1) flip-flop signal (Q(N-1)) generated by the (N-1) flip-flop (140) and output from the output terminal (Q) of the (N-1) flip-flop (140) may transition from the first logic level to the second logic level after a first delay time (D1) has elapsed from the point in time when the rising edge of the (N-2) flip-flop signal occurs (i.e., the rising edge may occur).

[0050] The Nth flip-flop (150) may have a (N-1) flip-flop signal (Q(N-1)) input to its clock input terminal (CK), and a data signal (DAT) having the second logic level input to its data input terminal (D). The Nth flip-flop signal (QN), i.e., the first output signal (QN), generated by the Nth flip-flop (150) and output from the output terminal (Q) of the Nth flip-flop (150), may transition from the first logic level to the second logic level at time t13 after a first delay time (D1) has elapsed from the point in time when the rising edge of the (N-1) flip-flop signal (Q(N-1)) occurs (i.e., a rising edge may occur).

[0051] In this case, assuming that delay caused by other elements is ignored or non-existent, the second output signal (DOUT) obtained by performing an XOR operation on the clock signal (CLK) and the first output signal (QN) may have the second logic level between time t12 and time t13 and the first logic level during the remaining interval.

[0052] In one embodiment, in the first measurement mode, the first delay of the sequential logic cell (100a) can be calculated based on a first width (W1) between time t12 and time t13 during which the second output signal (DOUT) has the second logic level. The first width (W1) may be described as the width between the first edge (i.e., rising edge) and the second edge (i.e., falling edge) of the second output signal (DOUT).

[0053] Specifically, the first width (W1) can correspond to N times the first delay time (D1) (i.e., W1 = N * D1). Accordingly, the first delay time (D1) can be obtained by dividing the first width (W1) by N, and the first delay time (D1) can correspond to a low-to-high delay generated by a single flip-flop, and thus the first delay time (D1) can be obtained as the first delay of the sequential logic cell (100a).

[0054] Referring to FIG. 4, the operation of measuring the second delay of the sequential logic cell (100a) in the second measurement mode is illustrated. Descriptions that overlap with FIG. 3 are omitted below.

[0055] At time t21, the data signal (DAT) can be transitioned from the first logic level to the second logic level, and the inverted data signal ( / DAT) can be transitioned from the second logic level to the first logic level. The second delay of the sequential logic cell (100a) measured in the second measurement mode can correspond to the delay that occurs when transitioning from the logic high level to the logic low level, i.e., the high-to-low delay.

[0056] At time t21, the clock signal (CLK) may transition from the first logic level to the second logic level. Subsequently, the operation of the first to (N-1) flip-flops (110, 120, 130, 140) generating the first to (N-1) flip-flop signals (Q1, Q2, Q3, ..., Q(N-1)) may be substantially the same as described above with reference to FIG. 3.

[0057] The Nth flip-flop (150) may have the (N-1) flip-flop signal (Q(N-1)) input to the clock input terminal (CK), and the inverted data signal ( / DAT) having the first logic level input to the data input terminal (D). The Nth flip-flop signal (QN), i.e., the first output signal (QN), generated by the Nth flip-flop (150) and output from the output terminal (Q) of the Nth flip-flop (150), may transition from the second logic level to the first logic level at time t23 after a second delay time (D2) has elapsed from the point in time when the rising edge of the (N-1) flip-flop signal (Q(N-1)) occurs (i.e., a falling edge may occur).

[0058] In this case, assuming that delays caused by other elements are ignored or non-existent, the second output signal (DOUT) obtained by performing an XOR operation on the clock signal (CLK) and the first output signal (QN) may have the first logic level between time t22 and time t23 and the second logic level during the remaining interval.

[0059] In one embodiment, in the second measurement mode, the second delay of the sequential logic cell (100a) can be calculated based on a second width (W2) between time t22 and time t23 during which the second output signal (DOUT) has the first logic level. The second width (W2) may be described as the width between the third edge (i.e., falling edge) and the fourth edge (i.e., rising edge) of the second output signal (DOUT).

[0060] Specifically, the second width (W2) can correspond to the sum of (N-1) times the first delay time (D1) and the second delay time (D2) (i.e., W2 = (N-1) * D1 + D2). As described above with reference to FIG. 3, the first delay time (D1) can be obtained, and the second delay time (D2) can be obtained by subtracting (N-1) times the first delay time (D1) from the second width (W2). The second delay time (D2) can correspond to a high-to-low delay generated by a single flip-flop, and thus the second delay time (D2) can be obtained as the second delay of the sequential logic cell (100a).

[0061] Referring to FIG. 5, an example is shown of a simulation of the operation in the second measurement mode described above with reference to FIG. 4.

[0062] The data signal (DAT) of FIG. 5 is similar to the data signal (DAT) of FIG. 4, and in FIG. 5, the first to Nth flip-flop signals (Q1~QN) are superimposed. In reality, a delay caused by the XOR gate (231) included in the first output circuit (230a) (and / or a delay caused by other components) may also occur, and thus the second width (W2') included in the second output signal (DOUT) of FIG. 5 may correspond to the sum of the delay caused by the sequential logic cell (100a) and the delay caused by the XOR gate (231) (and / or a delay caused by other components).

[0063] FIG. 6 is a block diagram showing a delay measurement circuit and a test circuit including the same according to embodiments of the present invention. Descriptions that overlap with FIG. 1 are omitted below.

[0064] Referring to FIG. 6, the test circuit (12) may include a sequential logic cell (100) and a delay measurement circuit (202). The delay measurement circuit (202) may include a data selection circuit (210) and a first output circuit (230), and may further include a second output circuit (250).

[0065] Except that the delay measurement circuit (202) further includes a second output circuit (250), the test circuit (12) and the delay measurement circuit (202) may be substantially identical to the test circuit (10) and the delay measurement circuit (200) of FIG. 1, respectively.

[0066] The second output circuit (250) can generate a third output signal (DOUT') representing the delay of the sequential logic cell (100) based on the second output signal (DOUT). An exemplary structure of the second output circuit (250) will be described later with reference to FIG. 7.

[0067] FIG. 7 is a block diagram showing a specific example of the delay measurement circuit of FIG. 6 and a test circuit including the same. Descriptions that overlap with FIG. 2 are omitted below.

[0068] Referring to FIG. 7, the test circuit (12a) may include a sequential logic cell (100a), a data selection circuit (210a), and a first output circuit (230a), and may further include a second output circuit (250a).

[0069] Except for further including a second output circuit (250a), the test circuit (12a) and the delay measurement circuit may be substantially identical to the test circuit (10a) and the delay measurement circuit of FIG. 2, respectively.

[0070] The second output circuit (250a) may correspond to the second output circuit (250) of FIG. 6. The second output circuit (250a) may include an inverter (251) and a multiplexer (253).

[0071] The inverter (251) can invert the second output signal (DOUT) to generate a second inverted output signal ( / DOUT). The multiplexer (253) can output either the second output signal (DOUT) or the second inverted output signal ( / DOUT) as a third output signal (DOUT') based on a selection signal (WSEL). The selection signal (WSEL) for selecting either the second output signal (DOUT) or the second inverted output signal ( / DOUT) may be referred to as a wave selection signal.

[0072] When passing through a circuit configured with low-to-high type data and high-to-low type data, a difference in delay may occur that is significant enough not to be ignored. In this case, a second output circuit (250a) including an inverter (251) and a multiplexer (253) can be implemented to correct the difference in delay. For example, in each measurement mode, two output signals of different waveforms are obtained by first obtaining the second output signal (DOUT) and then obtaining the second inverted output signal ( / DOUT), two widths corresponding to the delay in the two output signals (e.g., W1 in FIG. 3 and / or W2 in FIG. 4) are obtained, the two widths are averaged to finally obtain an average width, and the delay is calculated based on the average width. In this case, the value contaminated by the above-mentioned difference in delay can be refined, and the delay of the sequential logic cell (100a) can be obtained more accurately.

[0073] FIG. 8 is a block diagram showing an integrated circuit including a delay measurement circuit according to embodiments of the present invention.

[0074] Referring to FIG. 8, the integrated circuit (1000) may include an internal circuit (1100) and a test circuit (1200).

[0075] The internal circuit (1100) can perform unique operations and / or specific operations to operate the integrated circuit (1000). For example, if the integrated circuit (1000) is any semiconductor chip and / or device, the internal circuit (1100) may include various circuits such as a processor, memory, interface, etc., necessary to operate the semiconductor chip normally.

[0076] The test circuit (1200) is formed independently of the internal circuit (1100) and may be a circuit for verifying the characteristics of the internal circuit (1100). The test circuit (1200) may be used during the manufacturing and / or testing of the integrated circuit (1000) and may not operate while the integrated circuit (1000) is operating normally.

[0077] The test circuit (1200) is the test circuit described above with reference to FIGS. 1 to 7 and may include a delay measurement circuit (DMC) according to embodiments of the present invention. For example, the test circuit (1200) includes a sequential logic cell that operates based on a clock, and the delay measurement circuit (DMC) is implemented to measure the characteristics (i.e., delay) of the sequential logic cell, and can effectively verify minute AC characteristics and correlations. Accordingly, the characteristics of the integrated circuit (1000) and the internal circuit (1100) (i.e., the characteristics of the sequential logic included in the integrated circuit (1000) and the internal circuit (1100)) can be identified, and MHC consistency can be verified by supplementing the characteristics of the sequential logic in MHC analysis, which is limited to conventional combinational logic. Industrial applicability

[0078] Embodiments of the present invention may be usefully applied to any electronic device and system including a semiconductor integrated circuit. For example, embodiments of the present invention may be more usefully applied to electronic systems such as a PC (Personal Computer), server computer, cloud computer, data center, workstation, laptop, cellular phone, smartphone, MP3 player, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), digital TV, digital camera, portable game console, navigation device, wearable device, IoT (Internet of Things) device, IoE (Internet of Everything) device, e-book, VR (Virtual Reality) device, AR (Augmented Reality) device, drone, automotive, etc.

[0079] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

Claim 1 A delay measuring circuit for measuring a delay of a sequential logic cell comprising a plurality of serially connected flip-flops that operate based on a data signal and a clock signal, comprising: a data selection circuit that outputs a selection data signal provided to the sequential logic cell based on the data signal; a first output circuit that generates a first output signal generated from the sequential logic cell based on the data signal, the selection data signal and the clock signal, and a second output signal that represents the delay of the sequential logic cell based on the clock signal; and a second output circuit that generates a third output signal that represents the delay of the sequential logic cell based on the second output signal. Claim 2 A delay measurement circuit for measuring the delay of a sequential logic cell comprising a plurality of serially connected flip-flops that operate based on a data signal and a clock signal, wherein the delay measurement circuit outputs a selection data signal provided to the sequential logic cell based on the data signal; A delay measurement circuit comprising a first output circuit that generates a first output signal generated from the sequential logic cell based on the data signal, the selection data signal, and the clock signal, and a second output signal representing the delay of the sequential logic cell based on the clock signal, wherein the plurality of flip-flops included in the sequential logic cell include first to N (N is a natural number greater than or equal to 3) flip-flops arranged sequentially and each including a data input terminal, a clock input terminal, and an output terminal, wherein the data signal is applied to the data input terminal of the first to (N-1) flip-flops, the selection data signal is applied to the data input terminal of the N flip-flop, the clock signal is applied to the clock input terminal of the first flip-flop, the clock input terminal of the K (K is a natural number greater than or equal to 2 and less than or equal to N) flip-flop is connected to the output terminal of the (K-1) flip-flop, and the first output signal is provided from the output terminal of the N flip-flop. Claim 3 A delay measurement circuit according to claim 2, wherein the data selection circuit comprises: an inverter that inverts the data signal to generate an inverted data signal; and a multiplexer that outputs one of the data signal and the inverted data signal as the selected data signal based on a selection signal. Claim 4 A delay measurement circuit according to claim 3, wherein in a first measurement mode for measuring a first delay of the sequential logic cell that occurs when the data signal transitions from a first logic level to a second logic level, the data selection circuit outputs the data signal as the selected data signal and provides it to the sequential logic cell, and in the first measurement mode, the first delay of the sequential logic cell is calculated based on a first width between the first edge and the second edge of the second output signal. Claim 5 A delay measurement circuit according to claim 4, wherein in a second measurement mode for measuring a second delay of the sequential logic cell that occurs when the data signal transitions from the second logic level to the first logic level, the data selection circuit outputs the inverted data signal as the selected data signal and provides it to the sequential logic cell, and in the second measurement mode, the second delay of the sequential logic cell is calculated based on the second width between the third edge and the fourth edge of the second output signal. Claim 6 A delay measurement circuit according to claim 3, wherein the first output circuit comprises an XOR gate that generates the second output signal by performing an XOR operation on the first output signal and the clock signal. Claim 7 A delay measurement circuit according to claim 2, characterized in that the delay of the sequential logic cell corresponds to the delay from the clock input terminal to the output terminal of each of the first to Nth flip-flops. Claim 8 delete Claim 9 A delay measurement circuit according to claim 1, wherein the second output circuit comprises: an inverter that inverts the second output signal to generate a second inverted output signal; and a multiplexer that outputs one of the second output signal and the second inverted output signal as the third output signal based on a selection signal. Claim 10 An integrated circuit comprising: an internal circuit; and a test circuit formed independently of the internal circuit and for verifying the characteristics of the internal circuit, wherein the test circuit comprises a sequential logic cell comprising a plurality of serially connected flip-flops that operate based on a data signal and a clock signal; and a delay measurement circuit for measuring a delay of the sequential logic cell, wherein the delay measurement circuit comprises: a data selection circuit that outputs a selection data signal provided to the sequential logic cell based on the data signal; a first output circuit that generates a first output signal generated from the sequential logic cell based on the data signal, the selection data signal and the clock signal, and a second output signal that represents the delay of the sequential logic cell based on the clock signal; and a second output circuit that generates a third output signal that represents the delay of the sequential logic cell based on the second output signal.

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