Nonvolatile memory apparatus generating a read refeence and operating method thereof

Abstract

A non-volatile memory device may include a control circuit, a sense amplifier, and a reference generator. The control circuit may apply a read voltage to a target memory cell through a selected global bit line and a selected global word line. The sense amplifier may generate an output signal by comparing the voltage levels of the selected global word line and the reference line. The reference generator may change the voltage level of the reference line by charging and discharging a capacitor connected to the reference line.

Description

Technology Field

[0001] The present invention relates to a memory device, and more specifically, to a non-volatile memory device and a method of operating the same. Background Technology

[0002] Electronic devices contain many electronic components, and among them, they may include many electronic components composed of computer system semiconductors. The computer system may include a memory device. DRAM is widely used as a general memory device because it has the advantage of being able to store and output data at a fast and constant speed and allows random access. However, since DRAM is equipped with memory cells composed of capacitors, it has a volatile characteristic in which stored data is lost when the power supply is cut off. Flash memory devices were developed to improve upon the disadvantages of DRAM mentioned above. Flash memory devices include memory cells composed of floating gates and can have a non-volatile characteristic that allows stored data to be retained even when the power supply is cut off. However, compared to DRAM, it has the disadvantage of slower data storage and output speeds and difficulty in random access.

[0003] Recently, next-generation memory devices such as phase change RAM, magnetic RAM, resistive RAM, and ferroelectric RAM, which possess fast operating speeds and non-volatility characteristics, are being developed. These next-generation memory devices have the advantage of being able to operate at high speeds while maintaining non-volatility. In particular, the PRAM includes memory cells composed of chalcogenides and can store data by changing the resistance value of the memory cells. The problem to be solved

[0004] An embodiment of the present invention can provide a non-volatile memory device capable of detecting data stored in a memory cell connected to the selected global word line by precharging a reference line of a sense amplifier to the same voltage level as the selected global word line and then boosting the voltage level of the reference line. means of solving the problem

[0005] A non-volatile memory device according to an embodiment of the present invention may include: a control circuit that applies a read voltage to a target memory cell through a selected global bit line and a selected global word line; a sense amplifier that generates an output signal by comparing the voltage levels of the selected global word line and a reference line; and a reference generator that changes the voltage level of the reference line by charging and discharging a capacitor connected to the reference line.

[0006] A method of operation of a non-volatile memory device according to an embodiment of the present invention is a method of operation of a non-volatile memory device for accessing a target memory cell connected between a selected bit line and a selected word line, and may include the steps of: applying a first read boundary voltage to the selected bit line and applying a second read boundary voltage to the selected word line and pre-charging a reference line with the second read boundary voltage; providing a first low voltage to a capacitor connected to the reference line to raise the voltage level of the reference line; and generating an output signal by comparing the voltage level of the selected word line, which changes according to data stored in the target memory cell, with the voltage level of the reference line.

[0007] A non-volatile memory device according to an embodiment of the present invention may include: a first global word line connected to a first memory cell; a second global word line connected to a second memory cell; a sense amplifier that generates an output signal by comparing the voltage levels of the first and second input terminals, and a reference generator that changes the voltage level of the second input terminal by charging and discharging a capacitor connected to the second input terminal. Effects of the invention

[0008] An embodiment of the present invention can reduce the core area of ​​a non-volatile memory device because it minimizes the circuit for generating a reference used for a read operation and eliminates global signals and lines for transmitting the reference.

[0009] In addition, embodiments of the present invention can generate references having various voltage levels depending on the characteristics of a non-volatile memory device. Brief explanation of the drawing

[0010] FIG. 1 is a diagram showing the configuration of a non-volatile memory device according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of a non-volatile memory device according to an embodiment of the present invention. FIG. 3 is a timing diagram showing the operation of a non-volatile memory device according to an embodiment of the present invention. FIG. 4 is a diagram showing the configuration of a non-volatile memory device according to an embodiment of the present invention. Figure 5 is a diagram showing the configuration of the variable capacitor illustrated in Figure 4. FIG. 6 is a diagram showing the configuration of a non-volatile memory device according to an embodiment of the present invention. Figure 7 is a diagram showing the connection relationship between a memory cell array and a global switching circuit. Figure 8 is a diagram showing the configuration of the global switching circuit illustrated in Figure 7. FIG. 9 is a block diagram for explaining an electronic device having a non-volatile memory device according to an embodiment of the present invention. FIG. 10 is a block diagram showing a data storage device having a non-volatile memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0011] FIG. 1 is a diagram showing the configuration of a non-volatile memory device (100) according to an embodiment of the present invention. Referring to FIG. 1, the non-volatile memory device (100) may include a memory cell array (110). A plurality of bit lines (BL) may be arranged in the column direction in the memory cell array (110), and a plurality of word lines (WL) may be arranged in the row direction in the memory cell array (110). A plurality of memory cells (MC) may be connected at points where the plurality of bit lines (BL) and the plurality of word lines (WL) intersect. A plurality of memory cells (MC) may each be connected between a corresponding bit line (BL) and a word line (WL). The memory cells (MC) may be composed of a resistance change element and, for example, may include a phase change material. The non-volatile memory device (100) may be a resistive memory device or a phase change memory device. The memory cell array (110) may be composed of a cross-point array.

[0012] The plurality of memory cells (MC) may each include a storage element and a switching element connected to each other. The storage element may maintain a physical state corresponding to the stored data for a long period of time even if a refresh or rewrite operation is not performed. The plurality of memory cells (MC) may be accessed when a voltage greater than a threshold voltage is applied to the switching element connected to the storage element. When a voltage greater than the threshold voltage is applied to the switching element, the switching element is turned on and / or snapped back, and the memory cell may be in a state where current can flow. The storage element may include a floating gate of a dual-gate transistor, a phase change material, a variable resistor material, etc., and the non-volatile memory device may include a PCM (Phase Change Memory), RRAM (Resistive RAM), STTMRAM (Spin Torque Transfer RAM), etc. The switching element may include a two-terminal switching element such as a diode, an ovonic threshold switch, a tunnel junction, or a mixed-ion electric conductor. In one embodiment, the switching element may include a three-terminal switching element such as an electric field-effect transistor or a bipolar junction transistor.

[0013] The memory cell array (110) may have a hierarchical connection structure. A plurality of global bitlines (GBL) and a plurality of local bitlines (not shown) may be arranged in the memory cell array (110). A plurality of global bitlines (GBL) may be connected to a plurality of local bitlines. Each of the plurality of local bitlines may be connected to a plurality of bitlines (BL). Accordingly, a memory cell (MC) of the memory cell array (110) may be accessed by sequentially selecting the global bitline (GBL), local bitline, and bitline (BL). A plurality of global wordlines (GWL) and a plurality of local wordlines (not shown) may be arranged in the memory cell array (110). Each of the plurality of global wordlines (GWL) may be connected to a plurality of local wordlines. Each of the plurality of local wordlines may be connected to a plurality of wordlines (WL). The memory cells of the memory cell array (110) can be accessed sequentially as the global word line (GWL), local word line, and word line (WL) are selected.

[0014] The above non-volatile memory device (100) may include a column selection circuit (120) and a row selection circuit (130). The column selection circuit (120) may be connected between a global bit line (GBL) and a plurality of bit lines (BL). The column selection circuit (120) may connect a selected bit line among the plurality of bit lines (BL) to the global bit line (GBL). The column selection circuit (120) may select a specific bit line among the plurality of bit lines (BL) based on a column selection signal (YS) that may be generated based on a column address signal, and may connect the selected bit line to the global bit line (GBL). The row selection circuit (130) may be connected between a global word line (GWL) and the plurality of word lines (WL). The row selection circuit (130) may connect a selected word line among the plurality of word lines (WL) to the global word line (GWL). The row selection circuit (130) can select a specific word line among the plurality of word lines (WL) based on a row selection signal (XS) that can be generated based on a row address signal, and can connect the selected word line to the global word line (GWL).

[0015] The above non-volatile memory device (100) may include a control circuit to access a memory cell (MC) of the memory cell array (110). The control circuit receives a command signal, an address signal, and a data signal, etc., from a controller of the non-volatile memory device (100), and may access the memory cell (MC) based on the command signal, the address signal, and the data signal to write data to the memory cell (MC) or read data stored in the memory cell. The control circuit may include a bitline control circuit (140) and a wordline control circuit (150). The bitline control circuit (140) may be connected to the global bitline (GBL). The bitline control circuit (140) may change the voltage level of the global bitline (GBL) for read and write operations of the non-volatile memory device (100). The bitline control circuit (140) can receive a lead signal (RD) and a write signal (WT) and change the voltage level of the global bitline (GBL).

[0016] The above read signal (RD) and the above write signal (WT) may be generated based on the command signal received from the controller. The read signal (RD) may be a signal enabled when the non-volatile memory device (100) performs a read operation. The read operation may refer to an operation in which the non-volatile memory device (100) reads data stored in the memory array (110) and outputs the read data to the controller of the non-volatile memory device (100). The above write signal (WT) may be a signal enabled when the non-volatile memory device (100) performs a write operation. The write operation may refer to an operation in which the non-volatile memory device (100) stores or programs a data signal received from the controller in the memory cell array (110). The write operation may include a reset write operation and a set write operation. The above write signal (WT) may include a reset write signal and a set write signal. The memory cell (MC) can be programmed into a low resistance state and a high resistance state to store data. In one embodiment, the memory cell (MC) may have a plurality of low resistance states and a plurality of high resistance states, and may store multi-bit data specified by a plurality of low resistance states and a plurality of high resistance states. The reset write signal may be a signal for programming the memory cell (MC) into a high resistance state, and the set write signal may be a signal for programming the memory cell (MC) into a low resistance state.

[0017] The bitline control circuit (140) may provide at least one voltage to the global bitline (GBL) based on the lead signal (RD) and the write signal (WT). For example, the bitline control circuit (140) may receive a power supply voltage (VPP) and provide a first lead boundary voltage (VBLRD) to the global bitline (GBL) based on the lead signal (RD) during the lead operation. The first lead boundary voltage (VBLRD) may have a voltage level lower than the power supply voltage (VPP). The bitline control circuit (140) may apply a first write boundary voltage (VBLWT) to the global bitline (GBL) based on the write signal (WT) during the write operation. The first write boundary voltage (VBLWT) may be equal to or lower than the power supply voltage (VPP) and may have a voltage level higher than the first lead boundary voltage (VBLRD). As will be described later, the voltage level of the first read boundary voltage (VBLRD) can be set so that a read voltage can be applied across the memory cell (MC), and the voltage level of the first write boundary voltage (VBLWT) can be set so that a write voltage can be applied across the memory cell (MC). The read voltage may have an appropriate voltage level capable of determining the resistance state of the memory cell (MC). For example, the read voltage may have a voltage level that is higher than the maximum threshold voltage of a memory cell distribution in a low resistance state and lower than the minimum threshold voltage of a memory cell distribution in a high resistance state.

[0018] The wordline control circuit (150) may be connected to the global wordline (GWL). The wordline control circuit (150) may change the voltage level of the global wordline (GWL) for read and write operations of the non-volatile memory device (100). The wordline control circuit (150) may receive the read signal (RD) and the write signal (WT) and provide at least one voltage to the global wordline (GWL). The wordline control circuit (150) may change the current flowing through the global wordline (GWL) based on the read signal (RD) and the write signal (WT) to change the current flowing through the memory cell (MC).

[0019] The wordline control circuit (150) may provide one or more voltages and one or more currents to the global wordline (GWL) based on the lead signal (RD) and the write signal (WT). For example, the wordline control circuit (150) may receive a second lead boundary voltage (VWLRD) and apply the second lead boundary voltage (VWLRD) to the global wordline (GWL) based on the lead signal (RD) during the lead operation. The second lead boundary voltage (VWLRD) may have a lower voltage level than the first lead boundary voltage (VBLRD). For example, the second lead boundary voltage (VWLRD) may be a negative voltage having a voltage level below ground voltage. The voltage level of the second lead boundary voltage (VWLRD) can be set so that the difference in voltage levels between the first lead boundary voltage (VBLRD) and the second lead boundary voltage (VWLRD) corresponds to the level of the lead voltage. The wordline control circuit (150) can cause a clamping current to flow through the global wordline (GWL) based on the lead signal (RD). The clamping current may have a minimum amount of current that changes the voltage level of the global wordline (GWL) according to the resistance state of the memory cell (MC) when the memory cell (MC) is turned on.

[0020] The wordline control circuit (150) receives the second light boundary voltage (VWLWT) and can apply the second light boundary voltage (VWLWT) to the global wordline (GWL) based on the light signal (WT). The second light boundary voltage (VWLWT) may have a voltage level equal to or lower than the second lead boundary voltage (VWLRD). The voltage level of the second light boundary voltage (VWLWT) may be set so that the difference in voltage levels between the first light boundary voltage (VBLWT) and the second light boundary voltage (VWLWT) corresponds to the level of the light voltage. The wordline control circuit (150) allows various currents to flow through the global wordline (GWL) based on the light signal (WT). For example, the wordline control circuit (150) may cause a set current to flow through the global wordline (GWL) to program the memory cell (MC) to a low resistance state based on a set write signal. The wordline control circuit (150) may cause a reset current to flow through the global wordline (GWL) to program the memory cell (MC) to a high resistance state based on a reset write signal. The set current may be smaller than the reset current. The time during which the set current flows to program the memory cell (MC) to a low resistance state may be longer than the time during which the reset current flows to program the memory cell to a high resistance state.

[0021] The above non-volatile memory device (100) may further include a sense amplifier (160) and a reference generator (170). The sense amplifier (160) may be connected to the global word line (GWL). The sense amplifier (160) may be connected to a reference line (RL). The sense amplifier (160) may generate an output signal (DOUT) by comparing the voltage level of the global word line (GWL) and the voltage level of the reference line (RL) during a read operation of the non-volatile memory device (100). During the read operation, the voltage level of the global word line (GWL) may change according to the data stored in the memory cell (MC) connected to the global word line (GWL). The voltage level of the global word line (GWL) may change between a set detection voltage and a reset detection voltage. When the memory cell (MC) is in a low resistance state, the voltage level of the global word line (GWL) may change to the voltage level of the set detection voltage. When the memory cell (MC) is in a high resistance state, the voltage level of the global word line (GWL) may change to the reset detection voltage having a voltage level relatively lower than the set detection voltage. The sense amplifier (160) may receive a sensing enable signal (SEN). The sensing enable signal (SEN) may be enabled after the voltage level change of the global word line (GWL) is sufficiently developed according to the data stored in the memory cell (MC). The sensing enable signal (SEN) may be enabled in the form of a pulse at any point between the time after which the read voltage is applied to the memory cell (MC) and the time required for the snapback of the memory cell to occur, and the time when the read operation ends.

[0022] The reference generator (170) may be connected to the reference line (RL). The reference generator (170) may change the voltage level of the reference line (RL). The reference generator (170) may set the voltage level of the reference line (RL) to a voltage level corresponding to the reference voltage during the lead operation. The reference voltage may have a voltage level between the set detection voltage and the reset detection voltage, and preferably may have a voltage level corresponding to the middle of the set detection voltage and the reset detection voltage. The reference generator (170) may have a capacitor connected to the reference line (RL) and may change the voltage level of the reference line (RL) by charging or discharging the capacitor.

[0023] Although not illustrated, the control circuit may further include a column decoding circuit and a row decoding circuit. The column decoding circuit may generate a column address signal based on an address signal received from the controller and may generate a column select signal (YS) to select a global bit line (GBL) and a bit line connected to a memory cell (MC) to be accessed based on the column address signal. The row decoding circuit may generate a row address signal based on an address signal received from the controller and may generate a row select signal (XS) to select a global word line and a word line connected to a memory cell (MC) to be accessed based on the row address signal.

[0024] FIG. 2 is a diagram showing the configuration of a non-volatile memory device (200) according to an embodiment of the present invention. FIG. 2 may partially illustrate components for accessing a memory cell and performing a read operation among the components of the non-volatile memory device (100) shown in FIG. 1. The memory cell being accessed may also be referred to as a target memory cell. Referring to FIG. 2, the non-volatile memory device (200) includes a memory cell (210), and one end of the memory cell (210) may be connected to a bit line (BL), and the other end of the memory cell (210) may be connected to a word line (WL). The bit line (BL) may be connected to a global bit line (GBL) through a local bit line (LBL), and the word line (WL) may be connected to a global word line (GWL) through a local word line (LWL).

[0025] The above non-volatile memory device (200) may include a bitline control circuit (240), a wordline control circuit (250), a sense amplifier (260), and a reference generator (270). The bitline control circuit (240) may receive a power supply voltage (VPP) and provide a first read boundary voltage (VBLRD) to the global bitline (GBL) based on the read control signal (RDEN). Since the bitline control circuit (240) may include a P-channel MOS transistor, it may operate by receiving a complementary signal (RDENB) of the read control signal. The read control signal (RDEN) may be a signal generated from the read signal (RD) of FIG. 1. The wordline control circuit (250) may provide a second read boundary voltage (VWLRD) to the global wordline (GWL) based on the read control signal (RDEN). The wordline control circuit (250) can cause a clamping current (Ic) to flow through the global wordline (GWL) based on the lead control signal (RDEN). The wordline control circuit (250) can precharge the voltage level of the global wordline (GWL) to the second lead boundary voltage (VWLRD) based on the precharge signal (PCG). The precharge signal (PCG) can be generated from the lead control signal (RDEN).

[0026] The sense amplifier (260) is connected to the global word line (GWL) and the reference line (RL), and can generate an output signal (DOUT) by comparing the voltage level of the global word line (GWL) with the voltage level of the reference line (RL). The sense amplifier (260) may include a first input terminal (+) and a second input terminal (-). The first input terminal (+) may be connected to the global word line (GWL), and the second input terminal (-) may be connected to the reference line (RL). The voltage level of the global word line (GWL) may change according to the data stored in the memory cell (210). When the memory cell (210) is in a low resistance state, the voltage level of the global word line (GWL) can be changed to a set detection voltage, and when the memory cell (210) is in a high resistance state, the voltage level of the global word line (GWL) can be changed to a reset detection voltage.

[0027] The reference generator (270) can precharge the voltage level of the reference line (RL) based on the lead control signal (RDEN) and set the voltage level of the reference line (RL) to a voltage level corresponding to the reference voltage. The reference voltage may have a voltage level between the set detection voltage and the reset detection voltage, and may have a voltage level corresponding to the middle of the set detection voltage and the reset detection voltage. The reference generator (270) may include a capacitor (271) connected to the reference line (RL). The reference generator (270) can change the voltage level of the reference line (RL) by providing one of a first low voltage (VL1) and a second low voltage (VL2) to the capacitor (271) to charge and discharge the capacitor (271). The first low voltage (VL1) may have a higher voltage level than the second low voltage (VL2) and may have a higher voltage level than the second lead boundary voltage (VWLRD). The first low voltage (VL1) may have a lower voltage level than the first lead boundary voltage (VBLRD). The second low voltage (VL2) may have a voltage level equal to or lower than the second lead boundary voltage (VWLRD). The reference generator (270) may increase the voltage level of the reference line (RL1) by providing the first low voltage (VL1) to the capacitor (271) and discharge the capacitor (271) by providing the second low voltage (VL2) to the capacitor (271). The reference generator (270) can provide one of the first and second low voltages (VL1, VL2) to a capacitor (271) connected to the reference line (RL) based on a boosting control signal (BSTEN). The boosting control signal (BSTEN) can be generated based on the precharge signal (PCG) and the lead control signal (RDEN).

[0028] The above non-volatile memory device (200) may include a local column switch (221), a global column switch (222), a local row switch (231), and a global row switch (232). The local column switch (221) and the global column switch (222) may be components of the column selection circuit (120) of FIG. 1, and the local row switch (231) and the global row switch (232) may be components of the row selection circuit (130) of FIG. 1. The local column switch (221) may connect a bit line (BL) connected to the memory cell (210) to a local bit line (LBL) based on a local column selection signal (LY). The global column switch (222) may connect the local bit line (LBL) to the global bit line (GBL) based on a global column selection signal (GY). The column selection signal (YS) of FIG. 1 may include the local column selection signal (LY) and the global column selection signal (GY). The local row switch (231) may connect the word line (WL) connected to the memory cell (210) to the local word line (LWL) based on the local row selection signal (LX). The global row switch (232) may connect the local word line (LWL) to the global word line (GWL) based on the global row selection signal (GX). The row selection signal (XS) of FIG. 1 may include the local row selection signal (LX) and the global row selection signal (GX).

[0029] The wordline control circuit (250) may include a first switch (S1), a second switch (S2), and a current source (I1). The first switch (S1) is connected between the global wordline (GWL) and the terminal to which the second lead boundary voltage (VWLRD) is supplied, and can receive the precharge signal (PCG). When the precharge signal (PCG) is enabled, the first switch (S1) can precharge the global wordline (GWL) to the second lead boundary voltage (VWLRD) by connecting the global wordline (GWL) to the terminal to which the second lead boundary voltage (VWLRD) is supplied. The second switch (S2) is connected between the global wordline (GWL) and the current source (I1) and can receive the lead control signal (RDEN). The second switch (S2) can connect the global word line (GWL) and the current source (I1) when the lead control signal (RDEN) is enabled. The current source (I1) can be connected between the second switch (S2) and the terminal to which the second lead boundary voltage (VWLRD) is supplied. The current source (I1) can generate the clamping current (Ic). When the lead control signal (RDEN) is enabled, the current source (I1) can cause the clamping current (Ic) to flow through the global word line (GWL).

[0030] The reference generator (270) may include the capacitor (271), the precharge circuit (272), and the boosting control circuit (273). The precharge circuit (272) receives the precharge signal (PCG) and can precharge the reference line (RL) to the second lead boundary voltage (VWLRD) based on the precharge signal (PCG). When the precharge signal (PCG) is enabled, the precharge circuit (272) can provide the second lead boundary voltage (VWLRD) to the reference line (RL) to change the voltage level of the reference line (RL) to a voltage level corresponding to the second lead boundary voltage (VWLRD). The capacitor (271) may be a boosting capacitor for boosting the voltage level of the reference line (RL). One end of the capacitor (271) may be connected to the reference line (RL), and the other end of the capacitor (271) may be connected to the boosting control circuit (273). The boosting control circuit (273) may charge and discharge the capacitor (271) by providing one of the first low voltage (VL1) and the second low voltage (VL2) to the capacitor (271) based on the boosting control signal (BSTEN). The boosting control circuit (273) may charge the capacitor (271) by providing the first low voltage (VL1) to the capacitor (271) when the boosting control signal (BSTEN) is enabled. The boosting control circuit (273) can discharge the capacitor (271) by providing the second low voltage (VL2) to the capacitor (271) when the boosting control signal (BSTEN) is disabled.

[0031] The reference generator (270) may further include a reference switching circuit (274). The reference switching circuit (274) receives the lead control signal (RDEN) and can connect the reference line (RL) and the capacitor (271) based on the lead control signal (RDEN). The reference switching circuit (274) can connect the reference line (RL) to the capacitor (271) when the lead control signal (RDEN) is enabled. When the lead enable signal (RDEN) is disabled, the reference switching circuit (274) can electrically disconnect the capacitor (271) from the reference line (RL) to prevent the voltage level of the reference line (RL) from changing due to the capacitor (271) and to prevent the consumption of constant current.

[0032] The above precharge circuit (272) may include a third switch (S3). The third switch (S3) is connected between the reference line (RL) and the terminal to which the second lead boundary voltage (VWLRD) is supplied, and can receive the precharge signal (PCG). The third switch (S3) can connect the reference line (RL) to the terminal to which the second lead boundary voltage (VWLRD) is supplied when the precharge signal (PCG) is enabled.

[0033] The boosting control circuit (274) may include a fourth switch (S4) and a fifth switch (S5). The fourth switch (S4) is connected between the other end of the capacitor (271) and the terminal to which the first low voltage (VL1) is supplied, and can receive the boosting control signal (BSTEN). The fourth switch (S4) can connect the other end of the capacitor (271) to the terminal to which the first low voltage (VL1) is supplied when the boosting control signal (STEN) is enabled. The fifth switch (S5) is connected between the other end of the capacitor (271) and the terminal to which the second low voltage (VL2) is supplied, and can receive the complementary signal (BSTENB) of the boosting control signal. The above 5th switch (S5) can connect the other end of the capacitor (271) to the terminal to which the second low voltage (VL2) is supplied when the boosting control signal (BSTEN) is disabled.

[0034] The reference switching circuit (274) may include a sixth switch (S6). The sixth switch (S6) is connected between the reference line (RL) and one end of the capacitor (271) and can receive the read enable signal (RDEN). The sixth switch (S6) can connect the capacitor (271) to the reference line (RL) when the read enable signal (RDEN) is enabled.

[0035] FIG. 3 is a timing diagram showing the operation of a non-volatile memory device according to an embodiment of the present invention. Referring to FIGS. 1 to 3 together, the operation of a non-volatile memory device (200) according to an embodiment of the present invention is described as follows. A controller of the non-volatile memory device (200) may provide a command signal and an address signal to the non-volatile memory device (200) to read data stored in a target memory cell (210). A control circuit of the non-volatile memory device (200) may enable the read signal (RD) based on the command signal and generate the column select signal (YS) and the row select signal (XS) based on the address signal. When the global column select signal (GY) and the local column select signal (LY) are enabled, a bit line (BL), a local bit line (LBL), and a global bit line (GBL) connected to the target memory cell (210) may be selected. When the global low select signal (GY) and the local low select signal (LY) are enabled, the word line (WL), local word line (LWL), and global word line (GWL) connected to the target memory cell (210) can be selected. The voltage level of the selected global word line (GWL) can maintain an initial voltage level (Vint). The initial voltage level (Vint) is the voltage level of the global word line when no access operation is performed on the memory cell, for example, the initial voltage level (Vint) can correspond to ground voltage.

[0036] Based on the lead signal (RD), the lead control signal (RDEN) can be enabled. The lead control signal (RDEN) can remain enabled while the lead operation is being performed. When the lead control signal (RDEN) is enabled, the precharge signal (PCG) can be enabled in the form of a pulse. The wordline control circuit (250) can precharge the selected global wordline (GWL) to the voltage level of the second lead boundary voltage (VWLRD) based on the precharge signal (PCG). Additionally, when the precharge signal (PCG) is enabled, the reference generator (270) can precharge the reference line (RL) to the second lead boundary voltage (VWLRD). Thus, when the precharge signal (PCG) is enabled, the voltage levels of the selected global wordline (GWL) and the reference line (RL) can become the same. The reference generator (270) can connect the capacitor (271) to the reference line (RL) based on the lead control signal (RDEN).

[0037] The bitline control circuit (240) provides the first read boundary voltage (VBLRD) to the selected global bitline (GBL) based on the read control signal (RDEN), and the voltage level of the selected global bitline (GBL) can be raised to a voltage level corresponding to the first read boundary voltage (VBLRD). The wordline control circuit (250) provides the second read boundary voltage (VWLRD) to the selected global wordline (GWL) based on the read control signal (RDEN), and can cause a clamping current (Ic) to flow through the selected global wordline (GWL). Accordingly, the voltage level of the selected global wordline (GWL) can be lowered from the initial voltage level (Vint) to a voltage level corresponding to the second read boundary voltage (VWLRD), and a read voltage can be applied across the target memory cell (210). When the precharge signal (PCG) is disabled, the reference line (RL) is floated, and the boosting control signal (BSTEN) can be enabled. When the boosting control signal (BSTEN) is enabled, the boosting control circuit (273) provides the first low voltage (VL1) to the capacitor (271), and as the capacitor (271) is charged, the voltage level of the reference line (RL) can be boosted. Thus, the voltage level of the reference line (RL) can be raised to a voltage level corresponding to the reference voltage (REF).

[0038] When the data stored in the target memory cell (210) is set data and the target memory cell (210) is in a low resistance state (indicated by a dotted line), the target memory cell (210) can be snapped back by the read voltage, and the amount of current (Icell) flowing through the target memory cell (210) can increase rapidly, causing a spike. After the spike occurs, the current flowing through the target memory cell (210) can correspond to a clamping current (Ic), and the voltage level of the selected global word line (GWL) can rise to the level of the set detection voltage (GWL(SET)). The sense amplifier (260) can compare the voltage level of the selected global word line (GWL) and the reference line (RL) when the sensing enable signal (SEN) is enabled. Since the voltage level of the selected global word line (SWL) is higher than the voltage level of the reference line (RL), the sense amplifier (260) can generate an output signal (DOUT) having a logic high level.

[0039] When the data stored in the target memory cell (210) is reset data and the target memory cell (210) is in a high resistance state (indicated by a dashed line), the target memory cell (210) may not snap back even if the read voltage is applied. Therefore, the amount of current (Icell) flowing through the memory cell (210) does not change, and the voltage level of the selected global word line (GWL) can have a voltage level of the reset detection voltage (GWL(RST)) while maintaining the precharged voltage level. The sense amplifier (260) can compare the voltage levels of the selected global word line (GWL) and the reference line (RL) when the sensing enable signal (SEN) is enabled. Since the voltage level of the selected global word line (GWL) is lower than the voltage level of the reference line (RL), the sense amplifier (260) can generate an output signal (DOUT) having a logic low level.

[0040] The reference generator (270) can form a reference for detecting the voltage level of the selected global word line (GWL) by pre-charging the voltage level of the reference line (RL) to be equal to the voltage level of the selected global word line (GWL), and then boosting the voltage level of the reference line (RL) through a capacitor (271) connected to the reference line (RL). Accordingly, the reference generator (270) can generate a valid reference within the range in which the voltage level of the selected global word line (GWL) changes with only a simple circuit configuration. In addition, by providing the reference generator (270), the core area efficiency of the non-volatile memory device (200) can be increased because the conventional reference voltage generation circuit and the global line for the reference voltage generation circuit to provide a reference voltage to the sense amplifier (260) can be eliminated.

[0041] FIG. 4 is a diagram showing the configuration of a non-volatile memory device (400) according to an embodiment of the present invention. The non-volatile memory device (400) has the same configuration as the non-volatile memory device (200) shown in FIG. 2, except for some components, and redundant descriptions of the same components are omitted. Referring to FIG. 4, the reference generator (470) in the non-volatile memory device (400) may include a variable capacitor (471). The variable capacitor (471) receives a trimming control signal (TC<1:n>) and may have a capacitance that varies based on the trimming control signal (TC<1:n>). The non-volatile memory device (400) can finely adjust the voltage level of the reference line (RL) and optimize the voltage level of the reference line (RL) by varying the capacitance of the variable capacitor (471).

[0042] FIG. 5 is a diagram showing the configuration of the variable capacitor (471) illustrated in FIG. 4. Referring to FIG. 5, the variable capacitor (471) may include n+1 capacitors and n switches. The n+1 capacitors may each have the same capacitance, or some or all of them may have different capacitances. The first capacitor (C1) may be connected between the reference line (RL) and the boosting control circuit (273). The second capacitor (C2) and the first switch (S11) may be connected in series between the reference line (RL) and the boosting control circuit (273). The first switch (S11) is the first bit (TC) of the trimming control signal. <1> ) can be received. The first switch (S11) is the first bit (TC) of the trimming control signal. <1> When ) is at a logic high level, the second capacitor (C2) can be connected between the reference line (RL) and the boosting control circuit (273) to increase the capacitance of the variable capacitor (471). The n+1 capacitor (Cn+1) and the n switch (S1n) can be connected in series between the reference line (RL) and the boosting control circuit (273). The n switch (S1n) is the n-th bit (TC) of the trimming control signal. <n>) can be received. The n-th switch (S1n) is the n-th bit (TC) of the trimming control signal. <n>When the logic is at a high level, the n+1 capacitor (Cn+1) can be connected between the reference line (RL) and the boosting control circuit (273) to increase the capacitance of the variable capacitor (471).

[0043] FIG. 6 is a diagram showing the configuration of a non-volatile memory device (600) according to an embodiment of the present invention. The non-volatile memory device (600) has the same configuration as the non-volatile memory device (200) shown in FIG. 2, except for some components, and redundant descriptions of the same components are omitted. Referring to FIG. 6, the memory cell (210) is connected to a first global word line (GWLU), and the second global word line (GWLD) may be connected to a memory cell (not shown) other than the memory cell (210). A sense amplifier (660) may be connected to the first and second global word lines (GWLU, GWLD). The sense amplifier (660) may include a first input terminal (+) and a second input terminal (-). The first input terminal (+) of the sense amplifier (660) may be connected to a global word line connected to the memory cell (210) and the memory cell being accessed among the other memory cells. The second input terminal (-) of the sense amplifier (660) may be connected to a global word line connected to the memory cell and the memory cell that is not being accessed among the other memory cells. The first input terminal (+) may be connected to a selected global word line, and the second input terminal (-) may be connected to a non-selected global word line. The sense amplifier (660) may generate an output signal (DOUT) by comparing the voltage levels of the first and second input terminals (+, -).

[0044] The wordline control circuit (650) can be connected to the first input terminal (+) of the sense amplifier (660). The reference generator (670) can be connected to the second input terminal (-) of the sense amplifier (660). The reference generator (670) includes a capacitor (671) connected to the second input terminal (-), and can change the voltage level of the second input terminal (-) and / or the unselected global wordline by charging and discharging the capacitor (671).

[0045] The above non-volatile memory device (600) may further include a global switching circuit (680). The global switching circuit (680) is connected to the first global word line (GWLU) and the second global word line (GWLD), and the first and second global word lines (GWLU, GWLD) may be connected to the first and second input terminals (+, -) of the sense amplifier (660), respectively. When a read operation is performed on the memory cell (210), the global switching circuit (680) may connect the first global word line (GWLU) to the first input terminal (+) of the sense amplifier (660) and connect the second global word line (GWLD) to the second input terminal (-) of the sense amplifier (660). The sense amplifier (660) may use the second global word line (GWLD), which is a non-selected word line, as a reference line to detect the voltage level of the first global word line (GWLU), which is a selected global word line. When a read operation is performed on the other memory cell, the global switching circuit (680) may connect the first global word line (GWLU) to the second input terminal (-) of the sense amplifier (660) and connect the second global word line (GWLD) to the first input terminal (+) of the sense amplifier (660). The sense amplifier (660) may use the first global word line (GWLU), which is a non-selected word line, as a reference line to detect the voltage level of the second global word line (GWLD), which is a selected global word line.

[0046] FIG. 7 is a diagram showing the connection relationship between a memory cell array (710) and a global switching circuit (780). The connection relationship of the components shown in FIG. 7 can be applied to the connection relationship of the memory cell (210), other memory cells, the first global word line (GWLU), the second global word line (GWLD), the global switching circuit (680), and the sense amplifier (660) shown in FIG. 6. The memory cell array (710) may be composed of an up tile (711) and a down tile (712). The up tile (711) and the down tile (712) may constitute a sub-memory cell array of the memory cell array (710). The down tile (712) may be a sub-memory cell array adjacent to the up tile (711). The same number of word lines may be arranged in the up tile (711) and the down tile (712), respectively. In one embodiment, the number of word lines placed on the up tile (711) may differ from the number of word lines placed on the down tile (712). The first global word line (GWLU) may be connected to the word line (WLm) placed on the up tile (711), and the second global word line (GWLD) may be connected to the word line (WLk) placed on the down tile (712). Here, m and k may be any natural numbers. The first global word line (GWLU) may be connected to the word line (WLm) through the first local low switch (7311) and the first global low switch (7321). The first local low switch (7311) may connect the word line (WLm) to the local word line (LWLU) based on the first local low select signal (LX1). The first global low switch (7321) can connect the local word line (LWLU) to the first global word line (GWLU) based on the first global low select signal (GX1).The second global word line (GWLD) can be connected to the word line (WLk) through the second local low switch (7312) and the second global low switch (7322). The second local low switch (7312) can connect the word line (WLk) to the local word line (LWLD) based on the second local low select signal (LX2). The second global low switch (7322) can connect the local word line (LWLD) to the second global word line (GWLD) based on the second global low select signal (GX2). The global switching circuit (780) can connect the first and second global word lines (GWLU, GWLD) to the first and second input terminals (+, -) of the sense amplifier (660), respectively. The global switching circuit (780) can connect one of the first and second global word lines (GWLU, GWLD) to the first input terminal (+) of the sense amplifier (660) based on the tile selection signal (TSEL), and connect the other of the first and second global word lines (GWLU, GWLD) to the second input terminal (-) of the sense amplifier (660).

[0047] The control circuit of the non-volatile memory device (600) may enable the first global row select signal (GX1) and the second global row select signal (GX2) together based on some bits of the row address signal. The control circuit may enable one of the first and second local row select signals (LX1, LX2) based on the remaining bits of the row address signal, and may selectively enable the tile select signal (TSEL). For example, when a memory cell connected to a word line (WLm) placed on the up tile (711) is accessed, the first global row select signal (GX1) and the second global row select signal (GX2) may be enabled together. The first local row select signal (LX1) may be enabled, but the second local row select signal (LX2) may not be enabled. Additionally, the tile selection signal (TSEL) may be enabled. Accordingly, the global switching circuit (780) may connect the first global word line (GLWU) to the first input terminal (+) of the sense amplifier (660) and the second global word line (GWLD) to the second input terminal (-) of the sense amplifier (660). Conversely, when a memory cell connected to the word line (WLk) placed on the down tile (712) is accessed, the first and second global row selection signals (GX1, GX2) may be enabled together. The second local row selection signal (LX2) may be enabled, but the first local row selection signal (LX1) may not be enabled. Additionally, the tile selection signal (TSEL) may be disabled. Accordingly, the global switching circuit (780) can connect the second global word line (GWLD) to the first input terminal (+) of the sense amplifier (660) and connect the first global word line (GWLU) to the second input terminal (-) of the sense amplifier (660).

[0048] FIG. 8 is a diagram showing the configuration of the global switching circuit (780) illustrated in FIG. 7. Referring to FIG. 8, the global switching circuit (780) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), and a fourth transistor (T4). The first to fourth transistors (T1, T2, T3, T4) may be N-channel MOS transistors. The first transistor (T1) is connected between the first global word line (GWLU) and the second input terminal (-) of the sense amplifier (660) and can receive the complementary signal (TSELB) of the tile selection signal through its gate. The second transistor (T2) is connected between the first global word line (GWLU) and the first input terminal (+) of the sense amplifier (660) and can receive the tile selection signal (TSEL) through its gate. The third transistor (T3) is connected between the second global word line (GWLD) and the first input terminal (+) of the sense amplifier (660), and can receive the complementary signal (TSELB) of the tile selection signal through its gate. The fourth transistor (T4) is connected between the second global word line (GWLD) and the second input terminal (-) of the sense amplifier (660), and can receive the tile selection signal (TSEL) through its gate. When the tile selection signal (TSEL) is enabled to a logic high level, the second transistor (T2) and the fourth transistor (T4) can be turned on, and the first transistor (T1) and the third transistor (T3) can be turned off. The second transistor (T2) can connect the first global word line (GWLU) to the first input terminal (+) of the sense amplifier (660), and the fourth transistor (T4) can connect the second global word line (GWLD) to the second input terminal (-) of the sense amplifier (660).When the tile selection signal (TSEL) is disabled to a logic low level, the first transistor (T1) and the third transistor (T3) can be turned on, and the second transistor (T2) and the fourth transistor (T4) can be turned off. The first transistor (T1) can connect the first global word line (GWLU) to the second input terminal (-) of the sense amplifier (660), and the third transistor (T3) can connect the second global word line (GWLD) to the first input terminal (+) of the sense amplifier (660).

[0049] FIG. 9 is a block diagram for illustrating an electronic device having a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 9, the electronic device (4200) may include a processor (4210), a memory (4220), and an input / output device (I / O, 4230). The processor (4210), the memory (4220), and the input / output device (4230) may be connected via a bus (4246).

[0050] The memory (4220) may receive control signals from the processor (4210). The memory (4220) may store code and data for the operation of the processor (4210). The memory (4220) may be used to store data accessed through the bus (4246). The memory (4220) may include at least one of the non-volatile memory devices (100, 200, 400, 600) according to the embodiments of the present invention described above. For specific realization and modification of the invention, additional circuits and control signals may be provided.

[0051] The electronic device (4200) can be configured to include various electronic control devices that require the memory (4220). For example, the electronic device (4200) can be used in computer systems, wireless communication devices such as PDAs, laptop computers, portable computers, web tablets, cordless telephones, mobile phones, digital music players, MP3 players, navigation systems, solid state disks (SSDs), household appliances, or any device capable of transmitting and receiving information in a wireless environment.

[0052] FIG. 10 is a block diagram showing a data storage device having a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 10, a data storage device such as a solid state disk (SSD; 4311) may be provided. The solid state disk (SSD; 4311) may include an interface (4313), a controller (4315), a non-volatile memory (4318), and a buffer memory (4319).

[0053] The solid state disk (4311) is a device that stores information using a semiconductor device. The solid state disk (4311) has the advantages of being faster than a hard disk drive (HDD), having less mechanical delay or failure rate, less heat generation and noise, and being able to be miniaturized and lightweight. The solid state disk (4311) can be widely used in notebook PCs, netbooks, desktop PCs, MP3 players, or portable storage devices.

[0054] The controller (4315) may be formed adjacent to and electrically connected to the interface (4313). The controller (4315) may be a microprocessor including a memory controller and a buffer controller. The non-volatile memory (4318) may be formed adjacent to the controller (4315) and electrically connected to the controller (4315) via a connection terminal (T). The data storage capacity of the solid-state disk (4311) may correspond to the non-volatile memory (4318). The buffer memory (4319) may be formed adjacent to and electrically connected to the controller (4315).

[0055] The interface (4313) can be connected to a host (4302) and can transmit and receive electrical signals such as data. For example, the interface (4313) may be a device using a standard such as SATA, IDE, SCSI, and / or a combination thereof. The non-volatile memory (4318) may be connected to the interface (4313) via the controller (4315).

[0056] The above non-volatile memory (4318) can serve to store data received through the interface (4313). The above non-volatile memory (4318) may include at least one of the non-volatile memory devices (100, 200, 400, 600) according to the embodiments of the present invention described above. Even if the power supply to the solid state disk (4311) is cut off, the data stored in the above non-volatile memory (4318) has the characteristic of being preserved.

[0057] The above buffer memory (4319) may include volatile memory or non-volatile memory. The volatile memory may be DRAM and / or SRAM. The non-volatile memory may include at least one of the non-volatile memory devices (100, 200, 400, 600) according to the embodiments of the present invention described above.

[0058] The data processing speed of the interface (4313) may be relatively faster than the operating speed of the non-volatile memory (4318). Here, the buffer memory (4319) may serve to temporarily store data. Data received through the interface (4313) may be temporarily stored in the buffer memory (4319) via the controller (4315), and then permanently stored in the non-volatile memory (4318) in accordance with the data writing speed of the non-volatile memory (4318).

[0059] Additionally, frequently used data among the data stored in the non-volatile memory (4318) can be read out in advance and temporarily stored in the buffer memory (4319). That is, the buffer memory (4319) can serve to increase the effective operating speed of the solid-state disk (4311) and reduce the error rate.

[0060] Those skilled in the art to which the present invention pertains should understand that the embodiments described above are illustrative in all respects and not restrictive, as the present invention may be implemented in other specific forms without altering its technical concept or essential features. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention.< / n> < / n>

Claims

Claim 1 A non-volatile memory device comprising: a control circuit that applies a read voltage to a target memory cell through a selected global bitline and a selected global wordline; a sense amplifier that generates an output signal by comparing the voltage levels of the selected global wordline and a non-selected global wordline not connected to the target memory cell; and a reference generator that changes the voltage level of the non-selected global wordline by charging and discharging a capacitor connected to the non-selected global wordline. Claim 2 In claim 1, the control circuit comprises: a bitline control circuit that provides a first lead boundary voltage to the selected global bitline based on a lead control signal; and a wordline control circuit that provides a second lead boundary voltage to the selected global wordline based on the lead control signal and causes a clamping current to flow through the global wordline, wherein the voltage level difference between the first and second lead boundary voltages corresponds to the voltage level of the lead voltage, a non-volatile memory device. Claim 3 A non-volatile memory device according to claim 1, wherein the voltage level of the global wordline changes between a set detection voltage and a reset detection voltage according to data stored in the target memory cell, and the reference generator sets the voltage level of the unselected global wordline to a voltage level corresponding to the middle of the set detection voltage and the reset detection voltage. Claim 4 A non-volatile memory device according to claim 1, wherein the reference generator comprises: a precharge circuit that precharges the unselected global wordline based on a read control signal; the capacitor, one end of which is connected to the unselected global wordline; and a boosting control circuit that provides one of a first low voltage and a second low voltage to the other end of the capacitor based on a boosting control signal. Claim 5 A non-volatile memory device according to claim 4, wherein the reference generator further comprises a reference switching circuit provided between the non-selected global word line and the one end of the capacitor, and connecting the one end of the capacitor to the non-selected global word line based on the read control signal. Claim 6 In claim 4, the boosting control circuit provides the first low voltage to the capacitor when the boosting control signal is enabled, and provides the second low voltage to the capacitor when the boosting control signal is disabled, and the first low voltage is a non-volatile memory device having a voltage level higher than the second low voltage. Claim 7 In claim 4, the first low voltage is a non-volatile memory device having a voltage level higher than the voltage provided to the selected global wordline by the control circuit. Claim 8 In claim 4, the capacitor further receives a trimming control signal and is a non-volatile memory device having a variable capacitance based on the trimming control signal. Claim 9 delete Claim 10 A non-volatile memory device according to claim 1, wherein the selected global word line is placed on a first tile of a memory cell array and the unselected global word line is placed on a second tile of the memory cell array, and further comprising a global switching circuit that connects the unselected global word line to the sense amplifier based on a tile selection signal that selects one of the first and second tiles. Claim 11 A method of operation of a non-volatile memory device for accessing a target memory cell connected between a selected bit line and a selected word line, comprising: a step of applying a first read boundary voltage to the selected bit line and applying a second read boundary voltage to the selected word line, and pre-charging a reference line with the second read boundary voltage; a step of providing a first low voltage to a capacitor connected to the reference line to raise the voltage level of the reference line; and a step of generating an output signal by comparing the voltage level of the selected word line, which changes according to data stored in the target memory cell, with the voltage level of the reference line. Claim 12 A method of operation of a non-volatile memory device according to claim 11, wherein the step of applying a second lead boundary voltage to the selected word line comprises the step of precharging the selected word line with the second lead boundary voltage and causing a clamping current to flow through the selected word line. Claim 13 A method of operation of a non-volatile memory device according to claim 11, wherein the first lead boundary voltage has a higher voltage level than the second lead boundary voltage, and the voltage level difference between the first and second lead boundary voltages corresponds to the voltage level of the lead voltage. Claim 14 In claim 11, the method of operation of a non-volatile memory device having a voltage level higher than the second lead boundary voltage, wherein the first low voltage is a voltage level higher than the second lead boundary voltage. Claim 15 A method of operation of a non-volatile memory device according to claim 11, wherein when the target memory cell is in a low resistance state, the voltage level of the selected word line changes to a set detection voltage, and when the target memory cell is in a high resistance state, the voltage level of the selected word line changes to a reset detection voltage, and the voltage level of the raised reference line has a voltage level between the set detection voltage and the reset detection voltage. Claim 16 A method of operation of a non-volatile memory device according to claim 11, further comprising the step of providing a second low voltage to a capacitor connected to the reference line after the step of generating the output signal. Claim 17 In claim 16, the method of operation of a non-volatile memory device having a voltage level lower than the first low voltage, wherein the second low voltage is lower than the first low voltage. Claim 18 A non-volatile memory device comprising: a first global word line connected to a first memory cell; a second global word line connected to a second memory cell; a sense amplifier comprising a first input terminal connected to a global word line connected to a memory cell accessed among the first and second memory cells, and a second input terminal connected to a global word line connected to a memory cell not accessed, and generating an output signal by comparing the voltage levels of the first and second input terminals; and a reference generator that changes the voltage level of the second input terminal by charging and discharging a capacitor connected to the second input terminal. Claim 19 A non-volatile memory device according to claim 18, wherein the voltage level of the first input terminal changes between a set detection voltage and a reset detection voltage according to data stored in the accessed memory cell, and the reference generator sets the voltage level of the second input terminal to a voltage level corresponding to the middle of the set detection voltage and the reset detection voltage. Claim 20 In claim 18, the reference generator comprises: a precharge circuit that precharges the voltage level of the second input terminal based on a read control signal; the capacitor having one end connected to the second input terminal; and a boosting control circuit that provides one of a first low voltage and a second low voltage to the other end of the capacitor based on a boosting control signal, thereby forming a non-volatile memory device. Claim 21 A non-volatile memory device according to claim 20, wherein the reference generator is provided between a global word line connected to the unaccessible memory cell and one end of the capacitor, and further comprises a switching circuit that connects one end of the capacitor to the global word line connected to the unaccessible memory cell based on the read control signal. Claim 22 In claim 20, the boosting control circuit provides the first low voltage to the capacitor when the boosting control signal is enabled, and provides the second low voltage to the capacitor when the boosting control signal is disabled, and the first low voltage has a higher voltage level than the second low voltage, in a non-volatile memory device. Claim 23 A non-volatile memory device according to claim 18, wherein the first memory cell is included in a first tile of a memory cell array, and the second memory cell is included in a second tile of the memory cell array adjacent to the first tile. Claim 24 A non-volatile memory device according to claim 23, further comprising a global switching circuit that connects one of the first and second global word lines to the first input terminal and the other to the second input terminal based on a tile selection signal that selects one of the first and second tiles. Claim 25 A non-volatile memory device comprising: a control circuit that applies a read voltage to a target memory cell through a selected global bitline and a selected global wordline; a sense amplifier that generates an output signal by comparing the voltage levels of the selected global wordline and a reference line; a capacitor connected to one end of the reference line; and a boosting circuit that provides one of a first low voltage and a second low voltage to the other end of the capacitor based on a boosting control signal.

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