Display device

Abstract

A display device according to one embodiment includes a substrate, a semiconductor layer including a driving transistor and a fourth transistor located on the substrate, wherein the first electrode of the driving transistor is connected to a driving voltage line to receive a driving voltage, the first electrode of the fourth transistor is connected to a first initialization voltage line to receive a first initialization voltage, the second electrode of the fourth transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the fourth transistor and the first electrode, and no low-placing region is located between the channel of the fourth transistor and the second electrode.

Description

Technology Field

[0001] The present disclosure relates to a display device, and more specifically, to a display device that reduces leakage current. Background Technology

[0002] A display device is a device that displays images, and recently, an organic light emitting diode display, which is a type of light-emitting display device, is attracting attention.

[0003] Light-emitting display devices possess self-emissive properties and, unlike liquid crystal display devices, do not require a separate light source, thereby allowing for reduced thickness and weight. Furthermore, light-emitting display devices exhibit high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0004] Generally, a light-emitting display device includes a substrate, a plurality of thin-film transistors located on the substrate, a plurality of insulating layers disposed between wirings constituting the thin-film transistors, and an organic light-emitting element connected to the thin-film transistors.

[0005] The light-emitting display device includes a plurality of pixels, and each pixel includes a plurality of transistors. The problem to be solved

[0006] The embodiments are intended to provide a display device that reduces leakage current. means of solving the problem

[0007] A display device according to one embodiment includes a substrate, a semiconductor layer including a driving transistor and a fourth transistor located on the substrate, wherein the first electrode of the driving transistor is connected to a driving voltage line to receive a driving voltage, the first electrode of the fourth transistor is connected to a first initialization voltage line to receive a first initialization voltage, the second electrode of the fourth transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the fourth transistor and the first electrode, and no low-placing region is located between the channel of the fourth transistor and the second electrode.

[0008] The semiconductor layer further includes a second transistor, the first electrode of the second transistor is connected to a data line to receive a data voltage, the second electrode of the second transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the second transistor and the first electrode, and a low-placing region may be located between the channel of the second transistor and the second electrode.

[0009] The semiconductor layer further includes a third transistor, the first electrode of the third transistor is connected to the second electrode of the driving transistor, the second electrode of the third transistor is connected to the gate electrode of the driving transistor, a low-placing region may be located between the channel of the third transistor and the first electrode, and a low-placing region may be located between the channel of the third transistor and the second electrode.

[0010] The semiconductor layer further includes a fifth transistor, the first electrode of the fifth transistor is connected to a driving voltage line to receive a driving voltage, the second electrode of the fifth transistor is connected to the gate electrode of the driving transistor, a low-placing region may be located between the channel of the fifth transistor and the first electrode, and a low-placing region may be located between the channel of the fifth transistor and the second electrode.

[0011] The semiconductor layer further includes a sixth transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor can be connected to a light-emitting diode.

[0012] The semiconductor layer further includes a seventh transistor, the first electrode of the seventh transistor is connected to a second initialization voltage line to receive a second initialization voltage, and the second electrode of the seventh transistor can be connected to a light-emitting diode.

[0013] The semiconductor layer further includes a plurality of doping patterns located on the semiconductor layer, and the doping patterns may be positioned in an overlapping direction perpendicular to the low-doping region and the substrate.

[0014] It may further include a hold capacitor located between the second electrode of the fifth transistor and the driving voltage line.

[0015] It may further include a holding capacitor located between the second electrode of the second transistor and the gate electrode of the driving transistor.

[0016] A display device according to another embodiment comprises a substrate, a semiconductor layer positioned on the substrate and including a driving transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, a gate conductive layer positioned on the semiconductor layer, and a plurality of doping patterns positioned on the gate conductive layer, wherein each of the doping patterns is positioned to overlap with the second transistor, the third transistor, the fourth transistor, and the fifth transistor, and one edge of the doping pattern positioned to overlap with the fourth transistor is positioned on the gate conductive layer that overlaps with the fourth transistor.

[0017] The channel of the fourth transistor may overlap with the gate conductive layer, one side region adjacent to the channel may overlap with the doping pattern, and the other side region adjacent to the channel may not overlap with the doping pattern.

[0018] The doping concentration of one side region overlapping with the above doping pattern may be lower than the doping concentration of the other side region that does not overlap with the above doping pattern.

[0019] The above-mentioned fourth transistor includes a channel, a first electrode and a second electrode located on both sides of the channel, and a low-doping region located between the first electrode and the channel, wherein the low-doping region may have a lower doping concentration than the first electrode and the second electrode.

[0020] The above low-doping region may overlap with the above doping pattern.

[0021] The first electrode of the driving transistor may be connected to a driving voltage line to receive a driving voltage, the first electrode of the fourth transistor may be connected to a first initialization voltage line to receive a first initialization voltage, and the second electrode of the fourth transistor may be connected to the gate electrode of the driving transistor.

[0022] The channel of the second transistor overlaps with the gate conductive layer, and both adjacent regions to the channel can overlap with the doping pattern.

[0023] The channel of the third transistor overlaps with the gate conductive layer, and both regions adjacent to the channel may overlap with the doping pattern.

[0024] The channel of the fifth transistor overlaps with the gate conductive layer, and both regions adjacent to the channel can overlap with the doping pattern.

[0025] The second transistor, the third transistor, and the fifth transistor may each include a channel overlapping with the gate conductive layer, a first electrode and a second electrode located on both sides of the channel, and a low-placing region located between the channel and the first electrode and between the channel and the second electrode.

[0026] The above low-doping region may overlap with the above doping pattern. Effects of the invention

[0027] According to the embodiments, a display device that reduces leakage current is provided. Brief explanation of the drawing

[0028] FIG. 1 is an equivalent circuit diagram of a single pixel included in a light-emitting display device according to one embodiment. Figure 2 illustrates the flow of leakage current (Ioff) within the circuit. Figure 3 illustrates a circuit diagram according to the present embodiment. Figure 4 illustrates a configuration in which low-pounding regions are formed on both sides of the fourth transistor. Figures 5 to 7 illustrate the doping process for a cross-sectional view taken along the VV' line of Figure 4. FIG. 8 illustrates a fourth transistor according to the present embodiment. FIGS. 9 to 11 illustrate the doping process for a cross-sectional view taken along the line IX-IX' of FIG. 8. FIGS. 12 to 18 illustrate a stacked structure of pixels according to one embodiment in steps. FIG. 19 is a cross-sectional view taken along the line IXX-IXX' of FIG. 18. Specific details for implementing the invention

[0029] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0030] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0031] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0032] Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity.

[0033] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0034] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0035] Then, a display device according to one embodiment will be described in detail below with reference to the drawings.

[0036] FIG. 1 is an equivalent circuit diagram of a single pixel included in a light-emitting display device according to one embodiment.

[0037] Referring to FIG. 1, a pixel includes a light-emitting diode (LED) and a pixel circuit that drives it, and the pixel circuit is arranged in a matrix form. The pixel circuit includes all other components except the light-emitting diode (LED) in FIG. 1, and the pixel circuit of the pixel according to the embodiment of FIG. 1 includes a driving transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a holding capacitor (Cst), and a hold capacitor (Chold). Additionally, the pixel circuit may be connected to a first scan line to which a first scan signal (GW) is applied, a second scan line to which a second scan signal (GC) is applied, a third scan line to which a third scan signal (GI) is applied, a light-emitting signal line to which a light-emitting control signal (EM) is applied, and a data line to which a data voltage (DATA) is applied. In addition, the pixel can receive a driving voltage (ELVDD), a driving low voltage (ELVSS), a first initialization voltage (Vint), and a second initialization voltage (AVint).

[0038] The structure of a pixel, focusing on each component included in the pixel (transistor, capacitor, and light-emitting diode (LED)), is as follows.

[0039] The driving transistor (T1) includes a gate electrode connected to the first electrode of a holding capacitor (Cst), a first electrode (input side electrode) connected to a driving voltage (ELVDD), and a second electrode (output side electrode) that outputs current according to the voltage of the gate electrode.

[0040] The gate electrode of the driving transistor (T1) is connected at the G node to the second electrode (output side electrode) of the third transistor (T3) and the second electrode (output side electrode) of the fourth transistor (T4). The second electrode of the driving transistor (T1) is connected at the D node to the first electrode (input side electrode) of the third transistor (T3) and the first electrode (input side electrode) of the sixth transistor (T6). The output current of the driving transistor (T1) passes through the sixth transistor (T6) and is transmitted to the light-emitting diode (LED), causing the light-emitting diode (LED) to emit light. The brightness of the light emitted by the light-emitting diode (LED) is determined by the magnitude of the output current of the driving transistor (T1).

[0041] The second transistor (T2) includes a gate electrode connected to a first scan line to which a first scan signal (GW) is applied, a first electrode (input side electrode) connected to a data line to which a data voltage (DATA) is applied, and a second electrode (output side electrode) connected to the second electrode of a holding capacitor (Cst). The second transistor (T2) allows the data voltage (DATA) to enter the pixel and be stored in the holding capacitor (Cst) according to the first scan signal (GW). The second electrode of the second transistor (T2) is also connected to the second electrode (output side electrode) of the fifth transistor (T5) at node A.

[0042] The holding capacitor (Cst) includes a first electrode connected to the gate electrode of the driving transistor (T1), a second electrode of the second transistor (T2), a second electrode of the fifth transistor (T5), and a second electrode connected to the first electrode of the hold capacitor (Chold). The holding capacitor (Cst) receives the data voltage (DATA) output from the second transistor (T2) and maintains it at the voltage of the gate electrode of the driving transistor (T1). In the pixel of this embodiment, the data voltage (DATA) is not directly transmitted to the gate electrode of the driving transistor (T1) but is transmitted through the holding capacitor (Cst). This is a method of indirectly transmitting the data voltage (DATA) to the gate electrode of the driving transistor (T1) by utilizing the fact that if the voltage of the second electrode of the holding capacitor (Cst) suddenly rises, the voltage of the first electrode, which is the other electrode, also rises. According to this method, even if leakage occurs in the second transistor (T2), the voltage of the gate electrode of the driving transistor (T1) is not directly leaked. In addition, in this embodiment, the data voltage (DATA) is transmitted directly to the gate electrode of the driving transistor (T1) by passing through the holding capacitor (Cst) without passing through other electrodes of the driving transistor (T1), so there is an advantage that the voltage stored in the holding capacitor (Cst) is determined without being affected by the difference in the driving voltage (ELVDD) even if there is a difference in the driving voltage (ELVDD) depending on the pixel position.

[0043] The hold capacitor (Chold) includes a first electrode connected to the second electrode of the holding capacitor (Cst) and a second electrode to which a driving voltage (ELVDD) is applied. The first electrode of the hold capacitor (Chold) is additionally connected to the second electrode of the second transistor (T2) and the second electrode of the fifth transistor (T5) at node A.

[0044] According to the hold capacitor (Chold), the voltage of the second electrode of the holding capacitor (Cst) is held without fluctuating even when the surrounding signal fluctuates, so that it can maintain a constant voltage.

[0045] The third transistor (T3) includes a gate electrode connected to a second scan line to which a second scan signal (GC) is applied, a first electrode (input side electrode) connected to the second electrode of the driving transistor (T1), and a second electrode (output side electrode) connected to the first electrode of the holding capacitor (Cst). The third transistor (T3) forms a compensation path that compensates the threshold voltage of the driving transistor (T1), so that the threshold voltage of the driving transistor (T1) can be transmitted to and compensated by the first electrode of the holding capacitor (Cst). As a result, even if the threshold voltage of the driving transistor (T1) included in each pixel is different, the driving transistor (T1) can output a constant output current according to the applied data voltage (DATA). The second electrode of the third transistor (T3) is also connected to the second electrode of the fourth transistor (T4).

[0046] The fourth transistor (T4) includes a gate electrode connected to a third scan line to which a third scan signal (GI) is applied, a first electrode to which a first initialization voltage (Vint) is applied, and a second electrode connected to the first electrode of the holding capacitor (Cst) (or the gate electrode of the driving transistor (T1) or the second electrode of the third transistor (T3). The fourth transistor (T4) serves to initialize the first electrode of the holding capacitor (Cst) and the gate electrode of the driving transistor (T1) to the first initialization voltage (Vint).

[0047] The fifth transistor (T5) includes a gate electrode connected to a second scan line to which a second scan signal (GC) is applied, a first electrode to which a driving voltage (ELVDD) is applied, a second electrode of a holding capacitor (Cst), a first electrode of a hold capacitor (Chold), and a second electrode connected to the second electrode of the second transistor (T2) at the A node.

[0048] The sixth transistor (T6) includes a gate electrode connected to a light-emitting signal line to which a light-emitting control signal (EM) is applied, a first electrode (input side electrode) connected to the second electrode of the driving transistor (T1), and a second electrode (output side electrode) connected to the anode electrode of the light-emitting diode (LED). Here, the first electrode of the sixth transistor (T6) is also connected to the first electrode of the third transistor (T3), and the second electrode of the sixth transistor (T6) is also connected to the second electrode of the seventh transistor (T7). The sixth transistor (T6) serves to transmit or block the output current of the driving transistor (T1) to the light-emitting diode (LED) based on the light-emitting control signal (EM).

[0049] The seventh transistor (T7) includes a gate electrode connected to a fourth scan line to which a fourth scan signal (GB) is applied, a first electrode to which a second initialization voltage (AVint) is applied, and a second electrode connected to the anode electrode of a light-emitting diode (LED). The second electrode of the seventh transistor (T7) is also connected to the second electrode of the sixth transistor (T6). The seventh transistor (T7) serves to initialize the anode electrode of the light-emitting diode (LED) with the second initialization voltage (AVint).

[0050] In the embodiment of FIG. 1, all transistors may be formed using polycrystalline semiconductors and may be doped with doping particles of the same type. However, they are not limited thereto, and the transistors may also include amorphous semiconductors. Depending on the embodiment, it is also possible for some transistors to include polycrystalline semiconductors and some embodiments to include amorphous semiconductors. In the embodiment of FIG. 1, embodiments in which all transistors are doped with P-type are disclosed, but they are not limited thereto.

[0051] A light-emitting diode (LED) includes an anode electrode connected to the second electrode of the sixth transistor (T6) and a cathode electrode connected to the driving low voltage (ELVSS). The light-emitting diode (LED) is connected between the pixel circuit and the driving low voltage (ELVSS) and can emit light with a brightness corresponding to the current supplied from the pixel circuit (specifically, the driving transistor (T1)). The light-emitting diode (LED) may include a light-emitting layer comprising at least one of an organic light-emitting material and an inorganic light-emitting material. Holes and electrons are injected into the light-emitting layer from the anode electrode and the cathode electrode, respectively, and light emission occurs when an exciton formed by the combination of the injected holes and electrons falls from an excited state to a ground state. The light-emitting diode (LED) can emit light of one of the primary colors or white light. Examples of primary colors include the three primary colors of red, green, and blue. Other examples of primary colors include yellow, cyan, and magenta. Depending on the embodiment, additional color filters or color conversion layers may be included to improve color display characteristics.

[0052] In a display device having such a circuit diagram, leakage current (Ioff) may occur due to various causes during circuit operation. Due to this leakage current (Ioff), the display device may exhibit a flicker phenomenon. Leakage current (Ioff) refers to a phenomenon in which current flows even when the transistor is not in an operating state, or flows to a place other than where it should flow.

[0053] FIG. 2 illustrates the flow of leakage current (Ioff) within the circuit. As shown in FIG. 2, the leakage current can flow through the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5). In FIG. 2, the transistor through which the leakage current flows is indicated by a dotted line (A).

[0054] Accordingly, to prevent flicker caused by the flow of leakage current, a low-doping region (LDA) can be formed on the electrodes of the second transistor (T2), third transistor (T3), fourth transistor (T4), and fifth transistor (T5) through which leakage current passes. As will be explained in detail later, the low-doping region (LDA) refers to an area of ​​the semiconductor layer that is less doped than other areas. Compared to areas where doping is sufficient, this low-doping region (LDA) has a lower dopant content, so less current flows and it functions like a resistor. Therefore, by forming a low-doping region (LDA) in the transistor in this way, the flow of leakage current in the circuit can be suppressed and the flicker phenomenon can be reduced.

[0055] The transistor labeled A in Fig. 2 is the transistor through which leakage current flows. Therefore, it is preferable that the low-doping region be formed in the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5).

[0056] However, when a low-doping region is formed in all of the second transistor (T2), third transistor (T3), fourth transistor (T4), and fifth transistor (T5) in this manner, design constraints may arise as a doping pattern for forming the low-doping region is added within the pixel. Consequently, it may be difficult to reduce the pixel size below a certain size due to the doping pattern, and high resolution may not be easily achieved.

[0057] However, in the case of the display device according to the present embodiment, the second transistor (T2), the third transistor (T3), and the fifth transistor (T5) have a low-doping region applied to both sides of the channel region, and the fourth transistor (T4) has a low-doping region applied to one side, thereby reducing the area of ​​the doping pattern. Therefore, compared to a structure where the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5) are all low-doped on both sides, the degree of design freedom can be increased and the pixel size can be reduced. Thus, high resolution is easily implemented.

[0058] FIG. 3 illustrates a circuit diagram according to the present embodiment. In FIG. 3, a transistor with a low-pending region formed on both sides is designated as A, and a transistor with a low-pending region formed on only one side is designated as B. As shown in FIG. 3, in the display device according to the present embodiment, the second transistor (T2), the third transistor (T3), and the fifth transistor (T5) have low-pending regions formed on both sides of the channel region, and the fourth transistor (T4) has a low-pending region formed on one side.

[0059] The low-pounding region of the present invention will be described in detail below.

[0060] To reduce leakage current, it is desirable to form a low-placing region on the drain electrode of each transistor. In the case of the second transistor (T2), the third transistor (T3), and the fifth transistor (T5), the source electrode and the drain electrode change depending on the displayed image or gradation. Therefore, for the second transistor (T2), the third transistor (T3), and the fifth transistor (T5), a low-placing region must be located on both sides of the transistor. However, in the case of the fourth transistor (T4), the source electrode and the drain electrode are the same even if the displayed image or gradation changes. Therefore, leakage current can be effectively reduced even if a low-placing region is formed on only one side. That is, even if a low-placing region is formed only on the drain electrode of the fourth transistor (T4), leakage current can be effectively reduced.

[0061] Table 1 below illustrates the source and drain electrodes of each transistor according to the image being displayed.

[0062] TFT pattern sauce drain Second transistor (T2) DATA A A DATA Third transistor (T3) Low-level G D Go Gye-jo D G 4th transistor (T4) All patterns G Vint Fifth transistor (T5) Low-level A ELVDD Go Gye-jo ELVDD A

[0063] Referring to Table 1 above, for the second transistor (T2), the third transistor (T3), and the fifth transistor (T5), the source electrode and the drain electrode change depending on the displayed image or gradation. That is, for the second transistor, in low gradation, the electrode connected to the data line becomes the source and the electrode connected to node A of FIG. 3 becomes the drain electrode, but in high gradation, the opposite is true. Similarly, for the third transistor, in low gradation, the electrode connected to node G of FIG. 3 becomes the source electrode and the place connected to node D of FIG. 3 becomes the drain electrode, but in high gradation, the opposite is true. For the fifth transistor, in low gradation, the electrode connected to node A of FIG. 3 becomes the source electrode and the place connected to the driving voltage line becomes the drain electrode, but in high gradation, the opposite is true. Thus, in the case of the second transistor (T2), the third transistor (T3), and the fifth transistor (T5), the source electrode and the drain electrode change and the current flow changes depending on the displayed image or gradation, so a low-doping region must be formed on both electrodes of the transistor. However, referring again to Table 1, in the case of the fourth transistor (T4), regardless of the gradation, for all patterns, the G node of FIG. 3 is the source electrode and the initial voltage line supplying the initial voltage (Vint) becomes the drain electrode. Therefore, even if a low-doping region is formed only on the drain electrode where leakage current flows, the flow of leakage current can be effectively blocked.

[0064] FIG. 4 illustrates a configuration in which a low-doping region is formed on both sides of the fourth transistor (T4). FIG. 5 to 7 illustrate the doping process with respect to a cross-sectional view cut along the VV' line of FIG. 4.

[0065] Referring to FIG. 5, a semiconductor layer (ACT) is first placed on a substrate (SUB). Next, referring to FIG. 6, a buffer layer (BUF) and a gate conductive layer (GAT) are formed on the semiconductor layer (ACT). At this time, the region of the semiconductor layer (ACT) that overlaps with the gate conductive layer (GAT) becomes the channel (C4).

[0066] Referring to Fig. 6, the semiconductor layer (ACT) is doped using the gate conductive layer (GAT) as a mask. In this process, the semiconductor layer (ACT) that does not overlap with the gate conductive layer (GAT) is doped first.

[0067] Referring to Figure 7, a gate insulating layer (GIL) and a doping pattern (DP) are formed on a gate conductive layer (GAT). A semiconductor layer (ACT) is doped a second time using the doping pattern (DP) as a mask. At this time, the semiconductor layer (ACT) covered by the doping pattern (DP) is not doped a second time.

[0068] Accordingly, as shown in FIG. 7, the semiconductor layer (ACT) includes a channel (C4), a low-plying region (LDA) located on both sides of the channel (C4), a first electrode (D4) and a second electrode (S4) located on both sides of the low-plying region (LDA).

[0069] In this way, for the display device of FIGS. 4 to 7, a low-doping region (LDA) is located on both sides of the fourth transistor (T4). The low-doping region (LDA) is located overlapping with the doping pattern (DP). Referring to FIGS. 4 and 7, the doping pattern (DP) is located on both sides of the channel (C4). Therefore, space must be secured to form the doping pattern (DP), and this may act as a difficulty in reducing the size of the pixel.

[0070] FIG. 8 illustrates a fourth transistor (T4) according to the present embodiment. Referring to FIG. 8, the fourth transistor (T4) according to the present embodiment has a low-doping region formed on only one side. FIGS. 9 to 11 illustrate the doping process with respect to a cross-sectional view cut along the line IX-IX' of FIG. 8.

[0071] Referring to Fig. 9, a semiconductor layer (ACT) is first placed on a substrate (SUB). Next, referring to Fig. 10, a buffer layer (BUF) and a gate conductive layer (GAT) are formed on the semiconductor layer (ACT). At this time, the region of the semiconductor layer (ACT) that overlaps with the gate conductive layer (GAT) becomes the channel (C4).

[0072] Referring to Fig. 10, the semiconductor layer (ACT) is doped using the gate conductive layer (GAT) as a mask. In this process, the semiconductor layer (ACT) that does not overlap with the gate conductive layer (GAT) is doped first.

[0073] Referring to the following Fig. 11, a gate insulating film (GIL) and a doping pattern (DP) are formed on the gate conductive layer (GAT). At this time, the doping pattern (DP) is formed to cover only one side of the semiconductor layer (ACT) with respect to the channel (C4).

[0074] Next, the semiconductor layer (ACT) is doped a second time using the doping pattern (DP) as a mask. At this time, the semiconductor layer (ACT) covered by the doping pattern (DP) is not doped a second time.

[0075] Accordingly, as shown in FIG. 11, the semiconductor layer (ACT) includes a channel (C4), a low-plying region (LDA) located on one side of the channel (C4), a first electrode (D4), and a second electrode (S4).

[0076] At this time, the low-pinning region (LDA) is located between the channel (C4) and the first electrode (D4), but is not located between the channel (C4) and the second electrode (S4). Referring to FIG. 3, the first electrode (D4) of the fourth transistor (T4) is connected to an initialization voltage line to receive an initialization voltage (Vint).

[0077] Comparing Fig. 4, in which a low-doping region is formed on both sides of the fourth transistor (T4), with Fig. 8, in which a low-doping region is formed on one side of the fourth transistor (T4), the distance (DS1) between the doping pattern (DP) and the semiconductor layer (ACT) in Fig. 4 appears narrow, whereas the distance (DS2) between the doping pattern (DP) and the semiconductor layer (ACT) in Fig. 8 appears longer than the distance (DS1) in Fig. 4. That is, in Fig. 8, as the size of the doping pattern (DP) is reduced, extra space is secured within the pixel, and since the pixel size can be formed smaller by the amount of extra space, it is advantageous for high resolution.

[0078] Then, with reference to FIGS. 12 to 19, a pixel arrangement diagram according to an embodiment of the present invention will be described below. FIGS. 12 to 18 illustrate a stacked structure of pixels according to an embodiment of the present invention in steps. FIG. 19 is a cross-sectional view taken along the line IXX-IXX' of FIG. 18.

[0079] However, the structure described below is merely an example, and the present invention is not limited thereto.

[0080] Referring to FIG. 12 and FIG. 19 simultaneously, a light-blocking layer (BML) is located on a substrate (SUB). A barrier layer (BA) is located on the light-blocking layer (BML), and a semiconductor layer (ACT) is located on the barrier layer (BA). Regions of the semiconductor layer (ACT) can each form a driving transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7). The semiconductor layer (ACT) may include a polycrystalline semiconductor layer.

[0081] The light blocking layer (BML) can be positioned overlapping the driving transistor (T1). The light blocking layer (BML) can block light from being incident on the driving transistor (T1).

[0082] Next, referring to FIGS. 13 and FIGS. 19 simultaneously, a buffer layer (BUF) and a first gate conductive layer (GAT1) are located on the semiconductor layer (ACT). The buffer layer (BUF) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon nitrate (SiO₂) x N y It may include amorphous silicon (Si).

[0083] The first gate conductive layer (GAT1) includes a first scan pattern (151) receiving a first scan signal (GW), a second scan line (152) transmitting a second scan signal (GC) signal, a third scan line (153) transmitting a third scan signal (GI) signal, a fourth scan line (154) transmitting a fourth scan signal (GB), a light emission signal line (161) transmitting a light emission control signal (EM), and a first holding pattern (CP1) overlapping with a driving transistor (T1). The first gate conductive layer (GAT1) may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be a single layer or multilayer structure including the same.

[0084] In the following Fig. 13, the semiconductor layer (ACT) is doped first using the first gate conductive layer (GAT1) as a mask. Thus, the semiconductor layer (ACT) that does not overlap with the first gate conductive layer (GAT1) is doped. The region of the semiconductor layer (ACT) that is not doped and overlaps with the first gate conductive layer (GAT1) becomes the channel. Referring to Fig. 19, the channel (C4) of the fourth transistor (T4) is located overlapping with the first gate conductive layer (GAT1), specifically the third scan line (153).

[0085] Next, referring to FIGS. 14 and FIGS. 19 simultaneously, a first gate insulating film (GIL1) and a plurality of doping patterns (DP) are located on a first gate conductive layer (GAT1). The first gate insulating film (GIL1) is silicon oxide (SiO₂). x ), silicon nitride (SiN x), silicon nitrate (SiO₂) x N y It may include ), and may be a single-layer or multi-layer structure including the same. The doping pattern (DP) may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be a single-layer or multi-layer structure including the same.

[0086] The doping pattern (DP) can be positioned overlapping the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5). As shown in FIG. 14, the doping pattern (DP) overlapping the second transistor (T2), the third transistor (T3), and the fifth transistor (T5) is located on both sides of the channel of each transistor, but in the case of the fourth transistor (T4), the doping pattern (DP) is located only on one side of the channel. That is, as previously explained, since the source electrode / drain electrode of the fourth transistor (T4) is constant regardless of the gradation, the doping pattern (DP) is located only on the side where the drain electrode is located.

[0087] The semiconductor layer (ACT) is secondarily doped using the doping pattern (DP) as a mask. In this process, the semiconductor layer (ACT) that is not covered by the doping pattern (DP) is secondarily doped. The semiconductor layer (ACT) that overlaps with the doping pattern (DP) undergoes only primary doping in the preceding step, and therefore has a lower doping concentration than the semiconductor layer (ACT) that undergoes secondary doping. Thus, the region of the semiconductor layer (ACT) that is first doped forms a low-doping region, and the flow of leakage current can be suppressed by this low-doping region.

[0088] Referring to FIG. 14, the low-doping region of the fourth transistor (T4) is located only on one side of the channel (C4) and not on the other side. Referring to FIG. 19, the low-doping region (LDA) is located between the channel (C4) of the fourth transistor (T4) and the first electrode (D4), and the low-doping region is not located between the channel (C4) and the second electrode (S4). The low-doping region (LDA) overlaps with the doping pattern (DP).

[0089] As shown in FIG. 14, the size of the doping pattern (DP) overlapping with the fourth transistor (T4) is also smaller than the size of the doping pattern (DP) overlapping with other transistors, and compared to an embodiment where the low-doping region is located on both sides, the design freedom is increased and the pixel size can be formed smaller.

[0090] Next, referring to FIGS. 15 and FIGS. 19 simultaneously, a second gate insulating film (GIL2) and a second gate conductive layer (GAT2) are located on the doping pattern (DP). The second gate insulating film (GIL2) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon nitrate (SiO₂) x N y It may include ), and may be a single-layer or multi-layer structure including the same. The second gate conductive layer (GAT2) may include molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc., and may be a single-layer or multi-layer structure including the same.

[0091] The second gate conductive layer (GAT2) may include a second holding pattern (CP2) that overlaps with the first holding pattern (CP1). The second holding pattern (CP2) may form a holding capacitor (Cst) together with the first holding pattern (CP1).

[0092] Next, referring to FIGS. 16 and FIGS. 19 simultaneously, a third gate insulating film (GIL3) and a third gate conductive layer (GAT3) are located on the second gate conductive layer (GAT2). The third gate insulating film (GIL3) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon nitrate (SiO₂) x N y It may include ), and may be a single-layer or multi-layer structure including the same. The third gate conductive layer (GAT3) may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be a single-layer or multi-layer structure including the same.

[0093] The third gate conductive layer (GAT3) includes a second initialization voltage line (175) that transmits a second initialization voltage (AVint) and a first hold pattern (HP1) that constitutes one electrode of a hold capacitor. The first hold pattern (HP1) may include a first hold opening (HO1) located inside the first hold pattern (HP1).

[0094] The first hold pattern (HP1) can form a hold capacitor (Chold) together with the second holding pattern (CP2).

[0095] Referring simultaneously to FIG. 17 and FIG. 19, a first interlayer insulating film (ILD1) and a first data conductive layer (DAT1) are positioned on a third gate conductive layer (GAT3). The first interlayer insulating film (ILD1) may include silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (SiOxNy), and may be a single layer or multilayer structure including the same. The first data conductive layer (DAT1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multilayer structure including the same.

[0096] The first data conductive layer (DAT1) includes a first initialization voltage line (173) that transmits a first initialization voltage (Vint), a first scan signal line (172) that transmits a first scan signal (GW), a first connection pattern (CN1), a second connection pattern (CN2), a third connection pattern (CN3), a fourth connection pattern (CN4), a fifth connection pattern (CN5), and a sixth connection pattern (CN6).

[0097] The first initialization voltage line (173) is connected to the semiconductor layer (ACT) through the first contact hole (H1) to transmit the initialization voltage (Vint) to the fourth transistor (T4).

[0098] The first connection pattern (CN1) is connected to one electrode of the fifth transistor (T5) through the second contact hole (H2). Additionally, the first connection pattern (CN1) is connected to the first hold pattern (HP1) of the third gate conductive layer (GAT3) through the third contact hole (H3).

[0099] The second connection pattern (CN2) is connected to the semiconductor layer (ACT) through the fourth contact hole (H4). Additionally, the second connection pattern (CN2) is connected to the second holding pattern (CP2) through the fifth contact hole (H5). That is, the second connection pattern (CN2) connects the third transistor (T3) and the holding capacitor (Cst) to each other.

[0100] The third connection pattern (CN3) is connected to the semiconductor layer (ACT) of the fifth transistor (T5) through the sixth contact hole (H6) and to the second holding pattern (CP2) through the seventh contact hole (H7). Additionally, it is connected to the semiconductor layer (ACT) of the second transistor (T2) through the eighth contact hole (H8). That is, the third connection pattern (CN3) connects the fifth transistor (T5), the second transistor (T2), and the holding capacitor (Cst).

[0101] Next, the fourth connection pattern (CN4) is connected to the semiconductor layer of the second transistor (T2) through the ninth contact hole (H9).

[0102] Additionally, the fifth connection pattern (CN5) is connected to the semiconductor layer of the seventh transistor (T7) through the tenth contact hole (H10) and to the second initialization voltage line (175) through the eleventh contact hole (H11). Thus, the fifth connection pattern (CN5) transmits the second initialization voltage of the second initialization voltage line (175) to the seventh transistor (T7).

[0103] The 6th connection pattern (CN6) is connected to the semiconductor layer of the 6th transistor (T6) through the 12th contact hole (H12).

[0104] The first scan signal line (172) is connected to the first scan pattern (151) of the first gate conductive layer through the 13th contact hole (H13). Thus, the first scan signal (GW) is transmitted to the gate electrode of the second transistor (T2).

[0105] Referring simultaneously to FIGS. 18 and FIGS. 19, a second interlayer insulating film (ILD2) and a second data conductive layer (DAT2) are positioned on a first data conductive layer (DAT1). The second interlayer insulating film (ILD2) may include silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (SiOxNy), and may be a single layer or multilayer structure including the same. The second data conductive layer (DAT2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multilayer structure including the same.

[0106] The second data conductive layer (DAT2) includes a data line (171), a driving voltage line (174), and a data connection pattern (177).

[0107] The data line (171) is connected to the fourth connection pattern (CN4) through the second contact hole (L1). Since the fourth connection pattern (CN4) is connected to the second transistor (T2), the data voltage (DATA) of the data line is transmitted to the second transistor (T2).

[0108] The driving voltage line (174) is connected to the first connection pattern (CN1) through the second contact hole (L2). The first connection pattern (CN1) is connected to one electrode of the fifth transistor (T5) through the second contact hole (H2), so that the driving voltage (ELVDD) is transmitted to the fifth transistor.

[0109] Additionally, the first connection pattern (CN1) is connected to the first hold pattern (HP1) of the third gate conductive layer (GAT3) through the third contact hole (H3), so that the driving voltage (ELVDD) is transmitted to one electrode of the hold capacitor.

[0110] The data connection pattern (177) is connected to the sixth connection pattern (CN6) through the 23rd contact hole (L3). The sixth connection pattern (CN6) is connected to the semiconductor layer of the sixth transistor (T6) through the 12th contact hole (H12).

[0111] Although not shown, an insulating film may be positioned on the second data conductive layer (DAT2). The insulating film may include organic insulating materials such as general-purpose polymers like polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide, and siloxane polymers.

[0112] The insulating film may include a pixel contact hole (PCT). A light-emitting diode may be positioned on the insulating film. A data connection pattern (177) may be connected to a light-emitting diode (not shown) through the pixel contact hole (PCT). The data connection pattern (177) connects the sixth transistor (T6) to the light-emitting diode, so that the sixth transistor (T6) can transmit the output current of the driving transistor (T1) to the light-emitting diode (LED) based on the light-emitting control signal (EM).

[0114] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0116] T1: Driving transistor T4: 4th transistor DP: Doping pattern ACT: Semiconductor layer GAT1: Gate 1 Challenge Floor GAT2: Gate 2 Challenge Floor GAT3: 3rd Gate Conductive Layer DAT1: 1st Data Conductive Layer DAT2: Second data conduction layer LDA: Low ping

Claims

Claim 1 A display device comprising: a substrate; a semiconductor layer including a driving transistor and a fourth transistor located on the substrate, wherein the first electrode of the driving transistor is connected to a driving voltage line to receive a driving voltage, the first electrode of the fourth transistor is connected to a first initialization voltage line to receive a first initialization voltage, the second electrode of the fourth transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the fourth transistor and the first electrode, and no low-placing region is located between the channel of the fourth transistor and the second electrode. Claim 2 A display device according to claim 1, wherein the semiconductor layer further comprises a second transistor, the first electrode of the second transistor is connected to a data line to receive a data voltage, the second electrode of the second transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the second transistor and the first electrode, and a low-placing region is located between the channel of the second transistor and the second electrode. Claim 3 A display device according to claim 1, wherein the semiconductor layer further comprises a third transistor, the first electrode of the third transistor is connected to the second electrode of the driving transistor, the second electrode of the third transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the third transistor and the first electrode, and a low-placing region is located between the channel of the third transistor and the second electrode. Claim 4 A display device according to claim 1, wherein the semiconductor layer further comprises a fifth transistor, the first electrode of the fifth transistor is connected to a driving voltage line to receive a driving voltage, the second electrode of the fifth transistor is connected to the gate electrode of the driving transistor, a low-placing region is located between the channel of the fifth transistor and the first electrode, and a low-placing region is located between the channel of the fifth transistor and the second electrode. Claim 5 A display device according to claim 1, wherein the semiconductor layer further comprises a sixth transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to a light-emitting diode. Claim 6 In claim 1, the semiconductor layer further comprises a seventh transistor, the first electrode of the seventh transistor is connected to a second initialization voltage line to receive a second initialization voltage, and the second electrode of the seventh transistor is connected to a light-emitting diode to form a display device. Claim 7 A display device according to claim 1, further comprising a plurality of doping patterns located on the semiconductor layer, wherein the doping patterns are positioned in an overlapping direction perpendicular to the low-doping region and the substrate. Claim 8 A display device according to claim 4, further comprising a hold capacitor located between the second electrode of the fifth transistor and the driving voltage line. Claim 9 A display device according to claim 2, further comprising a holding capacitor located between the second electrode of the second transistor and the gate electrode of the driving transistor. Claim 10 A substrate; a semiconductor layer located on the substrate and comprising a driving transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and a gate conductive layer located on the semiconductor layer;A plurality of doping patterns are positioned on the gate conductive layer, wherein the first electrode of the driving transistor is connected to a driving voltage line to receive a driving voltage, the first electrode of the second transistor is connected to a data line to receive a data voltage, the second electrode of the second transistor is connected to the gate electrode of the driving transistor, the first electrode of the third transistor is connected to the second electrode of the driving transistor, and the second electrode of the third transistor is connected to the gate electrode of the driving transistor, the first electrode of the fourth transistor is connected to a first initialization voltage line to receive a first initialization voltage, and the second electrode of the fourth transistor is connected to the gate electrode of the driving transistor, the first electrode of the fifth transistor is connected to a driving voltage line, and the second electrode of the fifth transistor is connected to the gate electrode of the driving transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to a light-emitting diode, and the first electrode of the seventh transistor is connected to a second initialization voltage line to receive a second initialization voltage A display device having received, wherein the second electrode of the seventh transistor is connected to a light-emitting diode, and the doping pattern is positioned overlapping the second transistor, the third transistor, the fourth transistor, and the fifth transistor, respectively, and one edge of the doping pattern positioned overlapping the fourth transistor is positioned on a gate conductive layer overlapping the fourth transistor, and the fourth transistor includes a channel positioned between the first electrode and the second electrode and a low-doping region positioned between the first electrode and the channel, and the low-doping region has a lower doping concentration than the first electrode and the second electrode of the fourth transistor. Claim 11 A display device according to claim 10, wherein the channel of the fourth transistor overlaps with the gate conductive layer, one side region adjacent to the channel overlaps with the doping pattern, and the other side region adjacent to the channel does not overlap with the doping pattern. Claim 12 In claim 11, a display device in which the doping concentration of one side region overlapping with the doping pattern is lower than the doping concentration of the other side region not overlapping with the doping pattern. Claim 13 delete Claim 14 In claim 10, the above-mentioned low-doping region is a display device that overlaps with the above-mentioned doping pattern. Claim 15 delete Claim 16 A display device according to claim 10, wherein the channel of the second transistor overlaps with the gate conductive layer, and both regions adjacent to the channel overlap with the doping pattern. Claim 17 A display device in which, in claim 10, the channel of the third transistor overlaps with the gate conductive layer, and both regions adjacent to the channel overlap with the doping pattern. Claim 18 A display device in which, in claim 10, the channel of the fifth transistor overlaps with the gate conductive layer, and both regions adjacent to the channel overlap with the doping pattern. Claim 19 In claim 10, the display device comprises a second transistor, a third transistor, and a fifth transistor each having a channel that overlaps with the gate conductive layer; a first electrode and a second electrode located on both sides of the channel; and a low-placing region located between the channel and the first electrode and between the channel and the second electrode. Claim 20 In paragraph 19, the above-mentioned low-doping region is a display device that overlaps with the above-mentioned doping pattern.

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