Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device comprises: a substrate; an information storage structure disposed on the substrate; an insulating structure disposed on the substrate and spaced apart from the information storage structure; conductive lines disposed between the information storage structure and the insulating structure, spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate and stacked; active layers spaced apart from each other in the vertical direction between the information storage structure and the insulating structure and intersecting the conductive lines; and a conductive pattern disposed between the insulating structure and the active layers and electrically connected to the active layers. The insulating structure comprises first insulating patterns spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate and a second insulating pattern disposed between the first insulating patterns, and the conductive pattern disposed between the second insulating pattern and the active layers, wherein the material of the second insulating pattern is different from the material of the first insulating patterns.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] Research is underway to reduce the size of the components constituting semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably form reduced-size components.

[0004] (Patent Document 1) US 20200279601 A1 The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device capable of improving electrical characteristics. means of solving the problem

[0007] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a substrate including a first region and a second region adjacent to the first region; a first conductive line group including first conductive lines stacked and spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the first region of the substrate; a second conductive line group including second conductive lines stacked and spaced apart from each other in the vertical direction on the first region of the substrate; first active groups disposed on the first region of the substrate and arranged and spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate; second active groups disposed on the first region of the substrate and arranged and spaced apart from each other in the first horizontal direction, and spaced apart from the first active groups in a second horizontal direction perpendicular to the first horizontal direction; and an insulating structure disposed between the first conductive line group and the second conductive line group. and includes first conductive patterns disposed between the insulating structure and the first active groups, and second conductive patterns disposed between the insulating structure and the second active groups. Each of the first active groups is spaced apart from each other in the vertical direction and stacked, and includes first active layers that intersect each of the first conductive lines, and each of the second active groups is spaced apart from each other in the vertical direction and stacked, and includes second active layers that intersect each of the second conductive lines, and the insulating structure includes first insulating patterns and second insulating patterns that are alternately and repeatedly arranged in the first horizontal direction on the first region of the substrate, and the material of the first insulating patterns is different from the material of the second insulating patterns.

[0009] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a substrate; an information storage structure disposed on the substrate; an insulating structure disposed on the substrate and spaced apart from the information storage structure; conductive lines disposed between the information storage structure and the insulating structure, spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate and stacked; active layers spaced apart from each other in the vertical direction between the information storage structure and the insulating structure and intersecting the conductive lines; and a conductive pattern disposed between the insulating structure and the active layers and electrically connected to the active layers. The insulating structure comprises first insulating patterns spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate and a second insulating pattern disposed between the first insulating patterns, wherein the conductive pattern is disposed between the second insulating pattern and the active layers, and the material of the second insulating pattern is different from the material of the first insulating patterns.

[0011] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a substrate; first insulating patterns disposed on the substrate and spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate; conductive patterns disposed on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; and a second insulating pattern disposed between the first insulating patterns and between the conductive patterns. The material of the second insulating pattern is different from the material of the first insulating patterns. Effects of the invention

[0013] According to embodiments of the technical concept of the present invention, an insulating layer can be provided to form an opening with a high aspect ratio that can minimize the bowing phenomenon. A semiconductor device including insulating patterns and conductive patterns formed using such an insulating layer can be provided.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIGS. 1a to 5 are schematic drawings illustrating exemplary examples of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a partially enlarged plan view schematically showing an example of a modified semiconductor device according to one embodiment of the present invention. FIG. 7 is a partially enlarged plan view schematically showing an example of a modified semiconductor device according to one embodiment of the present invention. FIG. 8 is a cross-sectional view schematically showing an example of a modified semiconductor device according to one embodiment of the present invention. FIGS. 9 and FIGS. 10 are schematic diagrams illustrating modified examples of a semiconductor device according to one embodiment of the present invention. FIGS. 11 to 35 are schematic drawings illustrating exemplary examples of a method for forming a semiconductor device according to one embodiment of the present invention. FIG. 36 is a graph showing the bowing characteristics of a semiconductor device according to one embodiment of the present invention. Specific details for implementing the invention

[0017] In the following, terms such as "upper," "middle," and "lower" may be replaced with other terms, such as "first," "second," and "third," to describe the components of the specification. While terms such as "first," "second," and "third" may be used to describe various components, they are not limited by these terms, and "first component" may be named "second component."

[0018] In addition, at least some of the different "components" using the same terminology may be described by distinguishing them by reference numerals rather than by terms such as "first," "second," etc. in the detailed description, and may be referred to by distinguishing them by terms such as "first," "second," etc., as in the claims, such as the first component and the second component. For example, in the detailed description, "insulating layer (00)" may mean an insulating layer referred to by reference numeral 00, and "insulating layer (01)" may mean an insulating layer referred to by reference numeral 01. Furthermore, the "insulating layer (00) and insulating layer (01)" described in the detailed description may be referred to and named as "first insulating layer and second insulating layer" in the claims.

[0019] First, with reference to FIGS. 1a to 5, an exemplary example of a semiconductor device according to an embodiment of the present invention will be described. FIG. 1a is a top view schematically showing an exemplary example of a semiconductor device according to an embodiment of the present invention, FIG. 1b is a partially enlarged top view showing an enlarged area marked 'A' in FIG. 1a, FIG. 2a is a cross-sectional view schematically showing areas taken along the lines I-I' and II-II' in FIG. 1a, FIG. 2b is a partially enlarged cross-sectional view showing an area marked 'B' in FIG. 2a, FIG. 3 is a cross-sectional view schematically showing areas taken along the lines III-III' and IV-IV' in FIG. 1a, FIG. 4 is a cross-sectional view schematically showing areas taken along the lines V-V' and VI-VI' in FIG. 1a, and FIG. 5 is a cross-sectional view schematically showing areas taken along the lines VII-VII' and VIII-VIII' in FIG. 1a.

[0020] Referring to FIGS. 1a through 5, a semiconductor device (1) according to one embodiment may include a substrate (3), first insulating patterns (78) disposed on the substrate (3) and spaced apart from each other in a first horizontal direction (Y) parallel to the upper surface of the substrate (3), conductive patterns (72) spaced apart from each other in a second horizontal direction (Y) perpendicular to the first horizontal direction (Y) on the substrate (3), and a second insulating pattern (74a) disposed between the first insulating patterns (78) and between the conductive patterns (72).

[0021] The semiconductor device (1) may further include dummy conductive patterns (72d') covering the side of the second insulating pattern (74a) at a level lower than the conductive patterns (72). The conductive patterns (72) and the dummy conductive patterns (72d') may be spaced apart from each other.

[0022] The second insulating pattern (74a) may include a material different from the material of the first insulating patterns (78). For example, the first insulating patterns (78) may include silicon oxide, and the second insulating pattern (74a) may include a material in which "element A" is doped into silicon oxide.

[0023] In one example, the first insulating patterns (78) may not contain the "A element." In another example, the first insulating patterns (78) may contain the "A element" doped to a lower concentration than the doping concentration of the "A element" in the second insulating pattern (74a).

[0024] The "A element" may include at least one of the elements of Group 13 or Group 15 of the periodic table. For example, the "A element" may include at least one of nitrogen (N), phosphorus (P), and boron (B). For example, the second insulating pattern (74a) may be silicon oxide doped with nitrogen (N), silicon oxide doped with phosphorus (P), or silicon oxide doped with boron (B).

[0025] In the second insulation pattern (74a) above, the content of the "A element" may be about 30% or less.

[0026] In one example, the first insulating patterns (78) may be silicon oxide that does not contain the "A element." In another example, the first insulating patterns (78) may be silicon oxide having a "A element" content less than the "A element" content of the second insulating pattern (74a).

[0027] The width of the second insulation pattern (74a) in the first horizontal direction (Y) may be smaller than the width of each of the second electrodes (103) in the first horizontal direction (Y).

[0028] In an embodiment, a plurality of second insulation patterns (74a) may be arranged, and the plurality of second insulation patterns (74a) may be alternately and repeatedly arranged in the first horizontal direction (Y) with the first insulation patterns (78).

[0029] The above second insulation patterns (74a) and the above first insulation patterns (78) can form an insulating structure (80).

[0030] In the top view, the insulating structure (80) may be in the shape of a line extending in the first horizontal direction (Y).

[0031] Each of the above second insulation patterns (74a) may have a height greater than the maximum width.

[0032] In the embodiments, the height of a component can be defined as the distance between the lower surface and the upper surface of the component.

[0033] In one example, in each of the second insulation patterns (74a), the height may be approximately 10 times or more the width. In another example, in each of the second insulation patterns (74a), the height may be approximately 50 times or more the width. In another example, in each of the second insulation patterns (74a), the height may be approximately 100 times or more the width.

[0034] In the first horizontal direction (Y), each of the first insulating patterns (78) may have concave sides facing each other, and each of the second insulating patterns (74a) may have convex sides in contact with the concave sides of the first insulating patterns (78).

[0035] The conductive patterns (72) can come into contact with the sides of the first insulating pattern (78) located in the second horizontal direction (Y).

[0036] Each of the above conductive patterns (72) may include at least two different conductive layers, for example, a first conductive layer (72a) and a second conductive layer (72b).

[0037] The substrate (3) may be a semiconductor substrate. For example, the substrate (3) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (5) may be provided as a bulk semiconductor wafer, a semiconductor substrate including an epitaxial layer, a Silicon On Insulator (SOI) substrate, or a Semiconductor On Insulator (SeOI) substrate, etc.

[0038] The above substrate (3) may include a first region (MCA) and a second region (GIA) adjacent to the first region (MCA).

[0039] The first region (MCA) may be referred to as a memory cell array region, and the second region (GIA) may be referred to as a gate connection region or a step region.

[0040] The semiconductor device (1) may further include a first conductive line group (70_1) comprising first conductive lines (70) that are spaced apart from each other in a vertical direction (Z) perpendicular to the upper surface of the substrate (3) on the first region (MCA) of the substrate (3), and a second conductive line group (70_2) comprising second conductive lines (70) that are spaced apart from each other in the vertical direction (Z) on the first region (MCA) of the substrate (3).

[0041] The semiconductor device (1) may further include first active groups (ACT_1) and second active groups (ACT_2).

[0042] The first active groups (ACT_1) are disposed on the first region (MCA) of the substrate (3) and can be arranged spaced apart from each other in the first horizontal direction (Y).

[0043] The second active groups (ACT_2) are disposed on the first region (MCA) of the substrate (3) and can be arranged spaced apart from each other in the first horizontal direction (Y), and can be spaced apart from the first active groups (ACT_1) in the second horizontal direction (Y) perpendicular to the first horizontal direction (Y).

[0044] The insulating structure (80) may be positioned between the first conductive line group (70_1) and the second conductive line group (70_2), and between the first active group (ACT_1) and the second active group (ACT_2).

[0045] The semiconductor device (1) may further include conductive patterns (72). The conductive patterns (72) may include first conductive patterns (72_1) disposed between the insulating structure (80) and the first active groups (ACT_1), and second conductive patterns (72_2) disposed between the insulating structure (80) and the second active groups (ACT_2).

[0046] Each of the above first active groups (ACT_1) may include first active layers (ACT) that are spaced apart from each other in the vertical direction (Z) and intersect with the first conductive lines (70) of the first conductive line group (70_1).

[0047] Each of the above-mentioned second active groups (ACT_2) may include second active layers (ACT) that are spaced apart from each other in the vertical direction (Z) and intersect with the first conductive lines (70) of the second conductive line group (70_2).

[0048] Each of the above active layers (ACT) may be in the shape of a line or bar extending in the second horizontal direction (Y).

[0049] Each of the active layers (ACT) of the first and second active groups (ACT_1, ACT_2) may include a first source / drain region (SD1) and a second source / drain region (SD2) spaced apart from each other, and a channel region (CH) between the first source / drain region (SD1) and the second source / drain region (SD2).

[0050] The first source / drain regions (SD1) of the active layers (ACT) of the first active group (ACT_1) can be electrically connected to the first conductive patterns (72_1), and the first source / drain regions (SD1) of the active layers (ACT) of the second active group (ACT_2) can be electrically connected to the second conductive patterns (72_2).

[0051] The conductive lines (70) of the first and second conductive line groups (70_1, 70_2) may overlap perpendicularly with the channel regions (CH) of the active layers (ACT) and extend in the first horizontal direction (Y). The conductive lines (70) may cover the upper and lower surfaces of the channel regions (CH) of the active layers (ACT).

[0052] The conductive lines (70) may include a pair of conductive lines (70a) covering the upper and lower surfaces of a first active layer of any one of the active layers (ACT).

[0053] The semiconductor device (1) may further include gate dielectric layers (68) interposed between at least the active layers (ACT) and the conductive lines (70).

[0054] The conductive lines (70) may be gate electrodes. The active layers (ACT), the conductive lines (70), and the gate dielectric layers (68), including the first and second source / drain regions (SD1, SD2) and the channel region (CH), may form transistors (TR). Thus, the transistors (TR) may be arranged three-dimensionally on the first region (MCA) of the substrate (3).

[0055] At least some of the conductive lines (70) may be word lines, and at least some of the conductive patterns (72) may be bit lines. For example, the highest conductive line and the lowest conductive line among the conductive lines (70) may be dummy conductive lines, and the middle conductive lines among the conductive lines (70) may be word lines.

[0056] The semiconductor device (1) may further include information storage structures (CAP) disposed on the substrate (3). The insulating structure (80) may be spaced apart from the information storage structures (CAP).

[0057] The insulating structure (80), the first and second active groups (ACT_1, ACT_2), and the first and second conductive line groups (70_1, 70_2) may be spaced apart from each other and placed between a pair of adjacent information storage structures (CAP).

[0058] The first active groups (ACT_1) and the first conductive line group (70_1) may be disposed between one of the pair of information storage structures (CAP) and the insulating structure (80), and the second active groups (ACT_2) and the second conductive line group (70_2) may be disposed between the other information storage structure (CAP) and the insulating structure (80).

[0059] Each of the above information storage structures (CAP) may include a first electrode (109), second electrodes (103) disposed between the first electrode (109) and the active layers (ACT), and a dielectric layer (107) disposed between at least the second electrodes (103) and the first electrode (109).

[0060] The first electrode (109) may include a first material layer (109a) in contact with the dielectric layer (107) and a second material layer (109b) on the first material layer (109a). The first material layer (109a) and the second material layer (109b) may be different conductive materials.

[0061] The information storage structures (CAP) above may be capacitors capable of storing information in a DRAM. For example, the first electrode (109) may be a plate electrode, the second electrodes (103) may be storage node electrodes, and the dielectric layer (107) may be a capacitor dielectric layer.

[0062] The second source / drain regions (SD2) of the active layers (ACT) of the first and second active groups (ACT_1, ACT_2) can be electrically connected to the second electrodes (103) of the information storage structures (CAP).

[0063] The conductive patterns (72) may have a wider width than the second electrodes (103).

[0064] In the second horizontal direction (Y), at least one of the conductive lines (70) may have a first width (W1) in a first portion that overlaps perpendicularly with the active layers (ACT), and may have a second width (W2) smaller than the first width (W1) in a second portion located between the first electrode (109) of the information storage structures (CAP) and the first insulating patterns (78).

[0065] The semiconductor device (1) may further include gate contact lines (88) and gate contact plugs (92). The gate contact lines (88) may include first gate contact lines (88a) disposed on the second region (GIA) of the substrate (3) and electrically connected to the first conductive line group (70_1), and second gate contact lines (88b) disposed on the second region (GIA) of the substrate (3) and electrically connected to the second conductive line group (70_2).

[0066] The conductive lines (70) may include a pair of conductive lines (70a) covering the upper and lower surfaces of any one of the active layers (ACT), and any one of the gate contact lines (88) may be electrically connected to the pair of conductive lines (70a).

[0067] One of the transistors (TR) may include an active layer (ACT) comprising the first and second source / drain regions (SD1, SD2) and the channel region (CH), a pair of conductive lines (70a) covering the upper and lower surfaces of the active layer (ACT), and a gate dielectric layer (68) between the pair of conductive lines (70a) and the active layer (ACT). In the transistor (TR), the pair of conductive lines (70a) may be a gate electrode.

[0068] Each of the above gate contact lines (88) can be extended in the first horizontal direction (Y).

[0069] The ends of the gate contact lines (88) can be arranged in a stepped shape.

[0070] In the second horizontal direction (Y) above, the width of each of the gate contact lines (88) may be greater than the width of each of the conductive lines (70).

[0071] The gate contact plugs (92) can be electrically connected to the gate contact lines (88) on the gate contact lines (88).

[0072] Each of the above gate contact plugs (92) may include a plug pattern (92b) and a barrier layer (92a) surrounding the side and bottom surfaces of the plug pattern (92b).

[0073] The semiconductor device (1) may further include an insulating layer (50a) disposed between the first gate contact lines (88a) and the second gate contact lines (88b) on the second region (GIA) of the substrate (3). The insulating layer (50a) may include the same material as the material of the second insulating patterns (74a).

[0074] The semiconductor device (1) may further include the information storage structures (CAP) and insulating layers (90) adjacent to the first horizontal direction (Y). The gate contact lines (88) and the insulating layer (50a) may be disposed between the insulating layers (90).

[0075] The material of the insulating layer (90) may be substantially the same as the material of the first insulating patterns (78).

[0076] The semiconductor device (1) may further include first semiconductor layers (8) and second semiconductor layers (10) disposed on the substrate (3).

[0077] The first semiconductor layers (8) may include a first semiconductor layer (8L1) in contact with the substrate (3) and a first semiconductor layer (8L2) on the first semiconductor layer (8L1).

[0078] The second semiconductor layers (10) may include a second semiconductor layer (10L1) on the first semiconductor layer (8L1) and a second semiconductor layer (10L2) on the first semiconductor layer (8L1).

[0079] The semiconductor material of the first semiconductor layers (8) may be different from the semiconductor material of the second semiconductor layers (10). For example, the first semiconductor layers (8) may be SiGe, and the second semiconductor layers (10) may be Si. The substrate (3) may be Si.

[0080] The substrate (3) and the first and second semiconductor layers (8, 10) may have a single crystal structure.

[0081] The insulating structure (80) can penetrate at least the first and second semiconductor layers (8L2, 10L2, 10L1).

[0082] The information storage structure (CAP) may penetrate at least the first and second semiconductor layers (8L2, 10L2, 10L1). The information storage structure (CAP) may penetrate the first and second semiconductor layers (8L1, 8L2, 10L2, 10L1) and come into contact with the substrate (3). For example, in the information storage structure (CAP), the first electrode (109) may be spaced apart from the substrate (3), and the dielectric layer (107) may extend between the first electrode (109) and the substrate (3) and include a portion interposed between the first electrode (109) and the substrate (3).

[0083] The semiconductor device (1) may further include insulating layers (62) between the conductive lines (70) and the conductive patterns (72), and insulating layers (99) between the conductive lines (70) and the information storage structures (CAP). The insulating layers (62, 99) may be formed of substantially the same material. The insulating layers (62, 99) may include silicon nitride. The insulating layers (62, 99) may include an insulating layer (62) covering the upper and lower surfaces of the first source / drain region (SD1) of each of the active layers (ACT), and an insulating layer (99) covering the upper and lower surfaces of the second source / drain region (SD2). The gate dielectric layers (68) may include a portion that surrounds structures including the conductive lines (70) and the insulating layers (62) and extends between the conductive lines (70) and the insulating layers (99). The semiconductor device (1) may further include insulating layers (98) that cover the lower and upper surfaces of each of the insulating layers (99) and extend to the side of each of the insulating layers (99) in the first horizontal direction (Y).

[0084] The semiconductor device (1) may further include insulating layers (34). Between a pair of insulating layers (34) adjacent to each other in the vertical direction (Z), one active layer (ACT), conductive lines (70) covering the lower and upper surfaces of the one active layer (ACT), a gate dielectric layer (68) between the conductive lines (70) and the active layer (ACT), and insulating layers (62, 99) covering the lower and upper surfaces of a portion of the one active layer (ACT) may be disposed.

[0085] Each of the above insulating layers (34) may further include an extension portion (34') extending into the information storage structure (CAP). One of the extension portions (34') may be positioned between a pair of the second electrodes (103). The vertical thickness of the extension portion (24') may be smaller than the vertical thickness of each of the insulating layers (34).

[0086] The semiconductor device (1) may further include insulating layers (50c) filling between the gate contact lines (88) on the second region (GIA) of the substrate (3), and insulating layers (50b) disposed between the second semiconductor layers (10L1, 10L2) below the insulating layers (50c). The insulating layers (50a, 50b, 50c) may form an insulating layer (50) formed integrally.

[0087] The semiconductor device (1) may further include an insulating layer (42a') disposed between the insulating layer (90) and the substrate (3), and an insulating layer (40) covering the side and bottom surfaces of the insulating layer (42a').

[0088] The semiconductor device (1) may further include an insulating structure (36) disposed between the information storage structures (CAP) and the insulating structure (80).

[0089] The insulating structure (36) may include an insulating layer (36a) adjacent to the insulating structure (78), an insulating layer (36b) adjacent to the information storage structure (CAP), an insulating layer (36c') disposed between the insulating layers (36a, 36b) and between the conductive lines (70), and an insulating layer (36d) disposed on the conductive lines (70). The second insulating pattern (74a) may further include an extension (74') extending onto the insulating layer (36d).

[0090] In the top view, the insulating layer (36c') may be positioned between portions of the conductive lines (70) positioned between the first active groups (ACT_1) and between portions of the conductive lines (70) positioned between the second active groups (ACT_2).

[0091] The semiconductor device (1) may further include an insulating layer (34") disposed on a portion of the second semiconductor layer (10L1) at a location spaced apart from the insulating structure (80) and at least partially overlapping with the second source / drain region (SD2) below the conductive lines (70) and the active layers (ACT), and an insulating layer (32') covering the upper and lower surfaces of the insulating layer (34") and covering one side of the insulating layer (34") located opposite the insulating structure (80).

[0092] The semiconductor device (1) may further include impurity regions (10i) disposed within the second semiconductor layers (10L1, 10L2) adjacent to the first electrode (109) between the second insulating pattern (74a) and the first electrode (109). The impurity regions (10i) may have the same conductivity type as the first and second source / drain regions (SD1, SD2), for example, an N-type conductivity type.

[0093] The semiconductor device (1) may further include insulating layers (82, 94) that are sequentially stacked on the insulating structure (36), the conductive patterns (72), the insulating structure (80), and the insulating layers (90, 50). The insulating layer (94) may cover the upper surface of the gate contact plug (92).

[0094] The semiconductor device (1) may further include, on the second region (GIA), an insulating layer (52) covering the insulating layer (50), and an insulating layer (54) on the insulating layer (52). The insulating layer (52) may be a liner. The insulating layer (52) and the insulating layer (54) may be formed of different insulating materials. For example, the insulating layer (52) may be formed of silicon nitride or a high dielectric, and the insulating layer (54) may be formed of silicon oxide.

[0095] The gate contact plugs (92) can penetrate the insulating layers (54, 52, 50) and be electrically connected to the gate contact lines (88).

[0096] In an embodiment, the transistors (TR) and information storage structures (CAP) disposed on one side of the insulating structure (80) may form a first memory block, and the transistors (TR) and information storage structures (CAP) disposed on the other side of the insulating structure (80) may form a second memory block. Accordingly, each of the first and second memory blocks (TR, CAP) may include transistors (TR) arranged three-dimensionally and information storage structures (CAP) electrically connected to the transistors (TR), and the insulating structure (80) may be disposed between the first memory blocks (TR, CAP) and the second memory blocks (TR, CAP).

[0098] Hereinafter, various modified examples of the components of the semiconductor device (1) described above will be explained with reference to FIGS. 6 to 10, respectively. The various modified examples of the components of the semiconductor device (1) described above described below will be explained with a focus on the modified components or the replaced components. In addition, the components that can be modified or replaced described below will be explained with reference to each drawing, but the components that can be modified may be combined with each other to form the semiconductor device (1) according to an embodiment of the present invention. FIGS. 6 to 10 are schematic drawings for explaining various modified examples of the components of the semiconductor device (1) described above. In FIGS. 6 to 10, FIG. 6 may show a modified example of a semiconductor device according to an embodiment of the present invention in a partially enlarged top view of FIG. 1b, FIG. 7 may show a modified example of a semiconductor device according to an embodiment of the present invention in a partially enlarged top view of FIG. 1b, FIG. 8 may show a modified example of the conductive patterns (72) in a II-II' cross-sectional structure of FIG. 2a, FIG. 9 may show a modified example of a semiconductor device according to an embodiment of the present invention in FIG. 1a, and FIG. 10 may show a cross-sectional structure of a region taken along the IIa-IIa' line of FIG. 9.

[0099] In a modified example, referring to FIG. 6, the conductive patterns (72) in FIG. 1b can be modified into conductive patterns (72') having a recessed side between the insulating pattern (74a) and the insulating layer (36a). Thus, the insulating pattern (78) can be extended between the insulating pattern (74a) and the insulating layer (36a).

[0100] In a modified example, referring to FIG. 7, the conductive patterns (72) in FIG. 1b can be modified into conductive patterns (72") having a width smaller than that of the second electrodes (103). For example, the width of the conductive patterns (72") in the first horizontal direction (Y) can be smaller than the width of the second electrodes (103) in the first horizontal direction (Y). The second insulating pattern (74a) in FIG. 1b can be modified into a second insulating pattern (74a') having a minimum width smaller than the width of each of the second electrodes (103) in the first horizontal direction (Y).

[0101] In a modified example, referring to FIG. 8, the conductive patterns (72) and the dummy conductive patterns (72d') in FIG. 2a can be modified into conductive patterns (272) that are connected to each other.

[0102] In a modified example, referring to FIGS. 9 and 10, the semiconductor device (1) may further include pad patterns (310) that penetrate the insulating layers (82, 94) and contact the upper regions of the conductive patterns (72), respectively. The pad patterns (310) may contact the insulating layers (74a, 36d).

[0104] Next, with reference to FIGS. 11 to 35, an exemplary example of a method for forming a semiconductor device according to one embodiment of the present invention will be described. FIGS. 11 to 35 are schematic drawings illustrating exemplary examples of a method for forming a semiconductor device according to an embodiment of the present invention, wherein FIGS. 11, 13, 15, 18, 20, 22, 24, 26, and 30 are partially enlarged top views of the area marked 'C' in FIG. 1a, FIGS. 12a, 14a, 16a, 17a, 19a, 21a, 23a, 25a, 27, 29, 34a, and 35 are cross-sectional views schematically illustrating regions taken along the lines I-I' and II-II' of FIG. 1a, and FIGS. 12b, 14b, 16b, 17b, 19b, 21b, 23b, 25b, and FIGS. 31, FIGS. 32a, and FIGS. 33a are schematic cross-sectional views of regions taken along the III-III' and IV-IV' lines of FIG. 1a, FIGS. 12c, FIGS. 14c, FIGS. 16c, FIGS. 17c, FIGS. 19c, FIGS. 21c, FIGS. 23c, FIGS. 25c, FIGS. 32b, and FIGS. 33b are schematic cross-sectional views of regions taken along the V-V' and VI-VI' lines of FIG. 1a, FIGS. 12d, FIGS. 14d, FIGS. 16d, FIGS. 17d, FIGS. 19d, FIGS. 21d, FIGS. 23d, FIGS. 25d, and FIGS. 34b are schematic cross-sectional views of regions taken along the VII-VII' and VIII-VIII' lines of FIG. 1a.

[0105] Referring to FIGS. 11, 12a to 12d, a substrate (3) comprising a first region (MCA) and a second region (GIA) adjacent to the first region (MCA) can be prepared. The substrate (3) may be a semiconductor substrate.

[0106] A mold structure (6) can be formed on the substrate (3). The mold structure (6) may include first semiconductor layers (8) and second semiconductor layers (10) that are alternately and repeatedly stacked. The semiconductor material of the first semiconductor layers (8) may be different from the semiconductor material of the second semiconductor layers (10). For example, the first semiconductor layers (8) may be SiGe, and the second semiconductor layers (10) may be Si. The substrate (3) may be Si.

[0107] The first semiconductor layers (8) may include first lower semiconductor layers (8L1, 8L2, 8L3), and the second semiconductor layers (10) may include second lower semiconductor layers (10L1, 10L2) and a second upper semiconductor layer (10U). Among the first and second semiconductor layers (8, 10), the uppermost layer may be the second upper semiconductor layer (10U), and the lowest layer may be the first lower semiconductor layer (8L1).

[0108] An insulating layer (12) can be formed on the above mold structure (6). The insulating layer (12) may be a mask layer.

[0109] The mold structure (6) can be etched to form openings using an etching process that utilizes the insulating layer (12) as an etching mask, and insulating layers (14, 16) can be formed within the openings. The insulating layers (14, 16) can be formed at different depths. For example, the lower surface of the insulating layers (14) can be formed at a higher level than the lower surface of the insulating layers (16).

[0110] The lower surface of the insulating layers (16) may be higher than the second lower semiconductor layer (10L1), and the lower surface of the insulating layers (14) may be higher than the second lower semiconductor layer (10L2).

[0111] The insulating layers (14, 16) can be placed on the first region (MCA).

[0112] In the top view, the insulating layers (14, 16) may be circular or elliptical in shape.

[0113] In the top view, the insulating layers (16) may be larger than the insulating layers (14).

[0114] The insulating layers (14, 16) may each contain the same material, for example, silicon oxide.

[0115] Referring to FIGS. 13, 14a to 14d, an insulating layer (18) can be formed on a substrate (3) comprising the insulating layers (14, 16). The insulating layer (18) may be a mask layer.

[0116] In an etching process using the insulating layer (18) as an etching mask, the mold structure (6) is etched to form line-shaped openings, a semiconductor layer (21) is formed on the inner wall of the mold structure (6) exposed by the openings, a conformal insulating layer (22) is formed, and insulating layers (24) that fill the openings can be filled. The insulating layer (22) may be an insulating liner covering the side and bottom surfaces of each of the insulating layers (24).

[0117] The above insulating layers (24) may be in the shape of a line extending in the first horizontal direction (Y).

[0118] The above insulating layers (14, 16) can be placed between the line-shaped insulating layers (24).

[0119] The insulating layers (24) may have lower surfaces located at a lower level than the lower surfaces of the insulating layers (14, 16). For example, the insulating layers (24) may penetrate to the second lower semiconductor layer (10L1) of the mold structure (6). The insulating layers (24) may be formed of silicon oxide.

[0120] Referring to FIGS. 15, 16a through 16d, an insulating layer (26) can be formed on a substrate (3) formed up to the insulating layers (24). The insulating layer (26) may be a mask layer that exposes at least the insulating layers (14, 16) and covers the insulating layers (24).

[0121] The above insulating layers (14, 16) can be removed to form openings (14_o, 16_o).

[0122] The first semiconductor layers (8) exposed by the openings (14_o, 16_o) can be partially etched to form openings (28) between the second semiconductor layers (10), and the second semiconductor layers (10) exposed by the openings (14_o, 16_o, 28) can be partially etched to form second semiconductor layers (10a) with reduced size.

[0123] The first semiconductor layers (8) may be formed as first semiconductor layers (8a) remaining on the second region (GIA). The second semiconductor layers (10a) may remain on the second region (GIA) without any reduction in thickness.

[0124] Referring to FIGS. 17a through 17d, insulating layers (32, 34) can be formed to fill the openings (28 in FIGS. 16a through 16d). Forming the insulating layers (32, 34) may include forming an insulating layer (32) that conformally covers the inner wall of the openings (28 in FIGS. 16a through 16d), forming an insulating layer (34) that fills the remaining portion of the openings (28 in FIGS. 16a through 16d), and etching the insulating layers (32, 34) so ​​as to remain within the openings (28 in FIGS. 16a through 16d).

[0125] The insulating layer (32) can be formed of silicon nitride, and the insulating layer (34) can be formed of silicon oxide.

[0126] Referring to FIGS. 18, 19a through 19d, an insulating layer (38) can be formed on a substrate (3) formed up to the insulating layers (32, 34). The insulating layer (38) may be a mask layer having an opening. The opening of the insulating layer (38) may be formed on the second region (GIA).

[0127] On the second region (GIA), the mold structure (6) can be etched by an etching process using the insulating layer (38) as an etching mask to form openings, form a conformal insulating layer (40), and form insulating layers (42) that fill the openings. On the second region (GIA), the insulating layers (42) may be in the shape of a line extending in the first horizontal direction (Y). The insulating layers (42) may be formed of silicon oxide. The insulating layer (40) may be an insulating liner that covers the bottom surface and sides of the insulating layers (42) and covers the top of the insulating layer (38).

[0128] The above insulating layers (42) may include insulating layers (42a, 42b) that are repeatedly arranged in the second horizontal direction (Y).

[0129] Referring to FIG. 20 and FIG. 21a to FIG. 21d, on a substrate (3) formed up to the insulating layers (42), the insulating layer (42b) is removed to form an opening, the first semiconductor layers (8) exposed by the opening are removed to form an opening while exposing the second semiconductor layers (10), and the second semiconductor layers (10) are partially etched to reduce the thickness of the second semiconductor layers (10). Subsequently, an insulating layer (50) that fills the opening can be formed. The insulating layer (50) may include an insulating layer (50a) that fills the space where the insulating layer (42b) was removed, insulating layers (50c) that fill between the second semiconductor layers (10), and an insulating layer (50b) disposed between the second semiconductor layers (10L1, 10L2) below the insulating layers (50c). The insulating layer (50) can be formed of silicon oxide.

[0130] The first and second semiconductor layers (8, 10) remaining on the second region (GIA) can be patterned to form a step shape.

[0131] Next, a conformal insulating layer (52) can be formed, and an insulating layer (54) covering the insulating layer (52) on a stepped structure on the second region (GIA) can be formed. The insulating layer (52) can be formed of silicon nitride or a high dielectric, and the insulating layer (54) can be formed of silicon oxide.

[0132] An insulating layer (56) may be formed on the insulating layers (52, 54). The insulating layer (56) may have an opening that exposes the insulating layer (24b) on the first region (MCA).

[0133] The insulating layer (24b) exposed by the insulating layer (56) can be optionally removed to form an opening (58). The opening (58) may be in the shape of a line extending in the first horizontal direction (Y).

[0134] An insulating layer (60) can be formed on the surface of the first and second semiconductor layers (8, 10) exposed by the opening (58). The insulating layer (60) can be formed of silicon oxide.

[0135] Referring to FIG. 22, FIG. 23a to FIG. 23d, the insulating layer (34) exposed by the opening (58) can be partially etched to form openings (62), an insulating layer (64) conformally covering the inner wall of the openings (62) and insulating layers (66) filling the openings (62) can be formed, and the insulating layers (64, 66) can be partially etched.

[0136] While partially etching the insulating layer (34), the insulating layer (56) may be etched and removed, and the insulating layer (52) may remain partially intact.

[0137] Next, a gate dielectric layer (68) is formed covering the inner wall of the remaining space of each of the openings (62), conductive lines (70) are formed on the gate dielectric layer (68) to fill the remaining space of the openings (62), and the conductive lines (70) can be partially etched.

[0138] Referring to FIGS. 24, 25a through 25d, insulating layers (62) can be formed to fill the remaining space of the opening filled with the conductive lines (70).

[0139] A first source / drain region (SD1) can be formed by performing an impurity implantation process. The first source / drain region (SD1) can be formed within the second semiconductor layer (10a) on the first region (MCA).

[0140] Conductive layers (71) in the form of spacers can be formed on the side walls of the opening (58). Forming the conductive layers (71) may include conformally forming a first layer (72a) and a second layer (72b) in sequence and performing anisotropic etching.

[0141] While forming the conductive layers (71) above, a dummy conductive layer (72d) may be formed on the side of the insulating layer (52).

[0142] An insulating layer (74, 74') can be formed on a substrate (3) formed up to the conductive layers (71). The insulating layer (74, 74') may include an insulating layer (74) that covers the conductive layers (71) and fills the opening (58), and an insulating layer (74') that covers the insulating layer (36).

[0143] The upper surface of the insulating layer (74') can form a co-surface with the upper surface of the insulating layer (52).

[0144] The insulating layer (74) may be formed from a material containing "element A". The insulating layer (74) may be formed from a material in which "element A" is doped into silicon oxide. The "element A" may include at least one of the elements of Group 13 or Group 15 of the periodic table. For example, the "element A" may include at least one of nitrogen (N), phosphorus (P), and boron (B). For example, the insulating layer (74) may be silicon oxide doped with nitrogen (N), silicon oxide doped with phosphorus (P), or silicon oxide doped with boron (B).

[0145] In the insulating layer (74) above, the content of the “A element” may be 30% or less.

[0147] Referring to FIGS. 26 and 27, the insulating layer (74) can be patterned to form openings (76) that expose the conductive layers (71). The remaining insulating layer (74) can be defined as insulating patterns (74a). Since the insulating layer (74) can be formed from a material containing the “A element,” bowing in the openings (76) can be minimized.

[0148] Referring to FIGS. 28 and 29, the conductive layers (71) exposed by the openings (76) that can minimize the bowing phenomenon can be selectively etched and removed. Thus, the conductive layers (71) in contact with the sides of the insulating patterns (74a) may remain. The remaining conductive layers (71) may be referred to as conductive patterns (72). The conductive patterns (72) can be formed to minimize the difference between the upper width and the lower width.

[0149] Insulating patterns (78) that fill the openings (76) can be formed. The insulating patterns (78) can be formed of silicon oxide.

[0150] Referring to FIGS. 30 and 31, the insulating layer (42a) can be partially etched to form openings (84). The openings (84) can be formed at a level higher than the second lower semiconductor layer (10L2). Insulating layers (42a') may remain below the openings (84).

[0151] Referring to FIGS. 32a and 32b, on the second region (GIA), the second semiconductor layers (10c) exposed by the openings (84) can be etched to form openings (86). Here, the second semiconductor layers (10a) on the first region (MCA) may remain.

[0152] Referring to FIGS. 33a and 33b, gate contact lines (88) that fill the openings (86) can be formed on the second region (GIA). The gate contact lines (88) can be electrically connected to the conductive lines (70). On the second region (GIA), gate contact plugs (92) that penetrate the insulating layers (52, 54) and contact the gate contact lines (88) can be formed.

[0153] Referring to FIGS. 34a and FIGS. 34b, the insulating layers (24a) can be etched to form openings (96), and the insulating layers (32, 34) exposed by the openings (96) can be partially etched to form openings (97) that expose the conductive lines (70) and the second semiconductor layers (10).

[0154] A source / drain process can be performed to form second source / drain regions (SD2) within the second semiconductor layers (10). The second semiconductor layers (10) remaining between the first and second source / drain regions (SD1, SD2) can be defined as a channel region (CH).

[0155] The first and second source / drain regions (SD1, SD2) and the channel region (CH) may be referred to as active layers (CH). Accordingly, the active layers (CH) may be stacked while being spaced apart from each other in the vertical direction (Z).

[0156] While forming the second source / drain regions (SD2), impurity regions (10i) may be formed within the exposed regions of the second semiconductor layers (10L1, 10L2).

[0157] The first and second source / drain regions (SD1, SD2) and the impurity regions (10i) may have an N-type conductivity.

[0158] Referring to FIG. 35, within the openings (97), insulating layers (99) covering the upper and lower surfaces of the second source / drain regions (SD2) can be formed.

[0159] Again, with reference to FIGS. 1 to 5, storage node electrodes (103) that contact the second source / drain regions (SD2) respectively can be formed within the openings (97). A capacitor dielectric layer (107) can be conformally formed on the substrate on which the storage node electrodes (103) are formed, and a plate electrode (109) covering the capacitor dielectric layer (107) can be formed.

[0161] With reference to FIG. 36, the bowing characteristics of a semiconductor device according to one embodiment of the present invention will be described. FIG. 36 is a graph for explaining the bowing phenomenon of openings (76) that expose the conductive layers (71) by patterning the insulating layer (74) described with reference to FIG. 26 and FIG. 27.

[0162] Referring to FIG. 36, when an opening is formed with the same depth using TEOS oxide (REF) and an insulating layer (SAMPLE) identical to the insulating layer (74) described with reference to FIG. 26 and FIG. 27, a bowing phenomenon may occur. In the graph of FIG. 36, the TEOS oxide (REF) can be seen to have a value of approximately 5.1%, and the insulating layer (SAMPLE) according to the embodiment of the present invention can be seen to have a value of approximately 2.4%. These figures indicate that the bowing occurring in the opening formed using the insulating layer (SAMPLE) according to the embodiment of the present invention is smaller than the bowing occurring in the opening formed using the TEOS oxide (REF). Therefore, the opening formed using the insulating layer (SAMPLE) according to the embodiment of the present invention may have a more uniform width across the upper and lower portions than the opening formed using the TEOS oxide (REF).

[0163] In this way, a conductive pattern formed by etching a conductive layer exposed by an opening formed using an insulating layer (SAMPLE) according to an embodiment of the present invention can be formed more uniformly across the upper and lower portions. Such a conductive pattern may be the conductive patterns (72) in FIGS. 1a to 5, and the conductive patterns (72) can be used as bit lines of a DRAM. Therefore, since bit lines can be formed with a more uniform size across the upper and lower portions, the electrical characteristics and reliability of the semiconductor device (1) can be further improved.

[0164] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A substrate comprising a first region and a second region adjacent to the first region; a first conductive line group comprising first conductive lines stacked and spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the first region of the substrate; a second conductive line group comprising second conductive lines stacked and spaced apart from each other in the vertical direction on the first region of the substrate; first active groups disposed on the first region of the substrate and arranged and spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate; second active groups disposed on the first region of the substrate and arranged and spaced apart from each other in the first horizontal direction, and spaced apart from the first active groups in a second horizontal direction perpendicular to the first horizontal direction; an insulating structure disposed between the first conductive line group and the second conductive line group. A semiconductor device comprising: first conductive patterns disposed between the insulating structure and the first active groups; and second conductive patterns disposed between the insulating structure and the second active groups, wherein each of the first active groups is spaced apart from each other in the vertical direction and stacked and includes first active layers intersecting each of the first conductive lines, and each of the second active groups is spaced apart from each other in the vertical direction and stacked and includes second active layers intersecting each of the second conductive lines, and the insulating structure comprises first insulating patterns and second insulating patterns alternately and repeatedly arranged in the first horizontal direction on the first region of the substrate, and the material of the first insulating patterns is different from the material of the second insulating patterns. Claim 2 A semiconductor device according to claim 1, wherein the material of the second insulating patterns is a material doped with "element A", and the material of the first insulating patterns is a material not doped with "element A". Claim 3 In claim 2, the semiconductor device wherein "element A" is at least one of nitrogen (N), phosphorus (P), and boron (B). Claim 4 A semiconductor device according to claim 2, wherein the content of "element A" within the second insulating patterns is 30% or less. Claim 5 A semiconductor device according to claim 1, wherein the material of the second insulating patterns is silicon oxide doped with "element A", and the material of the first insulating patterns is silicon oxide not doped with "element A". Claim 6 A semiconductor device according to claim 1, wherein each of the first and second active layers comprises a first source / drain region and a second source / drain region spaced apart from each other; and a channel region between the first source / drain region and the second source / drain region, wherein on the first region of the substrate, the first conductive lines overlap perpendicularly with the channel regions of the first active layers and extend in the first horizontal direction, and on the first region of the substrate, the second conductive lines overlap perpendicularly with the channel regions of the second active layers and extend in the first horizontal direction, wherein the first source / drain regions of the first active layers are electrically connected to the first conductive patterns, and the first source / drain regions of the second active layers are electrically connected to the second conductive patterns. Claim 7 A semiconductor device according to claim 6, further comprising information storage structures, wherein each of the information storage structures comprises a plate electrode, storage node electrodes, and a capacitor dielectric layer between the plate electrode and the storage node electrodes, and the storage node electrodes are electrically connected to the second source / drain regions of the first and second active layers. Claim 8 In claim 7, in the top view, each of the storage node electrodes is a "U" shaped semiconductor device. Claim 9 A semiconductor device according to claim 1, further comprising: first gate contact lines disposed on the second region of the substrate and electrically connected to the first group of conductive lines; second gate contact lines disposed on the second region of the substrate and electrically connected to the second group of conductive lines; gate contact plugs on the first and second gate contact lines and electrically connected to the first and second gate contact lines; and an insulating layer disposed between the first gate contact lines and the second gate contact lines on the second region of the substrate, wherein the insulating layer comprises the same material as the material of the second insulating patterns. Claim 10 A semiconductor device according to claim 9, further comprising gate dielectric layers interposed between at least the first active layers and the first conductive lines and interposed between at least the second active layers and the second conductive lines, wherein the first conductive lines comprise a pair of first conductive lines covering the upper and lower surfaces of any one of the first active layers, and any one of the first gate contact lines is in contact with and electrically connected to the pair of first conductive lines. Claim 11 A semiconductor device comprising: a substrate; an information storage structure disposed on the substrate; an insulating structure disposed on the substrate and spaced apart from the information storage structure; conductive lines disposed between the information storage structure and the insulating structure, spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate and stacked; active layers spaced apart from each other in the vertical direction between the information storage structure and the insulating structure and intersecting the conductive lines; and a conductive pattern disposed between the insulating structure and the active layers and electrically connected to the active layers, wherein the insulating structure comprises first insulating patterns spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate and a second insulating pattern disposed between the first insulating patterns, and the conductive pattern disposed between the second insulating pattern and the active layers, and the material of the second insulating pattern is different from the material of the first insulating patterns. Claim 12 In claim 11, the information storage structure comprises: a plate electrode; storage node electrodes disposed between the plate electrode and the active layers; and a capacitor dielectric layer disposed between at least the storage node electrodes and the plate electrode. Claim 13 In claim 11, the material of the second insulating pattern is a material doped with "element A", and the "element A" is at least one of nitrogen (N), phosphorus (P), and boron (B) in the semiconductor device. Claim 14 A semiconductor device according to claim 13, wherein the content of the "element A" within the second insulating pattern is 30% or less. Claim 15 In claim 13, the material of the first insulating patterns is a semiconductor device in which the material is not doped with the "element A". Claim 16 A semiconductor device according to claim 11, wherein in a second horizontal direction perpendicular to the first horizontal direction, at least one of the conductive lines has a first width in a portion that overlaps perpendicularly with the active layers, and has a second width smaller than the first width in a portion located between the information storage structure and the first insulating patterns. Claim 17 A semiconductor device comprising: a substrate; first insulating patterns disposed on the substrate and spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate; conductive patterns disposed on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; and a second insulating pattern disposed between the first insulating patterns and between the conductive patterns, wherein the material of the second insulating pattern is different from the material of the first insulating patterns. Claim 18 A semiconductor device according to claim 17, wherein the first insulating patterns comprise silicon oxide, and the second insulating pattern comprises a material in which "element A" is doped into the silicon oxide. Claim 19 In claim 18, the first insulating patterns are semiconductor devices that do not include the "A element". Claim 20 A semiconductor device according to claim 18, wherein the “A element” is at least one of nitrogen (N), phosphorus (P), and boron (B), and the content of the “A element” within the second insulating pattern is 30% or less.

Images