Memory device and method of manufacturing the same

Abstract

A memory device and a method for manufacturing the same are disclosed. The disclosed memory device may include a plurality of memory cells stacked in a vertical direction, and each of the plurality of memory cells may include a transistor and a capacitor electrically connected thereto to the side of the transistor, and the transistor may include a channel material layer, a word line disposed opposite thereto, and a gate insulating layer disposed between them, and may be provided with a bit line extended in a vertical direction to be connected to the plurality of transistors, and the capacitor may include an electrode member electrically connected to the transistor, a dielectric layer disposed on the surface of the electrode member, and a plate electrode disposed on the surface of the dielectric layer, and the electrode member may have a pillar structure extended in a first horizontal direction, and the dielectric layer may be disposed to surround the electrode member so as to contact the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member.

Description

Technology Field

[0001] The present invention relates to a semiconductor / electronic device and a method for manufacturing the same, and more specifically, to a memory device and a method for manufacturing the same. Background Technology

[0002] There is a continuous demand to increase the performance and integration density of semiconductor devices. However, arranging semiconductor unit cells two-dimensionally—that is, planarly—is reaching a limit in increasing the integration density of semiconductor devices. Accordingly, attempts are being made to develop technologies that significantly increase the integration density of semiconductor devices by integrating semiconductor unit cells three-dimensionally. In this regard, various attempts are being made to increase the integration density of memory devices, such as NAND and DRAM devices. Furthermore, research and development to improve the performance and operational characteristics of memory devices are also continuously being carried out.

[0003] As the number of stacked layers of a 3D memory device increases, scaling in the vertical direction may be required due to limitations in chip thickness. If the allowable height (thickness) per unit memory layer decreases, the minimum thickness of the thin film that can be deposited on each unit memory layer or the thickness of the unit element may also be limited. Consequently, for example, in the case of 3D DRAM, it may become difficult to form a capacitor with a cylinder structure. Therefore, structural modification of the cylinder-structured capacitor may be required, and along with this, technology to secure / improve the performance of the capacitor may be required. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a memory device having a three-dimensional structure that is advantageous for scaling in the vertical direction and also advantageous for securing and improving memory performance, and a method for manufacturing the same.

[0005] In addition, the technical problem that the present invention aims to solve is to provide a memory device having a three-dimensional structure that is advantageous for scaling in the vertical direction, can improve capacitance characteristics by securing the effective area of ​​the capacitor, and can also secure the formation margin of the capacitor dielectric layer, and a method for manufacturing the same.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be understood by those skilled in the art from the description below. means of solving the problem

[0007] According to one embodiment of the present invention, a memory device is provided that includes a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells includes a transistor and a capacitor electrically connected thereto to the side of the transistor, wherein the transistor includes a channel material layer, a word line disposed opposite thereto, and a gate insulating layer disposed between them, wherein a plurality of separation layers are provided to separate the plurality of transistors spaced apart in a vertical direction, and a bit line is provided that extends in a vertical direction to be connected to the plurality of transistors, wherein the capacitor includes an electrode member electrically connected to the transistor, a dielectric layer disposed on the surface of the electrode member, and a plate electrode disposed on the surface of the dielectric layer, wherein the electrode member has a pillar structure that extends in a horizontal direction, and the electrode member has a thickness greater than about 0.9 times the gap between two adjacent separation layers, and the dielectric layer is disposed to be in contact with the separation layer.

[0008] The electrode member may have a thickness corresponding to about 0.9 to 1.2 times the gap between the two adjacent separation layers.

[0009] The dielectric layer may be in planar contact with the side of the separation layer, and the electrode member may be positioned so as not to be in planar contact with the separation layer.

[0010] According to another embodiment of the present invention, a method for manufacturing a memory device is provided, comprising a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells comprises a transistor and a capacitor electrically connected thereto to the side of the transistor, the method comprising the steps of: providing a device structure including a transistor forming region and a capacitor forming region, wherein the transistor forming region includes a plurality of separation layers for separating the plurality of transistors in a vertical direction, and each of the plurality of separation layers includes an extension portion extended to the capacitor forming region; forming an electrode member having a pillar structure extended in a horizontal direction, the position of which is limited by the extension portion of the plurality of separation layers in the capacitor forming region; removing the extension portion of the plurality of separation layers in the capacitor forming region; forming a dielectric layer on the surface of the electrode member; and forming a plate electrode on the surface of the dielectric layer, wherein the electrode member, the dielectric layer, and the plate electrode constitute the capacitor, the electrode member has a thickness greater than about 0.9 times the gap between two adjacent separation layers, and the dielectric layer is arranged to be in contact with the separation layer.

[0011] The electrode member may have a thickness corresponding to about 0.9 to 1.2 times the gap between the two adjacent separation layers.

[0012] After the step of removing the above-mentioned extension, the electrode member may not be in planar contact with the separation layer, and the dielectric layer may be in planar contact with the side of the separation layer.

[0013] According to another embodiment of the present invention, a memory device is provided comprising a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells comprises a transistor and a capacitor electrically connected thereto to the side of the transistor, wherein the transistor comprises a channel material layer, a word line disposed opposite thereto, and a gate insulating layer disposed between them, and a bit line extended in a vertical direction to be connected to the plurality of transistors, and wherein the capacitor comprises an electrode member electrically connected to the transistor, a dielectric layer disposed on the surface of the electrode member, and a plate electrode disposed on the surface of the dielectric layer, wherein the electrode member has a pillar structure extended in a first horizontal direction, and the dielectric layer is disposed to surround the electrode member so as to contact the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member.

[0014] The electrode member may have a width greater than the channel material layer in a second horizontal direction orthogonal to the first horizontal direction.

[0015] The electrode member may have a width that extends to both sides of the channel material layer along a direction parallel to the second horizontal direction.

[0016] In the transistor forming region of the memory device, a separating material film may be provided on both sides of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction, and the separating material film may be in contact with the second side of the electrode member.

[0017] The above electrode member may have a thickness greater than the channel material layer in the vertical direction.

[0018] The channel material layer may be in contact with the central portion of the second side of the electrode member, and may further include a spacer insulating layer in contact with the lower portion and upper portion of the second side.

[0019] The above spacer insulating layer can be extended to contact the side of the word line.

[0020] A trench extending in a direction parallel to the word line may be provided in the capacitor forming region of the memory element, and a part of the dielectric layer and a part of the plate electrode may be disposed within the trench.

[0021] According to another embodiment of the present invention, a method for manufacturing a memory device is provided, comprising a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells comprises a transistor and a capacitor electrically connected thereto to the side of the transistor, the method comprising: a transistor forming region and a capacitor forming region; wherein the transistor forming region comprises a plurality of transistors spaced apart in a vertical direction, and the transistor comprises a channel material layer, a word line disposed opposite thereto, and a gate insulating layer disposed between them; wherein the capacitor forming region comprises an electrode member having a pillar structure electrically connected to the channel material layer and extended in a first horizontal direction, and wherein the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member are exposed; a dielectric layer covering the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member in the capacitor forming region; and a plate electrode being formed on the surface of the dielectric layer, wherein the electrode member, the dielectric layer, and the plate electrode constitute the capacitor.

[0022] The transistor forming region may include a separation layer for separating the plurality of transistors in a vertical direction, the separation layer may include a separation layer extension portion extended to the capacitor forming region, and the channel material layer may include a channel extension portion extended to the capacitor forming region.

[0023] The step of providing the above-described device structure may include: forming a spacer insulating layer covering the channel expansion portion and the separation layer expansion portion in the capacitor forming region; forming a filling insulating layer filling the space between and around the separation layer expansion portion and the channel expansion portion in the capacitor forming region; forming a vertical hole in the capacitor forming region to remove a portion of the spacer insulating layer and expose the side of the channel expansion portion; recessing the exposed channel expansion portion in the capacitor forming region to form a recess portion; and removing the portion of the spacer insulating layer exposed by the recess portion to expand the recess portion in the vertical direction.

[0024] Separation material films may be further provided on both sides of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction in the transistor forming region and the capacitor forming region.

[0025] The step of providing the above device structure may include: removing a portion of the separation material film exposed by the recess portion to expand the size of the recess portion in the second horizontal direction; and forming an electrode material layer that fills the recess portion having the expanded size.

[0026] The step of providing the above-described device structure may include: a step of defining the electrode member from the electrode material layer while forming a trench extending in the second horizontal direction in the capacitor forming region; and a step of removing the filling insulating layer, the spacer insulating layer, and the separation layer extension portion existing above and below the electrode member in the capacitor forming region through the trench, and removing the separation material film portion existing on both sides of the electrode member in the second horizontal direction to expose the upper surface, lower surface, front surface, and rear surface of the electrode member.

[0027] A portion of the dielectric layer and a portion of the plate electrode may be formed within the trench.

[0028] Separating material films may be further provided on both sides of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction in the transistor forming region and the capacitor forming region, and the step of providing the device structure may include: forming a recess portion for forming the electrode member in the capacitor forming region; removing a portion of the separating material film exposed by the recess portion to expand the size of the recess portion in the second horizontal direction; and forming an electrode material layer that fills the recess portion having the expanded size.

[0029] The step of providing the above device structure may include the step of defining the electrode member from the electrode material layer; and the step of removing the separation material film portions present on both sides of the electrode member in the second horizontal direction to expose the front and rear surfaces of the electrode member. Effects of the invention

[0030] According to embodiments of the present invention, a memory device having a three-dimensional structure that is advantageous for scaling in the vertical direction and also advantageous for securing and improving memory performance, and a method for manufacturing the same can be realized. Furthermore, according to embodiments of the present invention, a memory device having a three-dimensional structure that is advantageous for scaling in the vertical direction, can secure an effective area of ​​the capacitor to improve capacitance characteristics, and can also secure a formation margin for the capacitor dielectric layer, and a method for manufacturing the same can be realized. According to one example, the memory device may be configured to include a horizontally stacked DRAM device.

[0031] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0032] FIGS. 1 to 23 are drawings for exemplarily explaining a method for manufacturing a memory device according to an embodiment of the present invention. FIG. 23 is a cross-sectional view for explaining a memory element according to one embodiment of the present invention. FIGS. 24 to 40 are drawings for exemplarily illustrating a method for manufacturing a memory device according to another embodiment of the present invention. FIG. 40 is a cross-sectional view illustrating a memory element according to another embodiment of the present invention. Specific details for implementing the invention

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0034] The embodiments of the present invention described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments may be modified in various other forms.

[0035] The terms used herein are for describing specific embodiments and are not intended to limit the invention. Terms used herein in the singular form may include plural forms unless the context clearly indicates otherwise. Additionally, the terms “comprise” and / or “comprising” used herein specify the presence of the mentioned features, steps, numbers, actions, components, elements, and / or groups thereof, and do not exclude the presence or addition of one or more other features, steps, numbers, actions, components, elements, and / or groups thereof. Furthermore, the term “connected” used herein means not only that components are directly connected, but also includes the concept of indirectly connecting components through the interposition of additional components between them.

[0036] Furthermore, in the descriptions of this specification, terms such as "first" and "second," "upper or top," and "lower or bottom" are intended to distinguish members and are not used to limit the members themselves or to imply a specific order; rather, they indicate relative positional relationships and do not limit specific cases in which another member is introduced in direct contact with the member or at the interface between them. The same interpretation may apply to other expressions describing the relationships between components.

[0037] Furthermore, when a component is described in this specification as being located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components. The term "and / or" as used in this specification includes any one of the listed items and all combinations of one or more thereof. Additionally, terms of degree such as "about" and "substantially" as used in this specification are used to mean a range of numerical values ​​or degrees or approximate values, taking into account inherent manufacturing and material tolerances, and are used to prevent an infringer from unfairly exploiting the disclosures in which precise or absolute figures provided to aid in understanding this specification are mentioned.

[0038] Embodiments of the present invention will be described in detail below with reference to the attached drawings. The sizes or thicknesses of the areas or parts depicted in the attached drawings may be slightly exaggerated for the clarity of the specification and convenience of explanation. Throughout the detailed description, the same reference numerals indicate the same components.

[0039] FIGS. 1 to 23 are drawings for exemplarily explaining a method for manufacturing a memory device (stacked memory device) according to an embodiment of the present invention. FIGS. 1, FIGS. 3, FIGS. 5, FIGS. 7 to 23 are cross-sectional views cut along the XZ plane, and FIGS. 2, FIGS. 4, and FIGS. 6 are top-view views. FIG. 2 is a top-view of FIG. 1, FIG. 4 is a top-view of FIG. 3, and FIG. 6 is a top-view of FIG. 5.

[0040] Referring to FIGS. 1 and 2, a laminate can be formed on a substrate (SUB1) in which a first semiconductor layer (L1) and a second semiconductor layer (L2a, L2b) are alternately and repeatedly stacked. The material of the substrate (SUB1) can be selected from various materials. The substrate (SUB1) may be composed of a semiconductor material. The substrate (SUB1) may include a semiconductor wafer. The substrate (SUB1) may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate formed by an epitaxial growth process. The substrate (SUB1) may include a single-crystal semiconductor material. For example, the substrate (SUB1) may include any one of single-crystal silicon (Si), single-crystal germanium (Ge), and single-crystal silicon-germanium (SiGe).

[0041] The first semiconductor layer (L1) and the second semiconductor layer (L2a, L2b) may be formed, for example, on a substrate (SUB1) by an epitaxial process. The first semiconductor layer (L1) and the second semiconductor layer (L2a, L2b) may include a single-crystal semiconductor material. The first semiconductor layer (L1) may be, for example, a SiGe layer. The second semiconductor layer (L2a, L2b) may be, for example, a Si layer. The second-1 semiconductor layer (L2a) may have a relatively thin thickness, and the second-2 semiconductor layer (L2b) may have a relatively thick thickness. For example, the second-2 semiconductor layer (L2b) may have a thickness of at least about 1.2 times or at least about 1.3 times the thickness of the second-1 semiconductor layer (L2a). The thickness of the first semiconductor layer (L1) may be smaller than the thickness of the second-1 semiconductor layer (L2a) and the second-2 semiconductor layer (L2b), respectively. As a specific example, the laminate may have a structure in which a SiGe / Si(thin) / SiGe / Si(thick) structure is repeatedly stacked. When manufacturing an actual memory device, the number of repetitions of the SiGe / Si(thin) / SiGe / Si(thick) structure may be greater than that shown herein.

[0042] The above-described laminate can be patterned to form a plurality of pattern sections (line-type pattern sections) extended in a first horizontal direction (e.g., X-axis direction), and a separating material film (SM1) can be formed between the plurality of pattern sections and on both sides. The patterning may be for partitioning cell regions. A structure (S10) comprising the plurality of pattern sections and the separating material film (SM1) can be formed by filling the empty spaces on both sides of the pattern sections with the separating material film (SM1). The pattern sections may have a structure in which a first semiconductor layer (L1) and a second semiconductor layer (L2a, L2b) are alternately and repeatedly stacked. The separating material film (SM1) may be formed of a predetermined insulating material. As a non-limiting example, the separating material film (SM1) may be silicon oxide (e.g., SiO2) and silicon nitride (e.g., SiN x It can be formed from an insulating material having an etching selectivity ratio for )

[0043] Referring to FIGS. 3 and 4, a vertical hole (H10) can be formed in the transistor formation area (transistor formation planned area) of the structure (S10), and a vertical hole (H20) can be formed in the capacitor formation area (capacitor formation planned area). The vertical hole (H10) can be formed in the area where a bit line is to be formed. Therefore, the vertical hole (H10) can be referred to as a bit line hole. Meanwhile, the vertical hole (H20) can be referred to as a capacitor hole. Each of the vertical hole (H10) and the vertical hole (H20) can be formed to penetrate each of the aforementioned plurality of pattern portions to expose the upper surface of the substrate (SUB1). The vertical hole (H10) and the vertical hole (H20) can be formed by a dry etching process. A plurality of vertical holes (H10) can be formed spaced apart from each other in a second horizontal direction (e.g., the Y-axis direction) that is orthogonal to the first horizontal direction. In addition, a plurality of vertical holes (H20) may be formed spaced apart from each other in the second horizontal direction (e.g., the Y-axis direction).

[0044] Referring to FIGS. 5 and 6, the first semiconductor layer (L1 in FIG. 3) can be completely removed from the structure (S10). By utilizing the etching selectivity between the first semiconductor layer (L1) and the second semiconductor layers (L2a, L2b), the first semiconductor layer (L1) can be selectively etched and removed using a predetermined etching solution. The etching solution can be introduced through the vertical hole (H10) and the vertical hole (H20). The separation material film (SM1) extended in the first horizontal direction (e.g., X-axis direction) can support and hold the remaining second semiconductor layers (L2a, L2b).

[0045] Referring to FIG. 7, a second-1 semiconductor layer (L2a in FIG. 5) having a relatively thin thickness can be converted into a separation layer (SL1), and a gate insulating layer (GN1) can be formed on the surface of a second-2 semiconductor layer (L2b in FIG. 5) having a relatively thick thickness. According to one embodiment, through a thermal oxidation process for the second-1 semiconductor layer (L2a) and the second-2 semiconductor layer (L2b), the second-1 semiconductor layer (L2a) having a thin thickness can be entirely oxidized into an oxide layer, and the second-2 semiconductor layer (L2b) having a thick thickness can have a gate insulating layer (GN1) formed only on its surface. In this case, the separation layer (SL1) may be a silicon oxide layer (e.g., SiO2 layer). Additionally, the gate insulating layer (GN1) may also be a silicon oxide layer (e.g., SiO2 layer). The remaining semiconductor layer portion in the second semiconductor layer (L2b) can be used as a channel material layer (CM1). However, the method of forming the separation layer (SL1) and the method of forming the gate insulating layer (GN1) are not limited to those described above and may be changed depending on the circumstances. In addition, the material of the separation layer (SL1) and the material of the gate insulating layer (GN1) are not limited to those described above and may be changed in various ways.

[0046] Referring to FIG. 8, a first filling insulation layer (NF1) can be formed on the gate insulation layer (GN1) and the separation layer (SL1) to fill the empty regions between and around them. The first filling insulation layer (NF1) can be formed of an insulating material having an etch selectivity with respect to the gate insulation layer (GN1) and the separation layer (SL1). The first filling insulation layer (NF1) is, as a non-limiting example, silicon nitride (e.g., SiN x ) containing or silicon nitride (e.g., SiN x It can be formed as ). The first filling insulating layer (NF1) may be formed of a material other than silicon nitride. When forming the first filling insulating layer (NF1), a planarization process may be further performed on the upper surface and surrounding area after the deposition of the insulator for the first filling insulating layer (NF1).

[0047] Referring to FIG. 9, a vertical hole (H21) can be formed in the capacitor forming region. The vertical hole (H21) can be formed at a position corresponding to the vertical hole (H20) of FIG. 3. The vertical hole (H21) can be formed through a dry etching process, can be formed to remove a portion of the gate insulating layer (GN1), and can be formed to expose the side of the channel material layer (CM1). For reference, the expression 'corresponding' in this specification may mean the same thing, but may be a concept that encompasses things that are generally identical or similar. This may be applied equally throughout this specification.

[0048] Referring to FIG. 10, the gate insulating layer (GN1) portion in the capacitor formation region can be etched and removed. A predetermined etching solution can be introduced into the vertical hole (H21) to selectively wet-recess the gate insulating layer (GN1) portion in the capacitor formation region. Through this, a space for forming a capacitor can be secured. At this time, a portion of the separation layer (SL1) exposed by the vertical hole (H21) can also be etched.

[0049] Referring to FIG. 11, a second filling insulating layer (NF2) can be formed to fill the recessed portion and the vertical hole (H21) region in step 10. The second filling insulating layer (NF2) is, as a non-limiting example, silicon nitride (e.g., SiN x ) containing or silicon nitride (e.g., SiN x It can be formed as ). The second filling insulating layer (NF2) may be formed of a material other than silicon nitride. The second filling insulating layer (NF2) may be formed of the same material as the first filling insulating layer (NF1), but in some cases, it may be formed of a different material.

[0050] Referring to FIG. 12, a vertical hole (H11) can be formed in the transistor formation region. The vertical hole (H11) can be formed by a dry etching process. The vertical hole (H11) can be formed at a position corresponding to the vertical hole (H10) of FIG. 3. The vertical hole (H11) can be referred to as a bit line hole. When the vertical hole (H11) is formed, a portion of the gate insulating layer (GN1) may be etched, and a side of the channel material layer (CM1) may be exposed toward the vertical hole (H11).

[0051] Referring to FIG. 13, the first filled insulating layer (NF1) portion can be removed by recessing in the transistor formation region. The first filled insulating layer (NF1) portion can be selectively etched by introducing a predetermined etching solution through the vertical hole (H11). Through this, the surface of the gate insulating layer (GN1) can be exposed, and a space for transistor formation can be secured.

[0052] Referring to FIG. 14, a word line material layer (WM1) in contact with a gate insulating layer (GN1) can be formed in the transistor forming region. For example, the word line material layer (WM1) can be deposited in the transistor forming region, and the material deposited on the sidewall of the vertical hole (H11) can be removed through a wet etching process. The word line material layer (WM1) can be formed to extend between the gate insulating layer (GN1) and the separation layer (SL1).

[0053] Referring to FIG. 15, a portion of the material layer for the word line (WM1 in FIG. 14) adjacent to the vertical hole (H11) can be recessed and removed, and a word line (WL) can be defined from the material layer for the word line (WM1). A portion of the material layer for the word line (WM1) can be selectively recessed by introducing a predetermined etching solution through the vertical hole (H11). This may be a process for electrical separation between the bit line and the word line (WL) to be formed later. Thus, a transistor comprising a channel material layer (CM1), a word line (WL1) disposed opposite thereto, and a gate insulating layer (GN1) disposed between them can be defined. Additionally, a plurality of separation layers (SL1) for separating a plurality of transistors spaced apart in the vertical direction may be provided. According to one embodiment, the word line (WL1) may have a dual gate structure. Alternatively, the word line (WL1) may have a gate-all-around (GAA) structure. Thus, the transistor may have a dual-gate structure or a GAA structure.

[0054] The word line (WL1) may have a line shape (or a predetermined pattern shape) extended in the second horizontal direction (e.g., the Y-axis direction). After removing a portion of the separating material film (SM1) described in FIG. 6, the word line (WL1) having a shape extended in the second horizontal direction (e.g., the Y-axis direction) can be formed by filling the space where the portion of the separating material film (SM1) was removed with the material layer for the word line (WM1 in FIG. 14). Removing portions of the separating material film (SM1) in the transistor formation area and filling the space with the material layer for the word line (WM1 in FIG. 14) can be implemented in various ways.

[0055] Referring to FIG. 16, a gap-fill insulation layer (NG1) can be formed to fill the vertical hole (H11 in FIG. 15) and the surrounding space. The gap-fill insulation layer (NG1) can be formed to fill the empty space around the word line (WL1). The gap-fill insulation layer (NG1) can be formed of a predetermined insulating material.

[0056] Referring to FIG. 17, a vertical hole (H12) can be formed in the transistor formation region. The vertical hole (H12) can be formed by a dry etching process. The vertical hole (H12) can be formed at a position corresponding to the vertical hole (H11) in FIG. 14. With the formation of the vertical hole (H12), a side of the channel material layer (CM1) can be exposed toward the vertical hole (H12). In this specification, the term "transistor formation region" may, depending on the case, mean a region where a transistor is scheduled to be formed or a region where a transistor has been formed. The same applies to the term "capacitor formation region." The term "capacitor formation region" may, depending on the case, mean a region where a capacitor is scheduled to be formed or a region where a capacitor has been formed.

[0057] Referring to FIG. 18, a bit line (BL1) can be formed within the vertical hole (H12 in FIG. 17). The bit line (BL1) can be connected (contacted) to one end of the channel material layer (CM1). Accordingly, the bit line (BL1) can be formed to be connected (contacted) to one end of the channel material layer (CM1) in the area corresponding to the vertical hole (H12 in FIG. 17) in the transistor formation area. The bit line (BL1) may have a pillar shape that penetrates the structure (S10) in the vertical direction. The bit line (BL1) may be electrically connected to one end of the channel material layer (CM1) in the lateral direction. A bit line (BL1) connecting a plurality of channel material layers (CM1) may be formed. Additionally, a plurality of bit lines (BL1) may be formed. Although not illustrated, if there is a conductive material of the bit line (BL1) deposited on the upper side of the vertical hole (H12 in FIG. 17), it can be removed, for example, through an etchback process.

[0058] Referring to FIG. 19, after forming a vertical hole (H22) in the capacitor forming region, the channel material layer (CM1) portion and the first filling insulating layer (NF1) and the second filling insulating layer (NF2) in the capacitor forming region can be recessed to secure the capacitor forming space. The vertical hole (H22) can be formed, for example, by a dry etching process and can be formed at a position corresponding to the vertical hole (H21) in FIG. 9. Then, the channel material layer (CM1) portion can be recessed through the vertical hole (H22) by a wet etching process, and the first filling insulating layer (NF1) and the second filling insulating layer (NF2) can also be recessed by a wet etching process.

[0059] The device structure of FIG. 19 may include a transistor forming region and a capacitor forming region, and the transistor forming region may include a plurality of separation layers (SL1) for separating a plurality of transistors in a vertical direction, and each of the plurality of separation layers (SL1) may include an extension portion (SE1) extended to the capacitor forming region.

[0060] The method of providing a device structure such as that shown in FIG. 19 is not limited to the method described above with reference to FIG. 1 to FIG. 19, and various methodological variations may be possible. For example, instead of using a Si / SiGe repeating stacked structure, a repeating stacked structure of a semiconductor layer / insulating sacrificial layer may be used, and in this case, the channel material layer may include an amorphous semiconductor, a polycrystalline semiconductor, or an oxide semiconductor, etc., rather than a single-crystal semiconductor.

[0061] Referring to FIG. 20, an electrode member (EL1) can be formed in the capacitor forming region, the position of which is limited by an extension portion (SE1) of a plurality of separation layers (SL1). The electrode member (EL1) may have a pillar structure extended in a horizontal direction. The electrode member (EL1) may have a pillar structure extended in the first horizontal direction (e.g., X-axis direction). The electrode member (EL1) may be referred to as an electrode layer for a capacitor (first electrode layer). The electrode member (EL1) may be separated into individual capacitor regions. In other words, the electrode member (EL1) may be separated into unit cell regions.

[0062] Referring to FIG. 21, the extension portion (SE1 in FIG. 20) of a plurality of separation layers (SL1) in the capacitor forming region can be removed. For example, the extension portion (SE1 in FIG. 20) can be selectively recessed and removed by introducing a predetermined etching solution through a vertical hole (H22).

[0063] Referring to FIG. 22, a dielectric layer (DL1) can be formed on the surface of an electrode member (EL1) in the capacitor forming region. The dielectric layer (DL1) may be a dielectric layer for a capacitor. The dielectric layer (DL1) may be formed conformally along the surface shape of the electrode member (EL1). The dielectric layer (DL1) may be formed (deposited), for example, by an atomic layer deposition (ALD) process. The dielectric layer (DL1) may be formed to include at least one of various dielectric materials. For example, the dielectric layer (DL1) may include a high-k material having a dielectric constant higher than that of silicon nitride. The specific material of the dielectric layer (DL1) may vary.

[0064] The dielectric layer (DL1) may be positioned to contact the separating layer (SL1). The dielectric layer (DL1) may be in planar contact with the side of the separating layer (SL1). The dielectric layer (DL1) may be positioned in the space between two electrode members (EL1) that are adjacent to each other in the vertical direction, and a portion of the space may not be filled with the dielectric layer (DL1). Accordingly, in the space between two electrode members (EL1) that are adjacent to each other in the vertical direction, the dielectric layer (DL1) may have a U-shaped cross-sectional structure or a similar cross-sectional structure.

[0065] Referring to FIG. 23, a plate electrode (PL1) can be formed on the surface of a dielectric layer (DL1) in the capacitor forming region. The plate electrode (PL1) can be referred to as an electrode layer for a capacitor (second electrode layer). The plate electrode (PL1) can be formed to fill the space between a plurality of electrode members (EL1). The plate electrode (PL1) can be formed to include one or more of various electrode materials used in semiconductor device processes. The electrode members (EL1), the dielectric layer (DL1), and the plate electrode (PL1) can constitute a capacitor.

[0066] Hereinafter, the structure of a memory device according to one embodiment of the present invention will be described with reference to FIG. 23.

[0067] Referring to FIG. 23, a memory device according to one embodiment may include a plurality of memory cells stacked in a vertical direction, and each of the plurality of memory cells may include a transistor and a capacitor electrically connected thereto to the side of the transistor. The transistor may include a channel material layer (CM1), a word line (WL1) disposed opposite thereto, and a gate insulating layer (GN1) disposed between them. A plurality of separation layers (SL1) separating the plurality of transistors spaced apart in a vertical direction may be provided. A bit line (BL1) extended in a vertical direction to be connected to the plurality of transistors may be provided. The capacitor may include an electrode member (EL1) electrically connected to the transistor, a dielectric layer (DL1) disposed on the surface of the electrode member (EL1), and a plate electrode (PL1) disposed on the surface of the dielectric layer (DL1).

[0068] The electrode member (EL1) may have a thickness greater than approximately 0.9 times the gap between two adjacent separation layers (SL1). According to one example, the electrode member (EL1) may have a thickness corresponding to approximately 0.9 to 1.2 times the gap between the two adjacent separation layers (SL1). Since each electrode member (EL1) can have a pillar structure and a thickness (i.e., height) as large as possible, the maximum capacitor area can be secured, which is advantageous for securing capacitance. For example, the entire area in the height direction, excluding the area corresponding to the thickness of the separation layer (SL1), can be used as the capacitor area. Therefore, a pillar-type capacitor with the largest capacitor area can be implemented. In addition, because an electrode member (EL1) having a laterally extended pillar structure is used, it may be advantageous for vertical scaling compared to using a storage node having a cylinder structure, and consequently, it may be possible to implement a high-integration / high-density 3D memory device.

[0069] Additionally, the electrode member (EL1) may not be in planar contact with the separator layer (SL1), and the dielectric layer (DL1) may be in planar contact with the side of the separator layer (SL1). The dielectric layer (DL1) may be placed in the space between two mutually adjacent electrode members (EL1) in the vertical direction, and a portion of the space may not be filled with the dielectric layer (DL1). The plate electrode (PL1) may be placed to fill the space between the two adjacent electrode members (EL1) that is not filled with the dielectric layer (DL1).

[0070] The memory device of FIG. 23 may have a structure in which many more memory cells are stacked in the Z-axis direction than are illustrated. Additionally, the device structure of FIG. 23 may be repeatedly arranged in the X-axis direction and also repeatedly arranged in the Y-axis direction. According to these embodiments of the present invention, a memory device capable of significantly improving integration density while possessing excellent performance and operational characteristics can be realized. The memory device may be a memory device having a horizontal arrangement and a stacked structure. Furthermore, the memory device according to one embodiment of the present invention may be a three-dimensional DRAM device.

[0071] According to a specific example, in the memory device of FIG. 23, the capacitance (Cs) may be 4.5 fF, and the capacitor area is 39066.6 nm. 2 It can be, the width of the capacitor electrode member can be 125.3 nm, the thickness (height) of the capacitor electrode member can be 83.2 nm, the length of the capacitor electrode member can be 126 nm, and the unit cell area is 67350.0 nm 2 It can be, and the cell density is 1.93 Gb / mm 2 The thickness determining factor of the capacitor dielectric layer may be the thickness of the separator (e.g., 20 nm), the thickness of the gate insulating layer may be 10 nm, and the maximum thickness of the capacitor dielectric layer may be 8.5 nm. However, these specific figures are merely exemplary and may vary depending on the case.

[0072] FIGS. 24 to 40 are drawings for exemplarily illustrating a method for manufacturing a memory device (stacked memory device) according to another embodiment of the present invention. FIGS. 24 to 30 and FIGS. 36 to 40 are cross-sectional views cut along the XZ plane, and FIGS. 31 to 35 are cross-sectional views cut along the XY plane (i.e., Z-cut view).

[0073] Referring to FIG. 24, after providing a structure as shown in FIG. 18 through the method described above in FIG. 1 to 18, a vertical hole (H22) can be formed in the capacitor forming area. The vertical hole (H22) can be formed by a dry etching process and can be formed at a position corresponding to the vertical hole (H21) in FIG. 9. The size of the vertical hole (H22) may be slightly larger than the vertical hole (H21) in FIG. 9.

[0074] Referring to FIG. 25, the first filling insulating layer (NF1 in FIG. 24) and the second filling insulating layer (NF2 in FIG. 24) can be recessed in the capacitor forming region. The first filling insulating layer (NF1) and the second filling insulating layer (NF2) can be recessed by a wet etching process by introducing a predetermined etching solution through a vertical hole (H22). The structure of FIG. 25 may include a transistor forming region and a capacitor forming region. The transistor forming region may include a plurality of separation layers (SL1) for separating a plurality of transistors from one another in a vertical direction, and each of the plurality of separation layers (SL1) may include a separation layer extension portion (SE1) extended into the capacitor forming region. Additionally, the transistor forming region may include a plurality of channel material layers (CM1) spaced apart from one another in a vertical direction, and each of the plurality of channel material layers (CM1) may include a channel extension portion (CE1) extended into the capacitor forming region.

[0075] Referring to FIG. 26, a spacer insulating layer (SP1) covering a channel expansion portion (CE1) and a separation layer expansion portion (SE1) can be formed in the capacitor forming region. The spacer insulating layer (SP1) can be formed conformally along the surface shape of the capacitor forming region. The spacer insulating layer (SP1) can be formed (deposited), for example, by an ALD process. The spacer insulating layer (SP1) can be formed of silicon oxide (e.g., SiO2) or other insulating materials. The spacer insulating layer (SP1) can be formed with a thickness of about 15 nm or less or about 10 nm or less, but is not limited thereto. The spacer insulating layer (SP1) can be formed for the purpose of controlling the thickness (height) of the electrode member for the capacitor to be formed later. By forming the spacer insulating layer (SP1), the thickness (height) of the electrode member for the capacitor to be formed later can be increased. The thickness of the spacer insulating layer (SP1) can be determined by considering the appropriate thickness (height) of the electrode member for the capacitor to be formed later.

[0076] Referring to FIG. 27, a third filling insulating layer (NF3) can be formed to fill the space between and around the separation layer extension (SE1) and the channel extension (CE1) in the capacitor forming region. The third filling insulating layer (NF3) can be formed on the spacer insulating layer (SP1) and can be formed to fill the vertical hole (H22 in FIG. 26). As a non-limiting example, the third filling insulating layer (NF3) may be silicon nitride (e.g., SiN x ) containing or silicon nitride (e.g., SiN x It can be formed as ). The third filling insulating layer (NF3) may be formed of a material other than silicon nitride.

[0077] Referring to FIG. 28, a vertical hole (H23) can be formed in the capacitor forming region to remove a portion of the spacer insulating layer (SP1) and expose the side of the channel expansion portion (CE1) and the side of the separation layer expansion portion (SE1). The vertical hole (H23) can be formed by a dry etching process and can be formed at a position corresponding to the vertical hole (H22) of FIG. 24. The size of the vertical hole (H23) may be the same as or different from the size of the vertical hole (H22) of FIG. 24.

[0078] Referring to FIG. 29, the exposed channel expansion portion (CE1) in the capacitor forming region can be recessed to form a recessed portion (R1). By introducing an etching solution capable of selectively etching the channel expansion portion (CE1) through a vertical hole (H23), the channel expansion portion (CE1) can be recessed by a wet etching process.

[0079] Referring to FIG. 30, the recess (R1) can be expanded in the vertical direction by removing the portion of the spacer insulating layer (SP1) exposed by the recess (R1). Through this, the space for forming the electrode member for the capacitor to be formed later can be expanded in the vertical direction. This process can be described as "capacitor height widening" using the spacer insulating layer (SP1). In the process of removing the portion of the spacer insulating layer (SP1) exposed by the recess (R1), a portion of the separation layer expansion portion (SE1) can also be etched.

[0080] FIG. 31 is a cross-sectional view (i.e., Z-cut view) of the structure (S10) of FIG. 30 cut in the XY plane at the level of the channel material layer (CM1).

[0081] Referring to FIG. 32, the size of the recess (R1) in the second horizontal direction (e.g., Y-axis direction) can be expanded by removing a portion of the separation material film (SM1) exposed by the recess (R1). The recess (R1) can be expanded on both sides of the channel material layer (CM1) along a direction parallel to the second horizontal direction (e.g., Y-axis direction). The process of removing a portion of the separation material film (SM1) can be performed by a wet etching process. Thus, the step of FIG. 32 can be referred to as "side wet widening." The separation material film (SM1) can be etched in each of the directions on both sides of the recess (R1) by, for example, about 2 nm or more or about 3 nm or more.

[0082] Referring to FIG. 33, an electrode material layer (EM1) can be formed to fill a recess (R1 in FIG. 32) having the expanded size in the capacitor forming region. The electrode material layer (EM1) can be formed by a predetermined deposition process.

[0083] Referring to FIG. 34, an electrode member (EL1) can be defined from the electrode material layer (EM1 in FIG. 33) by forming a trench (T10) extending in the second horizontal direction (e.g., the Y-axis direction) in the capacitor forming area. The trench (T10) may have a line shape extending in the second horizontal direction. The trench (T10) may be formed to cross the area where the vertical holes (H23 in FIG. 32) are arranged, and may be formed to interconnect the vertical holes (H23 in FIG. 32).

[0084] Referring to FIG. 35, the portions of the separating material film (SM1) located on both sides of the electrode member (EL1) in the second horizontal direction (e.g., Y-axis direction) in the capacitor forming region can be removed (recessed) through a wet etching process, for example. Additionally, the third filling insulating layer (NF3), the spacer insulating layer (SP1), and the separating layer extension (SE1) located above and below the electrode member (EL1) in this step can be removed (recessed) through a wet etching process, for example (see FIG. 37 and FIG. 38). Along line (A) of FIG. 35, the third filling insulating layer (NF3), the spacer insulating layer (SP1), and the separating layer extension (SE1) in the capacitor forming region can be recessed, and along line (B), the portions of the separating material film (SM1) in the capacitor forming region can be recessed. Accordingly, the upper surface, lower surface, front surface, and rear surface of the electrode member (EL1) may be exposed. Since the first side of the electrode member (EL1) is already exposed, the upper surface, lower surface, front surface, rear surface, and first side of the electrode member (EL1) may be exposed.

[0085] Fig. 36 is an XZ planar cross-sectional view corresponding to the step of Fig. 33.

[0086] FIG. 37 is an XZ planar cross-sectional view corresponding to the step of FIG. 34. As shown in FIG. 37, the sides of the third filling insulating layer (NF3), the spacer insulating layer (SP1), and the separation layer extension (SE1) may be exposed by the trench (T10). Additionally, the first side of the electrode member (EL1) may be exposed by the trench (T10). The electrode member (EL1) may be electrically connected to the channel material layer (CM1) and may have a pillar structure extending in the first horizontal direction (e.g., the X-axis direction). The electrode member (EL1) may be referred to as an electrode layer for a capacitor (first electrode layer).

[0087] FIG. 38 is an XZ planar cross-sectional view corresponding to the step of FIG. 35. As shown in FIG. 38, the third filling insulating layer (NF3), the spacer insulating layer (SP1), and the separation layer extension (SE1) located above and below the electrode member (EL1) through the trench (T10) can be removed (recessed), for example, through a wet etching process. In addition, as previously described, the separation material film (SM1) portions located on both sides of the electrode member (EL1) in the second horizontal direction (e.g., Y-axis direction) in the capacitor forming region can be removed (recessed), for example, through a wet etching process. Thus, the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member (EL1) can be exposed.

[0088] The device structure of FIG. 38 may include a transistor forming region and a capacitor forming region, and the transistor forming region may include a plurality of transistors spaced apart in a vertical direction, and the transistor may include a channel material layer (CM1), a word line (WL1) disposed opposite thereto, and a gate insulating layer (GN1) disposed between them, and the capacitor forming region may be provided with an electrode member (EL1) having a pillar structure that is electrically connected to the channel material layer (CM1) and extends in a first horizontal direction, and the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member (EL1) may be exposed.

[0089] The method of providing a device structure such as that shown in FIG. 38 is not limited to the method described above with reference to FIG. 24 to FIG. 38, and various methodological variations may be possible. For example, instead of using a Si / SiGe repeating stacked structure, a repeating stacked structure of a semiconductor layer / insulating sacrificial layer may be used, and in this case, the channel material layer may include an amorphous semiconductor, a polycrystalline semiconductor, or an oxide semiconductor, etc., rather than a single-crystal semiconductor. In addition, depending on the case, at least one of the process of forming the spacer insulating layer (SP1) in FIG. 26 and the process of expanding the recess portion (R1) in FIG. 32 may be omitted. Furthermore, various other variations may be possible.

[0090] Referring to FIG. 39, a dielectric layer (DL1) can be formed covering the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member (EL1) in the capacitor forming region. The dielectric layer (DL1) may be a dielectric layer for a capacitor. The dielectric layer (DL1) may be formed conformally along the surface shape of the capacitor forming region including the electrode member (EL1). The dielectric layer (DL1) may be formed (deposited), for example, by an ALD process. The dielectric layer (DL1) may be formed to include at least one of various dielectric materials. For example, the dielectric layer (DL1) may include a high-k material having a dielectric constant higher than that of silicon nitride. The specific material of the dielectric layer (DL1) may vary. Since the dielectric layer (DL1) can be formed to cover the top, bottom, front, rear, and first side (i.e., five sides) of the electrode member (EL1), the effective area of ​​the capacitor can be greatly increased, and it can be significantly advantageous for securing characteristics such as capacitance. In addition, since the electrode member (EL1) can have a size expanded in the vertical direction and also a size expanded in the second horizontal direction, the contact area between the electrode member (EL1) and the dielectric layer (DL1) can be further increased, and it can be more advantageous for securing the characteristics of the capacitor.

[0091] Referring to FIG. 40, a plate electrode (PL1) can be formed on the surface of the dielectric layer (DL1) in the capacitor forming region. The plate electrode (PL1) can be referred to as an electrode layer for the capacitor (second electrode layer). The plate electrode (PL1) can be formed to fill the space between a plurality of electrode members (EL1). The plate electrode (PL1) can also be placed on the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member (EL1). When viewed from above, the plate electrode (PL1) can have a line shape. Therefore, the plate electrode (PL1) can also be referred to as a plate electrode line. The electrode member (EL1), the dielectric layer (DL1), and the plate electrode (PL1) can form a capacitor. A portion of the dielectric layer (DL1) and a portion of the plate electrode (PL1) can be placed within the trench (T10 in FIG. 39).

[0092] Hereinafter, the structure of a memory device according to another embodiment of the present invention will be described with reference to FIG. 40. At this time, the XY planar cross-sectional structure of FIG. 35 will be referred to for assistance.

[0093] Referring to FIG. 40, the memory device according to the present embodiment may include a plurality of memory cells stacked in a vertical direction, and each of the plurality of memory cells may include a transistor and a capacitor electrically connected thereto to the side of the transistor. The transistor may include a channel material layer (CM1), a word line (WL1) disposed opposite thereto, and a gate insulating layer (GN1) disposed between them, and may be provided with a bit line (BL1) extended in a vertical direction to be connected to the plurality of transistors. The capacitor may include an electrode member (EL1) electrically connected to the transistor, a dielectric layer (DL1) disposed on the surface of the electrode member (EL1), and a plate electrode (PL1) disposed on the surface of the dielectric layer (DL1). The electrode member (EL1) may have a pillar structure extended in a first horizontal direction. The dielectric layer (DL1) may be disposed to surround the electrode member (EL1) so as to contact the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member (EL1).

[0094] According to one embodiment, the electrode member (EL1) may have a width greater than that of the channel material layer (CM1) in a second horizontal direction (e.g., Y-axis direction) that is orthogonal to the first horizontal direction (e.g., X-axis direction) (see FIG. 35). The electrode member (EL1) may have a width that extends to both sides of the channel material layer (CM1) in a direction parallel to the second horizontal direction.

[0095] According to one embodiment, a separation material film (SM1) may be provided on both sides of a channel material layer (CM1) in a second horizontal direction (e.g., Y-axis direction) orthogonal to the first horizontal direction (e.g., X-axis direction) in a transistor forming region of the memory device, and the separation material film (SM1) may be in contact with a second side of an electrode member (EL1) (see FIG. 35). The channel material layer (CM1) may be in contact with a first region of the second side of the electrode member (EL1), and the separation material film (SM1) may be in contact with a second region of the second side of the electrode member (EL1).

[0096] According to one embodiment, the electrode member (EL1) may have a thickness greater than that of the channel material layer (CM1) in the vertical direction. The electrode member (EL1) may have a size (thickness) that is extended in the vertical direction compared to the channel material layer (CM1). As shown in FIG. 40, the channel material layer (CM1) may be in contact with the center of the second side of the electrode member (EL1), and a spacer insulating layer (SP1) may be further disposed in contact with the lower portion and upper portion of the second side. The spacer insulating layer (SP1) may be extended to surround one end of the channel material layer (CM1) and to be in contact with the side of the word line (WL1).

[0097] According to one embodiment, a trench (T10 in FIG. 35 and FIG. 39) extending in a direction parallel to the word line (WL1) may be provided in the capacitor forming region of the memory element, and a part of the dielectric layer (DL1) and a part of the plate electrode (PL1) may be disposed within the trench (T10).

[0098] According to an embodiment of the present invention, an electrode member (EL1) having a pillar structure, a dielectric layer (DL1), and a plate electrode (PL1) can form a capacitor. Since the dielectric layer (DL1) can be formed to cover the top surface, bottom surface, front surface, rear surface, and first side surface (i.e., five surfaces) of the electrode member (EL1), the effective area of ​​the capacitor can be greatly increased, and it can be significantly advantageous for securing characteristics such as capacitance. In addition, since the electrode member (EL1) can have a size expanded in the vertical direction and can also have a size expanded in the second horizontal direction, the contact area between the electrode member (EL1) and the dielectric layer (DL1) can be further increased, and it can be more advantageous for securing the characteristics of the capacitor.

[0099] In addition, according to an embodiment of the present invention, since an electrode member (EL1) having a laterally extended pillar structure is used, it may be advantageous for scaling in the vertical direction compared to when a storage node having a cylinder structure is used, and as a result, it may be possible to implement a high-integration / high-density three-dimensional memory device.

[0100] Furthermore, according to an embodiment of the present invention, the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member (EL1) are exposed without maximally expanding the thickness of the electrode member (EL1), and the size of the electrode member (EL1) in the second horizontal direction is expanded, thereby greatly expanding the contact area with the dielectric layer (DL1), which may be more advantageous for scaling the memory device in the vertical direction. In addition, since the spacing between the multiple electrode members (EL1) in the vertical direction is relatively large, the formation margin of the dielectric layer (DL1) can be easily secured, and the thickness of the dielectric layer (DL1) can be easily increased. Therefore, it may be more advantageous for improving the characteristics of the capacitor.

[0101] The memory device of FIG. 40 may have a structure in which many more memory cells are stacked in the Z-axis direction than are illustrated. Additionally, the device structure of FIG. 40 may be repeatedly arranged in the X-axis direction and also repeatedly arranged in the Y-axis direction. According to these embodiments of the present invention, a memory device capable of significantly improving integration density while possessing excellent performance and operational characteristics can be realized. The memory device may be a memory device having a horizontal arrangement and a stacked structure. Furthermore, the memory device according to one embodiment of the present invention may be a three-dimensional DRAM device.

[0102] According to a specific example, in the memory device of FIG. 40, the capacitance (Cs) may be 4.5 fF, and the capacitor area is 39067.2 nm. 2 It can be, the width of the capacitor electrode member can be 88.8 + 60 nm, the thickness (height) of the capacitor electrode member can be 60 nm, the length of the capacitor electrode member can be 107 nm, and the unit cell area is 52828.0 nm 2 It can be, and the cell density is 2.46 Gb / mm 2 The thickness determining factor of the capacitor dielectric layer may be the sum of the thickness of the separator and the thickness of two word line elements (e.g., 40 nm), the thickness of the gate insulating layer may be 10 nm, and the maximum thickness of the capacitor dielectric layer may be about 10 nm or more. However, these specific figures are merely exemplary and may vary depending on the case.

[0103] According to the embodiments of the present invention described above, a memory device having a three-dimensional structure that is advantageous for scaling in the vertical direction and also advantageous for securing and improving memory performance, and a method for manufacturing the same can be realized. Furthermore, according to the embodiments of the present invention, a memory device having a three-dimensional structure that is advantageous for scaling in the vertical direction, can secure an effective area of ​​the capacitor to improve capacitance characteristics, and can also secure a formation margin for the capacitor dielectric layer can be realized.

[0104] According to one example, a memory device according to an embodiment of the present invention may be configured to include a horizontally stacked DRAM device. However, at least some of the device structure and manufacturing method according to the embodiments of the present invention may be applied not only to DRAM devices but also to technical fields that implement other memory devices (e.g., PRAM, RRAM, SRAM, flash memory, MRAM, FRAM, etc.) or logic devices in which logic circuits are integrated.

[0105] This specification discloses preferred embodiments of the present invention. Although specific terms have been used, they are used merely in a general sense to facilitate the explanation of the technical content of the invention and to aid in understanding the invention, and are not intended to limit the scope of the invention. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other variations based on the technical concept of the present invention are possible. Those skilled in the art will understand that the memory device and the method for manufacturing the same according to the embodiments described with reference to FIGS. 1 to 40 can be variously substituted, changed, and modified within the scope of the technical concept of the present invention. Therefore, the scope of the invention should not be determined by the described embodiments but by the technical concept described in the claims. Explanation of the symbols

[0106] * Explanation of symbols for major parts of the drawing * SUB1: Substrate L1: First semiconductor layer L2a, L2b: Second semiconductor layer S10: Structure SM1: Separation membrane H10~H12: Vertical holes H20~H23: Vertical holes CM1: Channel material layer GN1: Gate insulation layer SL1: Separation layer NF1~NF3: Filled insulation layers WM1: Material layer for word lines WL1: Word line NG1: Gap-fill insulation layer BL1: Bit line SE1: Separation layer extension EL1: Electrode component DL1: Dielectric layer PL1: Plate electrode CE1: Channel expansion part SP1: Spacer insulation layer R1: Recess part EM1 : Electrode material layer T10 : Trench

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 A method for manufacturing a memory device comprising a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells comprises a transistor and a capacitor electrically connected thereto to the side of the transistor, the method comprising: providing a device structure including a transistor forming region and a capacitor forming region, wherein the transistor forming region includes a plurality of separation layers for separating the plurality of transistors in a vertical direction, and each of the plurality of separation layers includes an extension portion extended to the capacitor forming region; forming an electrode member having a pillar structure extended in a horizontal direction, wherein the position of the electrode member is limited by the extension portion of the plurality of separation layers in the capacitor forming region; removing the extension portion of the plurality of separation layers in the capacitor forming region; forming a dielectric layer on the surface of the electrode member; and forming a plate electrode on the surface of the dielectric layer, wherein the electrode member, the dielectric layer, and the plate electrode constitute the capacitor, the electrode member has a thickness greater than 0.9 times the gap between two adjacent separation layers, and the dielectric layer is arranged to contact the separation layer. Claim 5 A method for manufacturing a memory device according to claim 4, wherein the electrode member has a thickness corresponding to 0.9 to 1.2 times the gap between two adjacent separation layers. Claim 6 A method for manufacturing a memory device according to claim 4, wherein, after the step of removing the extension portion, the electrode member is not in planar contact with the separation layer, and the dielectric layer is in planar contact with the side of the separation layer. Claim 7 A memory device comprising a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells comprises a transistor and a capacitor electrically connected thereto to the lateral side of the transistor, wherein the transistor comprises a channel material layer, a word line disposed opposite thereto, and a gate insulating layer disposed between them, and is provided with a bit line extended in a vertical direction to be connected to the plurality of transistors, wherein the capacitor comprises an electrode member electrically connected to the transistor, a dielectric layer disposed on the surface of the electrode member, and a plate electrode disposed on the surface of the dielectric layer, wherein the electrode member has a pillar structure extended in a first horizontal direction, and the dielectric layer is disposed to surround the electrode member so as to contact the upper surface, lower surface, front surface, rear surface, and first side surface of the electrode member, wherein a separating material film is provided on both sides of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction in a transistor forming region of the memory device, wherein the separating material film extends vertically along the bit line, wherein the separating material film contacts a first region of a second side surface of the electrode member, and wherein the channel material layer is a second side surface of the electrode member Memory element in contact with area 2. Claim 8 In claim 7, the electrode member is a memory device having a width greater than that of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction. Claim 9 In claim 8, the electrode member is a memory element having a width extended on both sides of the channel material layer along a direction parallel to the second horizontal direction. Claim 10 delete Claim 11 In claim 7, the electrode member is a memory device having a thickness greater than that of the channel material layer in the vertical direction. Claim 12 A memory device according to claim 7, wherein the channel material layer is in contact with the central portion of the second side of the electrode member, and further comprises a spacer insulating layer in contact with the lower portion and upper portion of the second side. Claim 13 In claim 12, the spacer insulating layer is a memory element extended to contact the side of the word line. Claim 14 In claim 7, a memory element is provided with a trench extending in a direction parallel to the word line in a capacitor forming region of the memory element, and a part of the dielectric layer and a part of the plate electrode are disposed within the trench. Claim 15 A method for manufacturing a memory device comprising a plurality of memory cells stacked in a vertical direction, wherein each of the plurality of memory cells comprises a transistor and a capacitor electrically connected thereto to the side of the transistor, the method comprising: a step of providing a device structure having an upper surface, a lower surface, a front surface, a rear surface, and a first side surface of the electrode member, wherein the upper surface, a lower surface, a front surface, a rear surface, and a first side surface of the electrode member are exposed, and the upper surface, a lower surface, a front surface, a rear surface, and a first side surface of the electrode member are provided in the capacitor forming region; and a step of forming a dielectric layer covering the upper surface, a lower surface, a front surface, a rear surface, and a first side surface of the electrode member in the capacitor forming region. The method comprises the step of forming a plate electrode on the surface of the dielectric layer, wherein the transistor forming region includes a separation layer for separating the plurality of transistors from one another in a vertical direction, the separation layer includes a separation layer extension portion extended to the capacitor forming region, and the channel material layer includes a channel extension portion extended to the capacitor forming region, and the step of providing the device structure comprises: forming a spacer insulating layer covering the channel extension portion and the separation layer extension portion in the capacitor forming region; forming a filling insulating layer filling the space between and around the separation layer extension portion and the channel extension portion in the capacitor forming region; forming a vertical hole in the capacitor forming region to remove a portion of the spacer insulating layer and expose the side of the channel extension portion; and recessing the exposed channel extension portion in the capacitor forming region to form a recess portion.A method for manufacturing a memory element comprising the step of removing the spacer insulating layer portion exposed by the recess portion to expand the recess portion in the vertical direction, wherein the electrode member, the dielectric layer, and the plate electrode constitute the capacitor. Claim 16 delete Claim 17 In claim 15, a separation material film is further provided on both sides of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction in the transistor forming region and the capacitor forming region, and the step of providing the device structure comprises: a step of removing a portion of the separation material film exposed by the recess portion to expand the size of the recess portion in the second horizontal direction; and a step of forming an electrode material layer that fills the recess portion having the expanded size. Claim 18 A method for manufacturing a memory device according to claim 17, wherein the step of providing the device structure comprises: a step of defining the electrode member from the electrode material layer while forming a trench extending in the second horizontal direction in the capacitor forming region; and a step of removing the filling insulating layer, the spacer insulating layer, and the separation layer extension portion existing above and below the electrode member in the capacitor forming region through the trench, and removing the separation material film portion existing on both sides of the electrode member in the second horizontal direction to expose the upper surface, lower surface, front surface, and rear surface of the electrode member. Claim 19 A method for manufacturing a memory device according to claim 18, wherein a portion of the dielectric layer and a portion of the plate electrode are formed within the trench. Claim 20 In claim 15, a separation material film is further provided on both sides of the channel material layer in a second horizontal direction orthogonal to the first horizontal direction in the transistor forming region and the capacitor forming region, and the step of providing the device structure comprises: a step of forming a recess portion for forming the electrode member in the capacitor forming region; a step of removing a portion of the separation material film exposed by the recess portion to expand the size of the recess portion in the second horizontal direction; and a step of forming an electrode material layer that fills the recess portion having the expanded size. Claim 21 A method for manufacturing a memory device according to claim 20, wherein the step of providing the device structure comprises: a step of defining the electrode member from the electrode material layer; and a step of removing the separation material film portions existing on both sides of the electrode member in the second horizontal direction to expose the front and rear surfaces of the electrode member.

Images