Display device

Abstract

The display device comprises a substrate, a first conductive layer disposed on the substrate and including a data line extending in a first direction, a second conductive layer disposed on the first conductive layer and including a first scan line extending in a second direction intersecting the first direction and a second scan line extending in a second direction spaced apart from the first scan line, and a third conductive layer disposed on the second conductive layer and including a first driving voltage line extending in a second direction, a first common voltage line extending in the second direction spaced apart from the first driving voltage line, and a pixel electrode disposed between the first driving voltage line and the first common voltage line on a plane.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device that provides visual information. Background Technology

[0002] As information technology develops, the importance of display devices, which serve as a medium of connection between users and information, is being highlighted. Accordingly, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing.

[0003] The display device includes a transistor layer and a light-emitting element layer disposed on the transistor layer. The transistor layer has a structure in which a plurality of conductive patterns overlap each other and generates a driving current. The light-emitting elements included in the light-emitting element layer receive the driving current and emit light. The problem to be solved

[0004] The objective of the present invention is to provide a display device with improved display quality.

[0005] However, the purpose of the present invention is not limited to the aforementioned purpose and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0006] To achieve the aforementioned objectives of the present invention, a display device according to one embodiment of the present invention may include a substrate, a first conductive layer disposed on the substrate and including a data line extending in a first direction, a second conductive layer disposed on the first conductive layer and including a first scan line extending in a second direction intersecting the first direction and a second scan line extending in the second direction spaced apart from the first scan line, a first driving voltage line extending in the second direction disposed on the second conductive layer, a first common voltage line extending in the second direction spaced apart from the first driving voltage line, and a pixel electrode disposed between the first driving voltage line and the first common voltage line on a plane.

[0007] In one embodiment, the second scan wiring may overlap with at least one of the first driving voltage wiring and the first common voltage wiring on a plane.

[0008] In one embodiment, the first scan wiring may not overlap with the first driving voltage wiring and the first common voltage wiring, respectively, on a plane.

[0009] In one embodiment, the first driving voltage wiring and the first common voltage wiring may be arranged alternately along the first direction.

[0010] In one embodiment, the first conductive layer may further include a second common voltage wiring extending in the first direction and a second driving voltage wiring adjacent to the second common voltage wiring in the second direction and extending in the first direction.

[0011] In one embodiment, the first driving voltage wiring is electrically connected to the second driving voltage wiring, and the first common voltage wiring can be electrically connected to the second common voltage wiring.

[0012] In one embodiment, the first driving voltage wiring may include a first wiring portion extending in the second direction and a first branch portion protruding in the first direction from the first wiring portion.

[0013] In one embodiment, the first branch portion overlaps with the second driving voltage wiring on a plane, and the first driving voltage wiring can be electrically connected to the second driving voltage wiring through the first branch portion.

[0014] In one embodiment, the first common voltage wiring may include a second wiring portion extending in the second direction and a second branch portion protruding from the second wiring portion in a direction opposite to the first direction.

[0015] In one embodiment, the second branch may overlap with the second common voltage wiring on a plane, and the first common voltage wiring may be electrically connected to the second common voltage wiring through the second branch.

[0016] In one embodiment, the first conductive layer may further include a capacitor electrode.

[0017] In one embodiment, the display device further includes a gate conductive layer disposed between the first conductive layer and the second conductive layer, and the gate conductive layer may include a first gate wiring extending in the first direction and a second gate wiring extending in the first direction spaced apart from the first gate wiring.

[0018] In one embodiment, the first gate wiring may be electrically connected to the first scan wiring, and the second gate wiring may be electrically connected to the second scan wiring.

[0019] In one embodiment, the gate conductive layer further includes a gate electrode that overlaps with the capacitor electrode on a plane, and the gate electrode can form a storage capacitor together with the capacitor electrode.

[0020] In one embodiment, the display device further includes an active layer disposed between the first conductive layer and the gate conductive layer, and the active layer may include an active pattern that overlaps with the first gate wiring on a plane and is electrically connected to the gate electrode.

[0021] In one embodiment, the second conductive layer further includes a data electrode, and the data electrode can electrically connect the active pattern and the data wiring.

[0022] In one embodiment, the first scan wiring may include a first wiring portion extending in the second direction and a first branch portion protruding in the first direction from the first wiring portion.

[0023] In one embodiment, the display device further includes an active layer disposed between the first conductive layer and the second conductive layer, and the active layer includes an active pattern that overlaps the capacitor electrode and the first branch of the first scan wiring on a plane, and the active pattern can form a storage capacitor together with the capacitor electrode.

[0024] In one embodiment, the second scan wiring may include a second wiring portion extending in the second direction and a second branch portion protruding from the second wiring portion in the opposite direction to the first direction.

[0025] In one embodiment, the data wiring may overlap with the first driving voltage wiring and the first common voltage wiring on a plane. Effects of the invention

[0026] In a display device according to embodiments of the present invention, the driving voltage wiring and the common voltage wiring may be disposed on the same layer as the pixel electrodes. Accordingly, the parasitic capacitance between the driving voltage wiring and the common voltage wiring and the data wiring can be reduced, and sufficient space for the storage capacitor can be secured.

[0027] Additionally, the first scan wiring does not overlap with the driving voltage wiring and the common voltage wiring, respectively, while the second scan wiring may overlap with at least one of the driving voltage wiring and the common voltage wiring. By increasing the parasitic capacitance between the second scan wiring and at least one of the driving voltage wiring and the common voltage wiring, the interval between the first scan signal and the second scan signal can be secured. Accordingly, the display quality of the display device can be improved.

[0028] However, the effects of the present invention are not limited to the effects described above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0029] FIG. 1 is a block diagram illustrating a display device according to an embodiment of the present invention. Figure 2 is an equivalent circuit diagram of a light-emitting region included in the display device of Figure 1. FIGS. 3 to 7 are layout drawings for explaining an example of a pixel included in the display device of FIG. 1. FIG. 8 is a plan view for schematically illustrating the display device of FIG. 1. Figure 9 is a cross-sectional view taken along line II' of Figure 7. FIG. 10 is a block diagram illustrating a display device according to another embodiment of the present invention. FIGS. 11 to 14 are layout drawings for explaining an example of a pixel included in the display device of FIG. 10. FIG. 15 is a plan view for schematically illustrating the display device of FIG. 1. FIG. 16 is a cross-sectional view taken along the line II-II' of FIG. 14. Specific details for implementing the invention

[0030] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0031] FIG. 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0032] Referring to FIG. 1, a display device (10) according to one embodiment of the present invention may include a display panel (PNL), a data driving unit (DDV), a scan driving unit (SDV), and a control unit (CON).

[0033] The above display panel (PNL) may include a plurality of pixels (PX). The pixels (PX) may be arranged in a matrix form along a first direction (D1) and a second direction (D2) that intersects the first direction (D1). For example, the second direction (D2) may be perpendicular to the first direction (D1). Each of the pixels (PX) may include a plurality of subpixels. For example, each of the pixels (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). Each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may be provided with a data voltage (DATA), a scan signal (SCAN), a driving voltage (ELVDD), a common voltage (ELVSS), and an initialization voltage (VINT).

[0034] In one embodiment, the first subpixel (SPX1) may receive the data voltage (DATA) through the second data line (1520). The second subpixel (SPX2) may receive the data voltage (DATA) through the first data line (1510). The third subpixel (SPX3) may receive the data voltage (DATA) through the third data line (1530). Additionally, each of the first to third subpixels (SPX1, SPX2, SPX3) may receive the scan signal (SCAN) through the scan line (3200, 3500). However, the present invention is not limited thereto.

[0035] The data driver (DDV) can generate the data voltage (DATA) based on output image data (ODAT) and a data control signal (DCTRL). For example, the data driver (DDV) can generate the data voltage (DATA) corresponding to the output image data (ODAT) and output the data voltage (DATA) in response to the data control signal (DCTRL). The data control signal (DCTRL) may include an output data enable signal, a horizontal start signal, and a load signal. In one embodiment, the data driver (DDV) may be mounted on the display panel (PNL) or integrated in the periphery of the display panel (PNL). In another embodiment, the data driver (DDV) may be implemented as one or more integrated circuits (IC).

[0036] The scan driver (SDV) can generate the scan signal (SCAN) based on a scan control signal (SCTRL). The scan signal (SCAN) may include a first scan signal (e.g., the first scan signal (SC) of FIG. 2) and a second scan signal (e.g., the second scan signal (SS) of FIG. 2). For example, each of the first scan signal and the second scan signal may include a gate-on voltage that turns on a transistor and a gate-off voltage that turns off the transistor. The scan control signal (SCTRL) may include a vertical start signal, a clock signal, etc. In one embodiment, the scan driver (SDV) may be mounted on the display panel (PNL) or integrated in the periphery of the display panel (PNL). In another embodiment, the scan driver (SDV) may be implemented as one or more integrated circuits.

[0037] The above control unit (CON) (e.g., timing controller (T-CON)) may receive input image data (IDAT) and control signals (CTRL) from an external host processor (e.g., GPU). For example, the input image data (IDAT) may be RGB data including red image data, green image data, and blue image data. The control signals (CTRL) may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Based on the input image data (IDAT) and the control signals (CTRL), the control unit (CON) may generate the data control signal (DCTRL), the scan control signal (SCTRL), and the output image data (ODAT).

[0038] Figure 2 is an equivalent circuit diagram of a light-emitting region included in the display device of Figure 1.

[0039] Referring to FIG. 2, the first subpixel (SPX1) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a storage capacitor (CST), and a light-emitting element (LD). Each of the second subpixel (SPX2) and the third subpixel (SPX3) may have substantially the same circuit structure as the first subpixel (SPX1).

[0040] The first transistor (T1) may include a first terminal, a second terminal, and a gate terminal. The first terminal may receive the driving voltage (ELVDD). The second terminal may be connected to the light-emitting element (LD). The gate terminal may be connected to the second transistor (T2). The first transistor (T1) may generate a driving current based on the driving voltage (ELVDD) and the data voltage (DATA). For example, the first transistor (T1) may be a driving transistor for driving the light-emitting element (LD).

[0041] The second transistor (T2) may include a first terminal, a second terminal, and a gate terminal. The first terminal may receive the data voltage (DATA). The second terminal may be connected to the first transistor (T1). The gate terminal may receive a first scan signal (SC). The second transistor (T2) may transmit the data voltage (DATA) in response to the first scan signal (SC). For example, the second transistor (T2) may be a switching transistor.

[0042] The third transistor (T3) may include a first terminal, a second terminal, and a gate terminal. The first terminal may be connected to the first transistor (T1). The second terminal may receive the initialization voltage (VINT). The gate terminal may receive a second scan signal (SS). The third transistor (T3) may transmit the initialization voltage (VINT) in response to the second scan signal (SS). For example, the third transistor (T3) may be an initialization transistor.

[0043] The storage capacitor (CST) may include a first terminal and a second terminal. The first terminal may be connected to the gate terminal of the first transistor (T1). The second terminal may be connected to the first terminal of the third transistor (T3). The storage capacitor (CST) may maintain the voltage level of the gate terminal of the first transistor (T1) during the deactivation period of the first scan signal (SC).

[0044] The light-emitting element (LD) may include a first terminal and a second terminal. The first terminal may be connected to the second terminal of the first transistor (T1). The second terminal may receive the common voltage (ELVSS). The light-emitting element (LD) may emit light having a brightness corresponding to the driving current. The light-emitting element (LD) may include an organic light-emitting element utilizing an organic material as the light-emitting layer, an inorganic light-emitting element utilizing an inorganic material as the light-emitting layer, etc.

[0045] In FIG. 2, one subpixel (SPX) is illustrated as comprising three transistors (T1, T2, T3), one storage capacitor (CST), and one light-emitting element (LD), but the present invention is not limited thereto. For example, one subpixel may comprise at least one transistor, at least one storage capacitor, and at least one light-emitting element.

[0046] FIGS. 3 to 7 are layout drawings for explaining an example of a pixel included in the display device of FIG. 1. FIG. 8 is a plan view for schematically explaining the display device of FIG. 1, and FIG. 9 is a cross-sectional view taken along line II' of FIG. 7.

[0047] For example, FIGS. 3 to 9 may be drawings for illustrating an example of some of the plurality of conductive patterns included in the display device (10).

[0048] Referring to FIGS. 1, FIGS. 3 and FIGS. 9, the display device (10) may include a substrate (SUB) and a first conductive pattern (1000).

[0049] The above substrate (SUB) may include a transparent or opaque material. In one embodiment, examples of materials that can be used as the substrate (SUB) may include glass, quartz, plastic, etc. These may be used alone or in combination with each other.

[0050] The first conductive pattern (1000) may be disposed on the substrate (SUB). The first conductive pattern (1000) may include a first common voltage wiring (1100), an initialization voltage wiring (1200), a first driving voltage wiring (1300), a first capacitor electrode (1410), a second capacitor electrode (1420), a third capacitor electrode (1430), the first data wiring (1510), the second data wiring (1520), and the third data wiring (1530).

[0051] The first common voltage wiring (1100) may be extended in the first direction (D1). The first common voltage wiring (1100) may provide the common voltage (ELVSS) to the first to third subpixels (SPX1, SPX2, SPX3).

[0052] The initial voltage wiring (1200) may be adjacent to the first common voltage wiring (1100) in the second direction (D2) and may extend in the first direction (D1). The initial voltage wiring (1200) may provide the initial voltage (VINT) to the first to third subpixels (SPX1, SPX2, SPX3).

[0053] The first driving voltage wiring (1300) may be adjacent to the initialization voltage wiring (1200) in the second direction (D2) and may extend in the first direction (D1). The first driving voltage wiring (1300) may provide the driving voltage (ELVDD) to the first to third subpixels (SPX1, SPX2, SPX3).

[0054] The first to third capacitor electrodes (1410, 1420, 1430) may be adjacent to the first driving voltage wiring (1300) in the second direction (D2) and may be arranged along the first direction (D1).

[0055] In one embodiment, the first capacitor electrode (1410) may be electrically connected to the initialization voltage wiring (1200). For example, the first capacitor electrode (1410) may correspond to the second terminal of the storage capacitor (CST) included in the first subpixel (SPX1) described with reference to FIG. 2.

[0056] Additionally, the second capacitor electrode (1420) may be electrically connected to the initial voltage wiring (1200). The third capacitor electrode (1430) may be electrically connected to the initial voltage wiring (1200).

[0057] The first data wiring (1510) may be adjacent to the first to third capacitor electrodes (1410, 1420, 1430) in the second direction (D2) and may extend in the first direction (D1). The first data wiring (1510) may provide the data voltage (DATA) to the second subpixel (SPX2).

[0058] The second data line (1520) may be adjacent to the first data line (1510) in the second direction (D2) and may extend in the first direction (D1). The second data line (1520) may provide the data voltage (DATA) to the first subpixel (SPX1).

[0059] The third data line (1530) may be adjacent to the second data line (1520) in the second direction (D2) and may extend in the first direction (D1). The third data line (1530) may provide the data voltage (DATA) to the third subpixel (SPX3).

[0060] However, the connection relationship between the first to third data lines (1510, 1520, 1530) and the first to third subpixels (SPX1, SPX2, SPX3) is not limited thereto. The connection relationship between the first to third data lines (1510, 1520, 1530) and the first to third subpixels (SPX1, SPX2, SPX3) can be appropriately set as needed.

[0061] In one embodiment, the first conductive pattern (1000) may include a conductive material. Examples of conductive materials that can be used as the first conductive pattern (1000) include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. Additionally, the first conductive pattern (1000) may be composed of a single layer or multiple layers.

[0062] Referring to FIGS. 3, 4 and 9, the first insulating layer (IL1) is placed on the first conductive pattern (1000) and can cover the first conductive pattern (1000).

[0063] The first insulating layer (IL1) can prevent metal atoms or impurities from the substrate (SUB) from diffusing into the semiconductor pattern (2000). Additionally, the first insulating layer (IL1) can control the rate of heat supply during the crystallization process for forming the semiconductor pattern (2000). The first insulating layer (IL1) may include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the first insulating layer (IL1) include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc. These may be used alone or in combination with each other.

[0064] The semiconductor pattern (2000) may be disposed on the first insulating layer (IL1). The semiconductor pattern (2000) may include a first semiconductor pattern (2110), a second semiconductor pattern (2120), a third semiconductor pattern (2130), a fourth semiconductor pattern (2210), a fifth semiconductor pattern (2220), a sixth semiconductor pattern (2230), a first active pattern (2310), a second active pattern (2320), and a third active pattern (2330).

[0065] The first semiconductor pattern (2110), the second semiconductor pattern (2120), and the third semiconductor pattern (2130) can be arranged along the first direction (D1).

[0066] In one embodiment, the first semiconductor pattern (2110) may be electrically connected to the initialization voltage wiring (1200) and may transmit the initialization voltage (VINT) to the first subpixel (SPX1). For example, the first semiconductor pattern (2110) may correspond to the first terminal and the second terminal of the third transistor (T3) included in the first subpixel (SPX1) described with reference to FIG. 2.

[0067] Additionally, the second semiconductor pattern (2120) can be electrically connected to the initial voltage wiring (1200) and can transmit the initial voltage (VINT) to the second subpixel (SPX2). The third semiconductor pattern (2130) can be electrically connected to the initial voltage wiring (1200) and can transmit the initial voltage (VINT) to the third subpixel (SPX3).

[0068] The fourth semiconductor pattern (2210), the fifth semiconductor pattern (2220), and the sixth semiconductor pattern (2230) may be arranged along the first direction (D1). The fourth to sixth semiconductor patterns (2210, 2220, 2230) may overlap with the first to third capacitor electrodes (1410, 1420, 1430), respectively.

[0069] In one embodiment, the fourth semiconductor pattern (2210) may be electrically connected to the first driving voltage wiring (1300) and may transmit the driving voltage (ELVDD) to the first subpixel (SPX1). For example, the fourth semiconductor pattern (2210) may correspond to the first terminal and the second terminal of the first transistor (T1) included in the first subpixel (SPX1) described with reference to FIG. 2.

[0070] Additionally, the fifth semiconductor pattern (2220) can be electrically connected to the first driving voltage wiring (1300) and can transmit the driving voltage (ELVDD) to the second subpixel (SPX2). The sixth semiconductor pattern (2230) can be electrically connected to the first driving voltage wiring (1300) and can transmit the driving voltage (ELVDD) to the third subpixel (SPX3).

[0071] The first active pattern (2310), the second active pattern (2320), and the third active pattern (2330) can be arranged along the first direction (D1).

[0072] In one embodiment, the first active pattern (2310) may be electrically connected to the second data wiring (1520) and may transmit the data voltage (DATA) to the first subpixel (SPX1). For example, the first active pattern (2310) may correspond to the first terminal and the second terminal of the second transistor (T2) included in the first subpixel (SPX1) described with reference to FIG. 2.

[0073] Additionally, the second active pattern (2320) can be electrically connected to the first data wiring (1510) and can transmit the data voltage (DATA) to the second subpixel (SPX2). The third active pattern (2330) can be electrically connected to the third data wiring (1530) and can transmit the data voltage (DATA) to the third subpixel (SPX3).

[0074] In one embodiment, the semiconductor pattern (2000) may include a silicon semiconductor material or an oxide semiconductor material. Examples of silicon semiconductor materials that can be used as the semiconductor pattern (2000) include amorphous silicon, polycrystalline silicon, etc. Examples of oxide semiconductor materials that can be used as the semiconductor pattern (2000) include indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). These may each be used individually or in combination with each other.

[0075] Referring to FIGS. 4, 5, and 9, a second insulating layer (IL2) may be disposed on the semiconductor pattern (2000). In one embodiment, the second insulating layer (IL2) may include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the second insulating layer (IL2) include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0076] The second conductive pattern (3000) may be disposed on the second insulating layer (IL2). The second conductive pattern (3000) may overlap the second insulating layer (IL2) entirely. The second conductive pattern (3000) may include a first double electrode (3100), a first gate wiring (3500), a second double electrode (3310), a third double electrode (3320), a fourth double electrode (3330), a first gate electrode (3410), a second gate electrode (3420), a third gate electrode (3430), and a second gate wiring (3200).

[0077] The first double electrode (3100) can overlap with the first common voltage wiring (1100). The first double electrode (3100) can be electrically connected to the first common voltage wiring (1100) and can reduce the electrical resistance of the first common voltage wiring (1100). Accordingly, a voltage drop of the common voltage (ELVSS) can be prevented.

[0078] The second gate wiring (3200) may be adjacent to the first dual electrode (3100) in the second direction (D2) and may extend in the first direction (D1). The second gate wiring (3200) may overlap with the first to third semiconductor patterns (2110, 2120, 2130). The second gate wiring (3200) may provide the second scan signal (SS) to the first to third subpixels (SPX1, SPX2, SPX3).

[0079] The second to fourth dual electrodes (3310, 3320, 3330) may be adjacent to the second gate wiring (3200) in the second direction (D2) and may be arranged along the first direction (D1). The second to fourth dual electrodes (3310, 3320, 3330) may overlap with the first driving voltage wiring (1300). The second to fourth dual electrodes (3310, 3320, 3330) may be electrically connected to the first driving voltage wiring (1300) and may reduce the electrical resistance of the first driving voltage wiring (1300). Accordingly, a voltage drop of the driving voltage (ELVDD) may be prevented.

[0080] The first to third gate electrodes (3410, 3420, 3430) may be adjacent to the second to fourth dual electrodes (3310, 3320, 3330) in the second direction (D2) and may be arranged along the first direction (D1).

[0081] In one embodiment, the first gate electrode (3410) may be electrically connected to the first active pattern (2310) and may overlap with the fourth semiconductor pattern (2210). For example, the first gate electrode (3410) may correspond to the gate terminal of the first transistor (T1) included in the first subpixel (SPX1) described with reference to FIG. 2.

[0082] Additionally, the second gate electrode (3420) can be electrically connected to the second active pattern (2320) and can overlap with the fifth semiconductor pattern (2220). The third gate electrode (3430) can be electrically connected to the third active pattern (2330) and can overlap with the sixth semiconductor pattern (2230).

[0083] In one embodiment, the first gate electrode (3410) may overlap with the first capacitor electrode (1410). For example, the first gate electrode (3410) may correspond to the first terminal of the storage capacitor (CST) included in the first subpixel (SPX1) described with reference to FIG. 2. That is, the first capacitor electrode (1410) and the first gate electrode (3410) may form the storage capacitor (CST).

[0084] Additionally, the second gate electrode (3420) can overlap with the second capacitor electrode (1420) and form the storage capacitor (CST). The third gate electrode (3430) can overlap with the third capacitor electrode (1430) and form the storage capacitor (CST).

[0085] The first gate wiring (3500) may be adjacent to the first to third gate electrodes (3410, 3420, 3430) in the second direction (D2) and may extend along the first direction (D1). The first gate wiring (3500) may overlap with the first to third active patterns (2310, 2320, 2330). The first gate wiring (3500) may provide the first scan signal (SC) to the first to third subpixels (SPX1, SPX2, SPX3). For example, the first gate wiring (3500) may correspond to the gate terminal of the second transistor (T2) included in the first subpixel (SPX1) described with reference to FIG. 2.

[0086] The second conductive pattern (3000) may include a conductive material. Examples of conductive materials that can be used as the second conductive pattern (3000) include silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, nickel, chromium, chromium nitride, titanium, tantalum, platinum, scandium, indium tin oxide, indium zinc oxide, etc. These may be used alone or in combination with each other. Additionally, the second conductive pattern (3000) may be composed of a single layer or multiple layers.

[0087] Referring to FIGS. 5, 6 and 9, a third insulating layer (IL3) is disposed on the second conductive pattern (3000) and can cover the second conductive pattern (3000). In one embodiment, the third insulating layer (IL3) may include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the third insulating layer (IL3) include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0088] A third conductive pattern (4000) may be disposed on the third insulating layer (IL3). The third conductive pattern (4000) may include a first scan wiring (4100), a second scan wiring (4200), a common voltage connection electrode (4300), an initial voltage connection electrode (4400), a first driving voltage connection electrode (4510), a second driving voltage connection electrode (4520), a third driving voltage connection electrode (4530), a first anode pad (4610), a second anode pad (4620), a third anode pad (4630), a first connection electrode (4710), a second connection electrode (4720), a third connection electrode (4730), a first data electrode (4810), a second data electrode (4820), and a third data electrode (4830).

[0089] The first scan wiring (4100) may be extended in the second direction (D2). The first scan wiring (4100) may be in contact with the first gate wiring (3500) through at least one contact hole. The first scan wiring (4100) may be electrically connected to the first gate wiring (3500) and may transmit the first scan signal (SC) to the first gate wiring (3500).

[0090] The second scan wiring (4200) may be spaced apart from the first scan wiring (4100) in the first direction (D1) and may be extended in the second direction (D2). The second scan wiring (4200) may contact the second gate wiring (3200) through at least one contact hole. The second scan wiring (4200) may be electrically connected to the second gate wiring (3200) and may transmit the second scan signal (SS) to the second gate wiring (3200).

[0091] The common voltage connection electrode (4300) may be positioned on a plane between the first scan wiring (4100) and the second scan wiring (4200). The common voltage connection electrode (4300) may overlap with the first common voltage wiring (1100) and the first dual electrode (3100). The common voltage connection electrode (4300) may contact the first common voltage wiring (1100) and the first dual electrode (3100) through at least one contact hole.

[0092] The initial voltage connection electrode (4400) may be adjacent to the common voltage connection electrode (4300) in the second direction (D2). The initial voltage connection electrode (4400) may overlap with the initial voltage wiring (1200). The initial voltage connection electrode (4400) may contact the initial voltage wiring (1200) and the first to third semiconductor patterns (2110, 2120, 2130) through at least one contact hole. The initial voltage connection electrode (4400) may transmit the initial voltage (VINT) from the initial voltage wiring (1200) to the first to third semiconductor patterns (2110, 2120, 2130).

[0093] The first to third driving voltage connection electrodes (4510, 4520, 4530) may be adjacent to the initialization voltage connection electrode (4400) in the second direction (D2) and may be arranged along the first direction (D1). The first to third driving voltage connection electrodes (4510, 4520, 4530) may overlap with the first driving voltage wiring (1300).

[0094] The first driving voltage connecting electrode (4510) can contact the first driving voltage wiring (1300), the fourth semiconductor pattern (2210), and the second dual electrode (3310) through at least one contact hole. The first driving voltage connecting electrode (4510) can transmit the driving voltage (ELVDD) from the first driving voltage wiring (1300) to the fourth semiconductor pattern (2210).

[0095] Additionally, the second driving voltage connecting electrode (4520) can be in contact with the first driving voltage wiring (1300), the fifth semiconductor pattern (2220), and the third dual electrode (3320) through at least one contact hole. The third driving voltage connecting electrode (4530) can be in contact with the first driving voltage wiring (1300), the sixth semiconductor pattern (2230), and the fourth dual electrode (3330) through at least one contact hole.

[0096] The first to third anode pads (4610, 4620, 4630) may be adjacent to the first to third driving voltage connection electrodes (4510, 4520, 4530) in the second direction (D2) and may be arranged along the first direction (D1).

[0097] The first anode pad (4610) can contact the first capacitor electrode (1410), the first semiconductor pattern (2110), and the fourth semiconductor pattern (2210) through at least one contact hole. The first anode pad (4610) can transmit the initialization voltage (VINT) from the first semiconductor pattern (2110) to the first capacitor electrode (1410).

[0098] Additionally, the second anode pad (4620) can be in contact with the second capacitor electrode (1420), the second semiconductor pattern (2120), and the fifth semiconductor pattern (2220) through at least one contact hole. The third anode pad (4630) can be in contact with the third capacitor electrode (1430), the third semiconductor pattern (2130), and the sixth semiconductor pattern (2230) through at least one contact hole.

[0099] The first to third connecting electrodes (4710, 4720, 4730) may be adjacent to the first to third anode pads (4610, 4620, 4630) in the second direction (D2) and may be arranged along the first direction (D1).

[0100] The first connecting electrode (4710) may overlap with the first active pattern (2310) and the first gate electrode (3410). Additionally, the first connecting electrode (4710) may contact the first active pattern (2310) and the first gate electrode (3410) through at least one contact hole. The first connecting electrode (4710) may transmit the data voltage (DATA) from the first active pattern (2310) to the first gate electrode (3410).

[0101] Additionally, the second connecting electrode (4720) can contact the second active pattern (2320) and the second gate electrode (3420) through at least one contact hole. The third connecting electrode (4730) can contact the third active pattern (2330) and the third gate electrode (3430) through at least one contact hole.

[0102] The first to third data electrodes (4810, 4820, 4830) may be adjacent to the first to third connection electrodes (4710, 4720, 4730) in the second direction (D2) and may be arranged along the first direction (D1).

[0103] The first data electrode (4810) can contact the second data wiring (1520) and the first active pattern (2310) through at least one contact hole. The first data electrode (4810) can transmit the data voltage (DATA) from the second data wiring (1520) to the first active pattern (2310).

[0104] Additionally, the second data electrode (4820) can contact the first data wiring (1510) and the second active pattern (2320) through at least one contact hole. The third data electrode (4830) can contact the third data wiring (1530) and the third active pattern (2330) through at least one contact hole.

[0105] The third conductive pattern (4000) may include a conductive material. Examples of conductive materials that can be used as the third conductive pattern (4000) include silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, nickel, chromium, chromium nitride, titanium, tantalum, platinum, scandium, indium tin oxide, indium zinc oxide, etc. These may be used alone or in combination with each other. Additionally, the third conductive pattern (4000) may be composed of a single layer or multiple layers.

[0106] Referring to FIGS. 3 to 9, a fourth insulating layer (IL4) is disposed on the third conductive pattern (4000) and can cover the third conductive pattern (4000). The fourth insulating layer (IL4) may include an organic insulating material. Examples of organic insulating materials that can be used as the fourth insulating layer (IL4) include photoresist, polyacrylic resin, polyimide resin, acrylic resin, etc.

[0107] A fourth conductive pattern (5000) may be disposed on the fourth insulating layer (IL4). The fourth conductive pattern (5000) may include a second driving voltage wiring (5100), a second common voltage wiring (5200), a common voltage electrode (5300), a first pixel electrode (5410), a second pixel electrode (5420), and a third pixel electrode (5430).

[0108] The second driving voltage wiring (5100) may be extended in the second direction (D2). The second driving voltage wiring (5100) may overlap with the first driving voltage wiring (1300). For example, the first driving voltage wiring (1300) and the second driving voltage wiring (5100) may have a mesh shape in a plane. Additionally, the second driving voltage wiring (5100) may contact the first driving voltage connecting electrode (4510) through at least one contact hole. Accordingly, the second driving voltage wiring (5100) may transmit the driving voltage (ELVDD) to the first driving voltage wiring (1300).

[0109] In one embodiment, the second driving voltage wiring (5100) may include a first wiring portion (5110) extending in the second direction (D2) and a first branch portion (5120) protruding from the first wiring portion (5110). For example, the first branch portion (5120) may protrude from the first wiring portion (5110) in the first direction (D1), but the present invention is not limited thereto. The first branch portion (5120) may overlap with the second dual electrode (3310) and the first driving voltage connecting electrode (4510). Additionally, the first branch portion (5120) may overlap with the first driving voltage wiring (1300). Specifically, the first branch portion (5120) may contact the first driving voltage connecting electrode (4510) through at least one contact hole. That is, the second driving voltage wiring (5100) can be electrically connected to the first driving voltage wiring (1300) through the first branch (5120).

[0110] The second common voltage wiring (5200) may be spaced apart from the second driving voltage wiring (5100) in the first direction (D1) and may extend in the second direction (D2). The second common voltage wiring (5200) may overlap with the first common voltage wiring (1100). For example, the first common voltage wiring (1100) and the second common voltage wiring (5200) may have a mesh shape on a plane. Additionally, the second common voltage wiring (5200) may contact the common voltage connecting electrode (4300) through at least one contact hole. Accordingly, the second common voltage wiring (5200) may transmit the common voltage (ELVSS) to the first common voltage wiring (1100).

[0111] The second driving voltage wiring (5100) and the second common voltage wiring (5200) can overlap with the first to third data wirings (1510, 1520, 1530).

[0112] In one embodiment, the second common voltage wiring (5200) may include a second wiring portion (5210) extending in the second direction (D2) and a second branch portion (5220) protruding from the second wiring portion (5210). For example, the second branch portion (5220) may protrude from the second wiring portion (5210) in a direction opposite to the first direction (D1), but the present invention is not limited thereto. The second branch portion (5220) may overlap with the first dual electrode (3100) and the common voltage connection electrode (4300). Additionally, the second branch portion (5220) may overlap with the first common voltage wiring (1100). Specifically, the second branch portion (5220) may contact the common voltage connection electrode (4300) through at least one contact hole. That is, the second common voltage wiring (5200) can be electrically connected to the first common voltage wiring (1100) through the second branch (5220).

[0113] In one embodiment, the second driving voltage wiring (5100) and the second common voltage wiring (5200) may be arranged alternately along the first direction (D1). For each of the pixels arranged along the first direction (D1) (e.g., a plurality of pixels (PX) in FIG. 1), one of the wirings of the second driving voltage wiring (5100) and the second common voltage wiring (5200) may be arranged (see FIG. 8).

[0114] In one embodiment, the second scan wiring (4200) may overlap entirely with at least one of the second driving voltage wiring (5100) and the second common voltage wiring (5200). Additionally, the first scan wiring (4100) may not overlap with each of the second driving voltage wiring (5100) and the second common voltage wiring (5200).

[0115] For example, the second scan wiring (4200) included in the pixels (PX) placed in the second n-1 row may overlap with the second driving voltage wiring (5100), and the second scan wiring (4200) included in the pixels (PX) placed in the second n row may overlap with the second common voltage wiring (5200) (where n is a natural number). As another example, the second scan wiring (4200) included in the pixels (PX) placed in the second n-1 row may overlap with the second common voltage wiring (5200), and the second scan wiring (4200) included in the pixels (PX) placed in the second n row may overlap with the second driving voltage wiring (5100) (where n is a natural number).

[0116] The common voltage electrode (5300) may be positioned on a plane between the second driving voltage wiring (5100) and the second common voltage wiring (5200). The common voltage electrode (5300) may overlap with the common voltage connection electrode (4300). Additionally, the common voltage electrode (5300) may contact the common voltage connection electrode (4300) through at least one contact hole. Accordingly, the common voltage (ELVSS) may be provided to the common voltage electrode (5300).

[0117] The first to third pixel electrodes (5410, 5420, 5430) may be disposed on a plane between the second driving voltage wiring (5100) and the second common voltage wiring (5200). The first pixel electrode (5410) may contact the first anode pad (4610) through at least one contact hole. The second pixel electrode (5420) may contact the second anode pad (4620) through at least one contact hole. The third pixel electrode (5430) may contact the third anode pad (4630) through at least one contact hole. The first to third pixel electrodes (5410, 5420, 5430) can each receive the initialization voltage (VINT) or the driving current through the first to third anode pads (4610, 4620, 4630).

[0118] The fourth conductive pattern (5000) may include a conductive material. Examples of conductive materials that can be used as the fourth conductive pattern (5000) include silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, nickel, chromium, chromium nitride, titanium, tantalum, platinum, scandium, indium tin oxide, indium zinc oxide, etc. These may be used alone or in combination with each other. Additionally, the fourth conductive pattern (5000) may be composed of a single layer or multiple layers.

[0119] A pixel defining layer may be disposed on the fourth conductive pattern (5000). The pixel defining layer may define an opening that exposes at least a portion of each of the first to third pixel electrodes (5410, 5420, 5430).

[0120] The light-emitting layer (EL) may be disposed on the first to third pixel electrodes (5410, 5420, 5430) and the pixel defining layer. Specifically, the light-emitting layer (EL) may be disposed on the first to third pixel electrodes (5410, 5420, 5430) each exposed by the opening and may be continuously extended. That is, the light-emitting layer (EL) may be formed entirely on the display panel (PNL) shown in FIG. 1. For example, the light-emitting layer (EL) may have a multilayer structure including a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0121] A common electrode (CE) may be disposed on the light-emitting layer (EL). The common electrode (CE) may be continuously extended. That is, the common electrode (CE) may be formed entirely on the display panel (PNL) shown in FIG. 1. The common electrode (CE) may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. These may be used alone or in combination with each other.

[0122] Each of the first to third pixel electrodes (5410, 5420, 5430) can form a light-emitting layer (EL) and a common electrode (CE) and a light-emitting element (LD).

[0123] In the display device (10) according to one embodiment of the present invention, the second driving voltage wiring (5100) and the second common voltage wiring (5200) may be disposed in the same layer as the first to third pixel electrodes (5410, 5420, 5430). Accordingly, the parasitic capacitance between the second driving voltage wiring (5100) and the second common voltage wiring (5200) and the first to third data wirings (1510, 1520, 1530) may be reduced, and sufficient space for the storage capacitor (CST) may be secured.

[0124] Additionally, the second scan wiring (4200) may overlap with at least one of the second driving voltage wiring (5100) and the second common voltage wiring (5200). By increasing the parasitic capacitance between the second scan wiring (4200) and at least one of the second driving voltage wiring (5100) and the second common voltage wiring (5200), the interval between the first scan signal (SC) and the second scan signal (SS) can be secured.

[0125] FIG. 10 is a block diagram illustrating a display device according to another embodiment of the present invention.

[0126] In the following, descriptions that overlap with the display device (10) described with reference to FIG. 1 are omitted or simplified.

[0127] Referring to FIG. 10, a display device (20) according to another embodiment of the present invention may include the display panel (PNL), the data driving unit (DDV), the scan driving unit (SDV), and the control unit (CON).

[0128] In one embodiment, the first subpixel (SPX1) may receive the data voltage (DATA) through the third data line (1530). The second subpixel (SPX2) may receive the data voltage (DATA) through the first data line (1510). The third subpixel (SPX3) may receive the data voltage (DATA) through the second data line (1520). Additionally, each of the first to third subpixels (SPX1, SPX2, SPX3) may receive the scan signal (SCAN) through the scan line (3100, 3200). However, the present invention is not limited thereto.

[0129] FIGS. 11 to 14 are layout drawings for explaining an example of a pixel included in the display device of FIG. 10. FIG. 15 is a plan view for schematically explaining the display device of FIG. 1, and FIG. 16 is a cross-sectional view taken along the line II-II' of FIG. 14.

[0130] In the following, descriptions that overlap with the display device (10) described with reference to FIGS. 3 to 9 are omitted or simplified.

[0131] Referring to FIGS. 11 and FIGS. 16, the display device (20) may include the substrate (SUB) and the first conductive pattern (1000).

[0132] The first conductive pattern (1000) may be disposed on the substrate (SUB). The first conductive pattern (1000) may include the first common voltage wiring (1100), the initialization voltage wiring (1200), the first driving voltage wiring (1300), the first capacitor electrode (1410), the second capacitor electrode (1420), the third capacitor electrode (1430), the first data wiring (1510), the second data wiring (1520), the third data wiring (1530), the first lower electrode (1610), and the second lower electrode (1620).

[0133] Each of the first and second lower electrodes (1610, 1620) may be positioned on a plane between the first driving voltage wiring (1300) and the first data wiring (1510). Additionally, the second lower electrode (1620) may be spaced apart from the first lower electrode (1610) in the first direction (D1). Specifically, the first lower electrode (1610) may be adjacent to the first capacitor electrode (1410) in the opposite direction to the first direction (D1), and the second lower electrode (1620) may be adjacent to the third capacitor electrode (1430) in the first direction (D1).

[0134] Referring to FIGS. 11, 12 and 16, the first insulating layer (IL1) and the semiconductor pattern (2000) can be sequentially disposed on the first conductive pattern (1000).

[0135] The semiconductor pattern (2000) may include the first semiconductor pattern (2110), the second semiconductor pattern (2120), the third semiconductor pattern (2130), the fourth semiconductor pattern (2210), the fifth semiconductor pattern (2220), the sixth semiconductor pattern (2230), the first active pattern (2310), the second active pattern (2320), and the third active pattern (2330).

[0136] In one embodiment, the first active pattern (2310) may overlap with the first capacitor electrode (1410). For example, the first active pattern (2310) and the first capacitor electrode (1410) may correspond to the first terminal and the second terminal of the storage capacitor included in the first subpixel (SPX1) shown in FIG. 10, respectively. That is, the first capacitor electrode (1410) and the first active pattern (2310) may form the storage capacitor (CST).

[0137] Additionally, the second active pattern (2320) can overlap with the second capacitor electrode (1420) and can form the storage capacitor (CST). The third active pattern (2330) can overlap with the third capacitor electrode (1430) and can form the storage capacitor (CST).

[0138] Referring to FIGS. 12, 13 and 16, the second insulating layer (IL2) and the second conductive pattern (6000) can be sequentially disposed on the semiconductor pattern (2000).

[0139] The second conductive pattern (6000) may overlap entirely with the second insulating layer (IL2). The second conductive pattern (6000) may include a first scan wiring (6100), a second scan wiring (6200), a first auxiliary wiring (6310), a second auxiliary wiring (6320), a common voltage connection electrode (6400), an initial voltage connection electrode (6500), a first driving voltage connection electrode (6610), a second driving voltage connection electrode (6620), a first gate electrode (6710), a second gate electrode (6720), a third gate electrode (6730), a first anode pad (6810), a second anode pad (6820), a third anode pad (6830), a fourth anode pad (6840), a first data electrode (6910), a second data electrode (6920), and a third data electrode (6930).

[0140] The first scan wiring (6100) may be extended in the second direction (D2). In one embodiment, the first scan wiring (6100) may include a first wiring portion (6110) extending in the second direction (D2) and a first branch portion (6120) protruding from the first wiring portion (6110). For example, the first branch portion (6120) may protrude from the first wiring portion (6110) in the first direction (D1).

[0141] The first branch portion (6120) of the first scan wiring (6100) can overlap with the first to third active patterns (2310, 2320, 2330). The first scan wiring (6100) can provide the first scan signal (SC) to the first to third subpixels (SPX1, SPX2, SPX3).

[0142] The second scan wiring (6200) may be spaced apart from the first scan wiring (6100) in the first direction (D1) and may be extended in the second direction (D2). In one embodiment, the second scan wiring (6200) may include a second wiring portion (6210) extending in the second direction (D2) and a second branch portion (6220) protruding from the second wiring portion (6210). For example, the second branch portion (6220) may protrude from the second wiring portion (6210) in the opposite direction of the first direction (D1).

[0143] The second branch portion (6220) of the second scan wiring (6200) can overlap with the first to third semiconductor patterns (2110, 2120, 2130). The second scan wiring (6200) can provide the second scan signal (SS) to the first to third subpixels (SPX1, SPX2, SPX3).

[0144] Each of the first and second auxiliary wires (6310, 6320) may extend in the second direction (D2). The second auxiliary wire (6320) may be spaced apart from the first auxiliary wire (6310) in the first direction (D1). Specifically, the first auxiliary wire (6310) may be adjacent to the first scan wire (6100) in the opposite direction to the first direction (D1), and the second auxiliary wire (6320) may be adjacent to the second scan wire (6200) in the first direction (D1). The first auxiliary wire (6310) may be electrically connected to the first driving voltage wire (1300), and the second auxiliary wire (6320) may be electrically connected to the first common voltage wire (1100).

[0145] The common voltage connection electrode (6400) may be positioned on a plane between the first wiring portion (6110) of the first scan wiring (6100) and the second wiring portion (6210) of the second scan wiring (6200). The common voltage connection electrode (6400) may overlap with the first common voltage wiring (1100). The common voltage connection electrode (6400) may contact the first common voltage wiring (1100) through at least one contact hole.

[0146] The initial voltage connection electrode (6500) may be adjacent to the common voltage connection electrode (6400) in the second direction (D2). The initial voltage connection electrode (6500) may overlap with the initial voltage wiring (1200). The initial voltage connection electrode (6500) may contact the initial voltage wiring (1200) and the first to third semiconductor patterns (2110, 2120, 2130) through at least one contact hole. The initial voltage connection electrode (6500) may transmit the initial voltage (VINT) from the initial voltage wiring (1200) to the first to third semiconductor patterns (2110, 2120, 2130).

[0147] The first and second driving voltage connection electrodes (6610, 6620) may be adjacent to the initialization voltage connection electrode (6500) in the second direction (D2) and may be arranged along the first direction (D1). The first and second driving voltage connection electrodes (6610, 6620) may overlap with the first driving voltage wiring (1300).

[0148] The first driving voltage connecting electrode (6610) can contact the first driving voltage wiring (1300) and the fourth semiconductor pattern (2210) through at least one contact hole. The first driving voltage connecting electrode (6610) can transmit the driving voltage (ELVDD) from the first driving voltage wiring (1300) to the fourth semiconductor pattern (2210).

[0149] Additionally, the second driving voltage connection electrode (6620) can contact the first driving voltage wiring (1300), the fifth semiconductor pattern (2220), and the sixth semiconductor pattern (2230) through at least one contact hole.

[0150] The first to third gate electrodes (6710, 6720, 6730) may be adjacent to the first and second driving voltage connection electrodes (6610, 6620) in the second direction (D2) and may be arranged along the first direction (D1).

[0151] The first gate electrode (6710) can be electrically connected to the first active pattern (2310) and can overlap with the fourth semiconductor pattern (2210). The second gate electrode (6720) can be electrically connected to the second active pattern (2320) and can overlap with the fifth semiconductor pattern (2220). The third gate electrode (6730) can be electrically connected to the third active pattern (2330) and can overlap with the sixth semiconductor pattern (2230).

[0152] The first to third anode pads (6810, 6820, 6830) may be adjacent to the first and second driving voltage connection electrodes (6610, 6620) in the second direction (D2) and may be arranged along the first direction (D1). The fourth anode pad (6840) may be adjacent to the first anode pad (6810) in the second direction (D2).

[0153] The first anode pad (6810) can be in contact with the first semiconductor pattern (2110) and the fourth semiconductor pattern (2210) through at least one contact hole. The fourth anode pad (6840) can be in contact with the first capacitor electrode (1410) through at least one contact hole. The first and fourth anode pads (6810, 6840) can transmit the initialization voltage (VINT) from the first semiconductor pattern (2110) to the first capacitor electrode (1410).

[0154] Additionally, the second anode pad (6820) can be in contact with the second capacitor electrode (1420), the second semiconductor pattern (2120), and the fifth semiconductor pattern (2220) through at least one contact hole. The third anode pad (6830) can be in contact with the third capacitor electrode (1430), the third semiconductor pattern (2130), and the sixth semiconductor pattern (2230) through at least one contact hole.

[0155] The first to third data electrodes (6910, 6920, 6930) may be adjacent to the first to third anode pads (6810, 6820, 6830) in the second direction (D2) and may be arranged along the first direction (D1).

[0156] The first data electrode (6910) can contact the third data wiring (1530) and the first active pattern (2310) through at least one contact hole. The first data electrode (6910) can transmit the data voltage (DATA) from the third data wiring (1530) to the first active pattern (2310).

[0157] Additionally, the second data electrode (6920) can contact the first data wiring (1510) and the second active pattern (2320) through at least one contact hole. The third data electrode (6930) can contact the second data wiring (1520) and the third active pattern (2330) through at least one contact hole.

[0158] Referring to FIGS. 11 through 16, the third insulating layer (IL3), the fourth insulating layer (IL4), and the third conductive pattern (7000) may be sequentially arranged on the second conductive pattern (6000). In one embodiment, the third insulating layer (IL3) may be omitted.

[0159] The above third conduction pattern (7000) may include a second driving voltage wiring (7100), a second common voltage wiring (7200), a common voltage electrode (7300), a first pixel electrode (7410), a second pixel electrode (7420), and a third pixel electrode (7430).

[0160] The second driving voltage wiring (7100) may be extended in the second direction (D2). The second driving voltage wiring (7100) may overlap with the first driving voltage wiring (1300). In one embodiment, the second driving voltage wiring (7100) may include a first wiring portion (7110) extending in the second direction (D2) and a first branch portion (7120) protruding from the first wiring portion (7110). For example, the first branch portion (7120) may protrude from the first wiring portion (7110) in the first direction (D1), but the present invention is not limited thereto. The second driving voltage wiring (7100) may be electrically connected to the first driving voltage wiring (1300) through the first branch portion (7120).

[0161] The second common voltage wiring (7200) may be spaced apart from the second driving voltage wiring (7100) in the first direction (D1) and may be extended in the second direction (D2). The second common voltage wiring (7200) may be electrically connected to the first common voltage wiring (1100).

[0162] In one embodiment, the second driving voltage wiring (7100) and the second common voltage wiring (7200) may be arranged alternately along the first direction (D1) (see FIG. 15).

[0163] In one embodiment, the second scan wiring (6200) may overlap entirely with at least one of the second driving voltage wiring (7100) and the second common voltage wiring (7200). Additionally, the first scan wiring (6100) may not overlap with each of the second driving voltage wiring (7100) and the second common voltage wiring (7200).

[0164] For example, the second scan wiring (6200) included in the pixels (PX) placed in the second n-1 row may overlap with the second driving voltage wiring (7100), and the second scan wiring (6200) included in the pixels (PX) placed in the second n row may overlap with the second common voltage wiring (7200) (where n is a natural number). As another example, the second scan wiring (6200) included in the pixels (PX) placed in the second n-1 row may overlap with the second common voltage wiring (7200), and the second scan wiring (6200) included in the pixels (PX) placed in the second n row may overlap with the second driving voltage wiring (7100) (where n is a natural number).

[0165] The common voltage electrode (7300) may be positioned on a plane between the second driving voltage wiring (7100) and the second common voltage wiring (7200). The common voltage electrode (7300) may contact the common voltage connecting electrode (6400) through at least one contact hole.

[0166] The first to third pixel electrodes (7410, 7420, 7430) may be disposed on a plane between the second driving voltage wiring (7100) and the second common voltage wiring (7200). The first pixel electrode (7410) may contact the fourth anode pad (6840) through at least one contact hole. The second pixel electrode (7420) may contact the second anode pad (6820) through at least one contact hole. The third pixel electrode (7430) may contact the third anode pad (6830) through at least one contact hole.

[0167] The pixel defining layer, the light-emitting layer (EL), and the common electrode (CE) may be sequentially arranged on the third conductive pattern (7000). Each of the first to third pixel electrodes (7410, 7420, 7430) may form the light-emitting layer (EL) and the common electrode (CE) and the light-emitting element (LD).

[0168] In the display device (20) according to another embodiment of the present invention, the second driving voltage wiring (7100) and the second common voltage wiring (7200) may be placed in the same layer as the first to third pixel electrodes (7410, 7420, 7430). Accordingly, the parasitic capacitance between the second driving voltage wiring (7100) and the second common voltage wiring (7200) and the first to third data wirings (1510, 1520, 1530) may be reduced, and sufficient space for the storage capacitor (CST) may be secured.

[0169] Additionally, the second scan wiring (6200) may overlap with at least one of the second driving voltage wiring (7100) and the second common voltage wiring (7200). By increasing the parasitic capacitance between the second scan wiring (6200) and at least one of the second driving voltage wiring (7100) and the second common voltage wiring (7200), the interval between the first scan signal (SC) and the second scan signal (SS) can be secured. Industrial applicability

[0170] The present invention may be applied to display devices and electronic devices including the same. For example, the present invention may be applied to high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0171] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Explanation of the symbols

[0172] 10, 20: Display device D1: First direction D2: Second direction 1100: First common voltage wiring 1300: First driving voltage wiring 1510, 1520, 1530: Data wiring 4100, 6100: 1st scan wiring 4200, 6200: 2nd scan wiring 5100, 7100: Second driving voltage wiring 5200, 7200: Second common voltage wiring 5410, 5420, 5430, 7410, 7420, 7430: Pixel electrodes

Claims

Claim 1 A display device comprising: a substrate; a first conductive layer disposed on the substrate and including a data line extending in a first direction; a second conductive layer disposed on the first conductive layer and including a first scan line extending in a second direction intersecting the first direction and a second scan line extending in the second direction spaced apart from the first scan line; and a third conductive layer disposed on the second conductive layer and including a first driving voltage line extending in the second direction, a first common voltage line extending in the second direction spaced apart from the first driving voltage line, and a pixel electrode disposed between the first driving voltage line and the first common voltage line on a plane. Claim 2 A display device according to claim 1, characterized in that the second scan wiring overlaps with at least one of the first driving voltage wiring and the first common voltage wiring on a plane. Claim 3 A display device according to claim 1, characterized in that the first scan wiring does not overlap with the first driving voltage wiring and the first common voltage wiring, respectively, on a plane. Claim 4 A display device according to claim 1, characterized in that the first driving voltage wiring and the first common voltage wiring are alternately arranged along the first direction. Claim 5 A display device according to claim 1, wherein the first conductive layer further comprises: a second common voltage line extending in the first direction; and a second driving voltage line adjacent to the second common voltage line in the second direction and extending in the first direction. Claim 6 A display device according to claim 5, characterized in that the first driving voltage wiring is electrically connected to the second driving voltage wiring, and the first common voltage wiring is electrically connected to the second common voltage wiring. Claim 7 A display device according to claim 6, wherein the first driving voltage wiring comprises a first wiring portion extending in the second direction and a first branch portion protruding in the first direction from the first wiring portion. Claim 8 A display device according to claim 7, wherein the first branch portion overlaps with the second driving voltage wiring on a plane, and the first driving voltage wiring is electrically connected to the second driving voltage wiring through the first branch portion. Claim 9 A display device according to claim 6, wherein the first common voltage wiring comprises a second wiring portion extending in the second direction and a second branch portion protruding from the second wiring portion in a direction opposite to the first direction. Claim 10 A display device according to claim 9, characterized in that the second branch portion overlaps with the second common voltage wiring on a plane, and the first common voltage wiring is electrically connected to the second common voltage wiring through the second branch portion. Claim 11 A display device according to claim 1, wherein the first conductive layer further comprises a capacitor electrode. Claim 12 A display device according to claim 11, further comprising a gate conductive layer disposed between the first conductive layer and the second conductive layer, wherein the gate conductive layer comprises a first gate wiring extending in the first direction and a second gate wiring extending in the first direction spaced apart from the first gate wiring. Claim 13 A display device according to claim 12, characterized in that the first gate wiring is electrically connected to the first scan wiring, and the second gate wiring is electrically connected to the second scan wiring. Claim 14 A display device according to claim 12, wherein the gate conductive layer further comprises a gate electrode that overlaps with the capacitor electrode on a plane, and the gate electrode together with the capacitor electrode constitutes a storage capacitor. Claim 15 A display device according to claim 14, further comprising an active layer disposed between the first conductive layer and the gate conductive layer, wherein the active layer comprises an active pattern that overlaps with the first gate wiring on a plane and is electrically connected to the gate electrode. Claim 16 A display device according to claim 15, wherein the second conductive layer further comprises a data electrode, and the data electrode electrically connects the active pattern and the data wiring. Claim 17 A display device according to claim 11, wherein the first scan wiring comprises a first wiring portion extending in the second direction and a first branch portion protruding in the first direction from the first wiring portion. Claim 18 A display device according to claim 17, further comprising an active layer disposed between the first conductive layer and the second conductive layer, wherein the active layer comprises an active pattern that overlaps the capacitor electrode and the first branch portion of the first scan wiring on a plane, and wherein the active pattern constitutes a storage capacitor together with the capacitor electrode. Claim 19 A display device according to claim 11, wherein the second scan wiring comprises a second wiring portion extending in the second direction and a second branch portion protruding in the opposite direction from the second wiring portion in the first direction. Claim 20 A display device according to claim 1, characterized in that the data wiring overlaps the first driving voltage wiring and the first common voltage wiring on a plane.

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