Semiconductor package

Abstract

The present disclosure relates to an RF semiconductor package, specifically comprising: a plate for heat dissipation; an intermediate layer bonded to the plate, comprising a cavity formed through in a vertical direction or formed indented downward from the upper surface of the intermediate layer; a substrate bonded to the intermediate layer, wherein the cavity is extended from the lower surface of the substrate to the upper surface of the substrate; at least one semiconductor device mounted at a position surrounded by the cavity; at least one gate terminal and at least one drain terminal formed on the substrate and electrically connected to each of the semiconductor devices; upper surface terminals formed on the substrate; and a land portion formed between at least one of the gate terminal and the drain terminal and one of the upper surface terminals.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, specifically to a Radio Frequency (RF) semiconductor package, and more specifically to an RF semiconductor package having a lead-less package structure that can be electrically connected to an external circuit through terminals without external leads. The semiconductor package of the present invention includes a plate material for heat dissipation, an intermediate layer, a cavity, and a substrate to efficiently dissipate heat from a semiconductor device, and mounts a matching device capable of adjusting matching characteristics by frequency band through a gate terminal, a drain terminal, a top surface terminal, and a land portion formed on the substrate. Furthermore, the present invention minimizes distortion and loss of high-frequency signals by shortening the heat dissipation path within the semiconductor package and optimizing the structure of the plate material, the intermediate layer, and the substrate to accommodate various matching circuit configurations. Background Technology

[0002] In broadcasting systems, satellite communication systems, and mobile communication base station equipment, it is essential to stably amplify signals within the high-frequency band. Consequently, the heat dissipation performance and circuit matching characteristics of the RF semiconductor packages used for this purpose have been recognized as critical factors determining the overall reliability and efficiency of the system. Since RF amplifiers generate significant heat within their active components during the process of amplifying input signals and outputting them, failure to effectively dissipate this heat leads to instability in the electrical characteristics of the components and a shortened lifespan. Furthermore, as semiconductor devices are sensitive to the external environment, packaging technology that simultaneously ensures electrical protection and mechanical stability is also required.

[0003] Conventional RF semiconductor package structures primarily employ a method of transferring heat to the outside by joining a heat sink and a substrate through processes such as brazing or soldering. For example, Korean Registered Patent No. 10-1995229 discloses a structure in which a semiconductor device is mounted on a metal heat sink and a ceramic substrate is joined to simultaneously perform electrical connection and heat dissipation. However, this structure had the problem of significant thermal resistance occurring at the junction between the heat sink and the substrate, and the matching characteristics of the amplification device degrading due to processing tolerances associated with the brazing process. Furthermore, since a separate external matching circuit must be configured for impedance matching in the high-frequency band, there were limitations on miniaturization of the package and band extension design.

[0004] To solve these problems, the present invention proposes an RF semiconductor package that improves heat dissipation efficiency by shortening the heat dissipation path through the integral configuration of a substrate including a heat dissipation plate, an intermediate layer, and a cavity structure, while allowing for internal adjustment of matching characteristics by frequency band by forming a gate terminal, a drain terminal, an upper surface terminal, and a land portion on the upper surface of the substrate to easily mount a matching device. As a result, the complexity and processing error of the brazing process are reduced, and at the same time, loss and distortion of high-frequency signals are minimized, thereby ensuring stable amplification characteristics.

[0005] Furthermore, according to the present invention, the substrate and intermediate layer can be fabricated from different materials as needed, thereby increasing the degree of freedom in circuit design through various combinations of dielectric constant and thermal conductivity, and enabling the optimization of RF packages tailored to various frequency bands and output conditions. Consequently, the present invention provides an RF semiconductor package structure capable of achieving high performance, miniaturization, and low cost by simultaneously overcoming the heat dissipation limitations of the prior art and the external dependence of the matching circuit. Prior art literature

[0006] (Patent Document 0001) KR 10-1995229 B The problem to be solved

[0007] The present invention aims to solve the problems of reduced heat dissipation efficiency, complexity of the manufacturing process, external dependence of the matching circuit, and performance degradation in the high-frequency band that occur in conventional RF semiconductor packages. In the structure of the prior art, the heat sink and the substrate are joined together by brazing or soldering, which results in a long heat dissipation path and an increase in thermal resistance at the junction, leading to the disadvantage that heat generated by the amplification device is not effectively dissipated. Furthermore, high-precision machining and the use of expensive alloy materials for joining the heat sink and the substrate increase manufacturing costs, and there were also problems where signal matching characteristics became unstable due to machining tolerances.

[0008] In addition, conventional RF semiconductor packages had to mount components for impedance matching by frequency band on an external circuit board, which imposed many constraints on circuit design and made it difficult to adjust performance in various frequency environments. This acted as a limitation on package miniaturization and multi-frequency design.

[0009] To solve these problems, the present invention aims to improve heat dissipation efficiency by shortening the heat dissipation path through the adoption of a substrate structure including a plate material, an intermediate layer, and a cavity for heat dissipation in an RF semiconductor package, and to enable the internal implementation of matching characteristics for each frequency band by forming a gate terminal, a drain terminal, an upper surface terminal, and a land portion on the substrate so that a matching device can be directly mounted.

[0010] In addition, the present invention aims to enable various combinations of the material, thickness, and dielectric constant of the substrate and intermediate layer in an RF semiconductor package, thereby achieving stable and efficient signal amplification within the high-frequency band, while simplifying the manufacturing process and increasing the freedom of design changes. means of solving the problem

[0011] The characteristic configuration of the present invention for achieving the objectives of the present invention as described above and realizing the characteristic effects of the present invention described below is as follows.

[0012] A semiconductor package according to one aspect of the present disclosure is provided, the semiconductor package comprising: a plate for heat dissipation; an intermediate layer bonded to the plate, the intermediate layer comprising a cavity formed through in a vertical direction or formed indented downward from the upper surface of the intermediate layer; a substrate bonded to the intermediate layer, the substrate having the cavity extended from the lower surface of the substrate to the upper surface of the substrate; at least one semiconductor device mounted at a position surrounded by the cavity; at least one gate terminal and at least one drain terminal formed on the substrate and electrically connected to each of the semiconductor devices; upper surface terminals formed on the substrate; and a land portion formed between at least one of the gate terminal and the drain terminal and one of the upper surface terminals.

[0013] The electrical connection between the semiconductor device and the gate terminal and between the semiconductor device and the drain terminal may be formed by wire bonding or ribbon bonding.

[0014] Preferably, the intermediate layer further includes vias formed through in the vertical direction, and each of the upper surface terminals is electrically connected to each of the vias.

[0015] Advantageously, each of the gate terminals is electrically connected to at least one of the terminals of the semiconductor device on one side in the width direction of the cavity, and each of the drain terminals is electrically connected to at least one of the terminals of the semiconductor device on the other side in the width direction of the cavity.

[0016] According to an embodiment, at least one of the upper surface terminals may be an RF signal terminal and at least one of the upper surface terminals may be a DC power terminal, or at least one of the upper surface terminals may be a terminal configured to transmit RF signal and DC power in common.

[0017] Preferably, the plate includes lower surface terminals for connection with the outside, and the lower surface terminals are electrically connected to the upper surface terminals through the vias.

[0018] Preferably, the land portion includes a gate-side land portion formed between each of the gate terminals and each of the upper surface terminals, and a drain-side land portion formed between each of the drain terminals and each of the upper surface terminals.

[0019] More preferably, the land portion comprises at least one intermediate row land formed to be electrically isolated from each other at a distance, and at least one side row land formed to be electrically isolated from each other at a distance from each of the intermediate row lands in at least one direction of both sides of the intermediate row land.

[0020] More preferably, the gate-side land portion may include at least one gate-side intermediate row land formed to be electrically isolated from each other and spaced apart in the width direction of the cavity within each gate-side insulating portion surrounding one or more of the gate terminals and one or more of the upper surface terminals on the plane of the upper surface of the substrate, and at least one gate-side row land formed to be electrically isolated from each other and spaced apart from each of the gate-side intermediate row lands in at least one of the length directions of the cavity relative to the gate-side intermediate row land, and likewise, the drain-side land portion may include at least one drain-side intermediate row land formed to be electrically isolated from each other and spaced apart in the width direction of the cavity within each drain-side insulating portion surrounding one or more of the drain terminals and one or more of the upper surface terminals on the plane of the upper surface of the substrate, and at least one It may include drain-side side columns and lands.

[0021] Here, at least one of the gate-side insulating portion and the drain-side insulating portion may be formed of a material having a dielectric constant different from the dielectric constant of the substrate.

[0022] In one embodiment, the passive element includes a chip capacitor, and a plurality of chip capacitors having different capacities are mounted on two or more of the land portions.

[0023] In one embodiment, the semiconductor package further includes a matching circuit formed on the substrate through the land portion, and a matching circuit comprising a passive element seated on the land portion.

[0024] Advantageously, the matching circuit may include a capacitor for blocking the DC component.

[0025] Preferably, the matching circuit may be electrically connected to an external feedback circuit through wiring formed on the plate or substrate.

[0026] The semiconductor package according to the present invention can be configured to implement different matching characteristics for RF signals of different frequency bands through a combination of the semiconductor device and the matching circuit. Effects of the invention

[0027] According to the RF semiconductor package of the present invention, by integrating a plate material for heat dissipation, an intermediate layer, and a cavity structure, the heat dissipation path is shortened and thermal resistance is reduced, thereby enabling efficient dissipation of heat generated from a semiconductor device, such as an amplifier, and thus improving its reliability and lifespan.

[0028] In addition, according to the present invention, the via structure of the intermediate layer and the upper and lower terminals of the substrate are electrically connected, thereby increasing the stability of current flow and improving electrical connection along with heat dissipation.

[0029] According to the present invention, a matching element can be directly mounted through a gate terminal, a drain terminal, an upper terminal, and a land portion formed on a substrate, thereby enabling impedance matching by frequency band within the package, which has the effect of minimizing distortion and loss even in the high frequency band.

[0030] Meanwhile, according to one embodiment of the present invention, a plurality of chip capacitors having different capacities can be mounted on two or more of the gate-side and drain-side land portions, so that various frequency bands and output conditions can be accommodated, and frequency-specific matching characteristics can be adjusted within the same package.

[0031] Specifically, according to the present invention, the matching circuit can be directly formed on the substrate through the land portion, making design changes easy. Furthermore, by adjusting the values ​​of components such as capacitors and inductors constituting the matching circuit, performance optimization tailored to various RF environments is possible. Additionally, since the dielectric constant and thermal conductivity can be combined in various ways depending on the selection of the plate and substrate materials, the degree of freedom in circuit design is increased, and the limitations of high dielectric constant ceramic substrates are overcome, thereby providing stable and efficient signal amplification even within the high-frequency band.

[0032] Therefore, according to the present invention, there is an advantage of achieving a combination of effects such as improved heat dissipation efficiency, simplified manufacturing process, cost reduction, diversification of frequency matching, stabilization of high-frequency characteristics, and improved reliability of the package. Brief explanation of the drawing

[0033] For the purpose of understanding the present invention, embodiments will be described with reference to the accompanying drawings to illustrate the semiconductor package structure shown in this disclosure. These are merely non-limiting examples, and it is obvious that a person skilled in the art to which this disclosure pertains (hereinafter referred to as "person skilled in the art") can obtain other drawings based on these drawings without further effort to arrive at another invention. FIG. 1 is a perspective view of a semiconductor package according to one embodiment of the present invention, showing a state in which a matching circuit is not configured. FIG. 2 is an exemplary drawing showing the semiconductor package illustrated in FIG. 1 separated by layer. Figure 3 is a plan view of the semiconductor package shown in Figure 1. Figure 4 is a conceptual side perspective view of the semiconductor package illustrated in Figure 1. FIG. 5 is a conceptual plan view showing a matching circuit mounted on a semiconductor package illustrated in FIG. 1. FIG. 6 is a plan view of a semiconductor package according to another embodiment of the present invention. Specific details for implementing the invention

[0034] All prior art cited in this disclosure is incorporated by reference in its entirety as if fully presented in this disclosure. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art.

[0035] The following detailed description regarding the principles of construction of a semiconductor package according to the present disclosure refers to the accompanying drawings, which illustrate specific embodiments in which the present invention can be implemented in order to clarify the objects, technical solutions, and advantages of the invention as set forth in the present disclosure. In the description with reference to the accompanying drawings, identical components are given the same reference numerals regardless of the drawing symbols, and redundant descriptions thereof are omitted. It will be understood that the structure of the semiconductor package according to the present disclosure does not have length ratios as shown in the drawings, and that the dimensions of each part of the drawings are shown merely for illustrative purposes and do not limit the scope of the present invention.

[0036] Furthermore, while terms such as "first" or "second" may be used to describe various components, these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression, and vice versa, unless the context clearly indicates otherwise.

[0037] The term "terminal" as used in this disclosure refers to a conductive structure provided for the transmission of electrical signals, such as signal input / output between elements, and includes, but is not limited to, terminals made of metals such as copper, silver, and gold, i.e., metal terminals. For example, a terminal may correspond to a metal part printed on a layer, or a metal part formed to be embedded within a layer. For example, the thickness of such a metal part may be 0.005 millimeters to 0.1 millimeters.

[0038] Furthermore, the term "electrical connection" as used in this disclosure refers to a material, substance, or component that electrically connects components, including, but not limited to, bonding wires. For example, unless the context clearly indicates otherwise, "electrical connection" in this disclosure may be understood as wiring or connecting lines (e.g., which may be printed on a PCB), wires (e.g., which may be used for wire bonding), etc.

[0039] The term "formation" as used in this disclosure includes, but is not limited to, additionally forming or simultaneously forming a part at the location of the formation, as well as separately making and integrating.

[0040] Furthermore, the present invention encompasses all possible combinations of the embodiments shown herein. It should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in relation to one embodiment. The shapes depicted in the drawings are conceptual and are not intended to limit the scope of the invention by defining the exact shapes of structures or regions. For example, regions depicted as rectangular, square, etc., in the drawings may often be tapered, curved, or rounded.

[0041] FIG. 1 is a perspective view of a semiconductor package (100) according to an embodiment of the present invention, showing a state in which a matching circuit is not formed and a cover is not fastened; FIG. 2 is an exemplary drawing showing the semiconductor package shown in FIG. 1 separated by layer; FIG. 3 is a plan view of the semiconductor package shown in FIG. 1.

[0042] Referring to FIGS. 1 to 3, a stacked structure of a plate (110) for heat dissipation, an intermediate layer (120) bonded on the plate (110), and a substrate (130) bonded on the intermediate layer (120), and a gate terminal (141), drain terminal (142), upper surface terminal (133), and a land portion (150) for mounting a matching element on the substrate (130) are schematically shown.

[0043] FIGS. 1 and 2 illustrate a configuration in which a cavity (121) formed vertically through the interior of an intermediate layer (120), vias (122) formed through both sides in the width direction of the cavity (121), and a lower surface terminal (111) formed on a plate (110) and an upper surface terminal (133) on a substrate (130) are electrically connected through the vias (122). Each of the upper surface terminals can be electrically connected to each of the vias.

[0044] A semiconductor package (100) according to the present invention includes a plate (110) for securing heat dissipation efficiency, an intermediate layer (120) interposed between the plate (110) and a substrate (130), and a substrate (130) bonded on the intermediate layer (120).

[0045] In one embodiment, the plate (110) may include copper, copper alloy, aluminum, molybdenum, etc., but is not limited thereto. For example, the plate (110) may have a thickness of 0.2 to 2.0 millimeters, and for example, may have a thickness of 0.3 millimeters.

[0046] The intermediate layer (120) performs the function of bonding the substrate (130) and the plate (110) together.

[0047] In one embodiment, the intermediate layer (120) may be composed of an insulating resin layer made of an insulating material, such as an insulating layer formed by applying a paste, or may be composed of a prepreg (PP) layer, i.e., in the form of a sheet such as prepreg, or may include a metal plating layer. For example, the intermediate layer (120) may have a thickness of 0.1 to 0.5 millimeters, and for example, may have a thickness of 0.3 millimeters.

[0048] A cavity (121) formed through the intermediate layer (120) in a vertical direction is provided. Alternatively, by processing or molding the cavity (121) downward from the upper surface of the intermediate layer (120), i.e., toward the proximal end of the plate (110), it is also possible to form an indentation that does not completely penetrate to the lower surface of the intermediate layer (120). Depending on the thickness of the package or the frequency band to be applied, the depth and method of forming the cavity (121) can be selectively adjusted.

[0049] Meanwhile, vias (122) are formed through the intermediate layer (120). Although the drawing illustrates vias formed on both sides in the width direction of the cavity (121), the formation location of vias (122) is not limited thereto, and it is obvious that vias (122) can also be formed through both sides in the length direction, for example.

[0050] In a semiconductor package (100), since vias function as thermal paths that divert heat downward along with electrical connections, a method of arranging multiple vias in an array and designing the upper and lower copper layers thickly is known. For example, it is also possible to arrange multiple vias with a diameter of 0.1 to 0.5 millimeters for vias that function as thermal paths. Each of the vias (122) can be formed to electrically and thermally interconnect the plate (110) and the substrate (130) through a metal plating layer.

[0051] Meanwhile, separate from the vias (122), one or more non-conductive holes for heat dissipation or grounding may be formed in the substrate (130), intermediate layer (120), and plate (110), as shown in FIG. 2.

[0052] At least one of the intermediate layer (120) and the substrate (130) can be adjusted in terms of material and thickness according to the required RF characteristics.

[0053] Preferably, the substrate (130) may be formed of a printed circuit board (PCB), such as a metal PCB. For example, the substrate (130) may have a thickness of 5 to 50 mils, and for example, may have a thickness of 20 mils. Of course, a person skilled in the art will understand that the composition and dimensions of such plates, intermediate layers, and substrates are exemplary and may be configured in various ways within the scope of protection of the present invention.

[0054] It is known to those skilled in the art that a solder mask layer (PSR) can be formed on the upper surface of the substrate (130). Here, the PSR restricts solder flow to prevent bridging, but a process such as SMOBC (solder mask over bare copper) may be performed around the RF pad to avoid the phenomenon where the solder mask seeps into the solder joint and flows again.

[0055] As in the intermediate layer (120), a cavity (121) is extended and formed in the substrate (130), and the cavity (121) penetrates from the upper surface of the substrate (130) to the lower surface of the substrate (130).

[0056] At least one semiconductor device (140) is mounted on the bottom surface of the cavity (121) at a location surrounded by the cavity (121). For example, when the intermediate layer (120) completely penetrates to the plate (110), the semiconductor device (140) is mounted on the plate (110). Preferably, the cavity (121) formed in the substrate (130) and the intermediate layer (120) has a depth greater than the height of the semiconductor device (140). For example, the semiconductor device may be an amplification device, but is not limited thereto.

[0057] Since the semiconductor device (140) may not be visible from the side of the package (100) due to being obscured by the substrate (130) and the intermediate layer (120), FIG. 4 is a side view of the semiconductor package and conceptually illustrates the arrangement of the semiconductor device (140) mounted inside the cavity (121), and the gate terminal (141) and drain terminal (142) electrically connected to the semiconductor device (140).

[0058] The semiconductor device (140) may be a transistor-based device, for example, and may include FET, GaN HEMT, LDMOS, etc. The electrical connection part (143) that electrically connects the semiconductor device (140) and the gate terminal (141) and drain terminal (142) on the substrate (130) may be formed by wire bonding, and the number of wires may be multiple. Of course, although the electrical connection part (143) is illustrated as wire bonding in FIG. 4, it is not limited thereto, and other types of electrical connection parts such as ribbon bonding may be used.

[0059] The present invention can be implemented in a non-molding manner that does not apply the plastic molding process used in general DFN packages by applying a cavity (121) structure. That is, since the semiconductor device (140) is placed inside the cavity (121) and is not covered by a molding layer, a separate resin encapsulation process for forming the outer edge of the package is not required, and there is an advantage in that the increase in dielectric loss or fluctuation of parasitic components that may be caused by the plastic molding layer in the high-frequency band is suppressed. In addition, heat generated from the semiconductor device (140) is transferred upward through the air layer formed by the cavity (121) and can be released to the outside through a cover that is fastened as needed, so there is also an effect of improving the heat dissipation performance of the semiconductor device (140).

[0060] In addition, the via (122) hole structure serves to shorten the electrical and thermal path between the substrate (130) and the plate (110), thereby simultaneously improving the stability of current flow and the efficiency of heat dissipation. The arrangement of these vias (122) can function as a heat passage that quickly diverts heat generated during operation toward the lower plate (110).

[0061] Additionally, if necessary, a cover may be attached to the upper part of the substrate (130) to seal the interior of the cavity (121) and a portion of the matching circuit (160; not shown). The material of the cover may include plastic, ceramic, metal, PCB, etc. A person skilled in the art can easily envision the cover to be attached to the upper part of the semiconductor package (100) by referring to prior art. For example, if the cover is formed concavely upward to have an internal space, an additional space continuous with the cavity (121) is secured, allowing heat to be smoothly transferred to the upper space without causing physical interference to the semiconductor device (140), thereby further improving heat dissipation performance.

[0062] A land portion (150) for mounting a matching element is formed on the substrate (130) as illustrated in FIG. 3. Each land included in the land portion (150) is a terminal configured to allow passive elements to be mounted, and may be formed in a rectangular shape, but is not limited to a specific shape.

[0063] In one embodiment illustrated in FIG. 3, the land portion (150) may include a gate-side land portion (151a) disposed between the gate terminal (141) and the upper terminal (133), and a drain-side land portion (151b) disposed between the drain terminal (142) and the upper terminal (133). FIG. 3 is illustrated exemplarily as having the gate-side land portion (151a) composed of three lines in the width direction and the drain-side land portion (151b) composed of one line in the width direction, but is not limited thereto and the number of lines may vary depending on the band of the target frequency.

[0064] For example, in a band of 3 GHz or higher, it is preferable that the number of lines in the gate-side land portion is greater than the number of lines in the drain-side land portion.

[0065] An insulating region surrounding the corresponding terminals on the upper plane of the substrate (130) may be provided around each land portion (151a, 151b), and a gate-side insulating portion (152a) may be formed corresponding to each gate terminal (141), and a drain-side insulating portion (152b) may be formed corresponding to each drain terminal (142).

[0066] The gate-side insulating portion (152a) and the drain-side insulating portion (152b) may each be formed as a closed curve surrounding one of the corresponding terminals and one of the upper surface terminals (133), having a thickness that is constant or non-constant on a plane. Additionally, if necessary, at least one of the gate-side insulating portion (152a) and the drain-side insulating portion (152b) may be formed of a material having a dielectric constant different from the dielectric constant of the substrate (130).

[0067] The above insulating sections serve not only as electrical insulation but also as separation spaces for RF impedance matching. In particular, by adjusting the combination of the width and thickness of the insulating sections and the dielectric constant of the insulating material used, they can be designed to maintain a matching impedance of approximately 50 Ω. In this way, the insulating region also performs the function of minimizing reflection losses in the high-frequency band by controlling the distribution of the electromagnetic field around the RF signal path.

[0068] The land portion (150) may be configured to include intermediate row lands formed to be electrically isolated from each other and spaced apart in the width direction of the cavity (121), namely, a gate-side intermediate row land (153a) and a drain-side intermediate row land (153b), and side row lands formed to be electrically isolated from each other and spaced apart in at least one of the two sides in the length direction of the cavity (121) with respect to the intermediate row lands, namely, a gate-side side row land (154a) and a drain-side side row land (154b). That is, for each intermediate row land, the corresponding side row land may be formed on both sides as exemplified in FIG. 3, or, contrary to the example, may be formed on only one of the two sides. Such 'one side' does not need to be in the same direction (i.e., it does not need to be uniformly in the upward or downward direction based on the drawing).

[0069] A circuit pattern may be formed to selectively connect at least one of the following: between at least one of the gate-side intermediate row lands (153a) and at least one of the gate-side row lands (154a), and between at least one of the drain-side intermediate row lands (153b) and at least one of the drain-side row lands (154b).

[0070] The matching circuit portion (160) is formed on the substrate (130) through the land portion (150), and includes a passive element for impedance matching.

[0071] FIG. 5 is a conceptual plan view showing a matching circuit portion (160; 161 to 169) mounted on a semiconductor package according to one embodiment of the present invention, wherein FIG. 5 illustrates the arrangement of a component mounted on a land portion (150) with solid lines.

[0072] Reference numerals 161 to 169 refer to passive components for impedance matching, such as capacitors, inductors, resistors, etc. Passive components can be mounted as single components using two lands, or, if necessary, configured to mount components such as single-layer ceramic capacitors (SLCC) using multiple lands, such as nine lands. Pads configured with multiple lands in this way are advantageous for increasing heat dissipation and current capacity, and for optimizing ESR (equivalent series resistance) and ESL (equivalent series inductance) characteristics.

[0073] According to the configuration of the above land portion, impedance matching can be achieved by selectively mounting passive components of various values, and each land portion can be configured to mount chip capacitors having different passive component values. In addition, design freedom for impedance adjustment can be secured by changing the pattern of the above land portion.

[0074] In addition, this configuration has the advantage of enabling cost reduction and ensuring diversity in internal matching through the selective mounting of various passive components. That is, since the capacitance of the capacitor used for matching can be directly adjusted within the semiconductor package of the present invention, not only can costs incurred during the matching process be reduced, but optimized matching characteristics for various frequency bands can also be provided.

[0075] In one embodiment, the matching circuit (160) may include a passive component such as a capacitor for blocking DC components, and the impedance matching circuit is a network that minimizes reflection loss and optimizes gain and efficiency by matching the input and output impedances of the component to a target impedance such as 50 Ω of the transmission line, and may be implemented, for example, as an L, Π, or T type topology or transmission line segmentation, and it is known to a person skilled in the art that the DC blocking capacitor stabilizes the operating point by separating the bias and RF signal paths.

[0076] The matching circuit portion (160) according to the present invention may be designed to cooperate with a circuit outside the substrate, such as a feedback circuit, as needed. Wiring and / or external terminals (not shown) for this purpose may be formed within the plate material (110) or within the substrate (130), and the matching circuit portion (160) may be electrically connected to an external feedback circuit through this wiring and / or external terminals (not shown).

[0077] For example, feedback circuits can contribute to frequency response flattening, gain setting, and securing oscillation margins, and external feedback resulting therefrom can perform the function of improving stability and linearity in high-power ranges by compensating for the internal capacitance limits of the package, as is known to those skilled in the art.

[0078] The present invention enables different matching characteristics for RF signals of different frequency bands to be easily implemented by the combination of the matching circuit part (160) and the semiconductor device (140).

[0079] In one embodiment, the matching circuit portion (160) may be configured to include a pattern or passive element connecting the land of the gate-side land portion (151a) and the land of the drain-side land portion (151b) to each other.

[0080] The arrangement of the gate terminal (141) and the drain terminal (142) may be configured to correspond to both sides in the width direction of the cavity (121). For example, the gate terminal (141) may be electrically connected to a terminal of the semiconductor device (140) on one side in the width direction of the cavity (121), and the drain terminal (142) may be electrically connected to a terminal of the semiconductor device (140) on the other side in the width direction of the cavity (121). Additionally, an example of the flow of electrical connection of the drain path is that it extends from the drain electrode of the semiconductor device (140) through the electrical connection part (143) to the drain terminal (142), and then sequentially extends from the drain terminal (142) to the upper surface terminal (133), from the upper surface terminal (133) to the via (122), and from the via (122) to the lower surface terminal (111).

[0081] This arrangement is advantageous for shortening the bonding length, reducing deviations in parasitic components, and lowering losses in the high-frequency band.

[0082] Additionally, the arrangement of the gate terminal (141) and the drain terminal (142) may be designed based on the rotational direction (clockwise or counterclockwise) and symmetry of the electromagnetic field. This arrangement optimization reduces losses due to asymmetry in the magnetic field distribution, improves matching characteristics in high-frequency transmission lines, and facilitates phase correction in specific frequency bands.

[0083] For example, it is known that if the gate and drain are separated and positioned in the cavity width direction, the bonding wire length is shortened, which reduces parasitic inductance, and this can lower the sensitivity of input-output matching at high frequencies and increase repeatability productivity.

[0084] In another embodiment, a first electrical connection may be further included to connect one of the gate terminals (141) to the element mounted on the gate-side land portion (151a), and a second electrical connection may be further included to connect one of the drain terminals (142) to the element mounted on the drain-side land portion (151b).

[0085] The upper terminal (133) may be configured as a terminal for transmitting RF signals or a DC power terminal, and may also be configured as a terminal that transmits RF signals and DC power in common as needed. When transmitting RF and DC in common, it is possible to minimize mutual interference between the RF signal path and the bias path by appropriately placing a bias tee or a choke inductor and a DC blocking capacitor outside the board. The lower terminal (111) may be electrically connected to the upper terminal (133) through vias (122) to provide a stable electrical and mechanical connection with an external board.

[0086] As illustrated in the drawings, the package according to the present invention can be implemented as a lead-less package structure that is electrically connected to an external circuit through terminals arranged inward from the edge of the substrate, particularly the bottom terminal (111), without external leads. Since there are no leads protruding outward, this lead-less structure shortens the electrical path between the leads and the chip, thereby reducing parasitic inductance and resistance and is advantageous for reducing losses and instability in the high-frequency band.

[0087] In addition, as illustrated in the drawings, the semiconductor package according to the present invention can be directly attached to a substrate using a lamination process without mechanical processing (such as cutting) of an external substrate. Therefore, it has the advantage of reducing manufacturing costs and time, as well as preventing performance variations caused by processing tolerances, thereby ensuring the reliability and uniformity of performance of the device.

[0088] FIG. 6 is a plan view of a semiconductor package (100') according to another embodiment of the present invention. If necessary, as shown in FIG. 6, a pair of upper surface terminals may be arranged (134) bent toward one side in the longitudinal direction of the cavity with respect to the corresponding intermediate row lands. According to the embodiment, for example, if it is difficult to form gate-side row lands on both sides in the longitudinal direction of the gate-side intermediate row lands due to the bent arrangement (134) of the upper surface terminals, the formation of the gate-side row lands on one side may be omitted, as illustrated in reference numeral 158. The same applies to the formation of drain-side row lands (159). If necessary, a passive component may be mounted using each of these pairs of lands (158, 159).

[0089] Additionally, in FIG. 6, surplus upper surface terminals (133') that do not contribute to the function of the semiconductor package (100') are shown. This is for design and production economics, and it is easily understood by a person skilled in the art that they can be omitted.

[0090] Although the present invention has been described using drawings showing specific embodiments, the present invention is not limited to the above embodiments. For example, modifications are possible, such as implementing part or all of the matching circuit section (160) in an external circuit or changing the layout of the land section (150) to change the combination of passive components. In addition, a multi-cavity or parallel cavity structure may be applied in addition to a single cavity structure, and a multi-channel structure may be implemented by arranging a set of multiple semiconductor devices (140) on the same plate material (110), wherein the matching circuit section (160) may be formed independently for each channel or configured in part in common.

[0091] In addition, the shape of the illustrated cavity (121), the number of vias (122), and the materials of the plate (110) and substrate (130) can be varied according to the target frequency band and output conditions, and all such variations are possible within the scope that does not deviate from the essence of the present invention.

[0092] As described above, the semiconductor package (100) according to the present invention can simultaneously achieve shortening of the heat dissipation path and integration of impedance matching, thereby simplifying the manufacturing process and reducing costs, and providing stable amplification characteristics and reliability in the high-frequency band without constraints on external physical phenomena.

[0093] According to the semiconductor package of the present disclosure described above, by ensuring diversity in substrate materials, such as using a PCB substrate, not only are manufacturing costs reduced, but design changes are also facilitated, resulting in a reduction in the manufacturing time of the semiconductor package. Furthermore, by diversifying the dielectric constant of the PCB substrate, the degree of freedom in circuit design is increased, and optimal performance can be easily realized within various frequency bands. Additionally, by overcoming the limitations of high-dielectric-constant ceramic substrates, stable performance can be provided even within high-frequency bands.

[0094] A person skilled in the art will be able to easily understand the concept on which this disclosure is based and will be able to easily utilize that concept as a basis for designing modified structures to carry out some of the objectives of the present invention.

[0095] The foregoing examples merely illustrate various possible embodiments of the various aspects of this disclosure, and equivalent variations and / or modifications will be made by others skilled in the art who have read and understood this specification and the accompanying drawings. Additionally, even if a particular feature of this disclosure may be described and / or illustrated with respect to only one of the embodiments, such feature may be combined with one or more other features of other embodiments that may be desirable and advantageous for any given use or specific use. Furthermore, insofar as the words “comprising,” “to include,” “comprising,” “having,” “having,” or variations thereof are used in the detailed description and / or claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” Explanation of the symbols

[0096] 100: Semiconductor package 110: Plate 111: Terminal 120: Middle layer 121: Cavity 122: Via 130: Substrate 133: Top terminal 133': Redundant upper terminal 134: Curved part 140: Semiconductor device 141: Gate terminal connected to the gate electrode of a semiconductor device 142: Drain terminal connected to the drain electrode of a semiconductor device 143: Electrical connection 150: Landbu 151a: Gate-side land section 151b: Drain-side land part 152a: Gate-side insulation 152b: Drain-side insulation 153a: Gate-side middle column land 153b: Drain-side middle column land 154a: Gate-side side row land 154b: Drain-side side row land 160 (161 to 169): Matching circuit section

Claims

Claim 1 A semiconductor package comprising: a plate for heat dissipation; an intermediate layer bonded to the plate, comprising a cavity formed through in a vertical direction or recessed downward from the upper surface of the intermediate layer; a substrate bonded to the intermediate layer, wherein the cavity is formed extending from the lower surface of the substrate to the upper surface of the substrate; at least one semiconductor device mounted at a position surrounded by the cavity; and at least one gate terminal formed on the outer side of the cavity on the substrate, electrically connected to at least one of the semiconductor devices on one side in the width direction of the cavity, and at least one drain terminal electrically connected to at least one of the semiconductor devices on the other side in the width direction of the cavity. A semiconductor package comprising upper surface terminals formed respectively on one side and the other side in the width direction of a cavity on the substrate, wherein the upper surface terminals on the one side in the width direction are formed outwardly from the gate terminal and the upper surface terminals on the other side in the width direction are formed outwardly from the drain terminal, and the semiconductor package further comprises a land portion formed between at least one of the gate terminal and the drain terminal and one of the upper surface terminals. Claim 2 A semiconductor package according to claim 1, wherein the intermediate layer further comprises vias formed through in a vertical direction, and each of the upper surface terminals is electrically connected to each of the vias. Claim 3 A semiconductor package according to paragraph 2, wherein the plate includes lower surface terminals for connection with the outside, and the lower surface terminals are electrically connected to the upper surface terminals through the vias. Claim 4 delete Claim 5 A semiconductor package according to claim 1, wherein the electrical connection between the semiconductor device and the gate terminal and between the semiconductor device and the drain terminal is formed by wire bonding or ribbon bonding. Claim 6 A semiconductor package according to claim 1, wherein at least one of the upper surface terminals is an RF signal terminal and at least one of the upper surface terminals is a DC power terminal, or at least one of the upper surface terminals is a terminal configured to transmit RF signal and DC power in common. Claim 7 A semiconductor package according to claim 1, further comprising a matching circuit portion formed on the substrate through the land portion, the matching circuit portion including a passive element seated on the land portion. Claim 8 A semiconductor package according to claim 1, wherein the land portion comprises a gate-side land portion formed between each of the gate terminals and each of the upper surface terminals, and a drain-side land portion formed between each of the drain terminals and each of the upper surface terminals. Claim 9 A semiconductor package according to claim 1, wherein the land portion comprises at least one intermediate row land formed to be electrically isolated from each other at a distance, and at least one side row land formed to be electrically isolated from each other at a distance from each of the intermediate row lands in at least one direction of both sides of the intermediate row land. Claim 10 A semiconductor package according to claim 9, further comprising a gate-side insulating portion surrounding one or more of the gate terminals and one or more of the upper surface terminals on a plane of the upper surface of the substrate, and a drain-side insulating portion surrounding one or more of the drain terminals and one or more of the upper surface terminals on a plane of the upper surface of the substrate, wherein at least one of the gate-side insulating portion and the drain-side insulating portion is formed of a material having a dielectric constant different from the dielectric constant of the substrate. Claim 11 A semiconductor package according to claim 7, wherein the passive element includes a chip capacitor, and a plurality of chip capacitors having different capacities are mounted on two or more of the land portions. Claim 12 A semiconductor package according to claim 7, configured to implement different matching characteristics for RF signals of different frequency bands through a combination of the semiconductor device and the matching circuit.

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