Semiconductor package

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a first semiconductor layer having a first front surface and a first rear surface on which a first integrated circuit is disposed; a first semiconductor chip comprising a plurality of first through-vias electrically connected to the first integrated circuit and divided into at least first and second groups of first through-vias; a second semiconductor chip comprising a second integrated circuit electrically connected to the first through-vias of the first group; and a third semiconductor chip comprising a third through-via electrically connected to the first through-vias of the second group, wherein the first through-vias of the first group transmit input / output signals of the first integrated circuit and the first through-vias of the second group supply power to the first integrated circuit.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0003] Semiconductor packages mounted on electronic devices require high performance and high capacity along with miniaturization. To achieve this, research and development are being conducted on semiconductor packages in which semiconductor chips including through silicon vias (TSVs) are stacked vertically. The problem to be solved

[0005] One of the problems that the present invention aims to solve is to provide a semiconductor package in which voltage drop is reduced, switching time is shortened, and the occupied area is minimized. means of solving the problem

[0007] As a means for solving the aforementioned problem, one embodiment of the present invention comprises: a first semiconductor chip having a first front surface on which a first integrated circuit is disposed and a first rear surface located opposite to the first front surface, and a plurality of first through-vias that penetrate the first semiconductor layer and are electrically connected to the first integrated circuit and are divided into at least first and second groups of first through-vias; and a second semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a second semiconductor layer having a second front surface on which a second integrated circuit is disposed and electrically connected to the first group of first through-vias, and a second rear surface located opposite to the second front surface, and a second through-via that penetrates the second semiconductor layer and is electrically connected to the second integrated circuit. A semiconductor package comprising: a third semiconductor layer disposed on the first rear surface of the first semiconductor chip and having a third front surface and a third rear surface located opposite the third front surface, and a third through-via electrically connected to the first through-via of the second group by penetrating at least a portion of the third semiconductor layer; and a plurality of connection bumps disposed on the second and third semiconductor chips and electrically connected to at least one of the second through-via and the third through-via; wherein the first through-via of the first group transmits an input / output signal of the first integrated circuit and the first through-via of the second group supplies power to the first integrated circuit.

[0009] Additionally, a first semiconductor chip comprising a first semiconductor layer having a first front surface on which a first integrated circuit is disposed and a first rear surface located opposite to the first front surface, and a plurality of first through-vias electrically connected to the first integrated circuit by penetrating the first semiconductor layer and divided into at least first and second groups of first through-vias; a second semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a second semiconductor layer having a second front surface on which a second integrated circuit is disposed and a second rear surface located opposite to the second front surface, and a second through-via electrically connected to the second integrated circuit by penetrating the second semiconductor layer; and a third semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a third semiconductor layer having a third front surface and a third rear surface located opposite to the third front surface, and a third through-via electrically connected to the second group of first through-vias by penetrating at least a portion of the third semiconductor layer. It includes, wherein the width of the first semiconductor chip in a first direction horizontal to the first rear surface is greater than or equal to the sum of the width of the second semiconductor chip and the width of the third semiconductor chip in the first direction, and the first through-via and the third through-via of the second group provide a semiconductor package that supplies power to the first integrated circuit.

[0011] Additionally, a first semiconductor chip comprising a first semiconductor layer having a first front surface on which a first integrated circuit is disposed and a first rear surface located opposite to the first front surface, and a plurality of first through-vias electrically connected to the first integrated circuit through the first semiconductor layer and divided into at least first to third groups of first through-vias; and a second semiconductor chip disposed on the first semiconductor chip such that the second front surface faces the first rear surface, comprising a second semiconductor layer having a second front surface on which a second integrated circuit electrically connected to the first group of first through-vias is disposed and a second rear surface located opposite to the second front surface, and a second through-via electrically connected to the second integrated circuit through the second semiconductor layer; A semiconductor package comprising: a third semiconductor layer having a third front surface and a third rear surface located opposite the third front surface, and a third through-via electrically connected to the first through-via of the second group penetrating the third semiconductor layer, wherein the third front surface faces the first rear surface; a fourth semiconductor chip having a fourth front surface and a fourth rear surface located opposite the fourth front surface, wherein the fourth front surface faces the first rear surface; and a fourth semiconductor chip having a fourth semiconductor layer having a memory circuit electrically connected to the first through-via of the third group, wherein the fourth front surface faces the first rear surface; wherein the second semiconductor chip transmits an input / output signal of the first integrated circuit, the third semiconductor chip supplies power to the first integrated circuit, and the fourth semiconductor chip provides cache information to the first integrated circuit. Effects of the invention

[0013] According to embodiments of the present invention, by placing a second semiconductor chip for signal input / output and a third semiconductor chip for power supply on the back of a first semiconductor chip, a semiconductor package can be provided in which voltage drop is reduced, switching time is shortened, and the occupied area is minimized. Brief explanation of the drawing

[0015] FIG. 1a is a drawing showing a semiconductor package according to one embodiment of the present invention. Figure 1b is a drawing showing the II' cross-section of Figure 1a. FIG. 2 is a drawing showing a semiconductor package according to one embodiment of the present invention. FIG. 3 is a drawing showing a semiconductor package according to one embodiment of the present invention. FIG. 4 is a drawing showing a semiconductor package according to one embodiment of the present invention. FIG. 5 is a drawing showing a semiconductor package according to one embodiment of the present invention. FIG. 6 is a drawing showing a semiconductor package according to one embodiment of the present invention. Figure 7 is a drawing showing the II-II' cross-section of Figure 6. FIGS. 8a to 8c are schematic diagrams illustrating a method for manufacturing a semiconductor package of FIG. 1a. FIG. 9 is a drawing showing a semiconductor package according to one embodiment of the present invention. FIG. 10 is a drawing showing a semiconductor package according to one embodiment of the present invention. Specific details for implementing the invention

[0016] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0018] Referring to FIGS. 1a and 1b, a semiconductor package (1000A) may include a first semiconductor chip (100) and second and third semiconductor chips (200, 300) disposed on the lower surface of the first semiconductor chip (100). Additionally, the semiconductor package (1000A) may further include a first sealing layer (410), a second sealing layer (420), a rewiring structure (430), and a plurality of connection bumps (440). The first to third semiconductor chips (100, 200, 300) may have a hybrid bonding structure that is directly attached without a separate connection member (e.g., solder bump, copper pillar, etc.). For example, the first semiconductor chip (100) and the second semiconductor chip (200) are electrically connected to each other through the first wiring structure (132) and the second circuit structure (222), and the first wiring structure (132) can come into direct contact with the second circuit structure (222).

[0020] The first semiconductor chip (100) can receive input / output signals through the second semiconductor chip (200) and receive power through the third semiconductor chip (300). In one embodiment, the first through-via (141) of the first group can transmit input / output signals of the first integrated circuit to the first integrated circuit or an external device through the second through-via (241) and the second integrated circuit. The first through-via (142) of the second group can supply power to the first integrated circuit through the third through-via (341). In an integrated circuit having ultra-fine pitch, the input / output circuit and the power supply circuit can increase the congestion of the integrated circuit and cause problems such as voltage drop. However, in one embodiment, by placing a second semiconductor chip (200) including an input / output circuit for the first semiconductor chip (100) and a third semiconductor chip (300) for power supply for the first semiconductor chip (100) on the first semiconductor chip (100), the congestion of the first wiring structure (122) constituting the first integrated circuit of the first semiconductor chip (100) can be reduced. Accordingly, the voltage drop of the first integrated circuit can be reduced and the switching time can be shortened. In addition, since the second and third semiconductor chips (200, 300) are located within the area of ​​the first semiconductor chip (100), the occupied area of ​​the semiconductor package (1000A) can be minimized. For example, in a direction (X-axis direction) parallel to the lower surface or the first rear surface (110S2) of the first semiconductor chip (100), the width (100w) of the first semiconductor chip (100) may be greater than the sum of the width (200w) of the second semiconductor chip (200) and the width (300w) of the third semiconductor chip (300).

[0022] The first semiconductor chip (100) may include a first semiconductor layer (110), a first circuit layer (120), a first wiring layer (130), and a plurality of first through-vias (141, 142). The first semiconductor layer (110) may include a first front surface (110S1) on which a first integrated circuit is disposed and a first back surface (110S2) located opposite to the first front surface (110S1), and may include a semiconductor substrate (111), a plurality of conductive regions formed within the semiconductor substrate (111), and isolated regions on one side of the conductive regions. The semiconductor substrate (111) may be a semiconductor wafer. The semiconductor substrate (111) may include a semiconductor element such as silicon or germanium, or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The conductive region may be, for example, an impurity-doped well or an impurity-doped structure. The isolation region may be a device isolation structure having a shallow trench isolation (STI) structure and may include silicon oxide.

[0024] A first circuit layer (120) may be disposed on a first front surface (110S1) of a first semiconductor layer (110). The first circuit layer (120) may include a front interlayer insulating layer (121), a plurality of first individual elements (ID1), and a first circuit structure (122) electrically connected to the plurality of first individual elements (ID1). The front interlayer insulating layer (121) is disposed on the upper surface of a semiconductor substrate (111) and may include silicon oxide or silicon nitride. The plurality of first individual elements (ID1) may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), a system LSI (large scale integration), a micro-electro-mechanical system (MEMS), active devices, passive devices, etc. The plurality of first individual elements (ID1) may include a gate structure disposed between conductive regions of the semiconductor substrate (111).

[0025] The first circuit structure (122) includes at least one wiring line extending in the horizontal direction (X-axis direction) and at least one wiring via extending in the vertical direction (Z-axis direction), and may be electrically connected to a conductive region on a semiconductor substrate (111) and at least one of a plurality of first individual elements (ID1). The first circuit structure (122) may have a multilayer structure including a plurality of wiring lines and a plurality of wiring vias. The wiring lines and wiring vias may include a metallic material including, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring lines or / and wiring vias and the interlayer insulating layer (121). It is obvious that in addition to the first circuit structure (122) shown in the drawing, there is a first circuit structure (122) that interconnects the first individual elements (ID1) or connects the first individual elements (ID1) and the first through vias (141, 142).

[0026] A plurality of first individual elements (ID1) and a first circuit structure (122) may be combined with each other to provide a first integrated circuit. The first integrated circuit may include a logic circuit. The logic circuit may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processing unit (DSP), an image signal processing unit (ISP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, and an application-specific integrated circuit (ASIC).

[0028] A first wiring layer (130) may be disposed on the first rear surface (110S2) of the first semiconductor layer (110). The first wiring layer (130) may include a rear interlayer insulating layer (131) and a first wiring structure (132) electrically connected to the first circuit structure (122). The rear interlayer insulating layer (131) is disposed on the lower surface of the semiconductor substrate (111) and may include silicon oxide or silicon nitride. The first wiring structure (132) may have a single layer or a multilayer structure. For example, the first wiring structure (132) may include at least one wiring line and at least one wiring via, similar to the first circuit structure (122), to rewire the first through-vias (141, 142). A passivation film may be further included on the lower surface of the first wiring layer (130). The passivation film may be an insulating layer comprising silicon oxide, silicon nitride, a polymer, or a combination thereof. The passivation film may cover a portion (e.g., a back pad) of the first wiring structure (132) exposed on the lower surface of the first semiconductor chip (100).

[0030] A plurality of first through-vias (141, 142) penetrate at least a portion of the first semiconductor layer (110) and are electrically connected to the first integrated circuit, and can be divided into at least first and second groups of first through-vias (141, 142). A plurality of first through-vias (141, 142) electrically connect the first circuit structure (122) and the first wiring structure (132) and can provide a transmission path for input / output signals and power of the first integrated circuit. For example, the input / output signals of the first integrated circuit can be transmitted to the first integrated circuit or an external device through a first group of first through-vias (141) connected to the second semiconductor chip (200). A first group of first through-vias (141) may be connected to the second circuit structure (222) to electrically connect the second individual elements (ID2) and the first individual elements (ID1). For example, power to the first integrated circuit may be supplied to the first integrated circuit through a second group of first through-vias (142) connected to the third semiconductor chip (300). The second group of first through-vias (142) may be connected to a power rail (122P) of a first circuit structure (122) that supplies power to the first individual elements (ID1). The second group of first through-vias (142) for power supply may have a different size from the first group of first through-vias (141). For example, in the horizontal direction (X-axis direction), the width (141w) of the first group of first through-vias (141) may be equal to or smaller than the width (142w) of the second group of first through-vias (142).

[0031] A plurality of first through-vias (141, 142) may include a metal plug extending in a vertical direction (Z-axis direction) between the upper and lower surfaces of the first semiconductor chip (100) and a barrier film surrounding the sides of the metal plug. The metal plug may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu). The metal plug may be formed by a plating process, a PVD process, or a CVD process. The barrier film may include a metal compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). The barrier film may be formed by a PVD process or a CVD process. A via insulating film may be formed on the sides of the plurality of first through-vias (141, 142). The via insulating film may be a single film or a multilayer film. The via insulating film may include silicon oxide, silicon oxide nitride, silicon nitride, a polymer, or a combination thereof.

[0033] The second semiconductor chip (200) is disposed on the lower or rear surface (110S2) of the first semiconductor chip (100) and may include a second semiconductor layer (210) having a second front surface (210S1) and a second rear surface (210S2), a second circuit layer (220), a second wiring layer (230), and a second through-via (241). Since the second semiconductor chip (200) may include the same or similar technical features as the first semiconductor chip (100) described above, redundant descriptions are omitted.

[0034] The second circuit layer (220) may include a second integrated circuit formed by combining a plurality of second individual elements (ID2) and a second circuit structure (222). The second integrated circuit may be electrically connected to a first through-via (141) of a first group. The second semiconductor chip (200) may be positioned such that the second front surface (210S1) on which the second integrated circuit is formed faces the first rear surface (110S2) of the first semiconductor chip (100). The second integrated circuit may include at least one of an input / output circuit, an analog circuit, a memory circuit, and a serial-to-parallel conversion circuit for the first integrated circuit. The memory circuit may include at least one of DRAM, SRAM, PRAM, MRAM, RRAM, and Flash memory.

[0035] Additionally, the second semiconductor chip (200) may further include a power through-via (242) that supplies power to the second individual components (ID2). The power through-via (242) can supply power to the second individual components (ID2) of the second integrated circuit. The power through-via (242) can supply power to the second integrated circuit through a path passing through the first wiring structure (132) and / or the first circuit structure (122). In the drawing, only a single layer of wiring lines is shown on the upper and lower surfaces of the power through-via (242). Alternatively, the power through-via (242) can be connected to the first wiring structure (132) and the rewiring structure (430) through a multilayer second circuit structure (222) and / or a multilayer second wiring structure (232), as with the second through-via (241). In one embodiment, the second semiconductor chip (200) is positioned so that the second front surface (210S1) faces the first rear surface (110S2) and can receive power through a power through-via (242). Accordingly, the congestion of the second circuit structure (222) is reduced, so that the voltage drop is reduced and the switching time can be shortened.

[0037] The third semiconductor chip (300) is disposed on the lower or rear surface (110S2) of the first semiconductor chip (100) and may include a third semiconductor layer (310) having a third front surface (310S1) and a third rear surface (310S2), a third circuit layer (320), a third wiring layer (330), and a third through-via (341). Since the third semiconductor chip (300) may include technical features identical or similar to those of the first semiconductor chip (100) described above, redundant descriptions are omitted.

[0038] The third circuit layer (320) may be disposed on the third front surface (310S1) of the third semiconductor layer (310). Unlike the first and second circuit layers (120, 220), the third circuit layer (320) may not include individual elements. The third circuit layer (320) may include a front interlayer insulating layer (321) surrounding the third through-via (341). The front interlayer insulating layer (321) may include silicon oxide or silicon nitride. In the drawing, the thickness of each of the third semiconductor layer (310), the third circuit layer (320), and the third wiring layer (330) is depicted as being similar to the thickness of the corresponding elements (210, 220, 230) of the second semiconductor chip (200), but is not limited thereto. In one example, the thickness of the third semiconductor layer (310) may be greater than the thickness of the third circuit layer (320) or the third wiring layer (330).

[0039] The third through-via (341) can penetrate at least a portion of the third semiconductor layer (310) and be electrically connected to the first through-via (142) of the second group. The third through-via (341) can supply power to the first individual elements (ID1) through the first through-via (142) of the second group. The third through-via (341) for power supply may have a different size from the second through-via (241). For example, in a direction (X-axis direction) parallel to the bottom surface or the first rear surface (110S2) of the first semiconductor chip (100), the width (241w) of the second through-via (241) may be equal to or smaller than the width (341w) of the third through-via (341). In the drawing, only a single layer of landing pads (341P1, 341P2) is shown on the top and bottom surfaces of the third through-via (341). In contrast, the third through-via (341) can be connected to the first wiring structure (132) and the redistribution structure (430) through a multilayer circuit or wiring structure.

[0041] The first sealing layer (410) is disposed on the lower surface or the first rear surface (110S2) of the first semiconductor chip (100) and can cover the sides of the second and third semiconductor chips (200, 300), respectively. The first sealing layer (410) can fill the space between the second semiconductor chip (200) and the third semiconductor chip (300) that are spaced apart in the first direction (X-axis direction). The first sealing layer (410) may include an insulating material. For example, the first sealing layer (410) may include materials such as silicon oxide, silicon oxynitride, silicon nitride, polymer, etc.

[0043] A second sealing layer (420) may be disposed between a plurality of connection bumps (440) and the first sealing layer (410), the second semiconductor chip (200), and the third semiconductor chip (300). The second sealing layer (420) may include an insulating material, but may include a material different from the first sealing layer (410) to form a redistribution structure (430). For example, the second sealing layer (420) may include at least one of a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg including an inorganic filler or / and glass fiber, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), EMC (Epoxy Molding Compound), and PID.

[0045] The rewiring structure (430) electrically connects a plurality of connection bumps (440), a second semiconductor chip (200), and a third semiconductor chip (300), and may be disposed within a second sealing layer (420). The rewiring structure (430) may include one or more rewiring lines extending in a horizontal direction (X-axis or Y-axis direction) and one or more rewiring vias extending in a vertical direction (Z-axis direction). The rewiring structure (430) may have a single-layer structure or a multi-layer structure. In one example, the rewiring structure (430) may be omitted, in which case the plurality of connection bumps (440) may be directly disposed on the lower surface of the second and third semiconductor chips (200, 300).

[0047] A plurality of connection bumps (440) are disposed on the second and third semiconductor chips (200, 300) and may be electrically connected to at least one of the second through-via (241) and the third through-via (341). A plurality of connection bumps (440) are disposed on the lower surface of the second sealing layer (420) and may be electrically connected to the second through-via (241), the power through-via (242), and the third through-via (341). A plurality of connection bumps (440) may be disposed to face the lower surface of the first semiconductor chip (100) or the first rear surface (110S2). At least some of the connection bumps (440) connected to the power through-via (242) and the third through-via (341) may transmit power and ground signals from or to the outside. The power through-via (242) and the third through-via (341) may also be used as ground vias. The remaining portion of the connection bumps (440) connected to the second through-via (241) can transmit input / output signals from or to the outside. The plurality of connection bumps (440) may include a conductive material and may have a land, ball, or pin structure.

[0049] FIG. 2 is a drawing showing a semiconductor package (1000B) according to an embodiment of the present invention. In FIG. 2, components having the same reference number as FIG. 1a have the same or similar features as described above, so redundant descriptions are omitted.

[0051] Referring to FIG. 2, in a semiconductor package (1000B), a third semiconductor chip (300) is positioned such that the third front side (310S1) faces the first rear side (110S2) and may further include a third circuit structure (322) that electrically connects a third through-via (341) and a second group of first through-vias (142). In one embodiment, the third semiconductor chip (300) may include a third semiconductor layer (310), a third circuit layer (320) positioned on the third front side (310S1) of the third semiconductor layer (310), and a third wiring layer (330) positioned on the third rear side (310S2). The third circuit layer (320) may include a third circuit structure (322) that connects the third through-via (341) and the first wiring structure (132) of the first semiconductor chip (100). The third circuit structure (322) may have a single-layer structure or a multi-layer structure. In the drawing, the third wiring structure (332) within the third wiring layer (330) is shown as a single layer, but the third wiring structure (332) may also be formed as a multi-layer structure like the third circuit structure (322). In this way, by using the third circuit structure (322) and / or the third wiring structure (332) to rewire the third through-via (341), the design freedom of the power lines of the first semiconductor chip (100) and the third semiconductor chip (300) can be improved.

[0053] FIG. 3 is a drawing showing a semiconductor package (1000C) according to an embodiment of the present invention. In FIG. 3, components having the same reference number as FIG. 1a have the same or similar features as described above, so redundant descriptions are omitted.

[0055] Referring to FIG. 3, in a semiconductor package (1000C), a second semiconductor chip (200) may be positioned such that the second rear surface (210S2) faces the first rear surface (110S2) of the first semiconductor chip (100). In one embodiment, the second semiconductor chip (200) has a second wiring layer (230) in contact with the first wiring layer (130), and a second integrated circuit within the second circuit layer (120) may be connected to the first integrated circuit of the first semiconductor chip (100) through a second through-via (241) and a second wiring structure (232). Second individual elements (ID2) may be electrically connected to the first semiconductor chip (100) through the second circuit structure (222) and the second through-via (241). In one example, the power through-via (242) can supply power to the first individual elements (ID1) via the first wiring structure (132) and / or the first circuit structure (122), so that it does not place a significant burden on the congestion of the second circuit structure (222).

[0057] FIG. 4 is a drawing showing a semiconductor package (1000D) according to an embodiment of the present invention. In FIG. 4, components having the same reference number as FIG. 1a have the same or similar features as described above, so redundant descriptions are omitted.

[0059] Referring to FIG. 4, in a semiconductor package (1000D), the second and third semiconductor chips (200, 300) of FIG. 1a, etc. are provided as a single semiconductor structure (500), and the width (100w) of the first semiconductor chip (100) in the first direction (X-axis direction) may differ from the width (500w) of the semiconductor structure (500). In one embodiment, since the semiconductor structure (500) is attached to the first semiconductor chip (100) in a wafer state before the dicing process, the width (500w) of the semiconductor structure (500) may be smaller than the width (100w) of the first semiconductor chip (100) after the dicing process. The side of the semiconductor structure (500) may be covered by a first sealing layer (410).

[0060] In one embodiment, the semiconductor structure (500) may include a semiconductor layer (510) having a front surface (510S1) and a rear surface (510S2), a circuit layer (520) disposed on the front surface (510S1) of the semiconductor layer (510), and a wiring layer (530) disposed on the rear surface (510S2) of the semiconductor layer (510). In the semiconductor structure (500), elements of reference numbers similar to the second and third semiconductor chips (200, 300) of FIG. 1a may have identical or similar technical features. For example, the semiconductor layer (510) of the semiconductor structure (500) may correspond to the second and third semiconductor layers (210, 310), the circuit layer (520) of the semiconductor structure (500) may correspond to the second and third circuit layers (220, 320), and the wiring layer (530) of the semiconductor structure (500) may correspond to the second and third wiring layers (230, 330). The semiconductor structure (500) may include an input / output circuit and a power circuit for the first semiconductor chip (100).

[0062] FIG. 5 is a drawing showing a semiconductor package (1000E) according to an embodiment of the present invention. In FIG. 5, components having the same reference numbers as FIG. 1a and FIG. 4 have the same or similar features as described above, so redundant descriptions are omitted.

[0064] Referring to FIG. 5, in a semiconductor package (1000E), the second and third semiconductor chips (200, 300) of FIG. 1a, etc. are provided as a single semiconductor structure (500), but unlike the embodiment shown in FIG. 4, the width (100w) of the first semiconductor chip (100) in the first direction (X-axis direction) may be the same as the width (500w) of the semiconductor structure (500). In one embodiment, the semiconductor structure (500) and the first semiconductor chip (100) may be bonded in a wafer state prior to the dicing process. Therefore, since the first semiconductor chip (100) and the semiconductor structure (500) are cut simultaneously during the dicing process, the first semiconductor chip (100) and the semiconductor structure (500) may have the same width (100w, 500w).

[0066] FIG. 6 is a drawing showing a semiconductor package (1000F) according to an embodiment of the present invention, and FIG. 7 is a drawing showing a cross-sectional view of FIG. 6 along line II-II'. FIG. 6 is a cross-sectional view showing a cross-sectional view of line AA' of FIG. 7 is illustrated with the landing pad (341P2), etc. of FIG. 6 omitted to show the arrangement relationship of the first to fourth semiconductor chips (100, 200, 300, 600) on the XY plane.

[0068] Referring to FIGS. 6 and 7, the semiconductor package (1000F) may further include a fourth semiconductor chip (600) having a fourth semiconductor layer (610) having a fourth front surface (610S1) and a fourth rear surface (610S2) located opposite the fourth front surface (610S1), and a fourth circuit layer (620) having a memory circuit disposed on the fourth front surface (610S1). In one example, the fourth semiconductor chip (600) may be disposed on the first semiconductor chip (100) such that the fourth front surface (610S1) faces the first rear surface (110S2). In the XY plane, second and third semiconductor chips (200, 300, 600) may be disposed within the first semiconductor chip (100). Since the fourth semiconductor chip (200) may include technical features identical or similar to those of the second semiconductor chip (200) described above, redundant descriptions are omitted.

[0069] The fourth circuit layer (620) may include a plurality of third individual elements (ID3) and a third circuit structure (622). The plurality of third individual elements (ID3) and the third circuit structure (622) may be combined with each other to provide a memory circuit. The memory circuit may be electrically connected to the first semiconductor chip (100). In one embodiment, the first semiconductor chip (100) may further include a third group of first through-vias (143) that electrically connect the first integrated circuit and the memory circuit. The memory circuit may include at least one of DRAM, SRAM, PRAM, MRAM, RRAM, and Flash memory. For example, the memory circuit may include a cache memory circuit that provides cache information to the first semiconductor chip (100). In one example, the fourth semiconductor chip (600) does not include a through-via penetrating the fourth semiconductor layer (610), and the memory circuit on the fourth semiconductor layer (610) can be electrically insulated from a plurality of connection bumps (440) and a rewiring structure (430).

[0071] FIGS. 8a to 8c are schematic drawings illustrating the method of manufacturing the semiconductor package (1000A) of FIG. 1a.

[0073] Referring to FIG. 8a, a first semiconductor chip (100) in a wafer state can be placed on a carrier (C). The first semiconductor chip (100) can be placed such that its first front surface (110S1) faces the carrier (C). The carrier (C) may be a resin substrate or a glass substrate including an adhesive layer. In one example, the carrier (C) may be a dummy wafer. The first wiring layer (130) of the first semiconductor chip (100) exposed on the carrier (C) may include a first back interlayer insulating layer (131) and a first wiring structure (132). The first back interlayer insulating layer (131) may include a silicon oxide film. The first wiring structure (132) may include multilayer wiring lines and wiring vias. The first wiring layer (130) can be formed by removing a portion of the first semiconductor layer (110) using a CMP process or the like, and then repeatedly performing a photolithography process, an etching process, a plating process, etc.

[0075] Referring to FIG. 8b, a second semiconductor chip (200) and a third semiconductor chip (300) that are diced can be attached to the first rear surface (110S2) of a first semiconductor chip (100) in a wafer state. The second and third semiconductor chips (200, 300) can be positioned such that the second front surface (210S1) and the third front surface (310S1), respectively, face the first rear surface (110S2) of the first semiconductor chip (100). The second and third semiconductor chips (200, 300) can be directly combined with the first semiconductor chip (100) without separate adhesive and connecting members. For example, the first rear interlayer insulation layer (131) and the second and third front interlayer insulation layers (221, 321) can be joined together by pressing and then heating to join the landing pad (341P1) of the contacted first wiring structure (132), second circuit structure (222), and third through-via (341).

[0077] Referring to FIG. 8c, a first sealing layer (410) can be formed to fill the space between the second and third semiconductor chips (200, 300), and a second sealing layer (420) and a redistribution structure (430) can be formed on the second and third semiconductor chips (200, 300). The first sealing layer (410) can be formed using a gap fill material such as an oxide or a nitride, and the second sealing layer (420) can be formed using a photosensitive resin such as PID. The redistribution structure (430) can be formed by performing a photolithography process, a plating process, etc. Subsequently, individual semiconductor packages can be separated through a sawing process, and a connection bump can be formed on the redistribution structure (430) (e.g., a pad portion) exposed on the second sealing layer (420) to complete the semiconductor package.

[0079] FIG. 9 is a drawing showing a semiconductor package (2000A) according to one embodiment of the present invention.

[0081] Referring to FIG. 9, a semiconductor package (2000A) may include a main semiconductor structure (1000) and a plurality of semiconductor chips (10, 20, 30, 40) disposed on a mounting substrate (50). The main semiconductor structure (1000) may include at least one of the semiconductor packages (1000A-1000F) of FIG. 1a to FIG. 7 described above. The plurality of semiconductor chips (10, 20, 30, 40) may be stacked in a vertical direction (Z-axis direction) on the mounting substrate (50).

[0083] The mounting board (50) may include a lower terminal (51) and an upper terminal (52) respectively disposed on the lower and upper surfaces, and a connecting wire (53) that electrically connects them. The mounting board (50) may be a substrate for a semiconductor package, such as a printed circuit board (PCB), a ceramic substrate, or a tape wiring board. For example, the mounting board (50) may be a silicon interposer substrate including a Through-Silicon Via (TSV). The connecting wire (53) may electrically connect a main semiconductor structure (1000) and a plurality of semiconductor chips (10, 20, 30, 40).

[0085] The main semiconductor structure (1000) may be a process unit such as a CPU or GPU. The main semiconductor structure (1000) may be a package with verified normal operation, such as a KGP (Known Good Package). The main semiconductor structure (1000) may be electrically connected to a mounting substrate (50) through a connection member.

[0087] A plurality of semiconductor chips (10, 20, 30, 40) may be electrically connected to each other through through vias (11, 12, 13) and connection bumps (B1, B2, B3). The plurality of semiconductor chips (10, 20, 30, 40) may include volatile memory chips such as DRAM or non-volatile memory chips such as PRAM, MRAM, RRAM, flash memory, etc. The plurality of semiconductor chips (10, 20, 30, 40) may be in a packaged form using a buffer chip and a molding member, etc. The plurality of semiconductor chips (10, 20, 30, 40) may have a hybrid bonding structure in which the landing pads of the through vias (11, 12, 13) directly contact each other without connection bumps (B1, B2, B3).

[0089] FIG. 10 is a drawing showing a semiconductor package (2000B) according to one embodiment of the present invention.

[0091] Referring to FIG. 10, the semiconductor package (2000B) may include a main semiconductor structure (1000) attached to a mounting substrate (50) and a plurality of semiconductor chips (10, 20, 30, 40) stacked vertically (Z-axis direction) on the main semiconductor structure (1000). The main semiconductor structure (1000) may be electrically connected to the plurality of semiconductor chips (10, 20, 30, 40) through a connection pad disposed on its upper surface. In FIG. 10, components having the same reference number as in FIG. 9 have the same or similar characteristics as described above, so redundant details are omitted.

[0093] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

Claims

Claim 1 A first semiconductor chip comprising a first semiconductor layer having a first front surface on which a first integrated circuit is disposed and a first rear surface located opposite to the first front surface, and a plurality of first through-vias electrically connected to the first integrated circuit by penetrating the first semiconductor layer and divided into at least first and second groups of first through-vias; a second semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a second semiconductor layer having a second front surface on which a second integrated circuit is disposed and electrically connected to the first group of first through-vias, and a second rear surface located opposite to the second front surface, and a second through-via electrically connected to the second integrated circuit by penetrating the second semiconductor layer; and a third semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a third semiconductor layer and a third through-via electrically connected to the second group of first through-vias by penetrating at least a portion of the third semiconductor layer. A semiconductor package comprising: a plurality of connection bumps disposed on the second and third semiconductor chips and electrically connected to at least one of the second through-via and the third through-via; wherein the first through-via of the first group transmits an input / output signal of the first integrated circuit, and the first through-via of the second group supplies power to the first integrated circuit, and either the second front or the second rear surface of the second semiconductor chip faces the first rear surface of the first semiconductor chip, and the third semiconductor chip has an upper surface facing the first rear surface of the first semiconductor chip and a lower surface opposite to the upper surface, and the plurality of connection bumps disposed on the other side of the second front or the second rear surface of the second semiconductor chip and the lower surface of the third semiconductor chip. Claim 2 In claim 1, the second semiconductor chip is a semiconductor package in which the second front surface is positioned to face the first rear surface. Claim 3 In claim 1, the semiconductor package further comprises a power through-via that penetrates the second semiconductor layer to supply power to the second integrated circuit. Claim 4 A semiconductor package according to claim 1, further comprising a first sealing layer disposed on the first rear surface of the first semiconductor chip and covering the sides of the second and third semiconductor chips, respectively. Claim 5 A semiconductor package according to claim 4, further comprising a second sealing layer disposed between the plurality of connection bumps and the first sealing layer, the second semiconductor chip, and the third semiconductor chip, and a rewiring structure within the second sealing layer that electrically connects the plurality of connection bumps, the second semiconductor chip, and the third semiconductor chip. Claim 6 A semiconductor package according to claim 1, wherein the first integrated circuit comprises a logic circuit, and the second integrated circuit comprises at least one of an input / output circuit for the logic circuit, an analog circuit, a memory circuit, and a serial-to-parallel conversion circuit. Claim 7 A semiconductor package according to claim 1, further comprising a fourth semiconductor chip having a fourth front surface disposed on the first rear surface of the first semiconductor chip and having a fourth rear surface disposed on the fourth front surface on which a memory circuit electrically connected to the first integrated circuit is disposed, and a fourth rear surface located opposite to the fourth front surface, wherein the plurality of first through-vias further comprise a third group of first through-vias electrically connecting the memory circuit and the first integrated circuit. Claim 8 In claim 7, the memory circuit is a semiconductor package including a cache memory circuit. Claim 9 A first semiconductor chip comprising a first semiconductor layer having a first front surface on which a first integrated circuit is disposed and a first rear surface located opposite to the first front surface, and a plurality of first through-vias electrically connected to the first integrated circuit by penetrating the first semiconductor layer and divided into at least first and second groups of first through-vias; a second semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a second semiconductor layer having a second front surface on which a second integrated circuit is disposed and electrically connected to the first group of first through-vias, and a second rear surface located opposite to the second front surface, and a second through-via electrically connected to the second integrated circuit by penetrating the second semiconductor layer; and a third semiconductor chip disposed on the first rear surface of the first semiconductor chip and comprising a third semiconductor layer having a third front surface and a third rear surface located opposite to the third front surface, and a third through-via electrically connected to the second group of first through-vias by penetrating at least a portion of the third semiconductor layer. A semiconductor package comprising, wherein the width of the first semiconductor chip in a first direction horizontal to the first rear surface is greater than or equal to the sum of the width of the second semiconductor chip and the width of the third semiconductor chip in the first direction, and wherein the first through-via and the second through-via of the first group transmit input / output signals of the first integrated circuit, and the first through-via and the third through-via of the second group supply power to the first integrated circuit. Claim 10 A first semiconductor chip comprising a first semiconductor layer having a first front surface on which a first integrated circuit is disposed and a first rear surface located opposite to the first front surface, and a plurality of first through-vias electrically connected to the first integrated circuit through the first semiconductor layer and divided into at least first to third groups of first through-vias; and a second semiconductor chip disposed on the first semiconductor chip such that the second front surface faces the first rear surface, comprising a second semiconductor layer having a second front surface on which a second integrated circuit electrically connected to the first group of first through-vias is disposed and a second rear surface located opposite to the second front surface, and a second through-via electrically connected to the second integrated circuit through the second semiconductor layer; A semiconductor package comprising: a third semiconductor layer having a third front surface and a third rear surface located opposite the third front surface, and a third through-via electrically connected to the first through-via of the second group penetrating the third semiconductor layer, wherein the third front surface faces the first rear surface; a fourth semiconductor chip having a fourth front surface and a fourth rear surface located opposite the fourth front surface, wherein the fourth front surface faces the first rear surface; wherein the second semiconductor chip transmits an input / output signal of the first integrated circuit, the third semiconductor chip supplies power to the first integrated circuit, and the fourth semiconductor chip provides cache information to the first integrated circuit.

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