Semiconductor package

Abstract

A semiconductor package according to embodiments of the present invention comprises: a redistribution substrate having first trenches in which a portion of the upper surface is recessed; a first semiconductor chip mounted on the redistribution substrate and comprising first chip pads and second chip pads; capacitor chips mounted on the second chip pads of the first semiconductor chip and comprising capacitor chip pads; and an underfill film provided on the lower surface of the first semiconductor chip, wherein the redistribution substrate comprises vertically stacked insulating layers; redistribution patterns provided within the insulating layers; and stack vias provided between the capacitor chips, wherein the stack vias are connected to the redistribution patterns and the first semiconductor chip, and the capacitor chip pads can be in direct contact with the first chip pads.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, more specifically, a semiconductor package including a capacitor, and a method for manufacturing the same. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, various studies are underway to improve the reliability of semiconductor packages. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package with improved reliability and a method for manufacturing the same. means of solving the problem

[0004] A semiconductor package according to the concept of the present invention is provided. According to the present invention, the semiconductor package comprises: a redistribution substrate having a first trench in which a portion of the upper surface is recessed; a first semiconductor chip mounted on the redistribution substrate; a capacitor chip mounted on the lower surface of the first semiconductor chip; and an underfill film provided on the lower surface of the first semiconductor chip, wherein the redistribution substrate comprises vertically stacked insulating layers; redistribution patterns provided within the insulating layers; and dummy redistribution patterns provided within the first trench and vertically overlapping with the first semiconductor chip, wherein the uppermost surface of the dummy redistribution pattern may be provided at a level higher than the bottom surface of the first trench.

[0005] According to embodiments of the present invention, a semiconductor package comprises: a redistribution substrate having first trenches in which a portion of the upper surface is recessed; a first semiconductor chip mounted on the redistribution substrate and comprising first chip pads and second chip pads; capacitor chips mounted on the second chip pads of the first semiconductor chip and comprising capacitor chip pads; and an underfill film provided on the lower surface of the first semiconductor chip, wherein the redistribution substrate comprises vertically stacked insulating layers; redistribution patterns provided within the insulating layers; and stack vias provided between the capacitor chips, wherein the stack vias are connected to the redistribution patterns and the first semiconductor chip, and the capacitor chip pads can be in direct contact with the first chip pads.

[0006] According to embodiments of the present invention, a redistribution substrate having first trenches in which a portion of the upper surface is recessed; a conductive terminal provided on the lower surface of the redistribution substrate; a first semiconductor chip mounted on the redistribution substrate and comprising first chip pads and second chip pads; capacitor chips mounted on the second chip pads of the first semiconductor chip and comprising capacitor chip pads; first connection terminals interposed between the capacitor chips and the second chip pads; and an underfill film provided on the lower surface of the first semiconductor chip, wherein the redistribution substrate comprises vertically stacked insulating layers; redistribution patterns provided within the insulating layers and comprising wiring portions and via portions; upper conductive patterns provided on wiring portions of the uppermost redistribution patterns among the redistribution patterns and connected to the first semiconductor chip; lower conductive patterns provided on via portions of the lowermost redistribution patterns among the redistribution patterns and connected to the conductive terminal; and a blocking insulating pattern provided between the capacitor chips. and includes stack vias that penetrate the blocking insulation pattern and are provided on the redistribution patterns, wherein the stack vias are connected to the redistribution patterns and the first semiconductor chip, and the underfill film fills the space between the lower surface of the first semiconductor chip and the upper surface of the capacitor chips and surrounds the first connection terminals, and the underfill film can be in direct contact with the lower surface of the first semiconductor chip and the upper surface of the capacitor chips. Effects of the invention

[0007] According to the present invention, a semiconductor chip may be mounted on a redistribution substrate including a trench. A capacitor chip may be provided on the lower surface of the semiconductor chip, and the capacitor chip may be provided inside the trench. Accordingly, noise of the power signal can be effectively removed, and a semiconductor package with improved integration density can be provided. Brief explanation of the drawing

[0008] FIG. 1 is a plan view illustrating a semiconductor package according to embodiments. Figure 2a is a cross-sectional view taken along the line I-I' of Figure 1. FIGS. 2B and FIGS. 2C are enlarged views for illustrating a semiconductor package according to embodiments, corresponding to area A of FIG. 2A. FIG. 3a is a plan view illustrating a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1. FIGS. 3b and FIGS. 3c are enlarged views for illustrating a semiconductor package according to embodiments, corresponding to area A of FIG. 3a. Figure 4 is an enlarged view of area B of Figure 2a. Figure 5 is a plan view cut along the line II-II' of Figure 4. FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1. FIG. 7 is a cross-sectional view illustrating a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1. FIG. 8 is a plan view illustrating a semiconductor package according to embodiments. FIGS. 9 and FIGS. 10 are cross-sectional views illustrating semiconductor packages according to embodiments, corresponding to a cross-section cut along the line III-III' of FIG. 8. FIGS. 11 to 19 are drawings for explaining a method of manufacturing a semiconductor package according to embodiments. Specific details for implementing the invention

[0009] In this specification, the same reference numerals throughout the text may refer to the same components. A semiconductor package and a method for manufacturing the same according to the concept of the present invention are described.

[0010] FIG. 1 is a plan view illustrating a semiconductor package according to embodiments. FIG. 2a is a cross-sectional view taken along the line I-I' of FIG. 1. FIG. 2b and FIG. 2c are enlarged views for explaining a semiconductor package according to embodiments, corresponding to area A of FIG. 2a.

[0011] Referring to FIG. 1 and FIG. 2a, a semiconductor package (10) according to embodiments of the present invention may include a package substrate (800), a redistribution substrate (100), a first semiconductor chip (210), a capacitor chip (400), chip stacks (250), an underfill film (300), and an upper molding film (360).

[0012] A package substrate (800) may be provided. The package substrate (800) may include a printed circuit board. The package substrate (800) may include a first metal pad (810), a second metal pad (820), and a metal wiring (830). The metal wiring (830) may be provided within the package substrate (800). In this specification, connecting to the package substrate (800) may mean connecting to the metal wiring (830). The first metal pad (810) may be provided on the upper surface (800a) of the package substrate (800) and electrically connected to the metal wiring (830). The second metal pad (820) may be provided on the lower surface (800b) of the package substrate (800) and electrically connected to the metal wiring (830). An external connection terminal (840) may be provided on the lower surface of the second metal pad (820) and connected to the metal wiring (830). External electrical signals can be transmitted to the metal wiring (830) through the external connection terminal (840). A solder ball can be used as the external connection terminal (840). The external connection terminal (840) may contain a metal such as a solder material.

[0013] A redistribution substrate (100) may be provided on the upper surface (800a) of a package substrate (800). The redistribution substrate (100) may include a lower conductive pattern (110), redistribution patterns (120), dummy redistribution patterns (130), an upper conductive pattern (140), insulating layers (101, 103, 105, 107), a blocking insulating pattern (BP), and a stack via (SP). The insulating layers (101, 103, 105, 107) may include first to fourth insulating layers (101, 103, 105, 107). The redistribution substrate (100) may also be referred to as an interposer substrate.

[0014] A lower conductive pattern (110) may be provided within the first insulating layer (101). The lower surface of the lower conductive pattern (110) may not be covered by the first insulating layer (101). Accordingly, the lower surface of the lower conductive pattern (110) may be exposed to the outside. The lower conductive pattern (110) may define a location where a conductive terminal (160) is placed. The lower conductive pattern (110) may function as a pad for the conductive terminal (160). The lower conductive pattern (110) may include a metallic material. For example, the lower conductive pattern (110) may include copper, tungsten, and / or titanium. The lower conductive pattern (110) may be provided in multiple numbers, and the lower conductive patterns (110) may be spaced apart from each other in a first direction (D1). In this specification, the first direction (D1) may be a direction parallel to the lower surface (100b) of the redistribution board (100). The second direction (D2) may be parallel to the lower surface (100b) of the redistribution substrate (100) and may be a direction that intersects the first direction (D1). The third direction (D1) may be a direction perpendicular to the first direction (D1) and the second direction (D2), respectively.

[0015] First to fourth insulating layers (101, 103, 105, 107) may be provided on the lower conductive patterns (110). The first insulating layer (101) may cover the upper surfaces and sides of the lower conductive patterns (110). The first insulating layer (101) may be the outermost insulating layer among the first to fourth insulating layers (101, 103, 105, 107). The lower surface of the first insulating layer (101) may be the lower surface (100b) of the redistribution board (100). The lower surface of the first insulating layer (101) may be disposed at substantially the same level as the lower surfaces of the lower conductive patterns (110). For example, the lower surface of the first insulating layer (101) may be coplanar with the lower surfaces of the lower conductive patterns (110). In this specification, the level may refer to a vertical level, and the difference in level may be measured in a direction perpendicular to the lower surface (100b) of the redistribution substrate (100). The first insulating layer (101) may include an organic material, for example, a photosensitive polymer. In this specification, the photosensitive polymer may include at least one of, for example, a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer. The first insulating layer (101) may be a positive type photosensitive polymer, but is not limited thereto.

[0016] A second insulating layer (103), a third insulating layer (105), and a fourth insulating layer (107) may be provided sequentially on the first insulating layer (101). The second insulating layer (103) may cover the upper surface of the first insulating layer (101). The third insulating layer (105) may cover the upper surface of the second insulating layer (103). The fourth insulating layer (107) may cover the upper surface of the third insulating layer (105). The upper surface of the fourth insulating layer (107) may be the upper surface (100a) of the redistribution board (100). The first insulating layer (101), the second insulating layer (103), the third insulating layer (105), and the fourth insulating layer (107) may each contain the same material. The second insulating layer (103), the third insulating layer (105), and the fourth insulating layer (107) may include, for example, a photosensitive polymer. The interfaces between the first insulating layer (101) and the second insulating layer (103), between the second insulating layer (103) and the third insulating layer (105), and between the third insulating layer (105) and the fourth insulating layer (107) may not be distinct, but are not limited thereto. The sides of the first insulating layer (101), the sides of the second insulating layer (103), the sides of the third insulating layer (105), and the sides of the fourth insulating layer (107) may be vertically aligned. The sides of the first redistribution board (100) may include the sides of the first insulating layer (101), the sides of the second insulating layer (103), the sides of the third insulating layer (105), and the sides of the fourth insulating layer (107).

[0017] The redistribution patterns (120) may be provided sequentially in a third direction (D3) from the upper surface of each of the lower conductive patterns (110). The redistribution patterns (120) may be provided inside the first to fourth insulating layers (101, 103, 105, 107). The redistribution patterns (120) may be surrounded by the first to fourth insulating layers (101, 103, 105, 107).

[0018] Each of the redistribution patterns (120) may include a barrier pattern (121) and a conductive pattern (123) provided on the barrier pattern (121). The conductive pattern (123) may be provided on the barrier pattern (121). The barrier pattern (121) may include copper, titanium, titanium nitride, and / or tantalum nitride. The conductive pattern (123) may include a metallic material, for example, copper, titanium, and / or an alloy thereof.

[0019] Each of the rewiring patterns (120) may include a via portion (120V) and a wiring portion (120W). The wiring portion (120W) is provided on the via portion (120V) and may be connected to the via portion (120V). The wiring portion (120W) may have a greater width or a greater length than the via portion (120V). The wiring portion (120W) may have a long axis extending parallel to the first direction (D1). The wiring portion (120W) is a portion extending parallel to the first direction (D1), and the via portion (120V) may be a portion protruding from the wiring portion (120W) toward the lower surface (100b) of the rewiring board (100). The rewiring patterns (120) can be aligned such that via portions (120V) face the lower surface (100b) of the rewiring board (100). Each via portion (120V) of the rewiring patterns (120) can come into contact with the upper surface of any of the lower conductive patterns (110) or with a wiring portion (120W) of any of the adjacent rewiring patterns (120). Each wiring portion (120W) of the rewiring patterns (120) can come into contact with a via portion (120V) of any of the adjacent rewiring patterns (120), a top conductive pattern (150), or a via portion (130V) of a dummy rewiring pattern (130).

[0020] For example, via portions (120V) of the lower conductive patterns (110) and the closest rewiring patterns (120) may each come into contact with the upper surface of the lower conductive patterns (110). The conductive patterns (123) of the rewiring patterns (120) may not come into direct contact with the lower conductive patterns (110). Barrier patterns (121) may be interposed between the conductive patterns (123) of the rewiring patterns (120) and the upper surfaces of the lower conductive patterns (110). The barrier patterns (121) may come into direct contact with the upper surface of the lower conductive patterns (110). As another example, via portions (120V) of some of the rewiring patterns (120) may each come into contact with the upper surfaces of the adjacent rewiring patterns (120).

[0021] Each of the via portion (120V) and the wiring portion (120W) may include a barrier pattern (121) and a conductive pattern (123). The barrier pattern (121) of the first via portion (120V) may be directly connected to the barrier pattern (121) of the first wiring portion (120W) without an interface. The barrier pattern (121) may be provided on the bottom surface of the conductive pattern (123) of the via portion (120V) and may be interposed between the side and adjacent insulating layer of the conductive pattern (123) of the via portion (120V) and between the bottom surface and adjacent insulating layer of the conductive pattern (123) of the wiring portion (120W). The barrier pattern (121) may not extend onto the side and top surfaces of the conductive pattern (123) of the wiring portion (120W). The conductive pattern (123) of the via portion (120V) can be directly connected to the conductive pattern (123) of the wiring portion (120W).

[0022] An upper conductive pattern (150) may be provided on adjacent redistribution patterns (120). Each upper conductive pattern (150) may include a barrier pattern and a conductive pattern disposed on said barrier pattern. The upper conductive pattern (150) may include a via portion connected to any one of the adjacent redistribution patterns (120) and a pad portion on said via portion. The pad portion may be exposed by a fourth insulating layer (107). The upper conductive pattern (150) may define a location where first connection terminals (350) are provided. The upper conductive pattern (150) may be connected to an adjacent redistribution pattern (120). More specifically, the upper conductive pattern (150) may be in contact with a conductive pattern (123) of an adjacent redistribution pattern (120). The upper conductive pattern (150) may include a conductive material. For example, the upper conductive pattern (150) may include a metal such as copper, titanium, aluminum, tungsten, and / or an alloy thereof. The number of the stacked first to fourth lower insulating layers (101, 103, 105, 107) and the number of redistribution patterns (150) are not limited to those illustrated and may vary in many ways.

[0023] Referring to FIG. 2a and FIG. 2b together, the redistribution substrate (100) may have first trenches (TR1). The first trenches (TR1) may be recessed regions of the upper surface (100a) of the redistribution substrate (100). The first trenches (TR1) may overlap with the first semiconductor chip (210) in a planar view. Each of the first trenches (TR1) may overlap with capacitor chips (400) in a planar view. For example, one capacitor chip (400) corresponding to the interior of one of the first trenches (TR1) may be placed. Each of the first trenches (TR1) may expose the upper surface (103a) of the second insulating layer (103), the side surface (105c) of the third insulating layer (105), and the side surface (107c) of the fourth insulating layer (107). The bottom surface (103a) of each of the first trenches (TR1) may be the top surface (103a) of the second insulating layer (103), and the inner wall of each of the first trenches (TR1) may include the side surface (105c) of the third insulating layer (105) and the side surface (107c) of the fourth insulating layer (107). The bottom surface (103a) of each of the first trenches (TR1) may be spaced vertically apart from the bottom surface (400b) of each of the capacitor chips (400). The width (W2) of each of the first trenches (TR1) in the first direction may be greater than the width (W1) of each of the capacitor chips (400) in the first direction (D1). The width (W2) of each of the first trenches (TR1) in the first direction may be 20 μm or more and 50 μm or less. The height (H2) of each of the first trenches (TR1) in the third direction (D3) may be 2 μm or more and 30 μm or less. The ratio of the height (H2) of each of the first trenches (TR1) to the height (H0) of the redistribution substrate (100) may be 0.1 or more and 0.5 or less.

[0024] A blocking insulation pattern (BP) may be provided between the first trenches (TR). More specifically, the blocking insulation pattern (BP) may define the first trenches (TR). For example, one inner wall of each of the first trenches (TR) may be a side (BPc) of the blocking insulation pattern (BP). The blocking insulation pattern (BP) may be placed between the capacitor chips (400). The blocking insulation pattern (BP) may include a first blocking insulation pattern (105B) and a second blocking insulation pattern (107B) stacked in turn. The first blocking insulation pattern (105B) may be formed simultaneously with the third insulation layer (105), and the second blocking insulation pattern (107B) may be formed simultaneously with the fourth insulation layer (107). The blocking insulation pattern (BP) may include the same material as the first to fourth insulation layers (101, 103, 105, 107).

[0025] Stack vias (SP) may be provided on the redistribution patterns (120). More specifically, the stack vias (SP) may penetrate the blocking insulation pattern (BP). The stack vias (SP) may be electrically connected to the first semiconductor chip (210) and the redistribution patterns (120). That is, the first semiconductor chip (210) may be electrically connected to the redistribution substrate (100) through the stack vias (SP). The stack vias (SP) may include a plurality of vertically stacked conductive vias (170). Each of the conductive vias (170) may be substantially identical to the redistribution patterns (120) or the upper conductive patterns (150).

[0026] More specifically, each of the conductive vias (170) may include a wiring portion and a via portion. The wiring portion of each of the conductive vias (170) may be provided on the via portion and may be connected to the via portion. The wiring portion may be a portion extending parallel to the first direction (D1), and the via portion may be a portion protruding from the wiring portion toward the lower surface (100b) of the redistribution board (100). The conductive vias (170) may be aligned such that the via portions face toward the lower surface (100b) of the redistribution board (100). The via portion of each of the conductive vias (170) may contact the wiring portion of an adjacent conductive via (170) or the wiring portion (120W) of any one of the adjacent redistribution patterns (120). The wiring portion of each of the conductive vias (170) may contact the via portion of any one of the adjacent conductive vias (170) or the first connection terminals (350). For example, the wiring portion of the uppermost conductive via (170) among the conductive vias (170) may be in contact with the first connection terminal (350), and the via portion of the lowermost conductive via (170) among the conductive vias (170) may be in contact with the rewiring patterns (120).

[0027] Each of the conductive vias (170) may include a barrier pattern (171) and a conductive pattern (173). The barrier pattern (171) of the conductive vias (170) may be identical to the barrier pattern (121) of the rewiring patterns (120). The conductive pattern (173) of the conductive vias (170) may be identical to the conductive pattern (123) of the rewiring patterns (120). Dummy rewiring patterns (130) may be provided on the rewiring patterns (120). Hereinafter, for convenience of explanation, the description will be based on a single dummy rewiring pattern (130). The dummy rewiring pattern (130) may be provided inside the first trench (TR1). The dummy rewiring pattern (130) may include a dummy barrier pattern (131) and a dummy conductive pattern (133). A dummy conduction pattern (133) may be provided on a dummy barrier pattern (131). The dummy barrier pattern (131) may include copper, titanium, titanium nitride, and / or tantanium nitride. The dummy conduction pattern (133) may include a metallic material, for example, copper, titanium, and / or an alloy thereof. The dummy redistribution pattern (130) may not be electrically connected to the first semiconductor chip (210) or capacitor chips (400).

[0028] The dummy redistribution pattern (130) may include a via portion (130V) and a wiring portion (130W). The wiring portion (130W) of the dummy redistribution pattern (130) is provided on the via portion (130V) of the dummy redistribution pattern (130) and may be connected to the via portion (130V) of the dummy redistribution pattern (130). The wiring portion (130W) may have a greater width or a greater length than the via portion (130V). The wiring portion (130W) may have a long axis extending parallel to the first direction (D1). The via portion (130V) of the dummy redistribution pattern (130) may penetrate the upper part of the second insulating layer (103) and come into contact with the wiring portion (120W) of the adjacent redistribution pattern (120). The via portion (130V) of the dummy redistribution pattern (130) may be surrounded by a second insulating layer (103). The wiring portion (130W) of the dummy redistribution pattern (130) may be provided on the upper surface (103a) of the second insulating layer (103). The wiring portion (130W) of the dummy redistribution pattern (130) may be exposed by a first trench (TR1). More specifically, the upper surface (130a) of the wiring portion (130W) and the side surface (130c) of the wiring portion (130W) may be exposed by the first trench (TR1).

[0029] The upper surface (130a) of the wiring portion (130W) may be defined as the upper surface (130a) of the dummy redistribution pattern (130), and the side surface (130c) of the wiring portion (130W) may be defined as the side surface (130c) of the dummy redistribution pattern (130). The upper surface (130a) of the dummy redistribution pattern (130) may be provided at a different level vertically from the bottom surface (103a) of the first trench (TR1). For example, the upper surface (130a) of the dummy redistribution pattern (130) may be provided at a higher level than the bottom surface (103a) of the first trench (TR1). The upper surface (130a) of the dummy redistribution pattern (130) may be provided at a lower level than the bottom surface (400b) of the capacitor chip (400). However, unlike what is described, the upper surface (130a) of the dummy rewiring pattern (130) may be coplanar with the bottom surface (103a) of the first trench (TR1).

[0030] A first semiconductor chip (210) may be mounted on the upper surface (100a) of a redistribution board (100). The first semiconductor chip (210) may be placed on the center region of the redistribution board (100). The first semiconductor chip (210) may overlap with the first trenches (TR1) in a planar view. The first semiconductor chip (200) may include first chip pads (213) and second chip pads (215). The first chip pads (213) and second chip pads (215) may include a metallic material, for example, copper, tungsten, titanium, and / or an alloy thereof. The first chip pads (213) and second chip pads (215) may be exposed on the lower surface (210b) of the first semiconductor chip (200). The first chip pads (213) can connect the first semiconductor chip (210) and the rewiring board (100), and the second chip pads (215) can connect the first semiconductor chip (210) and the capacitor chip (400). Integrated circuits may be provided within the first semiconductor chip (210). The integrated circuits may be disposed adjacent to the lower surface (210b) of the first semiconductor chip (210). The integrated circuits may include memory circuits, logic circuits, and / or a combination thereof. The first chip pads (213) and the second chip pads (215) may be electrically connected to the integrated circuits. A first connection terminal (350) may be interposed between the first chip pads (213) and the upper conductive patterns (150), respectively. The first connection terminal (350) may include at least one of solder, a pillar, and a bump. The first connection terminal (350) may include a conductive material such as a solder material. The solder material may include, for example, tin, bismuth, lead, silver, or an alloy thereof. The first semiconductor chip (210) may be electrically connected to the redistribution board (100) through the first connection terminal (350). In this specification, being connected may include being physically connected or being electrically connected directly or indirectly.

[0031] Capacitor chips (400) may be mounted on the lower surface (210b) of the first semiconductor chip (210). The capacitor chips (400) may be placed inside the first trenches (TR1). The capacitor chips (400) may be spaced horizontally apart with a blocking insulation pattern (BP) or a stack via (SP) in between. Each of the capacitor chips (400) may include capacitor chip pads (411). The capacitor chip pads (411) may include a metallic material, for example, copper, tungsten, titanium, and / or an alloy thereof. According to one embodiment, a first connection terminal (350) may be interposed between each of the capacitor chip pads (411) and the second chip pads (215). Each of the capacitor chips (400) may be electrically connected to the first semiconductor chip (210) through the first connection terminal (350). The width (W1) of each capacitor chip (400) in the first direction (D1) may be smaller than the width of the first semiconductor chip (210) in the first direction (D1). For example, the width (W1) of the capacitor chip (400) in the first direction (D1) may be 10 μm or more and 30 μm or less. The height (H1) of the capacitor chip (400) in the third direction (D3) may be 1 μm or more and 20 μm or less. The planar area of ​​each capacitor chip (400) may be smaller than the planar area of ​​the first semiconductor chip (210).

[0032] Meanwhile, according to another embodiment of the present invention, as shown in FIG. 2c, a first connection terminal (350) between the capacitor chip pads (411) and the second chip pads (215) may be omitted. The upper surfaces of the capacitor chip pads (411) and the lower surfaces of the second chip pads (215) may each come into direct contact. Accordingly, the capacitor chip (400) may be electrically connected to the first semiconductor chip (210) through the capacitor chip pads (411) and the second chip pads (215).

[0033] Figure 4 is an enlarged view of area B of Figure 2a. Figure 5 is a plan view cut along the line II-II' of Figure 4.

[0034] Referring to FIGS. 4 and 5, another capacitor chip in an embodiment of the present invention may include a capacitor substrate (430), a common insulating film (440), a first conductive layer (460), a capacitor insulating film (420), a capacitive structure (459), contacts (471, 473), wirings (417), vias (415), and a capacitor chip pad (411).

[0035] A capacitor substrate (430) may be provided. The capacitor substrate (430) may include, for example, a silicon substrate. A common insulating film (440) may be provided on the upper surface of the capacitor substrate (430). The common insulating film (440) may include an insulating material, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The common insulating film (440) may include a single layer or multiple layers. A first conductive layer (460) may be provided on the common insulating film (440). The first conductive layer (460) may include a metallic material, for example, copper, tungsten, and / or titanium.

[0036] A capacitor insulating film (420) having a plurality of through holes (TR2) in its lower portion may be provided on the first conductive layer (460). The capacitor insulating film (420) may include an insulating material, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0037] A capacitive structure (459) may be provided inside the capacitor insulating film (420). The capacitive structure (459) may be provided on the first conductive layer (460), and the capacitor insulating film (420) may surround the capacitive structure (459). The capacitive structure (459) may include first to fourth layers (451, 453, 455, 457) that fill the through holes (TR2) of the capacitor insulating film (420). In a planar view, the spacing (L1) of the through holes (TR2) may be 100 nm or more and 200 nm or less. The first to third layers (451, 453, 455) may be provided in sequence on the inner walls of the through holes (TR2). The first to third layers (451, 453, 455) may conformally cover the inner walls of the through holes (TR2). A first layer (457) may be provided on the third layer (455). A fourth layer (457) may fill the remaining portion of the through holes (TR2). Accordingly, as shown in FIG. 2c, the first to fourth layers (451, 453, 455, 457) may have a circular or circular ring shape in a planar view. The fourth layer (457) may include via portions (457V) extending into the interior of the through holes (TR2) and a horizontal portion (457P) provided on the via portions (457V). The via portions (457V) may be connected to the horizontal portion (457P). The first to fourth layers (451, 453, 455, 457)) may comprise, for example, titanium nitride and / or silicon germanium. The capacitive structure (459) may be a portion within the capacitor chip (400) where charge is substantially accumulated.

[0038] First contacts (471) may be provided on a capacitive structure (459), and second contacts (473) may be provided on a first conductive layer (460). Via (415) and wiring (417) may be provided on the first contacts (471) and the second contacts (473). The vias (415) and wiring (417) may electrically connect the first contacts (471) and the second contacts (473) with the capacitor chip pads (411). The first contacts (471), the second contacts (473), the vias (415), and the wiring (417) may comprise a metallic material, for example, copper, titanium, and / or tungsten.

[0039] Referring again to FIGS. 1 and FIGS. 2a, a chip stack (250) may be mounted on a rewiring substrate (100). From a planar perspective, the chip stack (250) may be placed on an outer region of the rewiring substrate (100). A plurality of chip stacks (250) may be provided. A first semiconductor chip (210) may be placed between the chip stacks (250). The chip stacks (250) may be spaced apart from each other in a first direction (D1) or a second direction (D2). The chip stacks (250) may be spaced apart from the first semiconductor chip (210) in a first direction (D1) or a second direction (D2). Hereinafter, for convenience of explanation, the description will be based on a single chip stack (250).

[0040] A chip stack (250) may include a plurality of stacked second semiconductor chips (220). Each of the second semiconductor chips (220) may be identical or similar to the first semiconductor chip (210) of FIG. 1 and FIG. 2a. However, the second semiconductor chips (220) may be semiconductor chips (200) of a different type from the first semiconductor chip (210). For example, the first semiconductor chip (210) may be any one of a logic chip, a buffer chip, and a system-on-chip (SOC), and the second semiconductor chip (220) may be another one of a logic chip, a memory chip, a buffer chip, and a system-on-chip (SOC). In this specification, the memory chip may include a High Bandwidth Memory (HBM) chip. For example, the first semiconductor chip (210) may be a logic chip, and the second semiconductor chips (220) may be High Bandwidth Memory (HBM) chips. As another example, the lowest second semiconductor chip (220) is a logic chip, and the remaining second semiconductor chips (220) may be high-bandwidth memory chips.

[0041] Each of the second semiconductor chips (220) may include a lower pad (225), a through electrode (223), and an upper pad (221). The lower pad (225) and the upper pad (221) may be provided on the lower surface and the upper surface, respectively, of each second semiconductor chip (220). At least one of the lower pad (225) and the upper pad (221) may be electrically connected to the integrated circuits of the second semiconductor chip (220). The through electrode (223) may be disposed within the second semiconductor chip (220) and may be connected to the lower pad (225) and the upper pad (221). The upper second semiconductor chip (220) may include the lower pad (225) but may not include the through electrode (223) and the upper pad (221). Unlike what is illustrated, the upper second semiconductor chip (220) may further include the through electrode (223) and the upper pad (221). An interposer terminal (235) is interposed between two adjacent second semiconductor chips (220) and can be connected to a lower pad (225) and an upper pad (221), respectively. Accordingly, a plurality of second semiconductor chips (220) can be electrically connected to each other. The interposer terminal (235) may include solder, a pillar, or a bump. The interposer terminal (235) may include a solder material, but is not limited thereto.

[0042] As another example, the interposer terminal (235) may be omitted. In this case, the facing lower pad (225) and upper pad (221) of adjacent semiconductor chips (220) may be directly bonded to each other.

[0043] A first connection terminal (350) is interposed between the lower second semiconductor chip (220) and the redistribution board (100) so as to be connected to a lower pad (225) and a corresponding upper conductive pattern (150). Accordingly, the second semiconductor chips (220) can be electrically connected to the first semiconductor chip (210) and the conductive terminal (160) through the redistribution board (100). The pitch of the plurality of first connection terminals (350) may be smaller than the pitch of the conductive terminals (1600) and the pitch of the external connection terminals (840).

[0044] An underfill film (300) may be provided between the redistribution board (100) and the first semiconductor chip (210). More specifically, the underfill film (300) may fill the gap area between the redistribution board (100) and the first semiconductor chip (210) and seal the first connection terminals (350). The underfill film (300) may surround the capacitor chip (400). The underfill film (300) may be interposed between the lower surface (210b) of the first semiconductor chip (210) and the bottom surface (103a) of the first trench (TR1). The underfill film (300) may extend between the side (400c) of the capacitor chip (400) and the side (BPc) of the blocking insulation pattern (BP), and may extend between the bottom surface (400b) of the capacitor chip (400) and the bottom surface (103a) of the first trench (TR1). Accordingly, the underfill film (300) may be in direct contact with at least a portion of the bottom surface (400b), sides (400c), and top surfaces (400a) of the capacitor chip (400). The underfill film (300) may cover the top surface (130a) and sides (130c) of the dummy redistribution pattern (130). More specifically, the underfill film (300) may be in direct contact with the top surface (130a) and sides (130c) of the wiring portion (130W) of the dummy redistribution pattern (130). The underfill film (300) can fill the interior of the first trench (TR1). More specifically, the underfill film (300) can come into direct contact with the inner walls (105c, 107c) and the bottom surface (103a) of the first trench (TR1).

[0045] An underfill film (300) may be provided between the lower surface of the redistribution substrate (100) and the chip stack (250). More specifically, the underfill film (300) may extend between the upper surface (100a) of the redistribution substrate (100) and the lower surface of the lowermost second semiconductor chip (220) of the chip stack (250) to seal the first connection terminals (350). The underfill film (300) may be in direct contact with the lower surface of the lowermost second semiconductor chip (220) of the chip stack (250). The underfill film (300) may include an insulating polymer such as an epoxy-based polymer. The underfill film (300) may include a filler. The filler may include, for example, silicon oxide and / or aluminum oxide.

[0046] Second underfill patterns (320) are provided in the second gap regions between the rewiring substrate (100) and the chip stacks (2000), respectively, to seal the corresponding second bonding terminal (252). The second underfill patterns (320) may include an insulating polymer such as an epoxy-based polymer. Unlike what is illustrated, a single underfill pattern may be provided between the first gap region and the second gap region to seal the first bonding terminal (251) and the second bonding terminal (252).

[0047] An upper molding film (360) may be provided on the upper surface (100a) of the redistribution substrate (100). The upper molding film (360) may be provided on the sidewalls of the chip stacks (250) and may be interposed between the chip stacks (250) and the first semiconductor chip (210). The upper molding film (360) may comprise an insulating polymer such as an epoxy-based polymer. The upper surface of the upper molding film (360) may be coplanar with the upper surface of the first semiconductor chip (210) and the upper surfaces of the chip stacks (250). However, not limited thereto, the upper molding film (360) may cover the upper surface of the first semiconductor chip (210) and the upper surfaces of the chip stacks (250). The sides of the upper molding film (360) may be aligned perpendicularly with the sides of the redistribution substrate (100).

[0048] FIG. 3a is a plan view illustrating a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1. FIG. 3b and FIG. 3c are enlarged views for explaining a semiconductor package according to embodiments, corresponding to area A of FIG. 3a. Hereinafter, redundant descriptions are omitted, and the differences are described in detail.

[0049] Referring to FIGS. 3a and 3b, a semiconductor package according to embodiments of the present invention may include a package substrate (800), a redistribution substrate (100), a first semiconductor chip (210), a capacitor chip (400), chip stacks (250), an underfill film (300), and an upper molding film (360). The substrate (800), the first semiconductor chip (210), the capacitor chip (400), the chip stacks (250), and the upper molding film (360) may be substantially the same as those described in FIGS. 2a to 2c.

[0050] The redistribution board (100) includes a lower conductive pattern (110), redistribution patterns (120), an upper conductive pattern (140), insulating layers (101, 103, 105, 107), a blocking insulating pattern (BP), and a stack via (SP), but dummy redistribution patterns may be omitted. Accordingly, the bottom surface (103a) of each of the first trenches (TR1) may be parallel to the bottom surface (400b) of each of the capacitor chips (400) without exposing the redistribution patterns (120).

[0051] An underfill film (300) may be provided between the redistribution board (100) and the first semiconductor chip (210). More specifically, the underfill film (300) may fill the gap area between the redistribution board (100) and the first semiconductor chip (210) and seal the first connection terminals (350). The underfill film (300) may surround the capacitor chip (400). The underfill film (300) may be interposed between the lower surface (210b) of the first semiconductor chip (210) and the bottom surface (103a) of the first trench (TR1). The underfill film (300) may extend between the side surface (400c) of the capacitor chip (400) and the blocking insulation pattern (BPc), and may extend between the lower surface (400b) of the capacitor chip (400) and the bottom surface (103a) of the first trench (TR1). Accordingly, the underfill film (300) can come into direct contact with at least a portion of the bottom surface (400b), sides (400c), and top surface (400a) of the capacitor chip (400).

[0052] FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1.

[0053] Referring to FIG. 6, a semiconductor package (20) according to embodiments of the present invention may include a package substrate (800), a redistribution substrate (100), a first semiconductor chip (210), a capacitor chip (400), chip stacks (250), an underfill film (300), and an upper molding film (360). The package substrate (800), the first semiconductor chip (210), the capacitor chip (400), the chip stacks (250), the underfill film (300), and the upper molding film (360) may be substantially the same as those described in FIG. 1, FIG. 2a to 2c, FIG. 4, and FIG. 5. Hereinafter, redundant descriptions are omitted and differences are described in detail.

[0054] Referring to FIG. 6, a redistribution board (100) may be provided. The redistribution board (100) may include a lower conductive pattern (110), redistribution patterns (120), dummy redistribution patterns (130), an upper conductive pattern (140), and insulating layers (101, 103, 105, 107), but may not include a blocking insulating pattern (BP) and a stack via (SP). The insulating layers (101, 103, 105, 107) may include first to fourth insulating layers (101, 103, 105, 107). The redistribution board (100) may also be referred to as an interposer board.

[0055] The redistribution board (100) may have a first trench (TR1). The first trench (TR1) may be a recessed area on the upper surface (100a) of the redistribution board (100). The first trench (TR1) may overlap with the first semiconductor chip (210) in a planar view. A plurality of capacitor chips (400) may be mounted on the lower surface of the first semiconductor chip (210). The first trench (TR1) may overlap with the capacitor chips (400) in a planar view. A plurality of capacitor chips (400) may be placed inside the first trench (TR1). When a plurality of capacitor chips (400) are placed inside a single first trench (TR1), space is saved compared to when a single capacitor chip (400) is placed inside a single first trench (TR1), and the integration density of the semiconductor package may be improved.

[0056] FIG. 7 is a cross-sectional view illustrating a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1.

[0057] Referring to FIG. 7, a semiconductor package (30) according to embodiments of the present invention may further include a package substrate (800), a redistribution substrate (100), a first semiconductor chip (210), a capacitor chip (400), chip stacks (250), an upper molding film (360), a lower molding film (290), and a conductive post (217). The package substrate (800), the first semiconductor chip (210), the capacitor chip (400), the chip stacks (250), and the upper molding film (360) may be substantially the same as those described in FIG. 1 to 6. Hereinafter, redundant descriptions are omitted and differences are described in detail.

[0058] Referring to FIG. 7, the redistribution substrate (100) may include a lower conductive pattern (110), redistribution patterns (120), and insulating layers (101, 103, 105, 107). The insulating layers (101, 103, 105, 107, 109) may include first to fifth insulating layers (101, 103, 105, 107). The redistribution substrate (100) may also be referred to as an interposer substrate.

[0059] The redistribution substrate (100) may not include the dummy redistribution patterns (130) of FIG. 2A. The redistribution patterns (120) may be provided inside the first to fifth insulating layers (101, 103, 105, 107, 109). The redistribution patterns (120) may be surrounded by the first to fifth insulating layers (101, 103, 105, 107, 109). The redistribution patterns (120) may be provided sequentially in a third direction (D3) from the upper surface of each of the plurality of lower conductive patterns (110).

[0060] Each of the redistribution patterns (120) may include a conductive pattern (123) and a barrier pattern (121) disposed on the conductive pattern (123). The barrier pattern (121) may include a conductive material such as copper, titanium, and / or an alloy thereof. The conductive pattern (123) may include a metallic material, for example, copper.

[0061] Each of the rewiring patterns (120) may include a via portion (120V) and a wiring portion (120W). The via portion (120V) may be provided on the wiring portion (120W) and may be connected to the wiring portion (120W). The wiring portion (120W) may have a greater width or a greater length than the via portion (120V). The wiring portion (120W) may have a long axis extending in a first direction. The wiring portion (120W) may be a portion extending parallel to the first direction (D1), and the via portion (120V) may be a portion protruding from the wiring portion (120W) toward the upper surface (100a) of the rewiring board (100). The rewiring patterns (120) may be aligned such that the via portions (120V) face toward the upper surface (100a) of the rewiring board (100). Each wiring portion (120W) of the rewiring patterns (120) may come into contact with the upper surface of any one of the lower conductive patterns (110) or with a via portion (120V) of any one of the adjacent rewiring patterns (120). Each via portion (120V) of the rewiring patterns (120) may come into contact with a wiring portion (120W) of any one of the adjacent rewiring patterns (120) or with a lower pad (225).

[0062] A lower molding film (290) may be provided on the lower surface of the first semiconductor chip (210). The lower molding film (290) may be interposed between the upper surface (100a) of the redistribution substrate (100) and the lower surface of the first semiconductor chip (210). The lower molding film (290) may seal the first connection terminals (350), capacitor chips (400), and conductive posts (217). The lower molding film (290) may include an insulating polymer such as an epoxy-based polymer. The sides of the lower molding film (290) may be aligned perpendicularly with the sides of the first semiconductor chip (210), but are not limited thereto.

[0063] Conductive posts (217) penetrating the lower molding film (290) may be provided within the lower molding film (290). The conductive posts (217) may be interposed between the third chip pads (219) and the first chip pads (213) provided on the lower surface of the lower molding film (290). The conductive posts (217) and the third chip pads (219) may comprise a metallic material, for example, copper, tungsten, and / or titanium. The conductive posts (217) may electrically connect the first chip pads (213) and the third chip pads (219). The upper molding film (360) may cover the sides of the first semiconductor chip (210), the sides of the chip stacks (250), and the sides of the lower molding film (290).

[0064] FIG. 8 is a plan view illustrating a semiconductor package according to embodiments. FIG. 9 and FIG. 10 are cross-sectional views illustrating a semiconductor package according to embodiments, corresponding to a cross section cut along line III-III' of FIG. 8.

[0065] Referring to FIGS. 8 and 9, a semiconductor package (40) according to embodiments of the present invention may include a first semiconductor package (1) and a second semiconductor package (2) provided on the first semiconductor package (1).

[0066] The first semiconductor package (1) may include a first rewiring substrate (100), a first semiconductor chip (210), a capacitor chip (400), an underfill film (300), a first upper molding film (360), a conductive structure (365), an intermediate connection terminal (380), and an intermediate insulating film (370).

[0067] The first redistribution substrate (100) and the first upper molding film (360) may be substantially identical to the redistribution substrate (100) and upper molding film (360) described in FIGS. 1 to 2b, respectively, and the first semiconductor chip (210) and capacitor chip (400) may be substantially identical to those described in FIGS. 1 to 2b.

[0068] The second semiconductor package (2) may include a second rewiring substrate (500), a lower connection pad (510), a second semiconductor chip, and a second upper molding film (600).

[0069] A first semiconductor chip (210) may be mounted on a redistribution board (100). An underfill film (300) may be provided between the upper surface of the redistribution board (100) and the first semiconductor chip (210). The underfill film (300) may fill the interior of the first trenches (TR1). The underfill film (300) may be vertically overlapped with the first semiconductor chip (210) and may be spaced apart from an adjacent conductive structure (365).

[0070] A first upper molding film (360) may be provided on the upper surface of a redistribution substrate (100). The first upper molding film (360) may cover the upper surface (100a) of the redistribution substrate (100). The first upper molding film (360) may include the same material as the upper molding film (360) described in FIGS. 1 to 2b. The first upper molding film (360) may cover the upper surface and sides of the first semiconductor chip (210) and may cover the sides of the underfill film (300). The first upper molding film (360) may surround the sides of the conductive structure (365).

[0071] The conductive structure (365) can penetrate the first upper molding film (360). The conductive structure (365) can extend parallel to the side of the first semiconductor chip (210). The conductive structure (365) can be interposed between the upper connection pad (367) and the upper conductive pattern (150). The conductive structure (365) can electrically connect the first redistribution board (100) and the second redistribution board (500).

[0072] An upper connection pad (367) may be provided on the upper surface of a conductive structure (365). The upper surface of the upper connection pad (367) may be exposed by an intermediate insulating film (370). The upper connection pad (367) may define a location where an intermediate connection terminal (380) is provided. The upper connection pad (367) and the conductive structure (365) may comprise a metallic material, for example, copper, tungsten, and / or titanium.

[0073] An intermediate connection terminal (380) may be provided on the upper surface of the upper connection pad (367) exposed by the intermediate insulating film (370). The intermediate connection terminal (380) may include at least one of solder, a pillar, and a bump. The intermediate connection terminal (380) may include a conductive material such as a solder material. The solder material may include, for example, tin, bismuth, lead, silver, or an alloy thereof.

[0074] An intermediate insulating film (370) may be provided on the upper surface of the first upper molding film (360). The intermediate insulating film (370) may cover the upper surface of the first upper molding film (360) but may not cover the upper surface of the upper connecting pad (367). The intermediate insulating film (370) may include an insulating material, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0075] A second semiconductor package (20) may be provided on the first semiconductor package (1). More specifically, a second redistribution substrate (500) may be provided on a plurality of intermediate connection terminals (380). The second redistribution substrate (500) may include first to third upper insulating layers (501, 503, 505) and upper redistribution patterns (520, 530). Unlike the first redistribution substrate (100), the second redistribution substrate (500) may not include trenches. The first to third upper insulating layers (501, 503, 505) and upper redistribution patterns (520, 530) of the second redistribution substrate (500) may be substantially identical to the first to fourth insulating layers (101, 103, 105, 107) and redistribution patterns (120) of the first redistribution substrate (100).

[0076] A lower connection pad (510) may be provided on the lower surface of the lowest redistribution patterns (530) among the upper redistribution patterns (520, 530). The lower connection pad (510) may serve as a pad for the intermediate connection terminal (380). The lower connection pad (510) may electrically connect the upper redistribution patterns (520, 530) to the intermediate connection terminal (380).

[0077] An upper conductive pattern (540) may be provided on the upper surface of the uppermost redistribution patterns (520) among the upper redistribution patterns (520, 530). The upper conductive pattern (540) may be substantially identical to the upper conductive pattern (150) of the first semiconductor package (1). A second semiconductor chip (220) may be mounted on the upper conductive pattern (540). The second semiconductor chip (220) may be substantially identical to the second semiconductor chips (220) described in FIGS. 1 to 2c. The second semiconductor chip (220) may include a lower pad (225), and second connection terminals (650) may be provided between the lower pad (225) and the upper conductive pattern (540). The second connection terminals (650) may be substantially identical to the first connection terminals (350) described in FIGS. 1 to 2c.

[0078] A second upper molding film (600) may be provided on the second redistribution substrate (500). The second upper molding film (600) may contain the same material as the first upper molding film (360). The third upper molding film (600) may cover the upper surface and sides of the second semiconductor chip (220) and seal the second connection terminals (650). The sides of the second upper molding film (600) may be aligned perpendicularly with the sides of the second redistribution substrate (500), but are not limited thereto.

[0079] Referring to FIG. 10, a semiconductor package (50) according to embodiments of the present invention may include a first semiconductor package (1) and a second semiconductor package (2) provided on the first semiconductor package (1).

[0080] The first semiconductor package (1) may include a first rewiring substrate (100), a first semiconductor chip (210), a capacitor chip (400), an underfill film (300), a first upper molding film (360), a connecting substrate (365, 367, 369), an intermediate connecting terminal (380), and an intermediate insulating film (370).

[0081] The first redistribution substrate (100) and the first upper molding film (360) may be substantially identical to the redistribution substrate (100) and upper molding film (360) described in FIGS. 1 to 2b, respectively, and the first semiconductor chip (210) and capacitor chip (400) may be substantially identical to those described in FIGS. 1 to 2b.

[0082] The second semiconductor package (2) may be substantially the same as the second semiconductor package (2) described in FIG. 10.

[0083] A connecting board (365, 367, 369) may be disposed on the first redistribution board (100). The connecting board (365, 367, 369) may have a substrate hole penetrating its interior. For example, the connecting board (365, 367, 369) may be manufactured by forming a substrate hole penetrating the upper and lower surfaces of a printed circuit board. From a planar perspective, the substrate hole may be formed in the center portion of the first redistribution board (100). The first semiconductor chip (200) may be disposed within the substrate hole of the connecting board (365, 367, 369). The first semiconductor chip (200) may be disposed spaced apart from the inner wall of the connecting board (365, 367, 369).

[0084] The connecting substrate (365, 367, 369) may include a base layer (369) and a conductive structure (365, 367). The base layer (369) may be a single layer or may include multiple stacked layers. The base layer (369) may include an insulating material. For example, the base layer (369) may include a carbon-based material, a ceramic, or a polymer. A substrate hole may penetrate the base layer (369). The conductive structure (365, 367) may be provided within the base layer (369). The conductive structure (365, 367) may include pads (367) and vias (365). The pads (367) may be exposed on the lower or upper surface of the connecting substrate (365, 367, 369). The vias (365) may be provided between the pads (367). vias (365) penetrate the base layer (369) and can be connected to pads (367). The pads (367) and the conductive vias (365) may be vertically aligned, but are not limited thereto. The conductive structure (365, 367) may comprise a metal. The conductive structure (365, 367) may comprise, for example, at least one selected from copper, aluminum, tungsten, titanium, tantalum, iron, and alloys thereof.

[0085] First connection terminals (350) may be disposed between the first redistribution board (100) and the connection boards (365, 367, 369). The first connection terminals (350) may be interposed between any one of the pads (367) and the corresponding upper conductive pattern (150) to be connected to any one of the pads (367) and the corresponding upper conductive pattern (150). The conductive structures (365, 367) may be electrically connected to the first redistribution board (100) by the first connection terminals (350). The first connection terminals (350) may include at least one of a solder ball, a bump, and a pillar. The first connection terminals (350) may include a metallic material. An underfill film (300) is provided in the gap between the first redistribution board (100) and the connection boards (365, 367, 369) to seal the first connection terminals (350). The underfill film (300) may include an insulating polymer.

[0086] [Manufacturing Method]

[0087] FIGS. 11 to 19 are drawings for explaining a method of manufacturing a semiconductor package according to embodiments.

[0088] Referring to FIG. 11, lower conductive patterns (110), first to third insulating layers (101, 103, 105), and redistribution patterns (120) may be formed on a carrier substrate (900).

[0089] A release layer (not shown) may be interposed between the carrier substrate (900) and the lower conductive patterns (110) and between the carrier substrate (900) and the first insulating layer (101). The release layer (not shown) may attach the first to third insulating layers (101, 103, 105) to the carrier substrate (900). Forming the redistribution substrate (100) may include forming a seed layer, forming a resist pattern having an opening on the seed layer, forming a conductive layer using the seed layer as an electrode within the opening, removing the resist pattern and patterning the seed layer, depositing an insulating layer, and performing a patterning process.

[0090] For example, a seed layer (not shown) can be formed on a carrier substrate (900). The seed layer can cover the upper surface of the carrier substrate (900). The seed layer can be formed by performing a deposition process. The seed layer may include a conductive material. For example, the seed layer may include at least one of copper, titanium, and alloys thereof.

[0091] A resist pattern having an opening can be formed on a seed layer. The opening can define the shape of a lower conductive pattern (110). The opening of the resist pattern can expose the upper surface of the seed layer. The resist pattern may include a photoresist material.

[0092] A lower conductive pattern (110) can be formed using a seed layer within the opening as an electrode. The lower conductive pattern (110) can be formed by performing an electroplating process using the seed layer as an electrode. The electroplating process can be terminated before the lower conductive pattern (110) extends onto the upper surface of the resist pattern. The resist pattern can be removed by performing a stripping process. Accordingly, the seed layer provided under the resist pattern can be exposed to the outside.

[0093] An etching process can be performed on the exposed seed layer to pattern the seed layer. Accordingly, the upper surface of the carrier substrate (900) can be exposed between the lower conductive patterns (110). A first insulating layer (101) can be formed on the lower conductive patterns (110). The first insulating layer (101) can conformally cover the upper surface and side of the exposed carrier substrate (900) and the lower conductive patterns (110). The first insulating layer (101) can be formed by a coating process such as skin coating or slit coating. By patterning the first insulating layer (101), via holes can be formed to form via portions of the redistribution patterns (120). A curing process can be performed on the first insulating layer (101) to harden the first insulating layer (101). The process described above can be repeated to form a lower conductive pattern (110), first to third insulating layers (101, 103, 105), and redistribution patterns (120).

[0094] Referring to FIG. 12, via holes (TRV1) and a first preliminary trench (TR1p) can be formed by patterning a third insulating layer. Patterning of the third insulating layer can be carried out by an exposure process and a development process. The via holes (TRV1) can expose the upper surfaces (120a) of the redistribution patterns (120). The first preliminary trench (TR1p) can expose the upper surface (130a) and side surfaces (130c) of each of the dummy redistribution patterns (130).

[0095] Referring to FIG. 13, redistribution patterns (120) filling the via holes (TRV1) and a fourth insulating layer (107) covering the dummy redistribution patterns may be formed. The redistribution patterns (120) filling the via holes (TRV1) may be formed in the same manner as described in FIG. 12. The fourth insulating layer (107) may be formed in the same manner as the first insulating layer (101). The fourth insulating layer (107) may cover the uppermost redistribution patterns (120) and fill the interior of the first preliminary trench (TR1p). Accordingly, the upper and side surfaces of the dummy redistribution patterns (130) provided within the first preliminary trench (TR1p) may be covered by the fourth insulating layer (107). At this time, the upper surface of the fourth insulating layer (107) may be undulated along the inner wall and bottom surface of the redistribution patterns (120) and the first preliminary trench (TR1p), but is not limited thereto.

[0096] Referring to FIG. 14, via holes (TRV1) and a first trench (TR1) can be formed by patterning the fourth insulating layer (107). The patterning of the fourth insulating layer (107) can be performed in the same way as the patterning of the third insulating layer in FIG. 13. The via holes (TRV1) can expose the upper surfaces (120a) of the top redistribution patterns (120). The first preliminary trench (TR1p) can expose the upper surface (130a) and sides (130c) of each of the dummy redistribution patterns (130). At this time, the bottom surface of the first trench (TR1) may be the exposed upper surface (103a) of the second insulating layer (103). The inner wall of the first trench (TR1) may include the side (105c) of the third insulating layer (105) and the side (107c) of the fourth insulating layer (107).

[0097] Referring to FIG. 15, a first redistribution substrate (100) can be manufactured by forming upper conductive patterns (150) that fill the interior of via holes (TRV1). The upper conductive patterns (150) can be formed in the same way as the redistribution patterns (120) described in FIG. 12.

[0098] When a power signal is applied to a semiconductor chip mounted inside a semiconductor package through an external terminal, the operational reliability of the semiconductor package is improved as the noise of the power signal is removed. In the semiconductor package according to the embodiments of the present invention, a capacitor chip (400) capable of removing the noise is mounted on the lower surface of a first semiconductor chip (210), and the capacitor chip (400) is placed inside the first trench (TR1) of the redistribution board (100) to efficiently utilize space. In particular, in the method of manufacturing the first trench (TR1), the first trench (TR1) is formed simultaneously while forming the redistribution board (100), without forming the first trench (TR1) through a separate process after forming the redistribution board (100). Accordingly, the process steps are shortened, process costs are reduced, and a thin semiconductor package can be provided.

[0099] Referring to FIG. 16, a preliminary first semiconductor substrate (210p) may be prepared. First chip pads (213) and second chip pads (215) may be formed on one side of the preliminary first semiconductor substrate (210p). Capacitor chips (400) may be mounted on the upper surface of the second chip pads (215). Multiple capacitor chips (400) may be mounted. Subsequently, the preliminary first semiconductor substrate (210p) may be sawed along a cutting line (SL) to manufacture first semiconductor chips (210) on which capacitor chips (400) are mounted.

[0100] Referring to FIG. 17, the first semiconductor chips (210) on which the capacitor chips (400) are mounted can be mounted on the upper surface (100a) of the redistribution board (100) described in FIG. 15. When mounting the first semiconductor chips (210), the capacitor chips (400) can be aligned toward the upper surface (100a) of the redistribution board (100). The capacitor chips (400) can be provided inside the first trench (TR1) of the redistribution board (100). The sides and bottom surfaces of the capacitor chips (400) can be spaced apart from the inner walls and bottom surfaces of the first trench (TR1). Chip stacks (250) can be mounted on the upper surface of the redistribution board (100). The chip stacks (250) can be mounted spaced horizontally apart from the first semiconductor chips (210).

[0101] Referring to FIG. 18, an underfill film (300) can be formed between the first semiconductor chip (210) and the redistribution substrate (100) and between the chip stacks (250) and the redistribution substrate (100). The underfill film (300) can surround and seal the dummy redistribution patterns (130) and capacitor chips (400) exposed by the first trench (TR1). An upper molding film (360) can be formed to cover the sides of the first semiconductor chip (210) and the chip stacks (250). Subsequently, the carrier substrate (900) can be removed so that the lower surface of the first insulating layer (101) and the lower surfaces (110b) of the lower conductive patterns (110) are exposed.

[0102] Referring to FIG. 19, external terminals (840) can be formed on the lower surfaces (110b) of the exposed lower conductive patterns (110). Forming the external terminals (840) may include performing a solder ball attachment process. According to the manufacturing method described above, a semiconductor package according to embodiments of the present invention can be manufactured.

[0104] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention.

Claims

Claim 1 A redistribution substrate having first trenches in which a portion of the upper surface is recessed; a first semiconductor chip mounted on the redistribution substrate and comprising first chip pads and second chip pads; capacitor chips mounted on the second chip pads of the first semiconductor chip and comprising capacitor chip pads; and an underfill film provided on the lower surface of the first semiconductor chip, wherein the redistribution substrate comprises: vertically stacked insulating layers; and redistribution patterns provided within the insulating layers. A semiconductor package comprising a stack via provided between the capacitor chips, wherein the stack via is connected to the redistribution patterns and the first semiconductor chip, the capacitor chip pads are in direct contact with the second chip pads, the underfill film surrounds the capacitor chip pads and the second chip pads, the underfill film extends from between the lower surface of the first semiconductor chip and the upper surface of the capacitor chips to between the lower surface of the capacitor chips and the bottom surface of the first trenches, the underfill film is in direct contact with the lower surface of the first semiconductor chip, the upper surface of the capacitor chips and the lower surface of the capacitor chips, and the material constituting the underfill film is different from the material constituting the insulating layers. Claim 2 In claim 1, the capacitor chips are semiconductor packages provided inside the first trenches, respectively. Claim 3 In claim 1, the redistribution substrate further comprises a blocking insulation pattern provided between the capacitor chips, wherein the stack via is a semiconductor package penetrating the blocking insulation pattern. Claim 4 In claim 3, the capacitor chips are spaced apart with the blocking insulation pattern in between in a semiconductor package. Claim 5 In claim 3, the underfill film extends between the sides of each of the capacitor chips and the sides of the blocking insulation pattern, forming a semiconductor package. Claim 6 A semiconductor package according to claim 1, wherein the height of each of the first trenches is 2 μm or more and 30 μm or less. Claim 7 In claim 1, the first semiconductor chip further comprises first connection terminals provided on the lower surfaces of the first chip pads, wherein the stack via is a semiconductor package in contact with the first connection terminal. Claim 8 A semiconductor package according to claim 7, wherein the stack via comprises a plurality of vertically stacked conductive vias, each of which comprises a via portion and a wiring portion provided on the via portion, wherein the wiring portion of the uppermost conductive via among the conductive vias contacts the first connection terminal, and the via portion of the lowermost conductive via among the conductive vias contacts the redistribution patterns. Claim 9 In claim 1, each of the capacitor chips comprises: a capacitor substrate; a first conductive layer provided on the capacitor substrate; a capacitor insulating film provided on the first conductive layer and having a plurality of through holes; and a capacitive structure filling the through holes, wherein the capacitor substrate comprises a silicon substrate and the first conductive layer comprises tungsten, forming a semiconductor package. Claim 10 A redistribution substrate having first trenches with a portion of the upper surface recessed; a conductive terminal provided on the lower surface of the redistribution substrate; a first semiconductor chip mounted on the redistribution substrate and comprising first chip pads and second chip pads; capacitor chips mounted on the second chip pads of the first semiconductor chip and comprising capacitor chip pads; first connection terminals interposed between the capacitor chips and the second chip pads; and an underfill film provided on the lower surface of the first semiconductor chip, wherein the redistribution substrate comprises: vertically stacked insulating layers; redistribution patterns provided within the insulating layers and comprising wiring portions and via portions; upper conductive patterns provided on the wiring portions of the uppermost redistribution patterns among the redistribution patterns and connected to the first semiconductor chip; lower conductive patterns provided on the via portions of the lowermost redistribution patterns among the redistribution patterns and connected to the conductive terminal; and a blocking insulating pattern provided between the capacitor chips. A semiconductor package comprising a stack via that penetrates the blocking insulation pattern and is provided on the redistribution patterns, wherein the stack via is connected to the redistribution patterns and the first semiconductor chip, and the underfill film fills the space between the lower surface of the first semiconductor chip and the upper surface of the capacitor chips and surrounds the first connection terminals, and the underfill film extends from the space between the lower surface of the first semiconductor chip and the upper surface of the capacitor chips to the space between the lower surface of the capacitor chips and the bottom surface of the first trenches, and the underfill film is in direct contact with the lower surface of the first semiconductor chip, the lower surface of the capacitor chips and the upper surface of the capacitor chips, and the material constituting the underfill film is different from the material constituting the insulation layers.

Images