Advanced lithography and self-assembled devices

Abstract

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and methods for manufacturing the same are described.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor devices and processing, in particular to the field of sub-10nm pitch patterning and self-assembled devices. Background Technology

[0002] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the continuously growing semiconductor industry. Scaling to increasingly smaller features enables an increased density of functional units on the limited real estate of semiconductor chips. For example, reducing transistor size makes it possible to integrate a larger number of memory or logic devices onto a chip, leading to the manufacture of products with increased capacity. However, the push for greater capacity is not without its challenges. The need to optimize the performance of each individual device is becoming increasingly important.

[0003] Variability in conventional and currently known manufacturing processes may limit the potential to further extend them to the sub-10 nm range. Consequently, the manufacturing of functional components required for future technology nodes may necessitate the introduction of new methodologies or the integration of new technologies into or in place of current manufacturing processes. Brief explanation of the drawing

[0004] FIG. 1a illustrates a cross-sectional view of a starting structure after the deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer, but before its patterning. FIG. 1b illustrates a cross-sectional view of the structure of FIG. 1a after patterning of the hard mask layer by pitch halving. Figure 2 illustrates cross-sectional views in a spacer-based-sextuple-patterning (SBSP) processing scheme involving pitch division by a factor of six. Figure 3 illustrates cross-sectional views in a spacer-based-nonuple-patterning (SBNP) processing scheme involving pitch division by a factor of nine. FIGS. 4a through 4n illustrate cross-sectional views of various operations in a method for manufacturing non-planar semiconductor devices according to one embodiment of the present disclosure. FIG. 5 illustrates the structure of FIG. 4n after exposing the upper portions of a plurality of pins, according to one embodiment of the present disclosure. FIG. 6a illustrates a cross-sectional view of a non-planar semiconductor device according to one embodiment of the present disclosure. FIG. 6b illustrates a plan view taken along the aa' axis of the semiconductor device of FIG. 6a according to one embodiment of the present disclosure. FIGS. 7a and 7b illustrate cross-sectional views of target base structures for enabling very dense pitch final patterns for semiconductor layers according to embodiments of the present disclosure. FIGS. 8a through 8h illustrate cross-sectional views illustrating various operations in a method for manufacturing target base structures to enable very dense pitch final patterns for semiconductor layers according to embodiments of the present disclosure. FIGS. 8ha ​​and FIGS. 8hb illustrate cross-sectional views of exemplary structures after via and plug patterning according to one embodiment of the present disclosure. FIGS. 9a through 9l illustrate angled cross-sectional views of portions of integrated circuit layers illustrating various operations in a method involving pitch-divided patterning with an increased overlay margin for manufacturing a back-end-of-line (BEOL) interconnect according to one embodiment of the present disclosure. FIGS. 10a through 10m illustrate portions of integrated circuit layers representing various operations in a method of self-aligned vias and metal patterning according to one embodiment of the present disclosure. FIGS. 11a through 11m illustrate portions of integrated circuit layers representing various operations in a method of self-aligned vias and metal patterning according to one embodiment of the present disclosure. FIGS. 12a through 12c illustrate inclined cross-sectional views illustrating various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure. FIG. 12d illustrates an inclined cross-sectional view illustrating an operation in a method using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure. FIG. 12e illustrates an inclined cross-sectional view illustrating work in another method using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to another embodiment of the present disclosure. FIG. 12f illustrates a triblock copolymer for forming self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure. FIGS. 12g and FIGS. 12h illustrate plan views and corresponding cross-sectional views illustrating various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure. FIGS. 12i to 12l illustrate plan views and corresponding cross-sectional views illustrating various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure. FIG. 13 illustrates a plan view and corresponding cross-sectional views of a self-aligned via structure after metal line, via, and plug formation according to one embodiment of the present disclosure. FIGS. 14a through 14n illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via and plug patterning according to one embodiment of the present disclosure. FIGS. 15a through 15d illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned plug patterning according to another embodiment of the present disclosure. FIGS. 16a through 16d illustrate cross-sectional views of portions of integrated circuit layers representing various operations in a method involving the formation of a dielectric helmet for manufacturing a back end of line (BEOL) interconnect according to one embodiment of the present disclosure. FIGS. 16e through 16p illustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving the formation of a dielectric helmet for manufacturing a back end of line (BEOL) interconnect according to one embodiment of the present disclosure. FIGS. 17a through 17j illustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving the formation of a dielectric helmet for manufacturing a back end of line (BEOL) interconnect according to one embodiment of the present disclosure. FIGS. 18a through 18w illustrate plan views and corresponding inclined views and cross-sectional views illustrating various operations in a metal via processing scheme for back end of line (BEOL) interconnects according to one embodiment of the present disclosure. FIGS. 19a through 19l illustrate plan views and corresponding inclined cross-sectional views illustrating various operations in grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects according to one embodiment of the present disclosure. FIGS. 20a through 20g illustrate plan views and corresponding cross-sectional views illustrating various operations in a method for manufacturing grating-based plugs and cuts for forming feature ends for BEOL (back end of line) interconnects according to one embodiment of the present disclosure. FIG. 21a illustrates a plan view of a metallized layer of a currently known semiconductor device and a corresponding cross-sectional view taken along the aa' axis of the plan view. FIG. 21b illustrates a cross-sectional view of a line end or plug manufactured using a currently known processing scheme. FIG. 21c illustrates another cross-sectional view of a line end or plug manufactured using a currently known processing scheme. FIGS. 21d to 21j illustrate cross-sectional views illustrating various operations in a process for patterning metal line ends for BEOL (back end of line) interconnects according to one embodiment of the present disclosure. FIG. 21k illustrates a cross-sectional view of a metallized layer of an interconnect structure for a semiconductor die comprising dielectric line ends or plugs having a seam, according to one embodiment of the present disclosure. FIG. 211 illustrates a cross-sectional view of a metallized layer of an interconnect structure for a semiconductor die comprising a dielectric line end or plug not immediately adjacent to a conductive via, according to one embodiment of the present disclosure. FIGS. 22a through 22g illustrate portions of integrated circuit layers representing various operations in a method involving self-aligned isotropic etching of pre-formed via or plug locations according to one embodiment of the present disclosure. FIGS. 22h to 22j illustrate inclined cross-sectional views illustrating portions of integrated circuit layers representing various operations in a method involving self-aligned isotropic etching of pre-formed via locations according to one embodiment of the present disclosure. FIGS. 23a through 23l illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via and plug patterning according to one embodiment of the present disclosure. FIGS. 23m to 23s illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via patterning according to one embodiment of the present disclosure. FIGS. 24a through 24i illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via and plug patterning according to one embodiment of the present disclosure. FIGS. 25a through 25h illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via patterning using multi-colored photobuckets according to one embodiment of the present disclosure. FIG. 25i illustrates an exemplary dual tone resist for one photobucket type and an exemplary single tone resist for another photobucket type according to one embodiment of the present disclosure. FIG. 26a illustrates a plan view of a conventional BEOL (back end of line) metallization layer. FIG. 26b illustrates a plan view of a back end of line (BEOL) metallization layer having a conductive tab coupling metal lines of the metallization layer according to one embodiment of the present disclosure. FIGS. 27a through 27k illustrate inclined cross-sectional views illustrating various operations in a method for manufacturing a back-end-of-line (BEOL) metallized layer having a conductive tab coupling metal lines of a metallized layer according to one embodiment of the present disclosure. FIGS. 28a to 28t illustrate inclined cross-sectional views illustrating various operations in a method for manufacturing a back-end-of-line (BEOL) metallized layer having a conductive tab coupling metal lines of a metallized layer according to one embodiment of the present disclosure. FIGS. 29a through 29c illustrate cross-sectional views and corresponding plan views of various operations in a patterning method using photobuckets comprising a two-stage bake photoresist according to one embodiment of the present disclosure. FIG. 29d illustrates a cross-sectional view of a conventional resist photobucket structure after photobucket development following mis-aligned exposure. FIGS. 30a through 30e illustrate schematic diagrams of various operations in a patterning method using photobuckets comprising a two-stage baked photoresist according to one embodiment of the present disclosure. FIG. 30aa illustrates a schematic diagram of an operation in another method of patterning using photobuckets according to one embodiment of the present disclosure. FIG. 30ab illustrates a schematic diagram of an operation in another method of patterning using photobuckets according to one embodiment of the present disclosure. FIG. 31 illustrates an inclined view of an alternating pattern of interlayer dielectric (ILD) lines and resist lines, in which a hole is formed in one of the resist lines, according to one embodiment of the present disclosure. FIGS. 32a through 32h illustrate cross-sectional views of a manufacturing process involving image tone-reversal by a dielectric using bottom-up cross-linking according to one embodiment of the present disclosure. FIG. 33a illustrates a trisilacyclohexane molecule according to one embodiment of the present disclosure. FIG. 33b illustrates two cross-linked (XL) trisilacyclohexane molecules to form a cross-linked material according to one embodiment of the present disclosure. FIG. 33c illustrates an idealized representation of a linked trisilacyclohexane structure according to one embodiment of the present disclosure. FIGS. 34a through 34x illustrate portions of integrated circuit layers representing various operations in a method of self-aligned via and plug patterning using diagonal hard masks according to one embodiment of the present disclosure. FIGS. 35a through 35d illustrate cross-sectional views and corresponding top-down views illustrating various operations in a patterning processing scheme using pre-patterned hard masks according to one embodiment of the present disclosure. FIG. 36a illustrates a top-down view of an overlay scenario in which a current layer is overlaid on a pre-patterned hard mask grid below, according to one embodiment of the present disclosure. FIG. 36b illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a positive overlay of 1 / 4 pitch with respect to a pre-patterned hardmask grid below it. FIG. 36c illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a positive overlay of 1 / 2 pitch with respect to a pre-patterned hardmask grid below it. FIG. 36d illustrates a top-down view of an overlay scenario having a positive overlay of an arbitrary value Δ for a pre-patterned hardmask grid below, according to one embodiment of the present disclosure. FIG. 36e illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a positive overlay of an arbitrary value Δ with respect to a pre-patterned hardmask grid below, and the measurable Δ is made as small as necessary by changing the s resist sensitivity and / or the derived feature size. FIG. 36f illustrates an exemplary measurement structure suitable for the approaches described above in relation to FIG. 36a through 36e, according to one embodiment of the present disclosure. FIG. 37a illustrates a top-down view of an overlay scenario in which a current layer is overlaid on a pre-patterned hard mask below, according to one embodiment of the present disclosure. FIG. 37b illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a positive overlay of 1 / 4 pitch with respect to a pre-patterned hardmask grid located below in the X-direction. FIG. 37c illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a negative overlay of 1 / 4 pitch with respect to a pre-patterned hardmask grid located below in the X-direction. FIG. 37d illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a positive overlay of 1 / 4 pitch with respect to a pre-patterned hardmask grid located below in the Y-direction. FIG. 37e illustrates a top-down view of an overlay scenario according to one embodiment of the present disclosure, in which the current layer has a positive overlay of 1 / 4 pitch for a pre-patterned hard mask grid below in the X-direction and a positive overlay of 1 / 4 pitch for a pre-patterned hard mask grid below in the Y-direction. FIG. 38 illustrates a cross-sectional view of a lithography mask structure according to one embodiment of the present disclosure. Figure 39 is a schematic cross-sectional view of the e-beam column of an electron beam lithography device. FIG. 40 illustrates the aperture (left) of a blanking aperture array (BAA) for the line (right) where vias are to be placed or cut at target locations while the line is scanned under the aperture. FIG. 41 illustrates two non-staggered apertures (left) of a BAA for two lines (right) to be placed or cut at target locations while the two lines are scanned under the apertures. FIG. 42 illustrates two columns (left) of staggered apertures of a BAA for a plurality of lines (right) to be placed or cut at target locations while a plurality of lines are scanned under apertures—the scanning direction is indicated by an arrow—according to one embodiment of the present disclosure. FIG. 43a illustrates two columns (left) of staggered apertures of a BAA for a plurality of lines (right) having cuts (breaks in horizontal lines) or vias (filled-in boxes) patterned using a staggered BAA according to one embodiment of the present disclosure—the scanning direction is indicated by an arrow. FIG. 43b illustrates a cross-sectional view of a stack of metallized layers in an integrated circuit based on metal line layouts of the type exemplified in FIG. 21a, according to one embodiment of the present disclosure. FIG. 44 illustrates a computing device according to one embodiment of the present disclosure. FIG. 45 illustrates an interposer comprising one or more embodiments of the present disclosure. Specific details for implementing the invention

[0005] Advanced pitch patterning techniques and methods for manufacturing self-assembled devices are described for producing advanced pitch patterning and self-assembled devices, specifically sub-10 nanometer (nm) devices and structures. In the following detailed description, numerous specific details, such as specific integration and material regimes, are described to provide a complete understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other cases, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be recognized that the various embodiments depicted in the drawings are exemplary representations and are not necessarily drawn to scale.

[0006] The following detailed description is by no means illustrative and is not intended to limit the subject matter, the embodiments of the application, or the uses of such embodiments. As used herein, the word “illustrative” means “serving as an example, case, or example.” Any embodiment described as illustrative herein is not to be interpreted as being more desirable or advantageous than other embodiments. Furthermore, there is no intention to be bound by any stated or implied theory presented in the foregoing art, background art, brief overview, or the following detailed description.

[0007] This specification includes references to "one embodiment" or "an embodiment." Appearances of phrases such as "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0008] Terms. The following paragraphs provide definitions and / or context for terms found in the present disclosure (including the appended claims).

[0009] "Comprising." This term is open-ended. As used in the appended claims, this term does not exclude additional structures or steps.

[0010] "Configured To." Various units or components may be described or claimed as being "configured to" perform a task or tasks. In such contexts, "configured to" is used to imply a structure by indicating that the units / components include a structure that performs that task or tasks during operation. As such, a unit / component may be said to be configured to perform a task even when the specified unit / component is not currently working (e.g., when not on / active). It is explicitly intended not to invoke 35 USC §112, 6th paragraph to that unit / component.

[0011] "First," "Second," etc. As used herein, these terms are used as labels for the nouns that follow them and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, a reference to a "first" solar cell does not necessarily imply that this solar cell is the first in order; instead, the term "first" is used to distinguish this solar cell from other solar cells (e.g., a "second" solar cell).

[0012] "Coupled"—The following description refers to elements, nodes, or features being "coupled" together. As used herein, "coupled" means that one element / node / feature is joined (or communicates directly or indirectly) to another element / node / feature, not necessarily mechanically.

[0013] In addition, specific terms may also be used in the following description for reference purposes only and are not intended to be restrictive. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the referenced drawings. Terms such as "front," "back," "rear," "side," "outboard," and "inboard" describe the orientation and / or position of parts of the component within a consistent but arbitrary frame of reference that becomes apparent by referring to the text describing the component under discussion and the associated drawings. Such terms may include words specifically mentioned above, their derivatives, and words of similar meaning.

[0014] "Inhibit" – As used herein, "inhibit" is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent a result, performance, or future state. In addition, "inhibit" may also refer to a reduction or degradation of a result, performance, and / or effect that might otherwise have occurred. Accordingly, when a component, element, or feature is described as inhibiting a result or state, it is not necessary to completely prevent or eliminate the result or state.

[0015] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned onto a semiconductor substrate or layer. FEOL generally covers everything up to the deposition of metal interconnect layers (but not the deposition itself). After the final FEOL operation, the result is typically a wafer having isolated transistors (e.g., having no wires).

[0016] The embodiments described herein may relate to back-end of line (BEOL) semiconductor processing and structures. BEOL is the latter part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer, such as metallization layers or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For recent IC processes, more than 10 metal layers may be added in BEOL. The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although exemplary processing schemes can be exemplified using FEOL processing scenarios, such approaches may also be applicable to BEOL processing. Likewise, although exemplary processing schemes can be exemplified using BEOL processing scenarios, such approaches may also be applicable to FEOL processing.

[0017] Pitch splitting processing and patterning schemes may be implemented to enable the embodiments described herein, or may be included as part of the embodiments described herein. Pitch splitting patterning typically refers to pitch halving, pitch quartering, etc. Pitch splitting schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or predominantly unidirectional) at a predefined pitch. Pitch splitting processing is then implemented as a technique to increase line density.

[0018] In one embodiment, the term “grating structure” for metal lines, ILD lines, or hard mask lines is used herein to refer to a tight pitch grating structure. In such an embodiment, the tight pitch is not directly achievable through conventional lithography. For example, a pattern based on conventional lithography may be formed first, but as is known in the art, the pitch may be divided into two by the use of spacer mask patterning. Furthermore, the original pitch may be divided into four by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have metal lines, ILD lines, or hard mask lines that are spaced at a substantially constant pitch and have a substantially constant width. For example, in some embodiments, the pitch variation will be within 10 percent and the width variation will be within 10 percent, and in some embodiments, the pitch variation will be within 5 percent and the width variation will be within 5 percent. The pattern may be manufactured by a pitch 2-part or pitch 4-part approach, or other pitch 2-part approach. In one embodiment, the grating is not necessarily a single pitch.

[0019] In the first example, pitch splitting can be implemented to double the line density of the manufactured grating structure. FIG. 1a illustrates a cross-sectional view of a starting structure after the deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer, but before its patterning. FIG. 1b illustrates a cross-sectional view of the structure of FIG. 1a after the patterning of the hard mask layer by pitch splitting.

[0020] Referring to FIG. 1a, the starting structure (100) has a hard mask material layer (104) formed on an interlayer dielectric (ILD) layer (102). A patterned mask (106) is placed on the hard mask material layer (104). The patterned mask (106) has spacers (108) formed along the sidewalls of its features (lines) on the hard mask material layer (104).

[0021] Referring to FIG. 1b, a hard mask material layer (104) is patterned using a pitch-divided approach. Specifically, the patterned mask (106) is removed first. The resulting pattern of spacers (108) has twice the density of the features of the mask (106) or half the pitch. As illustrated in FIG. 1b, the pattern of spacers (108) is transferred to the hard mask material layer (104), for example, by an etching process, to form a patterned hard mask (110). In such an embodiment, the patterned hard mask (110) is formed as a grating pattern having unidirectional lines. The grating pattern of the patterned hard mask (110) may be a dense pitch grating structure. For example, a dense pitch may not be directly achievable through conventional lithography techniques. In addition, although not illustrated, the original pitch can be divided into four by the second round of spacer mask patterning. Accordingly, the grating-like pattern of the patterned hard mask (110) of FIG. 1b may have hard mask lines that are spaced apart from each other at a constant pitch and have a constant width. The dimensions achieved may be much smaller than the critical dimension of the lithography technique used.

[0022] Accordingly, for either or both of the FEOL (front-end of line) or BEOL (back-end of line) integration schemes, a blanket film may be patterned using lithography and etching processes that may involve, for example, SBDP (spacer-based-double-patterning) or pitch splitting, or SBQP (spacer-based-quadruple-patterning) or pitch splitting. It should be recognized that other pitch splitting approaches may also be implemented.

[0023] For example, FIG. 2 illustrates cross-sectional views in a spacer-based-sextuple-patterning (SBSP) processing scheme involving six-fold pitch division. Referring to FIG. 2, in operation (a), a sacrificial pattern X is shown after litho, slim, and etching processing. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern of operation (b) is shown after the removal of spacer A. In operation (d), the pattern of operation (c) is shown after the deposition of spacer C. In operation (e), the pattern of operation (d) is shown after the etching of spacer C. In operation (f), a pitch / 6 pattern is achieved after the removal of sacrificial pattern X and spacer B.

[0024] In another example, FIG. 3 illustrates cross-sectional views in a spacer-based-nonuple-patterning (SBNP) processing scheme involving 9-fold pitch division. Referring to FIG. 3, in operation (a), a sacrificial pattern X is shown after lithography, slimming, and etching processing. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern of operation (b) is shown after the removal of spacer A. In operation (d), the pattern of operation (c) is shown after the deposition and etching of spacers C and D. In operation (e), a pitch / 9 pattern is achieved after the removal of spacer C.

[0025] In any case, in one embodiment, the gridded layout may be manufactured by conventional or state-of-the-art lithography, such as 193 nm immersion lithography (193i). Pitch splitting may be implemented to increase the density of lines in the gridded layout by a factor of n. The formation of the gridded layout using 193i lithography and n-fold pitch splitting may be denoted as 193i + P / n pitch splitting. In such an embodiment, 193 nm immersion scaling may be extended over many generations using cost-effective pitch splitting.

[0026] In the manufacturing of integrated circuit devices, as device dimensions continue to scale down, multi-gate transistors, such as tri-gate transistors, have become more common. In conventional processes, tri-gate transistors are typically fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0027] However, scaling multi-gate transistors had side effects. As the dimensions of these basic building blocks of microelectronic circuits decreased and the number of basic building blocks manufactured in a given area increased, the constraints on the semiconductor processes used to manufacture these building blocks became overwhelming.

[0028] In one embodiment, a directed self-assembly (DSA) is implemented for hard mask differentiation (e.g., forming hard masks having different etching properties). In some embodiments, the differentiated hard masks may also be referred to as "colored" hard masks, wherein hard masks having the same color have the same or similar etching selectivity, and hard masks having different colors have different etching selectivity. It should be noted that in actual practice, the term "color" does not refer to the actual color of the hard mask material. Hard mask differentiation (or coloring) may be used to pattern or selectively remove semiconductor pins among a plurality of grid-type semiconductor pins. One or more embodiments described herein relate to processes and structures based on and resulting from aligned pitch quaternized (or other) patterning approaches for edge placement error (EPE) rectification. One or more embodiments may be described as a differentiated or "colored" alternating hardmask approach for semiconductor fin patterning. The embodiments may include one or more of DSA, semiconductor material patterning, pitch splitting such as pitch 4-way splitting, differentiated hardmask selectivity, and self-alignment for fin patterning. One or more embodiments are particularly suitable for manufacturing non-planar semiconductor devices.

[0029] According to one embodiment of the present disclosure, doubling of the allowable edge placement error for very fine pin patterning and doubling of the cut size for cutting small features at a dense pitch are implemented. In one embodiment, all features (e.g., pin lines) are transferred to a semiconductor substrate having a single critical dimension (CD) variation group. This approach is in contrast to conventional approaches that rely on spacer-based pitch quaternion having three discrete line width groups (e.g., backbone or mandrel, complement, and spacer dimensions).

[0030] To provide context, it may be desirable to use bulk silicon for pins or tri-gate based semiconductor devices. In one embodiment, directed self-assembly (DSA) is implemented to achieve pitch splitting and “coloring” of every other feature into a desired pattern. In such an embodiment, the patterning approach is particularly applicable to patterning silicon pins in a tri-gate transition patterning flow. In one embodiment, the advantages of implementing the approaches described herein may include one or more of: (1) enabling a single feature width group, (2) doubling the edge placement error requirements for feature cutting, (3) doubling the dimensions of holes or openings required to cut a single feature (e.g., relaxing restrictions on the size of the openings), or (4) reducing the cost of the patterning process. Structural artifacts resulting from the process include, in one embodiment, transitions from one pitch to another and / or from one grid to another in guard rings surrounding a single critical dimension group and the die of the chips. The embodiments can enable the cutting of dense pitch lines without scaling edge placement error requirements.

[0031] In an exemplary processing scheme, FIGS. 4a through 4n illustrate cross-sectional views of various operations in a method for manufacturing non-planar semiconductor devices according to one embodiment of the present disclosure.

[0032] FIG. 4a illustrates a bulk semiconductor substrate (402) on which a first patterned hard mask (404) is formed. In one embodiment, the bulk semiconductor substrate (402) is a bulk single-crystal silicon substrate on which pins (402) are etched. In one embodiment, the bulk semiconductor substrate (402) is undoped or lightly doped at this stage. For example, in a specific embodiment, the bulk semiconductor substrate (402) is approximately 1E17 atoms / cm³ 3 It has boron dopant impurity atoms at a concentration of less than [amount].

[0033] In one embodiment, the first patterned hard mask (404) includes features having a pitch (406). In such an embodiment, the first patterned hard mask (404) represents half of the possible number of pins ultimately formed on the substrate (402). That is, the pitch (406) is effectively relaxed to double the pitch of the final pattern of the pins formed. In one embodiment, the first hard mask (404) is directly patterned using a lithography process. However, in other embodiments, pitch splitting, e.g., pitch 2-segmentation, is applied and used to provide the patterned hard mask (404) having a pitch (406). In one embodiment, it should be recognized that the first guide pattern can be formed using conventional patterning (lithography / etching), using lithography alone, using spacer-based double patterning, or using other pitch splitting methods. In one embodiment, a guide pattern is separated from a DSA pattern through the use of two or more hard masks so that CDs are formed from a single group (e.g., one etching).

[0034] FIG. 4b illustrates the structure of FIG. 4a after forming a second hard mask layer (408) between the first patterned hard masks (404). In one embodiment, the second hard mask layer (408) is formed by forming a blanket hard mask layer on top of the substrate (402) and the first patterned hard mask (404), and then forming the second hard mask layer (408) by flattening the blanket hard mask layer, for example, by chemical mechanical planarization (CMP). In another embodiment, ALD or CVD techniques will follow the contour of the surface of the wafer, and since fin cuts are used as an example, the wafer is substantially flat at this point in the process.

[0035] In one embodiment, the second hard mask layer (408) has etching properties different from those of the first patterned hard mask (404). In one embodiment, one or both of the second hard mask layer (408) or the first patterned hard mask (404) are a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. In another embodiment, the hard mask material includes a metal species. For example, the material on the hard mask or other may include a layer of titanium nitride (e.g., titanium nitride) or another metal. Potentially, a smaller amount of other materials, such as oxygen, may be included in one or more of these layers. The hard mask layers may be formed by CVD, PVD, or other deposition methods.

[0036] FIG. 4c illustrates the structure of FIG. 4b after the application of the optional brush material layer (410). The optional brush material (410) is an optional material that, in some embodiments, can be applied by a brush. It should be noted that "brush material" is often used as a term of art in DSA processes and does not imply that the optional material (410) is used as a brush. In one embodiment, as depicted in FIG. 4c, the optional brush material layer (410) is attached only to the first patterned hard mask (404). However, in another embodiment, the optional brush material is applied to the second hard mask layer (408) instead. In yet another embodiment, the optional brush material layer (410) is attached only to the first patterned hard mask (404), and a second different optional brush material is formed on the second hard mask layer (408).

[0037] In one embodiment, the optional brush material layer (410) comprises molecular species including polystyrene having a head group selected from the group consisting of -SH, -PO3H2, -CO2H, -NRH, -NRR', and -Si(OR)3. In another embodiment, the optional brush material layer (410) comprises molecular species including polymethacrylate having a head group selected from the group consisting of -SH, -PO3H2, -CO2H, -NRH, -NRR', and -Si(OR)3. In one embodiment, the optional brush material layer (410) is drawn toward one component of a DSA block copolymer (e.g., polystyrene or polymethyl methacrylate). In other embodiments, the optional material layer (410) may comprise other suitable materials.

[0038] FIG. 4d illustrates the structure of FIG. 4c after the application of a direct self-assembly (DSA) block copolymer (414 / 416A / 416B) and a polymer assembly process. In one embodiment, the DSA block copolymer is coated on a surface and annealed to segregate the polymer into first polymer blocks (414) and second polymer blocks (416) (identified as 416A and 416B in FIG. 4d). In one embodiment, the polymer blocks (416) are preferentially attached to an optional brush material layer (410) during the annealing process. The polymer blocks (414) adhere to the second hard mask layer (408). However, in a specific embodiment, the pitch of this assembly is half the pitch of the first patterned hard mask (404). In this case, parts (416A) of the polymer blocks (416) are adhered to the optional brush material layer (410) on the first hard mask (404), while parts (416B) of the polymer blocks (416) are formed on the second hard mask layer (408) between the polymer blocks (414).

[0039] In one embodiment, the block copolymer molecule (414 / 416A / 416B) is a polymer molecule formed from a chain of covalently bonded monomers. In a di-block copolymer, there are two different types of monomers, and these different types of monomers are mainly contained within two different blocks or contiguous sequences of monomers. The illustrated block copolymer molecule comprises a polymer block (414) and a polymer block (416A / 416B). In one embodiment, the polymer block (414) mainly comprises a chain of covalently linked monomer A (e.g., AAAAA...), while the polymer block (416A / 416B) mainly comprises a chain of covalently linked monomer B (e.g., BBBBB...). Monomers A and B may represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A may represent monomers for forming polystyrene and monomer B may represent monomers for forming poly(methyl methacrylate) (PMMA), or vice versa, but the scope of the disclosure is not so limited. In other embodiments, there may be more than two blocks. Furthermore, in other embodiments, each of the blocks may contain different types of monomers (e.g., each block may itself be a copolymer). In one embodiment, polymer block (414) and polymer block (416A / 416B) are covalently bonded together. Polymer block (414) and polymer block (416A / 416B) may be approximately the same length, or one block may be significantly longer than the other.

[0040] Typically, each of the blocks of the block copolymer (e.g., polymer block (414) and polymer block (416A / 416B)) may have different chemical properties. As an example, one of the blocks may be relatively more hydrophobic (e.g., water-repelling) and the other block may be relatively more hydrophilic (water-attracting). At least conceptually, one of the blocks may be relatively more oil-like and the other block may be relatively more water-like. Such differences in chemical properties between the different polymer blocks, whether hydrophilic-hydrophobic differences or others, may cause the block copolymer molecules to self-assemble. For example, self-assembly may be based on the microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water, which are generally immiscible. Similarly, differences in hydrophilicity between polymer blocks (e.g., one block is relatively hydrophobic and the other is relatively hydrophilic) can cause roughly similar microphase separation when different polymer blocks attempt to "separate" from each other due to chemical dislike.

[0041] However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot be completely separated on a macroscopic scale. Rather, polymer blocks of a given type may tend to be segregated or conglomerated with polymer blocks of other molecules of the same type in extremely small (e.g., nano-sized) regions or phases. The specific size and shape of those regions or microphases generally depend at least partially on the relative lengths of the polymer blocks. In one embodiment, for example, in two block copolymers, when the blocks are approximately the same length, a grid-like pattern of alternating polymer (414) lines and polymer (416A / 416B) lines is created.

[0042] In one embodiment, the polymer (414) / polymer (416A / 416B) grating is first applied as a portion of an unassembled block copolymer layer comprising a block copolymer material applied, for example, by a brush or other coating process. The unassembled mode refers to scenarios in which, at deposition, the block copolymer is not yet substantially phase separated and / or self-assembled to form nanostructures. In this unassembled mode, the block copolymer molecules are relatively highly randomized, so that different polymer blocks are relatively highly randomly oriented and positioned. The portion of the unassembled block copolymer layer can be applied in various different ways. For example, the block copolymer can be dissolved in a solvent and then spin-coated onto the surface. Alternatively, the unassembled block copolymer can be spray-coated, dip-coated, immersed, or coated or applied onto the surface in other ways. Other methods for applying block copolymers, as well as other methods known in the art for applying similar organic coatings, may potentially be used. Subsequently, the unassembled layer may form an assembled block copolymer layer portion, for example, by microphase separation and / or self-assembly of the unassembled block copolymer layer portion. Microphase separation and / or self-assembly occurs through the rearrangement and / or rearrangement of block copolymer molecules, and in particular through the rearrangement and / or rearrangement of different polymer blocks of block copolymer molecules.

[0043] In one such embodiment, an annealing treatment may be applied to an unassembled block copolymer to initiate, accelerate, improve the quality of, or otherwise promote microphase separation and / or self-assembly. In some embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. Examples of such treatments include baking the layer, heating the layer in an oven or under a heat lamp, applying infrared radiation to the layer, or otherwise applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and / or self-assembly of the block polymer without damaging any other important materials or structures of the block copolymer or integrated circuit board. Typically, the heating may be in the range of about 50°C to about 300°C, or about 75°C to about 250°C, but does not exceed the thermal degradation limits of the block copolymer or integrated circuit board. Heating or annealing can help provide energy to block copolymer molecules to make them more mobile / flexible, in order to increase the rate of microphase separation and / or improve the quality of microphase separation. Such microphase separation or rearrangement / relocation of block copolymer molecules can lead to self-assembly to form extremely small (e.g., nano-scale) structures. Self-assembly can occur under the influence of surface energy, molecular affinities, and other surface-related and chemical-related forces.

[0044] In any case, in some embodiments, the self-assembly of block copolymers can be used to form extremely small periodic structures (e.g., nano-scale structures or lines at precise intervals), whether based on hydrophobic-hydrophilic differences or in other ways. In some embodiments, they can be used to form nano-scale lines or other nano-scale structures that can ultimately be used to form semiconductor fin lines.

[0045] FIG. 4e illustrates the structure of FIG. 4d after the removal of one of the blocks of the diblock copolymer. In one embodiment, the polymer portions (414) are selectively removed via a wet or dry etching process, leaving portions (416A / 416B). The pitch of the remaining portions (416A / 416B) is approximately half the pitch of the first patterned hard mask (404).

[0046] FIG. 4f illustrates the structure of FIG. 4e after the transfer of the pattern of the remaining polymer portions into the bulk crystalline semiconductor substrate below. In one embodiment, the pattern of the remaining polymer portions (416A / 416B), i.e., the pattern of the first patterned hard mask (404) as pitch-divided, is etched into the bulk semiconductor substrate (402). The patterning patterns the second hard mask layer (408) to form a second patterned hard mask layer (424) corresponding to the polymer portions (416B). The first patterned hard mask (404) corresponds to the polymer portions (416A). In one embodiment, a plurality of pins (418) are formed directly on a bulk substrate (402) that becomes a patterned substrate (420), and thus are formed continuously with the bulk substrate (402 / 420) on a roughly flat surface (422).

[0047] FIG. 4g illustrates the structure of FIG. 4f after the removal of the remaining polymer layer and any brush layers. In one embodiment, the remaining polymer layer (416A / 416B) and brush layer (410) are removed, leaving a plurality of alternating pins (418) having alternating "colored" first patterned hard mask (404) and second patterned hard mask (424). In one embodiment, the remaining polymer layer (416A / 416B) and brush layer (410) are removed using an ashing and cleaning process. The resulting pitch (426) of the pins is half the pitch (406) of the original first patterned hard mask (404).

[0048] FIG. 4h illustrates the structure of FIG. 4g after the formation of an interlayer dielectric (ILD) layer (428) between a plurality of pins (418). In one embodiment, the ILD layer (428) is composed of silicon dioxide, such as that used in the shallow trench isolation manufacturing process. However, other dielectrics, such as nitrides or carbides, may be used instead. The ILD layer (428) may be deposited by chemical vapor deposition (CVD) or other deposition processes (e.g., ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD) and flattened by a chemical mechanical polishing (CMP) technique to reveal the top surfaces of the hard mask layers (404 and 428).

[0049] FIG. 4i illustrates the structure of FIG. 4h after the formation and patterning of a photoresist material for forming a patterned mask (430). In one embodiment, an opening (432) is formed in the patterned mask (430). The opening (432) exposes a target pin among a plurality of pins (418) having a first patterned hard mask (404) for ultimate pin removal. The opening (432) has a cut dimension (436). In one embodiment, the limitations on the cut dimension (436) are relaxed, and even portions of neighboring pins having a second patterned hard mask (424) may be exposed. In one embodiment, the patterning operation prepares to cut away unwanted features using "coloring" or hard mask material differentiation so that the cut sizes can be twice the pitch (426) of the features (418) (i.e., to result in the original pitch (406). In one embodiment, the hard mask material enables differentiation through plasma or wet etching selectivity between two hard mask materials. Furthermore, the edge placement error (EPE) (434) is 1 / 2 pitch. In contrast, in a standard patterning process that does not use coloring, the cut dimensions are 1X pitch and the edge placement error (EPE) is 1 / 4 pitch. Accordingly, in one embodiment, the process described herein doubles the edge placement error budget and doubles the size of the holes or openings required to cut a single feature.

[0050] In one embodiment, the patterned mask (430) is composed of a photoresist layer as is known in the art and can be patterned by conventional lithography and development processes. In a specific embodiment, portions of the photoresist layer exposed to a light source are removed when the photoresist layer is developed. Accordingly, the patterned photoresist layer is composed of a positive photoresist material. In a specific embodiment, the photoresist layer is composed of a positive photoresist material such as, but not limited to, a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultraviolet (EUV) resist, an e-beam resist, an imprint layer, or a phenolic resin matrix having a diazonaphthoquinone sensitizer. In other specific embodiments, when developing the photoresist layer, portions of the photoresist layer exposed to a light source are retained. Accordingly, the photoresist layer is composed of a negative photoresist material. In specific embodiments, the photoresist layer is composed of a negative photoresist material such as, but not limited to, poly-cis-isoprene or poly-vinyl-cinnamate. In one embodiment, lithography operations are performed using 193 nm immersion lithography (193i), EUV and / or EBDW (electron-beam direct write) lithography, or a similar method. A positive tone or negative tone resist may be used.In one embodiment, the patterned mask (430) is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific of these embodiments, the topographic masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating layer is a silicon-containing ARC layer. In such an embodiment, a spin-on glass material having added chromophores is used to help suppress reflectivity. Chemically, these are (siloxane) silicon-carbon containing polymers. When annealed, they form a mixture of silicon dioxide and carbon polymers.

[0051] FIG. 4j illustrates the structure of FIG. 4i after the etching of a selected pin among a plurality of pins (418) and the subsequent removal of the patterned mask (430). In one embodiment, this process is referred to as a "fin cut" or "feature selection" operation of the process. In one embodiment, one pin among the plurality of pins (418) is removed at position (438) to form a plurality of patterned pins (418') having a first interrupted pattern. In such an embodiment, an exposed first patterned hard mask (404) is first removed using an etching process that is selective for any exposed second patterned hard mask (424) and selective for the ILD layer (428). In another embodiment, a "fin keep" approach is used in which features are selected using a photoresist of opposite tone and protected during the etching process, while background or unprotected pins are removed. This is the reverse polarity of the lithography process (e.g., negative-to-positive tone imaging). It should be recognized that either process may be used in this operation. Using an etching process that is selective for the exposed second patterned hard mask (424) and selective for the ILD layer (428), the exposed pin is subsequently removed at position (438). In the first embodiment, the pin is removed from position (438) to level (440), leaving a protrusion (446) above the planar surface (422). In the second embodiment, the pin is removed from position (438) to level (442), which is approximately co-planar with the planar surface (422). In the third embodiment, the pin is removed from position (438) to level (444), leaving a recess (448) below the planar surface (422).

[0052] FIG. 4k illustrates the structure of FIG. 4j after the formation and patterning of a photoresist material for forming a patterned mask (450). In one embodiment, an opening (452) is formed in the patterned mask (450). The opening (452) exposes a target second pin among a plurality of pins (418') having a second patterned hard mask (424) for ultimate pin removal. In one embodiment, the patterning operation prepares to cut off unwanted features using "coloring" or hard mask material differentiation so that the cut sizes can be twice the pitch (426) of the features (418'). As described in relation to FIG. 4i, the process described herein doubles the edge placement error budget and doubles the size of the holes or openings required to cut a single feature. In one embodiment, the patterned mask (450) is composed of a material as described in relation to FIG. 4i.

[0053] FIG. 4L illustrates the structure of FIG. 4K after etching of a second pin selected among a plurality of pins (418'). In one embodiment, to form a plurality of patterned pins (418") having a second interrupted pattern, a second pin among the plurality of pins (418') is removed at position (454). In such an embodiment, an exposed second patterned hard mask (424) is first removed using an etching process that is selective for any exposed first patterned hard mask (404) and selective for the ILD layer (428). An exposed pin is then removed at position (454) using an etching process that is selective for the exposed first patterned hard mask (404) and selective for the ILD layer (428). In the first embodiment, the pin is removed from position (454) to level (456), leaving a protrusion on the flat surface (422) at some height above the surface (440) of the protrusion (446). In the second embodiment, the pin is removed from position (454) to level (458), A protrusion (464) is left above the flat surface (422) at approximately the same height as the surface (440) of the protrusion (446). In the third embodiment, the pin is removed from position (454) to level (460), so as to be approximately coplanar with the flat surface (422). In the fourth embodiment, the pin is removed from position (454) to level (462), leaving a recess (466) below the flat surface (422).

[0054] FIG. 4m illustrates the structure of FIG. 4l after the removal of the patterned mask (450) and the formation of an interlayer dielectric (ILD) layer (468) above the plurality of pins (418) and at the locations (438, 454) of the removed pins. In one embodiment, the ILD layer (468) is composed of silicon dioxide, such as that used in the shallow trench isolation manufacturing process. However, other dielectrics, such as nitrides or carbides, may be used instead. The ILD layer (468) may be deposited by chemical vapor deposition (CVD) or other deposition processes (e.g., ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD). Spin-on materials are another common option for these films. Many low-k dielectric materials can be spin-on onto a wafer and cured. These are commonly used in industry.

[0055] FIG. 4n illustrates the structure of FIG. 4m after flattening of the ILD layer (468) and removal of the first and second patterned hard masks (404 and 424). In one embodiment, a chemical mechanical polishing (CMP) technique is used to remove the first patterned hard mask (404) and the second hard mask (424), to reset the ILD layers (428 and 468) to form flattened ILD layers (428' and 468'), and to expose the surfaces of a plurality of pins (418"). In one embodiment, the flattened ILD layer (428') is composed of substantially the same material as the flattened ILD layer (468'). In another embodiment, the flattened ILD layer (428') is composed of a different material from the flattened ILD layer (468'). In either case, in one embodiment, a seam is formed between the ILD layer (468') and the ILD layer (428'), for example, at a location (438 or 454). In one embodiment, the exposed surfaces of the plurality of pins (418") are used to form planar semiconductor devices. It must be recognized that it is possible.

[0056] According to another embodiment, FIG. 5 illustrates the structure of FIG. 4n after exposing the upper portions of a plurality of pins (418"). Referring to FIG. 5, the ILD layer (468') and the ILD layer (428') are recessed to expose the protruding portions (472) of the pins (418') and to provide the recessed ILD layer (468") and the recessed ILD layer (428") to a recess height (476). The recess height (476) defines the position between the upper pin portions (472) and the lower pin portions (474). Recessing of the ILD layer (468') and the ILD layer (428') can be performed by a plasma, vapor, or wet etching process. In one embodiment, an optional dry etching process is used for the silicon pins (418"), and the dry etching process is typically 30 to It is based on plasma generated from gases such as, but not limited to, NF3, CHF3, C4F8, HBr, and O2, having pressures in the range of 100 mTorr and a plasma bias of 50 to 1000 watts.

[0057] In an exemplary embodiment, referring again to FIG. 4j, FIG. 4l and FIG. 5, the semiconductor structure comprises a plurality of semiconductor pins (418") protruding from a substantially flat surface (422) of a semiconductor substrate (420). The plurality of semiconductor pins (418") have a grating pattern interrupted by a first position (438) having a first pin portion (446) having a first height. The grating pattern of the semiconductor pins is further interrupted by a second position (454) having a second pin portion (464) having a second height. In one embodiment, the second height of the second pin portion (454) is different from the first height of the first pin portion (446). In another embodiment, the second height of the second pin portion (454) is the same as the first height of the first pin portion (446). In one embodiment, the grating pattern has a constant pitch (126) when viewed without interruptions.

[0058] In an exemplary embodiment, referring again to FIG. 4j, FIG. 4l, and FIG. 5, the semiconductor structure comprises a plurality of semiconductor pins (418") protruding from a substantially flat surface (422) of a semiconductor substrate (420). The plurality of semiconductor pins (418") have a grating pattern interrupted by a first position (438) having a first recess. In one embodiment, the grating pattern of the semiconductor pins is further interrupted by a second recess, or a second position (454) having one of the pin portions. In one embodiment, the grating pattern has a constant pitch (426) when viewed without the interruptions. In one embodiment, a trench isolation layer (468") is disposed within the recess and above the recess.

[0059] It should be recognized that the above approach can be applied to manufacturing semiconductor geometries other than semiconductor pins. For example, in one embodiment, the approach is implemented to manufacture semiconductor nanowires or semiconductor nanoribbons. In one embodiment, the terms "semiconductor body" or "semiconductor bodies" generally refer to geometries such as pins, nanowires, and nanoribbons.

[0060] It should be recognized that structures resulting from the exemplary processing schemes above, such as structures from FIG. 4n and FIG. 5, may be used in the same or similar form for subsequent processing operations to complete device manufacturing, such as PMOS and NMOS device manufacturing. As an example of a completed device, FIG. 6a and FIG. 6b respectively illustrate a cross-sectional view and a plan view (taken along the aa' axis of the cross-sectional view) of a non-planar semiconductor device according to one embodiment of the present disclosure.

[0061] Referring to FIG. 6a, the semiconductor structure or device (600) comprises a non-planar active region (e.g., a fin structure including protruding fin portions (604) and sub-fin regions (605)) formed from a substrate (602) and formed within an isolation region (606). A gate line (608) is positioned above the protruding portions (604) of the non-planar active region as well as above a portion of the isolation region (606). As illustrated, the gate line (608) comprises a gate electrode (650) and a gate dielectric layer (652). In one embodiment, the gate line (608) may also comprise a dielectric cap layer (654). A gate contact (614) and a gate contact via (616) above it are also shown, in this view, together with a metal interconnect (660) above it, all of which are positioned within interlayer dielectric stacks or layers (670). Also, as seen in Fig. 6a, the gate contact (614) is positioned over the isolation region (606) in one embodiment, but not over the non-planar active regions.

[0062] As also depicted in FIG. 6a, in one embodiment, artifacts of pin-selective recessing remain in the final structure. For example, in the illustrated embodiment, a residual protrusion (699) remains. In other embodiments, as previously described, a recess may remain.

[0063] As also depicted in FIG. 6a, in one embodiment, an interface (680) exists between the protruding fin portion (604) and the sub-fin region (605). The interface (680) may be a transition region between the doped sub-fin region (605) and the upper fin portion (604) that is low-concentration doped or undoped. In such an embodiment, each fin is approximately 10 nanometers or less in width, and sub-fin dopants are supplied from an adjacent solid-state doping layer at the sub-fin location. In a specific such embodiment, each fin is less than 10 nanometers in width.

[0064] Referring to FIG. 6b, the gate line (608) is shown positioned above the protruding pin portions (604). The source and drain regions (604A and 604B) of the protruding pin portions (604) can be seen in this view. In one embodiment, the source and drain regions (604A and 604B) are doped portions of the original material of the protruding pin portions (604). In another embodiment, the material of the protruding pin portions (604) is removed and replaced with another semiconductor material, for example, by epitaxial deposition. In either case, the source and drain regions (604A and 604B) may extend below the height of the dielectric layer (606), i.e., into the sub-pin region (605). According to one embodiment of the present disclosure, sub-fin regions that are doped to a higher concentration, i.e., doped portions of the fins below the interface (680), suppress source-to-drain leakage through this portion of the bulk semiconductor fins.

[0065] In one embodiment, the semiconductor structure or device (600) is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In this embodiment, the corresponding semiconducting channel region is composed of or formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines (608) surround at least the top surface and a pair of sidewalls of the three-dimensional body.

[0066] The substrate (602) may be composed of a semiconductor material capable of withstanding a manufacturing process and capable of migrating charges. In one embodiment, the substrate (602) is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof to form an active region (604). In one embodiment, the concentration of silicon atoms within the bulk substrate (602) is greater than 97%. In another embodiment, the bulk substrate (602) is composed of an epitaxial layer grown on a separate crystalline substrate, e.g., a silicon epitaxial layer grown on a boron-doped bulk silicon single-crystal substrate. Alternatively, the bulk substrate (602) may be composed of a Group III-V material. In one embodiment, the bulk substrate (602) is composed of a Group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate (602) is composed of a Group III-V material, and the charge carrier dopant impurity atoms are such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0067] The isolation region (606) may be composed of a material suitable for ultimately electrically isolating parts of the permanent gate structure from the bulk substrate below, or for isolating active regions formed within the bulk substrate below, such as isolating pin active regions. For example, in one embodiment, the isolation region (606) is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0068] The gate line (608) may be composed of a gate electrode stack comprising a gate dielectric layer (652) and a gate electrode layer (650). In one embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Additionally, a portion of the gate dielectric layer may include a layer of natural oxide formed from the upper few layers of the substrate (602). In one embodiment, the gate dielectric layer is composed of a lower portion and an upper high-K portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some embodiments, one portion of the gate dielectric is a “U” shaped structure comprising a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate.

[0069] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In certain embodiments, the gate electrode is composed of a non-work-function setting charge material formed on a metal work-function setting layer. The gate electrode layer may be composed of a P-type work-function metal or an N-type work-function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work-function metal layers and at least one metal layer is a conductive charge layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer will enable the formation of a PMOS gate electrode having a work function of about 4.9 eV to about 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode having a work function of about 3.9 eV to about 4.2 eV. In some embodiments, the gate electrode may be formed of a “U” shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments of the present disclosure, the gate electrode may be composed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0070] Spacers associated with gate electrode stacks may be composed of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts, such as self-aligning contacts, or for contributing to such isolation. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0071] The gate contact (614) and the gate contact via (616) above it may be composed of a conductive material. In one embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0072] In one embodiment (although not illustrated), providing the structure (600) involves forming a contact pattern that aligns very well with the existing gate pattern while eliminating the use of lithography operations with a very strict registration budget. In such an embodiment, this approach enables the use of wet etching, which is inherently highly selective (compared to dry or plasma etching implemented in a conventional manner, e.g.), to create contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In such an embodiment, this approach makes it possible to eliminate the need for critical lithography operations, which would otherwise not be necessary to create the contact pattern as used in conventional approaches. In one embodiment, the trench contact grid is not patterned separately but is rather formed between the poly (gate) lines. For example, in such an embodiment, the trench contact grid is formed following the gate grating patterning but before the gate grating cuts.

[0073] Additionally, the gate stack structure (608) may be manufactured by an alternative gate process. In this scheme, a dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, unlike in a more earlier processing. In one embodiment, the dummy gates are removed by a dry etching or wet etching process. In one embodiment, the dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed using a dry etching process involving the use of SF6. In another embodiment, the dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed using a wet etching process involving the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gates are composed of silicon nitride and are removed using a wet etching process involving aqueous phosphoric acid.

[0074] In one embodiment, one or more approaches described herein consider essentially combining a dummy and alternate gate process with a dummy and alternate contact process to reach a structure (600). In such an embodiment, the alternate contact process is performed after the alternate gate process to enable high-temperature annealing of at least a portion of the permanent gate stack. For example, in such a particular embodiment, annealing of at least a portion of the permanent gate structures is performed at a temperature of approximately 600°C or higher, for example, after the gate dielectric layer is formed. The annealing is performed prior to the formation of the permanent contacts.

[0075] Referring again to FIG. 6a, the arrangement of the semiconductor structure or device (600) places the gate contacts above the isolation regions. Such an arrangement may be considered an inefficient use of layout space. However, in other embodiments, the semiconductor device has contact structures that contact portions of the gate electrode formed above the active region. Generally, prior to (e.g., in addition thereto) forming a gate contact structure (such as a via) above the active portion of the gate and on the same layer as the trench contact via, one or more embodiments of the present disclosure first include using a gate-aligned trench contact process. This process may be implemented to form trench contact structures for manufacturing semiconductor structures, e.g., for manufacturing integrated circuits. In one embodiment, a trench contact pattern is formed aligned with an existing gate pattern. In contrast, conventional approaches typically involve an additional lithography process involving strict registration of a lithographic contact pattern on an existing gate pattern along with selective contact etchings. For example, a conventional process may include patterning of a poly (gate) grid along with separate patterning of contact features.

[0076] It should be recognized that not all aspects of the processes described above need to be implemented within the spirit and scope of the embodiments of this disclosure. For example, in one embodiment, dummy gates never need to be formed prior to manufacturing gate contacts on the active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as formed initially. Additionally, the processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal oxide semiconductor (MOS) transistors for logic or memory, or bipolar transistors. Also, in one embodiment, the semiconductor devices have a three-dimensional architecture, such as a tri-gate device, an independently accessed double-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices with a sub-10 nanometer (10 nm) technology node.

[0077] In the exemplary FEOL embodiments above, it should be recognized that in one embodiment, sub-10 nanometer processing is directly implemented within the fabrication schemes and resulting structures. In other embodiments, FEOL considerations may be governed by BEOL sub-10 nanometer processing requirements. For example, material selection and layouts for FEOL layers and devices may need to accommodate BEOL sub-10 nanometer processing. In such an embodiment, material selection and gate stack architectures are chosen to accommodate high-density metallization of the BEOL layers, for example, to reduce fringe capacitance in transistor structures formed on the FEOL layers but coupled to each other by the high-density metallization of the BEOL layers. As such, FEOL structures and processing may be directly affected by sub-10 nanometer processing or indirectly affected as a result of sub-10 nanometer processing of the BEOL layers.

[0078] The back-end-of-line (BEOL) layers of integrated circuits typically include electrically conductive microelectronic structures, known in the art as vias, to electrically connect metal lines or other interconnects on the vias to metal lines or other interconnects below the vias. The vias are typically formed by a lithography process. Typically, a photoresist layer may be spin-coated over a dielectric layer, the photoresist layer may be exposed to actinic radiation patterned through a patterned mask, and the exposed layer may then be developed to form an opening in the photoresist layer. Next, an opening for the via may be etched into the dielectric layer by using the opening in the photoresist layer as an etching mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

[0079] In the past, via sizes and spacing have gradually decreased, and for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.), via sizes and spacing are expected to continue gradually decreasing in the future. When patterning extremely small vias with extremely small pitches by such lithography processes, several challenges arise. One such challenge is that the overlay between vias and overlay interconnects, and the overlay between vias and underlay interconnects, generally need to be controlled with high tolerances of about one-quarter of the via pitch. As via pitches scale increasingly smaller over time, overlay tolerances tend to scale along with the via pitches at a rate much faster than the lithography equipment can keep up with.

[0080] Another such challenge is that the critical dimensions of via apertures generally tend to scale faster than the resolution capabilities of lithography scanners. Reduction techniques exist to reduce the critical dimensions of via apertures. However, the amount of reduction tends to be limited by the minimum via pitch as well as the ability of the reduction process to be sufficiently optical proximity correction (OPC) neutral, and tends not to significantly impair line width roughness (LWR) and / or critical dimension uniformity (CDU). Another such challenge is that the LWR and / or CDU characteristics of photoresists generally need to be improved as the critical dimensions of via apertures are reduced in order to maintain the same overall fraction of the critical dimension budget. However, the LWR and / or CDU characteristics of most photoresists currently are not improving as rapidly as the critical dimensions of via apertures are reduced.

[0081] An additional such challenge is that extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithography scanners. As a result, several different lithography masks may typically be used, which tends to increase costs. At some point, as pitches continue to decrease, it may not be possible to print via apertures for these extremely small pitches using EUV scanners, even with the use of multiple masks.

[0082] The above factors are also relevant to considering the placement and scaling of non-conductive spaces or interruptions between metal lines (referred to as "plugs," "dielectric plugs," or "metal line ends" between metal lines of BEOL (back end of line) metal interconnect structures). The above factors are also relevant to conductive tabs, which are conductive linkers between two conductive metal lines, such as between two parallel conductive lines, by definition. Tabs are typically on the same layer as the metal lines. Accordingly, improvements are needed in the field of back-end metallization manufacturing techniques for fabricating metal lines, metal vias, conductive tabs, and dielectric plugs.

[0083] In some of the embodiments described below, the patterning and alignment of via features (or other BEOL features) are achieved using several reticles and critical alignment strategies. In other embodiments, however, the approaches described herein enable the fabrication of self-aligned plugs and / or vias. In the latter embodiments, this may be a case where only one critical overlay step (Mx+1 grating) needs to be implemented.

[0084] It should be recognized that the layers and materials described below in relation to BEOL (back end of line) structures and processing are typically formed on or above an underlying semiconductor substrate or structure, such as device layer(s) located beneath an integrated circuit. In one embodiment, the underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often comprises a wafer or other piece of silicon or other semiconductor material. Suitable semiconductor substrates include, but are not limited to, single-crystal silicon, polycrystalline silicon, and SOI (silicon on insulator), as well as similar substrates formed from other semiconductor materials, such as substrates containing germanium, carbon, or III-V materials. Depending on the manufacturing stage, the semiconductor substrate often comprises transistors, integrated circuit parts, and similar components. The substrate may also comprise semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the illustrated structures can be manufactured on the lower-level interconnect layers below.

[0085] Although the following methods for manufacturing the metallization layer of the BEOL metallization layer or parts of the metallization layer of the BEOL metallization layer are described in detail in relation to selected operations, it should be recognized that additional or intermediate operations for manufacturing may include standard microelectronic manufacturing processes such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etching stop layers, the use of planarization stop layers, and / or any other action associated with the manufacture of microelectronic components. Furthermore, it should be recognized that the process operations described for the following process flows may be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed.

[0086] In some cases, the resulting structures enable the fabrication of vias centered directly on the underlying metal lines. The vias may be wider, narrower, or have the same thickness as the underlying metal lines, for example, due to imperfect selective etching processing. Nevertheless, in one embodiment, the centers of the vias are aligned (matched up) with the centers of the metal lines. As such, in one embodiment, an offset resulting from conventional lithography / dual damascene patterning, which must otherwise be allowed, may not be a factor for the resulting structures of one or more of the following process schemes.

[0087] It should be recognized that some of the interconnect manufacturing schemes described below may be implemented to reduce numerous alignments / exposures, to improve electrical contact (e.g., by reducing via resistance), or otherwise to reduce the total process operations and processing time required to pattern such features using conventional approaches. It should be recognized that in subsequent or additional manufacturing operations other than those illustrated, in some cases, dielectric layer(s) may be removed from the layer of metal lines to provide air gaps between the metal lines.

[0088] According to one embodiment of the present disclosure, a backbone approach is described. The backbone approach may involve a number of stages of atomic layer deposition (ALD). In one embodiment, dense pitch formation is achieved by iterative spacer formation, for example, using ALD processing.

[0089] To provide context, the lithographic patterning of features for semiconductor manufacturing is limited by the resolution of the imaging tool, whether it is optical (e.g., 193 nm), electron beam, or EUV. Process methods such as multiple pass patterning, pattern shrink methods, and spacer-based pitch splitting may be used to expand the resolution by two to four times, or even perhaps eight times. However, such methods may be limited in that process variations in the original lithography steps remain of a similar magnitude in the final pattern. For example, a lithography operation may have a variation of + / - 3 nm. If this is utilized in pitch splitting process methods to produce a final pitch of 8 nm (4 nm feature size), the resulting final patterns vary by 4 nm + / - 3 nm.

[0090] One or more embodiments described herein involve using iterative spacers or thin film deposition to define all or substantially all of the final critical small features for a layer such as a BEOL layer. Variations of such features may be better than + / - 1 nm, which is consistent with ALD technology. A number of materials may be used so that the "coloring" of the patterns can handle alternative features (e.g., vias, cuts, plugs, etc.) with an enlarged margin for edge placement errors.

[0091] FIGS. 7a and 7b illustrate cross-sectional views of target base structures for enabling very dense pitch final patterns for semiconductor layers according to embodiments of the present disclosure.

[0092] Referring to FIG. 7a, the target base layer (700) comprises a patterning layer (702) on a hard mask layer (704) on a transfer layer (706) on a substrate (708). The patterning layer (702) comprises backbone features (710). The backbone features (710) are relatively wider features (e.g., 6 to 12 nanometers) having interposed groupings (712) of relatively smaller features (e.g., 6 to hundreds of smaller features between adjacent backbone features (710), where the smaller features are, for example, 4 to 6 nanometers wide).

[0093] In one embodiment, each of the interposed groups (712) of relatively smaller features includes small features (716) of a first material type, small features (714) of a second material type different from the first material type, and small features (718) of a third material type different from the first and second material types. Differences in material types may provide different etching characteristics or selectivity between material types. In one embodiment, as depicted in FIG. 7a, the material of the backbone features (710) is the same as the material of the small features (718) of the third material type. In another embodiment, the material of the backbone features (710) is different from the material of the small features (718) of the third material type, but has etching characteristics or selectivity similar to the small features (718) of the third material type.

[0094] Referring to FIG. 7b, the target base layer (750) comprises a patterning layer (752) on a hard mask layer (754) on a transfer layer (756) on a substrate (758). The patterning layer (752) comprises backbone features (760). The backbone features (760) are relatively wider features (e.g., 6 to 12 nanometers) having interposed groupings (762) of relatively smaller features (e.g., 6 to hundreds of smaller features between adjacent backbone features (760), where the smaller features are, for example, 4 to 6 nanometers wide).

[0095] In one embodiment, each of the interposed groups (762) of relatively smaller features includes small features (764) of a first material type, small features (766) of a second material type different from the first material type, and small features (768) of a third material type different from the first material type and the second material type. Differences in material types may provide different etching characteristics or selectivity between material types. In one embodiment, as depicted in FIG. 7b, the material of the backbone features (760) is the same as the material of the small features (766) of the second material type. In another embodiment, the material of the backbone features (760) is different from the material of the small features (766) of the second material type, but has etching characteristics or selectivity similar to the small features (766) of the second material type.

[0096] Referring to both FIG. 7a and FIG. 7b, in one embodiment, the structures (700 or 750) comprise several repeating vertical layers of alternating materials that ultimately define the final locations of features (e.g., metals, transistors, etc.) in the semiconductor pattern. Because they have greater size variation, in one embodiment, there are occasionally larger features when they represent larger (wider) lithographically defined structures. In one embodiment, there are six to several hundred narrow features among the wide features.

[0097] FIGS. 8a through 8h illustrate cross-sectional views illustrating various operations in a method for manufacturing target base structures to enable very dense pitch final patterns for semiconductor layers according to embodiments of the present disclosure. Overall, in one embodiment, iterative thin film generation operations are utilized. For example, conformal thin film deposition followed by anisotropic etching (e.g., spacer formation), selective growth, or directed self-assembly (DSA) is performed. A patterning process such as that described below can be implemented to provide a patterning process suitable for generating very dense pitch final patterns for semiconductor layers. In one embodiment, advantages of implementing such a process flow include improved dimensional control of dense pitch features using a built-in method of coloring alternating features to enable self-aligned vias, plugs, and cuts.

[0098] FIG. 8a illustrates a process operation involving tall backbone formation. Multiple backbone features (808) are formed on a hard mask layer (806) formed on a transfer layer (804) formed on a substrate (802). In one embodiment, the formation of multiple backbone features (808) involves the use of a standard lithography operation (e.g., 193 nm or EUV) followed by etching transfer to a hard mask (e.g., SiN, SiO2, SiC) and subsequently the removal of any remaining resist and / or anti-reflective layers (e.g., through ashing or wet cleaning).

[0099] FIG. 8b illustrates a process operation involving the formation of a first spacer (spacer 1). A first set of small features (810) of a first material composition is formed along the sidewalls of each of the plurality of backbone features (808). In one embodiment, the first set of small features (810) is formed using a deposition (e.g., ALD) and etching approach. In another embodiment, the first set of small features (810) is formed using a selective growth approach.

[0100] FIG. 8c illustrates a process operation involving the formation of a second spacer (spacer 2), the formation of a third spacer (spacer 3), and the formation of a fourth spacer (spacer 4), having specific layers illustrated as one possible exemplary embodiment. A second set of small features (812) of a second material composition is formed along the exposed sidewalls of each of the first set of small features (810). A third set of small features (814) of a third material composition is formed along the exposed sidewalls of each of the second set of small features (812). A fourth set of small features (816) of a second material composition is formed along the exposed sidewalls of each of the third set of small features (814). In one embodiment, the second set of small features (812) is first formed using a deposition (e.g., ALD) and etching approach or a selective growth approach. A third set of small features (814) is subsequently formed using a different deposition (e.g., ALD) and etching approach or a selective growth approach. A fourth set of small features (816) is subsequently formed using a different deposition (e.g., ALD) and etching approach or a selective growth approach.

[0101] FIG. 8d illustrates a process operation involving the creation of a series of layers. Additional spacer layers (818) are formed sequentially according to a selected order of material types. The additional spacer layers (818) may be manufactured using deposition and etching approaches, selective growth approaches, or a combination thereof. It should be recognized that more layers than are illustrated may be added. For example, in one embodiment, 20 to 200 additional sets of spacers are formed at this stage. The deposition of spacers may be completed prior to the merging of adjacent sidewall growths, for example, spacer formation is stopped when an opening (820) remains. Although deposition and etching approaches or selective growth approaches are described as options for FIG. 8a through 8d, it should be recognized that directed self-assembly (DSA) may be used instead of or as one of the options for spacer formation described herein. In such an example, a tri-block based DSA is used. An example of a tri-block based DSA is described below in connection with FIGS. 12a to 12k.

[0102] In one embodiment, referring collectively to FIGS. 8a through 8d, the iterative generation of thin layers of alternating materials on sides of the original lithography-defined template features is performed. One potential method for achieving such a structure is through thin film deposition followed by anisotropic etching. In one embodiment, a single-process tool is used to perform both deposition and etching to significantly improve the efficiency of this approach. Other methods for generating thin layers of well-controlled thickness include selective growth or DSA.

[0103] FIG. 8e illustrates a process operation involving backbone removal. Backbone features (808) are removed, leaving openings (822). In one embodiment, as depicted in FIG. 8e, the openings (822) have a width approximately equal to the width of the opening (820). In one embodiment, each of the openings (820 and 822) has spacers (824) as sidewalls, which are spacers (824) of a first material composition. As indicated, some of the spacers (824) are reassigned from previously labeled spacers (810). In one embodiment, the backbone features (808) are removed to provide more space for creating additional small features.

[0104] FIG. 8f illustrates a process operation involving the creation of a continuous layer. The openings (820 and 822) are ultimately fully filled using the formation of a continuous spacer. In an exemplary embodiment, spacers (826) are formed along the exposed sidewalls of the spacers (824). In such an embodiment, the spacers (826) are made of a second material composition. In one embodiment, a final wide feature (828) is ultimately formed at the center of each of the openings (820 and 822) at a stage where additional spacer formation is not desired or achievable. In one embodiment, the formation of the final wide features (828) involves the merging of material growth formed along the adjacent sidewalls of the spacers (826). In such an embodiment, the merging of material growth provides the final wide features (828), each having a seam centered approximately within the final wide feature (828). In one embodiment, the final wide features (828) are made of a third material composition.

[0105] FIG. 8g illustrates a process operation involving planarization of the structure of FIG. 8f. In one embodiment, planarization is performed using a chemical mechanical polishing (CMP) operation. In one embodiment, the planarization process provides a flattened structure prior to plug / cut and via process operations. Positions (828) centered directly below the original lithographic features (resulting in the openings (822)) and spaced midway between the original lithographic features (resulting in the openings (820)) may be targeted to be larger to accommodate larger size variations associated with lithographic operations compared to a single thin film (and etching) operation. In one embodiment, as illustrated, the structure of FIG. 8g is similar or identical to that described in connection with FIG. 7a.

[0106] FIG. 8h illustrates a process operation involving the selective removal of all features of a first material composition, such as spacers (810 / 824), (corresponding to the small features (716) of the first material type from the structure of FIG. 7a as illustrated in FIG. 8g). In one embodiment, the small features (716) of the first material type are removed using a selective etching process that removes no or only a small portion of the remaining spacer materials. In the exemplary embodiment illustrated in FIG. 8h, following the removal of the small features (716) of the first material type, metal line patterning features (830) are formed in the openings created when all of the small features (716) of the first material type are removed. Some of the metal line patterning features (830) are associated with the via patterning features (832) below. Although not depicted, selected features among the small features (716) of the first material type may be retained (e.g., through a photolithographic blocking process that blocks the selected features among the small features (716) of the first material type so as not to be removed) to form plug patterning features. In one embodiment, metal line patterning features (830), via patterning features (832), and any plug patterning features are ultimately patterned into the hard mask layer (806) and the transfer layer (804) for the ultimate patterning of the layer below. In another embodiment, as depicted, the metal line patterning features (830), via patterning features (832), and any plug patterning features actually represent metal lines, vias, and plugs formed in the layer (834) as illustrated. As depicted in FIG. 8h, whether they are metal line patterning features (830) or actual metal lines, each may have a hard mask cap layer (836) on top to protect the features during subsequent processing of the layer (834).Referring again to FIG. 8h, in one embodiment, removing only one type of spacer provides an additional margin for process variation in plug, via, and / or cut patterning operations.

[0107] FIGS. 8ha ​​and FIGS. 8hb illustrate cross-sectional views of exemplary structures after via and plug patterning according to one embodiment of the present disclosure.

[0108] FIG. 8ha ​​illustrates a process operation involving the selective removal of all of the material of the backbone features (710) and all of the small features (718) of the third material type from the structure of FIG. 8h. In one embodiment, the backbone features (710) and the small features (718) of the third material type are removed using a selective etching process that removes or removes only a small amount of the remaining spacer materials or already replaced spacer materials. In the exemplary embodiment illustrated in FIG. 8ha, following the removal of the backbone features (710) and the small features (718) of the third material type, second metal line patterning features (838) are formed in most or all of the openings created when the backbone features (710) and the small features (718) of the third material type are removed. In one embodiment, any remaining openings among the openings created when removing backbone features (710) and small features (718) of the third material type are filled with a plug material (850) or preserved as plug regions (e.g., to provide a line-end feature composed of a non-conductive material such as SiN or SiO2). Some of the second metal line patterning features (838) are associated with the second via patterning features (840) below. In one embodiment, the second metal line patterning features (838), the second via patterning features (840), and any plug patterning features (850) are ultimately patterned into the hard mask layer (806) and the transfer layer (804) for the ultimate patterning of the layer below. In another embodiment, as described, the second metal line patterning features (838), the second via patterning features (840), and any plug patterning features (850) actually represent, respectively, metal lines, vias, and plugs.

[0109] As depicted in FIG. 8ha, whether the second metal line patterning features (838) or actual metal lines, or whether the patterning plug features (850) or actual plug features (850), each may have a hard mask cap layer (842) on top to protect the features during subsequent processing operations. In one embodiment, the hard mask cap layer (842) on top has a different composition compared to the hard mask cap layer (836) on top. Thus, in one embodiment, the alternating features have different hard mask materials. Such an arrangement can better facilitate subsequent connection of vias from a layer subsequently formed on top using an increased edge placement margin to prevent vias to the wrong metal features.

[0110] It should be recognized that because the metal lines (830) (or patterning features) and the second metal lines (838) (or patterning features) are formed in different processing operations, the compositions of the metal lines (830) and the second metal lines (838) may be different. In an exemplary embodiment, FIG. 8hb illustrates an example in which the metal lines (830') have a different composition from the metal lines (838). Accordingly, the alternating features may be composed of different conductive materials.

[0111] It should be recognized that any prior forms of spacer-based pitch splitting techniques can be used in mass manufacturing. The embodiments described above regarding the backbone approach can be implemented to extend one or two passes of spacer-based pitch splitting into a very high number of iterative spacer formation operations. One or more embodiments provide an approach for scaling semiconductor chip density at high manufacturing yields. One or more embodiments provide an approach for manufacturing high-density interconnects, or even transistors (when applied to FEOL processing), having consistently well-formed feature sizes. It should be recognized that reverse engineering of a product manufactured using the backbone approach can reveal predominantly dense pitch features (e.g., sub-10 nm pitch features) having occasionally wide one-dimensional (1D) features. Cross-sectional scanning electron microscopy (XSEM) can reveal "colored" (different from each other in terms of properties such as etching selectivity) hardmasks on alternating features.

[0112] According to one embodiment of the present disclosure, pitch splitting is applied to provide an approach for manufacturing alternating metal lines in a BEOL manufacturing scheme. One or more embodiments described herein relate to pitch splitting patterning process flows that increase the overlay margin for vias, cuts, and plugs. The embodiments can enable continuous scaling of the pitch of metal layers beyond the resolution capabilities of prior art lithography equipment. In one embodiment, the spacing between metal lines is constant and can be controlled to angstrom-level precision using ALD. In one embodiment, the process flow is designed to allow for an "alternative ILD" flow. That is, the ILD can be deposited after patterning and metallization are completed. While patterning flows typically damage the ILD through etching / cleaning steps, in this flow, the ILD can be deposited last and thus avoid damage during patterning.

[0113] To provide context, edge placement errors in via, cut, and plug patterning become a problem when feature sizes and pitches are scaled. Conventional solutions to address such problems involve attempts to tighten edge placement errors by improving scanner overlays and critical dimension (CD) control, or attempts to use super-self-aligned integration approaches. In contrast, the embodiments described herein involve the implementation of a process capable of achieving similar improvements in edge placement error margins without requiring improvements in lithographic tooling or super-self-alignment.

[0114] According to one embodiment of the present disclosure, metal lines are manufactured in two separate work sequences to double the amount of overlay margin for cuts / plugs and via patterning. In the first part of an exemplary process flow, pitch splitting methods are used to pattern metal lines, plugs, and subsequently vias in an interlayer dielectric material. In the second part of an exemplary process flow, trenches / via openings are filled with metal (e.g., dual damascene metallization) and subsequently polished. Sacrificial hardmask layers are subsequently removed between the metal lines. The metal lines are subsequently coated with a sacrificial dielectric material, for example, using atomic layer deposition (ALD). In the third part of an exemplary process flow, isotropic spacer etching is performed to expose the bottoms of the trenches. Using a plug patterning flow, dielectric material is added at locations where metal line ends are to occur, and via etchings are completed on the complementary metal lines. The metal from the first metal lines functions as an etching stop to prevent etching at these locations. In the fourth part of the exemplary process flow, the trenches are filled with metal and polished to expose the metal. After polishing, to complete the metallization process, the sacrificial hard mask material is removed, optionally replaced with a dielectric material, and then polished again. By tuning the deposition of the dielectric material, air gaps may also be inserted. Additionally, the embodiments may involve the use of a sacrificial hard mask material instead of metal. The sacrificial hard mask may be removed and replaced with metal during the "second" metallization operation.

[0115] In an exemplary processing scheme, FIGS. 9a through 9l illustrate inclined cross-sectional views of portions of integrated circuit layers representing various operations in a method involving pitch-divided patterning with an increased overlay margin for manufacturing a back-end-of-line (BEOL) interconnect according to one embodiment of the present disclosure.

[0116] Referring to FIG. 9a, a starting point structure (900) is provided as a starting point for manufacturing a new metallization layer. The starting point structure (900) includes a hard mask layer (902) disposed on a sacrificial layer (904) disposed on an interlayer dielectric (ILD) layer (906). The ILD layer may be disposed on a substrate and, in one embodiment, is disposed above the metallization layer below. In one embodiment, the hard mask layer (902) is a silicon nitride (SiN) or titanium nitride hard mask layer. In one embodiment, the sacrificial layer is a silicon layer, such as a polycrystalline silicon layer or an amorphous silicon layer.

[0117] Referring to FIG. 9b, the hard mask layer (902) and the sacrificial layer (904) of the structure of FIG. 9b are patterned. The hard mask layer (902) and the sacrificial layer (904) are patterned to form, respectively, a patterned hard mask layer (908) and a patterned sacrificial layer (910). The patterned hard mask layer (908) and the patterned sacrificial layer (910) include patterns of first line openings (912) and line end regions (914). In one embodiment, the silicon sacrificial layer is suitable for patterning fine features using an anisotropic plasma etching process. In one embodiment, a lithography resist mask exposure and etching process is used to form the patterned hard mask layer (908) and the patterned sacrificial layer (910) along with the subsequent removal of the resist layer or stack. In one embodiment, as depicted in FIG. 9b, the first line openings (912) have a grating-type pattern. In one embodiment, a pitch-divided patterning scheme is used to form the pattern of the first line openings (912). Examples of suitable pitch-divided schemes are described in more detail below. A subsequent line "cut" or plug-preserving lithography process may be used to define line end regions (914).

[0118] FIG. 9c illustrates the structure of FIG. 9b after via location patterning below. Via openings (916) may be formed at selected locations of the ILD layer (906) to form a patterned ILD layer (918). In one embodiment, the vias are patterned using a self-aligned via process. The selected locations are formed within regions of the ILD layer (906) exposed by the first line openings (912). In one embodiment, separate lithography and etching processes are used to form the via openings (916) following the lithography patterning process used to form the first line openings (912).

[0119] FIG. 9d illustrates the structure of FIG. 9c after the first metallization process. In one embodiment, a dual damascene metallization process is used in which vias and metal lines are filled simultaneously. Interconnect lines (920) and conductive vias (920) are formed in the first line openings and via openings (916). In one embodiment, a metal filling process is performed to provide the interconnect lines (920) and conductive vias (920). In one embodiment, the metal filling process is performed using a metal deposition and a subsequent planarization processing scheme, such as a chemical mechanical planarization (CMP) process. Where the patterned sacrificial hard mask layer (910) is substantially composed of silicon, a liner material may be deposited before forming the conductive filling layer to suppress silicide formation of the patterned sacrificial hard mask layer (910).

[0120] FIG. 9e illustrates the structure of FIG. 9d after the exposure of interconnect lines (920). The patterned hard mask layer (908) and the patterned sacrificial layer (910) are removed, leaving the interconnect lines (920) exposed along with the conductive vias underneath the patterned ILD layer (918). Line end openings (924) are exposed. The line end openings (924) provide breaks in the grating pattern of the interconnect lines (920). In one embodiment, the patterned hard mask layer (908) and the patterned sacrificial layer (910) are removed using an optional wet etching process.

[0121] FIG. 9f illustrates the structure of FIG. 9e after the formation of the conformal patterning layer. The spacer material layer (926) is formed over the grating pattern of the interconnect lines (920) and is conformal to this grating pattern. In one embodiment, atomic layer deposition (ALD) is used due to the fact that ALD is highly conformal and extremely precise (e.g., controlled at the angstrom level). It should be recognized that, in one embodiment, the line end openings (924) are too short to effectively block the overall grating pattern of the interconnect lines (920) in relation to the formation of the conformal spacer material layer (926). In such an embodiment, the line end openings (924) are filled with the spacer material layer (926) without blocking the overall grating pattern of the interconnect lines (920). In one embodiment, the spacer material layer (926) is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In one embodiment, the spacer material layer (926) is a silicon layer, such as a polycrystalline silicon layer or an amorphous silicon layer. In this particular embodiment, a liner material is deposited on the interconnect lines (920) before forming the silicon spacer material layer to suppress silicide formation of the spacer material layer (926). In one embodiment, the line end cuts (plugs) are no more than twice the thickness of the spacer so as to be fully filled with conformal dielectric material. If they are more than twice the thickness, seams may be formed and the metal may short-circuit the lines together during subsequent processing.

[0122] FIG. 9g illustrates the structure of FIG. 9f after the formation of spacer lines from a spacer material layer. In one embodiment, spacers (928) are formed along the sidewalls of interconnect lines (920) using an anisotropic plasma etching process. In one embodiment, a spacer material layer (926) remains in the line end openings (924) to form line end placeholder portions (930) for the interconnect lines (920).

[0123] FIG. 9h illustrates the structure of FIG. 9g after the formation of the plug placeholder layer. The plug placeholder layer (932) is formed between the spacers (928) of adjacent interconnect lines (920). The plug placeholder layer (932) is initially formed at the locations where the second set of interconnect lines will ultimately be formed. In one embodiment, the plug placeholder layer (932) is formed using a deposition and flattening process that defines the plug placeholder layer (932) between the spacers (928).

[0124] FIG. 9i illustrates the structure of FIG. 9h after patterning of the plug placeholder layer. The plug placeholder layer (932) is patterned to retain plug placeholders (934) at selected locations where line ends are ultimately formed. In one embodiment, a lithography resist mask exposure and etching process is used to form the plug placeholders (934) along with the subsequent removal of the resist layer or stack.

[0125] FIG. 9j illustrates the structure of FIG. 9i after the second metallization process. Interconnect lines (936) are formed in the openings (second line openings) formed during the patterning of the plug placeholder layer (932) to form the plug placeholders (934). Additionally, although separate processing operations are omitted from the drawings, via openings, and ultimately conductive vias (938), may be formed at selected locations below the conductive lines (936). Such a process results in a double-patterned (two different via patterning operations) ILD layer (940) as depicted in FIG. 9j.

[0126] In one embodiment, a metal filling process is performed to provide interconnect lines (936) and conductive vias (938). In one embodiment, the metal filling process is performed using a metal deposition and a subsequent planarization processing scheme, such as a chemical mechanical planarization (CMP) process. Where the spacers (928) are substantially composed of silicon, a liner material may be deposited before forming the conductive filling layer to suppress silicide formation of the spacers (928).

[0127] In one embodiment, since the interconnect lines (936) (and corresponding conductive vias (938)) are formed in a later process than the process used to manufacture the interconnect lines (920) (and corresponding conductive vias (922)), it should be recognized that the interconnect lines (936) may be manufactured using a different material than that used to manufacture the conductive lines (920). In such an embodiment, the metallization layer ultimately comprises conductive interconnects of different first and second compositions that alternate.

[0128] FIG. 9k illustrates the structure of FIG. 9j after exposure of two sets of interconnect lines (920 and 936). The spacers (928), line end placeholder portions (930), and plug placeholders (934) are removed, leaving the interconnect lines (920 and 936) respectively exposed along with the conductive vias (922 and 938) underneath the patterned ILD layer (940). Line end openings (942) are exposed. The line end openings (942) provide breaks in the grating pattern of the interconnect lines (920) and the grating pattern of the interconnect lines (936). In one embodiment, the spacers (928), line end placeholder portions (930), and plug placeholders (934) are removed using an optional wet etching process.

[0129] In one embodiment, the structure of FIG. 9k represents a final metallized structure having an air gap architecture. That is, an air gap architecture is made possible because the interconnect lines (920 and 936) are ultimately exposed in the process described herein. In another embodiment, because the interconnect lines (920, 936) are exposed at this stage of the process, there is an opportunity to remove the sidewall portions of the diffusion barrier layer of the interconnect lines. For example, in one embodiment, the removal of such a diffusion barrier layer physically thins the conductive features of the interconnect lines (920 and 936). In another embodiment, the resistance of such interconnect lines (920 and 936) is reduced upon the removal of the sidewall portions of such a diffusion barrier layer. As labeled in FIG. 9k, features of the sidewall portions (960) of the interconnect lines (920 and 936) are exposed, while the portions (962) below the lines are not exposed. As such, in one embodiment, the diffusion barrier layer of the interconnect lines (920 and 936) is removed from the sidewalls (960) of the interconnect lines (920 and 936) but not from the regions (962) of the interconnect lines (920 and 936). In a specific embodiment, the removal of the sidewall portions of such a diffusion barrier layer entails the removal of the Ta and / or TaN layer.

[0130] Accordingly, referring to operations (9A through 9K), in one embodiment, a method for manufacturing a back end of line (BEOL) metallization layer comprises the step of forming a plurality of conductive lines (920 / 936) in a sacrificial material (928) formed on a substrate. Each of the plurality of conductive lines (920 / 936) comprises a barrier layer formed along the bottom and sidewalls of a conductive fill layer. The sacrificial material (928) is subsequently removed. The barrier layer is removed from the sidewalls of the conductive fill layer (e.g., at location (960)). In one embodiment, the step of removing the barrier layer from the sidewalls of the conductive fill layer comprises the step of removing a tantalum or tantalum nitride layer from the sidewalls of the conductive fill layer comprising a material selected from the group consisting of Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof.

[0131] FIG. 91 illustrates the structure of FIG. 9k after the formation of a permanent ILD layer. An interlayer dielectric (ILD) layer (946 / 948) is formed between interconnect lines (920 and 936). The ILD layer (946 / 948) includes portions (946) between interconnect lines (920 and 936). The ILD layer (946 / 948) also includes line end (or dielectric plug) portions (948) at the locations of line breaks of interconnect lines (920 and 936) and between line breaks.

[0132] Referring again to FIG. 9l, in one embodiment, the semiconductor structure (999) comprises a substrate (an ILD layer (940) underneath it is shown). A plurality of alternating first (920) and second (936) conductive line types are arranged along the same direction of the back-end-of-line (BEOL) metallization layer placed on the substrate. In one embodiment, as described in relation to FIG. 9k, the overall composition of the first conductive line type (920) is different from the overall composition of the second conductive line type (936). In such a particular embodiment, the overall composition of the first conductive line type (920) is substantially composed of copper, and the overall composition of the second conductive line type (936) is substantially composed of a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof, or vice versa. However, in another embodiment, the total composition of the first conductive line type (920) is the same as the total composition of the second conductive line type (936).

[0133] In one embodiment, the lines of the first conductive line type (920) are spaced apart by a certain pitch, and the lines of the second conductive line type (936) are spaced apart by the same pitch. In one embodiment, a plurality of alternating first and second conductive line types are placed in an interlayer dielectric (ILD) layer (946 / 948). However, in another embodiment, as described in connection with FIG. 9k, the lines of the plurality of alternating first and second conductive line types (920 / 936) are separated by an air gap.

[0134] In one embodiment, each of the lines of the plurality of alternating first and second conductive line types (920 / 936) includes a barrier layer disposed along the bottom and sidewalls of the line. However, in another embodiment, as described in the embodiment of FIG. 9k, each of the lines of the plurality of alternating first and second conductive line types (920 / 936) includes a barrier layer disposed along the bottom (962) of the line but not along the sidewalls (960) of the line. In one embodiment, one or more of the lines of the plurality of alternating first and second conductive line types are connected to a via (922 / 938) located below, which is connected to a metallized layer located below the semiconductor structure. In one embodiment, one or more of the lines of the plurality of alternating first and second conductive line types (920 / 936) are interrupted by a dielectric plug (948).

[0135] The resulting structure (999), such as that described in relation to FIG. 9l (or the air gap structure of FIG. 9k), can subsequently be used as a basis for forming subsequent metal lines / vias and ILD layers. Alternatively, the structure (999) of FIG. 9l (or the structure of FIG. 9k) may represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations may be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. It should also be recognized that the examples focus on forming metal lines and plugs or line ends. However, in other embodiments, similar approaches may be used to form via openings in the ILD layer.

[0136] According to one or more embodiments of the present disclosure, self-aligned DSA double-block or selective growth bottom-up approaches are described. One or more embodiments described herein relate to self-aligned via and plug patterning. The self-alignment mode of the processes described herein may be based on a directed self-assembly (DSA) mechanism, as described in more detail below. However, it should be recognized that selective growth mechanisms may be used instead of or in combination with DSA-based approaches. In one embodiment, the processes described herein enable the realization of self-aligned metallization for back-end of line (BEOL) feature fabrication. More specifically, one or more embodiments relate to an approach using the metal below as a template for building non-conductive spaces or interruptions (referred to as "plugs") between conductive vias and metals.

[0137] FIGS. 10a through 10m illustrate portions of integrated circuit layers representing various operations in a method of self-aligned vias and metal patterning according to one embodiment of the present disclosure. In each example of each described operation, plan views are shown on the left and corresponding cross-sectional views are shown on the right. These drawings will be referred to herein as corresponding cross-sectional views and plan views.

[0138] FIG. 10a illustrates plan views and corresponding cross-sectional views of options for a prior layered metallized structure according to one embodiment of the present disclosure. Referring to plan view and corresponding cross-sectional view option (a), the start structure (1000) includes a pattern of metal lines (1002) and interlayer dielectric (ILD) lines (1004). The start structure (1000) may be patterned into a grating-like pattern having metal lines spaced at a constant pitch and having a constant width, as depicted in FIG. 10a (e.g., for DSA embodiments, but not necessarily for directed selective growth embodiments). The pattern may be produced, for example, by a pitch 2-part or pitch 4-part approach. Some of the lines may be associated with underlying vias, such as line (1002') shown as an example in the cross-sectional views.

[0139] Referring again to FIG. 10a, alternative options (b) through (f) address situations in which an additional film is formed on the surface of one or both of the metal lines (1002) and the interlayer dielectric lines (1004) (e.g., deposited, grown, or left as an artifact remaining from a previous patterning process). In example (b), an additional film (1006) is placed on the interlayer dielectric lines (1004). In example (c), an additional film (1008) is placed on the metal lines (1002). In example (d), an additional film (1006) is placed on the interlayer dielectric lines (1004), and an additional film (1008) is placed on the metal lines (1002). Furthermore, although the metal lines (1002) and interlayer dielectric lines (1004) are depicted as coplanar in (a), in other embodiments they are not coplanar. For example, in (e), the metal lines (1002) protrude over the interlayer dielectric lines (1004). In example (f), the metal lines (1002) are recessed under the interlayer dielectric lines (1004).

[0140] Referring again to Examples (b) through (d), an additional layer (e.g., layer (1006 or 1008)) may be used as a hard mask (HM) or a protective layer, or may be used to enable selective growth and / or self-assembly as described below in relation to subsequent processing operations. Such additional layers may also be used to protect the ILD lines from further processing. In addition, selectively depositing other materials over the metal lines may be beneficial for similar reasons. Referring again to Examples (e) and (f), it may also be possible to reset either the ILD lines or the metal lines having any combination of protective / HM materials on either one or both surfaces. Overall, there are numerous options at this stage for ultimately preparing the surfaces underneath for a selective or directed self-assembly process.

[0141] FIG. 10b illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10a after forming interlayer dielectric (ILD) lines (1010) on the structure of FIG. 10a according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (c), respectively taken along the aa' and cc' axes, the ILD lines (1010) are formed as a grating structure perpendicular to the direction of the lines (1004) below. In one embodiment, a blanket film of the material of the lines (1010) is deposited by chemical vapor deposition or similar techniques. In one embodiment, the blanket film is then patterned using lithography and etching processing that may involve, for example, spacer-based-quadruple-patterning (SBQP) or pitch quadruple division. It should be recognized that the grating pattern of the lines (1010) can be manufactured by numerous methods, including EUV and / or EBDW lithography, inductive self-assembly, etc. As will be described in more detail below, because the grating of the lines (1010) is orthogonal to the direction of the structure below, the subsequent metal layer will accordingly be patterned in a direction orthogonal to the previous metal layer. In one embodiment, a single 193 nm lithography mask is used for alignment / registration to the previous metal layer (1002) (e.g., the grating of the lines (1010) is aligned to the previous layer 'plug' pattern at X and to the previous metal grating at Y). Referring to cross-sectional structures (b) and (d), a hard mask (1012) may be formed on the dielectric lines (1010) or maintained after the patterning of the dielectric lines (1010). A hard mask (1012) can be used to protect the lines (1010) during subsequent patterning steps.As described in more detail below, the formation of lines (1010) into a grating pattern exposes regions of the previous metal lines (1002) and previous ILD lines (1004) (or corresponding hard mask layers on 1002 / 1004). The exposed regions correspond to all possible future via locations where the metal is exposed. In one embodiment, the previous layer metal layer (e.g., lines (1002)) is protected, labeled, brushed, etc. at this point in the process flow.

[0142] FIG. 10c illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10b after selective differentiation of all potential via locations from all plug locations according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken along the a-a', b-b', cc' and dd' axes, respectively, a surface modification layer (1014) is formed on the exposed regions of the underlying ILD lines (1004) after the formation of the ILD lines (1010). In one embodiment, the surface modification layer (1014) is a dielectric layer. In one embodiment, the surface modification layer (1014) is formed by a selective bottom-up growth approach. In one such embodiment, the bottom-up growth approach involves a directed self-assembly (DSA) brush coat having a polymer component that is preferentially assembled on the ILD lines (1004) below or, alternatively, on the metal lines (1002) (or on a sacrificial layer deposited or grown on the metal or ILD material below).

[0143] FIG. 10d illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10c after differential polymer addition to the exposed portions of the metal and ILD lines below FIG. 10c, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken, respectively along the a-a', b-b', cc' and dd' axes, directed self-assembly (DSA) or selective growth on the exposed portions of the metal / ILD (1002 / 1004) grating below is used to form intervening lines (1016) having alternating polymers or alternating polymer components between the ILD lines (1010). For example, as illustrated, a polymer (1016A) (or polymer component (1016A)) is formed on or over the exposed portions of the interlayer dielectric (ILD) lines (1004) of FIG. 10c, whereas a polymer (1016B) (or polymer component (1016B)) is formed on or over the exposed portions of the metal lines (1002) of FIG. 10c. Although the polymer (1016A) is formed on or over the surface modification layer (1014) described in relation to FIG. 10c (see cross-sectional views (b) and (d) of FIG. 10d), it should be recognized that in other embodiments, the surface modification layer (1014) may be omitted and alternating polymers or alternating polymer components may instead be formed directly on the structure described in relation to FIG. 10b.

[0144] Referring again to FIG. 10d, in one embodiment, once the surface of the underlying structure (e.g., the structure (1000) of FIG. 10a) (e.g., the structure of FIG. 10b or the structure of FIG. 10c) is prepared or used directly, a 50-50 diblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated and annealed on the substrate to promote self-assembly, resulting in the polymer (1016A) / polymer (1016B) layer (1016) of FIG. 10d. In such an embodiment, depending on appropriate surface energy conditions, the block copolymers are separated based on the exposed underlying material between the ILD lines (1010). For example, in a specific embodiment, the polystyrene is optionally aligned with the exposed portions of the underlying metal lines (1002) (or the corresponding metal line cap or hard mask material). Meanwhile, polymethyl methacrylate is selectively aligned with exposed portions of the ILD lines (1004) (or corresponding metal line caps or hard mask materials).

[0145] Accordingly, in one embodiment, the underlying metal and ILD grid, as exposed between the ILD lines (1010), are regenerated in the block copolymer (BCP, i.e., polymer (1016A) / polymer (1016B)). This may be particularly true if the BCP pitch is commensurate with the underlying grating pitch. In one embodiment, the polymer grid (polymer (1016A) / polymer (1016B)) is robust against specific small deviations from such a well-aligned grid. For example, if small plugs effectively place oxide or similar material where the well-aligned grid would have metal, a well-aligned polymer (1016A) / polymer (1016B) grid can still be achieved. However, since the ILD lines grating is an idealized grating structure that, in one embodiment, does not have metal blocks of the ILD backbone, it may be necessary to neutralize the ILD surface, because in such a case, both types of polymers (1016A and 1016B) will be exposed to the ILD-like material, whereas only one type is exposed to the metal.

[0146] In one embodiment, the thickness of the coated polymer (polymer (1016A) / polymer (1016B)) is approximately equal to or slightly thicker than the ultimate thickness of the ILD that is ultimately formed instead. In one embodiment, as described in more detail below, the polymer grid is not formed as an etching resist, but rather as a scaffolding to ultimately grow a permanent ILD layer around it. As such, the thickness of the polymer (1016) (polymer (1016A) / polymer (1016B)) may be important because this thickness can be used to define the ultimate thickness of the permanent ILD layer subsequently formed. That is, in one embodiment, the polymer grating shown in FIG. 10d is eventually replaced by an ILD grating of approximately the same thickness.

[0147] In one embodiment, as previously mentioned, the grid of polymer (1016A) / polymer (1016B) in FIG. 10d is a block copolymer. In such an embodiment, the block copolymer molecule is a polymer molecule formed from chains of covalently bonded monomers. In the block copolymer, there are at least two different types of monomers, and these different types of monomers are mainly contained within different blocks or consecutive sequences of monomers. The illustrated block copolymer molecule comprises a polymer block (1016A) and a polymer block (1016B). In one embodiment, the polymer block (1016A) mainly comprises a chain of covalently bonded monomer A (e.g., AAAAA...), while the polymer block (1016B) mainly comprises a chain of covalently bonded monomer B (e.g., BBBBB...). Monomers A and B may represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A may represent monomers for forming polystyrene and monomer B may represent monomers for forming poly(methyl methacrylate) (PMMA), but the scope of the disclosure is not so limited. In other embodiments, there may be more than two blocks. Furthermore, in other embodiments, each of the blocks may contain different types of monomers (e.g., each block may itself be a copolymer). In one embodiment, polymer block (1016A) and polymer block (1016B) are covalently bonded together. Polymer block (1016A) and polymer block (1016B) may be approximately the same length, or one block may be significantly longer than the other.

[0148] Typically, each of the blocks of the block copolymer (e.g., polymer block (1016A) and polymer block (1016B)) may have different chemical properties. As an example, one of the blocks may be relatively more hydrophobic (e.g., water-repellent) and the other block may be relatively more hydrophilic (water-absorbent). At least conceptually, one of the blocks may be relatively more similar to oil and the other block may be relatively more similar to water. Such differences in chemical properties between the different polymer blocks, whether hydrophilic-hydrophobic differences or others, may cause the block copolymer molecules to self-assemble. For example, self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water, which are generally immiscible. Similarly, differences in hydrophilicity between polymer blocks (e.g., one block is relatively hydrophobic and the other is relatively hydrophilic) can cause roughly similar microphase separation when different polymer blocks attempt to "separate" from each other due to chemical incompatibility with one another.

[0149] However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot be completely separated macroscopically. Rather, polymer blocks of a given type may tend to be separated or aggregated with polymer blocks of other molecules of the same type in extremely small (e.g., nano-sized) regions or phases. The specific size and shape of those regions or microphases generally depend at least partially on the relative lengths of the polymer blocks. In one embodiment, as an example (as shown in FIG. 10d), in two block copolymers, when the blocks are approximately the same length, a grid-like pattern of alternating polymer (1016A) lines and polymer (1016B) lines is created. In another embodiment (not shown), in two block copolymers, when one of the blocks is longer than the other but not too long, columnar structures may be formed. In columnar structures, block copolymer molecules can be aligned with their shorter polymer blocks that are microphase separated into the interior of the columns and with their longer polymer blocks that extend away from the columns and surround the columns. For example, if polymer block (1016A) is longer than polymer block (1016B) but not too long, columnar structures can be formed in which many block copolymer molecules are aligned with their shorter polymer blocks (1016B), thereby forming columnar structures surrounded by phases having longer polymer blocks (1016A). When this occurs in an area of ​​sufficient size, a two-dimensional array of columnar structures, generally packed in a hexagon, can be formed.

[0150] In one embodiment, the polymer (1016A) / polymer (1016B) grating is first applied as an unassembled block copolymer layer portion comprising a block copolymer material applied, for example, by a brush or other coating process. The unassembled mode refers to scenarios in which, at deposition, the block copolymer is not yet substantially phase-separated and / or self-assembled to form nanostructures. In this unassembled mode, the block copolymer molecules are relatively highly randomized, and the different polymer blocks are relatively highly randomly oriented and positioned, in contrast to the assembled block copolymer layer portion discussed in relation to the resulting structure of FIG. 10d. The unassembled block copolymer layer portion can be applied in various different ways. For example, the block copolymer can be dissolved in a solvent and then spin-coated onto the surface. Alternatively, the unassembled block copolymer can be spray-coated, dip-coated, immersed, or coated or applied onto the surface in other ways. Other methods for applying block copolymers, as well as other methods known in the art for applying similar organic coatings, may potentially be used. Subsequently, the unassembled layer may form an assembled block copolymer layer portion, for example, by microphase separation and / or self-assembly of the unassembled block copolymer layer portion. Microphase separation and / or self-assembly occurs through the rearrangement and / or rearrangement of block copolymer molecules, and in particular through the rearrangement and / or rearrangement of different polymer blocks of block copolymer molecules.

[0151] In one such embodiment, an annealing treatment may be applied to an unassembled block copolymer to initiate, accelerate, improve the quality of, or otherwise promote microphase separation and / or self-assembly. In some embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. Examples of such treatments include baking the layer, heating the layer in an oven or under a heat lamp, applying infrared radiation to the layer, or otherwise applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and / or self-assembly of the block polymer without damaging any other important materials or structures of the block copolymer or integrated circuit board. Typically, the heating may be in the range of about 50°C to about 300°C, or about 75°C to about 250°C, but does not exceed the thermal degradation limits of the block copolymer or integrated circuit board. Heating or annealing can help provide energy to block copolymer molecules to make them more mobile / flexible, in order to increase the rate of microphase separation and / or improve the quality of microphase separation. Such microphase separation or rearrangement / relocation of block copolymer molecules can lead to self-assembly to form extremely small (e.g., nano-scale) structures. Self-assembly can occur under the influence of surface energy, molecular affinities, and other surface-related and chemical-related forces.

[0152] In any case, in some embodiments, the self-assembly of block copolymers can be used to form extremely small periodic structures (e.g., nano-scale structures or lines at precise intervals), whether based on hydrophobic-hydrophilic differences or in other ways. In some embodiments, they can be used to form nano-scale lines or other nano-scale structures that can ultimately be used to form vias and openings. In some embodiments, the induced self-assembly of block copolymers can be used to form vias that self-align with interconnects, as described in more detail below.

[0153] Referring again to FIG. 10d, in one embodiment, for the DSA process, in addition to the orientation from the ILD / metal (1004 / 1002) surfaces below, the growth process may be influenced by the sidewalls of the material of the ILD lines (1010). As such, in one embodiment, the DSA is controlled through graphoepitaxy (from the sidewalls of the lines (1010)) and chemoepitaxy (from the exposed surface properties below). Physically and chemically constraining the DSA process can greatly aid the process in terms of defectivity. The resulting polymers (1016A / 1016B) have fewer degrees of freedom and are completely constrained in all directions by chemical (e.g., the ILD or metal lines below, or, for example, surface modifications made to them by a brush approach) and physical (e.g., from trenches formed between the ILD lines (1010)).

[0154] In an alternative embodiment, a selective growth process is used instead of the DSA approach. FIG. 10e illustrates a cross-sectional view of the structure of FIG. 10b after the selective exposure of portions of the metal and ILD lines below, according to another embodiment of the present disclosure. Referring to FIG. 10e, a first material type (1090) is grown over the exposed portions of the ILD lines (1004) below. A second different material type (1092) is grown over the exposed portions of the metal lines (1002) below. In one embodiment, selective growth is achieved by a dep-etch-dep-etch approach for each of the first and second materials, as depicted in FIG. 10e, resulting in multiple layers of each of the materials. Such an approach may be advantageous over conventional selective growth techniques that can form "mushroom-top" shaped films. The tendency for mushroom topping film growth can be reduced through an alternating dep-etch-dep-etch approach. In another embodiment, a film is selectively deposited on top of a metal and then a different film is selectively deposited on top of the ILD (or vice versa), and this is repeated several times to create a sandwich-like stack. In another embodiment, both materials, which are selectively grown on respective exposed areas of the substrate underneath, are grown simultaneously in a reaction chamber (e.g., by a CVD-style process).

[0155] FIG. 10f illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10d after the removal of one type of polymer, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken, respectively along the a-a', b-b', cc' and dd' axes, the polymer or polymer portion (1016A) is removed to re-expose the ILD lines (1004) (or hard mask or cap layers formed on the ILD lines (1004)), while the polymer or polymer portion (1016B) is retained on the metal line (1002). In one embodiment, a deep ultra-violet (DUV) flood exposure and subsequent wet etching or selective dry etching are used to selectively remove the polymer (1016A). It should be recognized that instead of removing the polymer from the ILD lines (1004) first (as described), removal from the metal lines (1002) may be performed first instead. Alternatively, a dielectric film is selectively grown over the region, and mixed scaffolding is not used.

[0156] FIG. 10g illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10f after the formation of an ILD material in locations open upon the removal of a type of polymer, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken along the a-a', b-b', cc', and dd' axes, respectively, the exposed regions of the underlying ILD lines (1004) are filled with a permanent interlayer dielectric (ILD) layer (1018). As such, as depicted in the plan view and cross-sectional views (b) and (d) of FIG. 10g, the open spaces between all possible via locations filled with the ILD layer (1018) include a hard mask layer (1020) disposed thereon. It should be recognized that the material of the ILD layer (1018) does not need to be the same material as the ILD lines (1010). In one embodiment, the ILD layer (1018) is formed by a deposition and polishing process. When the ILD layer (1018) is formed by an accompanying hard mask layer (1020), a special ILD filling material (e.g., polymer-encapsulated nanoparticles of ILD that fill holes / trenches) may be used. In this case, polishing may not be required.

[0157] Referring again to FIG. 10g, in one embodiment, the resulting structure comprises a uniform ILD structure (ILD lines (1010) + ILD layer (1018)), all possible plug locations are covered by a hard mask (1020), and all possible vias are in regions of the polymer (1016B). In such an embodiment, the ILD lines (1010) and the ILD layer (1018) are composed of the same material. In another such embodiment, the ILD lines (1010) and the ILD layer (1018) are composed of different ILD materials. In either case, in a particular embodiment, a distinction such as a seam between the materials of the ILD lines (1010) and the ILD layer (1018) may be observed in the final structure. An exemplary seam (1099) is shown in FIG. 10g for illustrative purposes.

[0158] FIG. 10h illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10g after via patterning, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken, respectively along the a-a', b-b', cc', and dd' axes, via locations (1022A, 1022B, and 1022C) are opened by removing the polymer (1016B) at selected locations. In one embodiment, the formation of selective via locations is achieved by using a lithography technique. In such an embodiment, the polymer (1016B) is globally removed using ashing and refilled with photoresist. The photoresist is highly sensitive and may have large acid diffusion and aggressive deprotection or crosslinking (depending on the resist tone) because the latent image is confined in both directions by the ILD (e.g., by ILD lines (1010) and ILD layer (1018)). The resist acts as a digital switch to turn "on" or "off" depending on whether vias are required at specific locations. Ideally, the photoresist can be used to fill only the holes without overflowing. In one embodiment, via locations (1022A, 1022B, and 1022C) are completely confined using this process so that line edge or width roughness (LWR) and line collapse and / or reflection are mitigated, if not eliminated. In one embodiment, low doses are used in EUV / EBDW, significantly increasing the run rate. In one embodiment, an additional advantage of using EBDW is that the run rate can be increased with only a single shot type / size by significantly reducing the number of required apertures as well as lowering the dose that needs to be delivered.When 193 nm immersion lithography is used, in one embodiment, the process flow limits via locations in both directions so that the size of the via actually patterned (e.g., assuming 1:1 line / space patterns) is twice the size of the actual via on the wafer. Alternatively, via locations can be selected in a reverse tone where vias to be retained are protected by photoresist, remaining sites are removed, and later filled with ILD. Such an approach can enable a single metal filling / polishing process at the end of the patterning flow rather than two separate metal deposition steps.

[0159] FIG. 10i illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10h after via formation, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken respectively along the a-a', b-b', cc' and dd' axes, via locations (1022A, 1022B and 1022C) are filled with metal to form vias (1024A, 1024B and 1024C), respectively. In one embodiment, the via locations (1022A, 1022B and 1022C) are filled with excess metal and subsequent polishing is performed. However, in another embodiment, the via locations (1022A, 1022B and 1022C) are filled without metal overfilling and polishing is omitted. It should be recognized that the via fill exemplified in FIG. 10i can be skipped in the inversion tone via selection approach.

[0160] FIG. 10j illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10i after the removal of the second type of polymer and replacement with an ILD material, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken along the a-a', b-b', cc', and dd' axes, respectively, the remaining polymer or polymer portion (1016B) (e.g., where via locations were not selected) is removed to re-expose the metal lines (1002). Subsequently, as depicted in FIG. 10j, an ILD layer (1026) is formed at the locations where the remaining polymer or polymer portion (1016B) was removed.

[0161] Referring again to FIG. 10j, in one embodiment, the resulting structure comprises a uniform ILD structure (ILD lines (1010) + ILD layer (1018) + ILD layer (1026)), and the locations of all possible plugs are covered by a hard mask (1020). In such an embodiment, the ILD lines (1010), ILD layer (1018), and ILD layer (1026) are made of the same material. In another such embodiment, two of the ILD lines (1010), ILD layer (1018), and ILD layer (1026) are made of the same material, and a third is made of a different ILD material. In yet another such embodiment, all of the ILD lines (1010), ILD layer (1018), and ILD layer (1026) are made of different ILD materials relative to one another. In any case, in a particular embodiment, a distinction point such as a seam between the materials of the ILD lines (1010) and the ILD layer (1026) may be observed in the final structure. Exemplary seams (1097) are illustrated in FIG. 10j for illustrative purposes. Likewise, a distinction point such as a seam between the materials of the ILD layer (1018) and the ILD layer (1026) may be observed in the final structure. Exemplary seams (1098) are illustrated in FIG. 10j for illustrative purposes.

[0162] FIG. 10k illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10j after patterning of a resist or mask at selected plug locations according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b) taken respectively along the aa' and bb' axes, the plug locations (1028A, 1028B, and 1028C) are preserved by forming a mask or resist layer over those locations. Such preservation patterning may be referred to as metal end-to-end lithographic patterning, wherein the plug locations where discontinuities in subsequently formed metal lines are required are determined. It should be recognized that the plugs may occur over the previous layer ILD lines (1004) because the plug locations may only be at those locations where the ILD layer (1018) / hard mask (1020) is placed. In one embodiment, patterning is achieved by using a lithographic operation (e.g., EUV, EBDW, or immersion 193 nm). In one embodiment, the process illustrated in FIG. 10k shows the use of a positive tone patterning process in which regions where spaces between metals need to occur are preserved. In another embodiment, it should be recognized that it is also possible to instead open holes and invert the tone of the process.

[0163] FIG. 10l illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10k after hard mask removal and ILD layer resetting according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b) taken respectively along the aa' and bb' axes, the hard mask (1020) is removed and the ILD layer (1018) and ILD layer (1026) are reset by etching these layers below their original top surfaces, respectively, to form the reset ILD layer (1018') and the reset ILD layer (1026'). It should be recognized that the resetting of the ILD layer (1018) and ILD layer (1026) is performed without etching or resetting the ILD lines (1010). Selectivity can be achieved by using a hard mask layer (1012) on the ILD lines (as depicted in cross-sectional views (a) and (b)). Alternatively, if the ILD lines (1010) are composed of an ILD material different from the material of the ILD layer (1018) and the ILD layer (1026), selective etching may be used even in the absence of the hard mask (1012). Recessing of the ILD layer (1018) and the ILD layer (1026) is intended to provide locations for a second level of metal lines, such as those isolated by the ILD lines (1010), as described below. In one embodiment, the degree or depth of the recess is selected based on the desired ultimate thickness of the metal lines formed thereon. It must be recognized that the ILD layer (1018) in the plug locations (1028A, 1028B and 1028C) is not reset.

[0164] FIG. 10m illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 10l after metal line formation according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a), (b) and (c) taken respectively along the a-a', bb' and cc' axes, metal for forming metal interconnect lines is conformally formed on the structure of FIG. 10l. The metal is then flattened, for example by CMP, to provide metal lines (1030) defined at locations on the reset ILD layer (1018') and the reset ILD layer (1026'). Metal lines (1030) are coupled to the metal lines (1002) below through predetermined via locations (1024A, 1024B, and 1024C) (1024B is shown in cross-sectional view (c); note that for illustrative purposes, another via (1032) is depicted immediately adjacent to the plug (1028B) in cross-sectional view (b), but this does not correspond to the previous drawings). The metal lines (1030) are isolated from each other by the ILD lines (1010) and are blocked or broken up by the preserved plugs (1028A, 1028B, and 1028C). Any hard mask remaining on the plug locations and / or on the ILD lines (1010) can be removed at this part of the process flow, as depicted in FIG. 10m. The metal (e.g., copper and associated barrier and seed layers) deposition and flattening process for forming the metal lines (1030) may be typically used for standard BEOL (back end of line) single or dual damascene processing. In one embodiment, in subsequent manufacturing operations, the ILD lines (1010) may be removed to provide air gaps between the resulting metal lines (1030).

[0165] The structure of FIG. 10m can subsequently be used as a basis for forming subsequent metal lines / vias and ILD layers. Alternatively, the structure of FIG. 10m can represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations can be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. Furthermore, although the process flow focuses on applications of directed self-assembly (DSA), selective growth processes may instead be used at one or more locations in the process flow. In any case, the resulting structures enable the fabrication of vias centered directly on the underlying metal lines. That is, the vias may be wider, narrower, or have the same thickness as the underlying metal lines, for example, due to imperfect selective etching processing. Nevertheless, in one embodiment, the centers of the vias are directly aligned (matched up) with the centers of the metal lines. As such, in one embodiment, the offset resulting from conventional lithography / dual damascene patterning, which must be allowed in a different way, is not a factor for the resulting structures described herein.

[0166] One or more embodiments described herein relate to prior layer self-aligned via and plug patterning. The self-alignment mode of the processes described herein may be based on a directed self-assembly (DSA) mechanism, as described in more detail below. However, it should be recognized that selective growth mechanisms may be used instead of or in combination with DSA-based approaches. In one embodiment, the processes described herein enable the realization of self-aligned metallization for back-end of line (BEOL) feature fabrication.

[0167] FIGS. 11a through 11m illustrate portions of integrated circuit layers representing various operations in a method of self-aligned vias and metal patterning according to one embodiment of the present disclosure. In each example of each described operation, plan views are shown on the left and corresponding cross-sectional views are shown on the right. These drawings will be referred to herein as corresponding cross-sectional views and plan views.

[0168] FIG. 11a illustrates plan views and corresponding cross-sectional views of options for a prior layered metallized structure according to one embodiment of the present disclosure. Referring to plan view and corresponding cross-sectional view option (a), the starter structure (1100) includes a pattern of metal lines (1102) and interlayer dielectric (ILD) lines (1104). The starter structure (1100) can be patterned into a grating-like pattern having metal lines spaced at a constant pitch and having a constant width, as depicted in FIG. 11a, when self-assembly materials are used. When an inductive selective growth technique is used, the pattern underneath does not need to be a single pitch or width. The pattern can be manufactured, for example, by a pitch split or pitch quadrupling approach. Some of the lines may be associated with vias underneath, such as line (1102') shown as an example in the cross-sectional views.

[0169] Referring again to FIG. 11a, alternative options (b) through (f) address situations in which an additional film is formed on the surface of one or both of the metal lines (1102) and the interlayer dielectric lines (1104) (e.g., deposited, grown, or left as an artifact remaining from a previous patterning process). In example (b), an additional film (1106) is placed on the interlayer dielectric lines (1104). In example (c), an additional film (1108) is placed on the metal lines (1102). In example (d), an additional film (1106) is placed on the interlayer dielectric lines (1104), and an additional film (1108) is placed on the metal lines (1102). Furthermore, although the metal lines (1102) and interlayer dielectric lines (1104) are depicted as coplanar in (a), in other embodiments they are not coplanar. For example, in (e), the metal lines (1102) protrude over the interlayer dielectric lines (1104). In example (f), the metal lines (1102) are recessed under the interlayer dielectric lines (1104).

[0170] Referring again to Examples (b) through (d), an additional layer (e.g., layer (1106 or 1108)) may be used as a hard mask (HM) or a protective layer, or may be used to enable selective growth and / or self-assembly as described below in relation to subsequent processing operations. Such additional layers may also be used to protect the ILD lines from further processing. In addition, selectively depositing other materials over the metal lines may be beneficial for similar reasons. Referring again to Examples (e) and (f), it may also be possible to reset either the ILD lines or the metal lines having any combination of protective / HM materials on either one or both surfaces. Overall, there are numerous options at this stage for ultimately preparing the surfaces underneath for a selective or directed self-assembly process.

[0171] FIG. 11b illustrates a plan view and corresponding cross-sectional views of options for directed self-assembly (DSA) growth on the metal / ILD grating below (e.g., on a structure such as that illustrated in FIG. 11a) according to one embodiment of the present disclosure. Referring to the plan view, the structure (1110) comprises layers having alternating polymers or alternating polymer components. For example, as illustrated, polymer A (or polymer component A) is formed on or above the interlayer dielectric (ILD) lines (1104) of FIG. 11a, while polymer B (or polymer component B) is formed on or above the metal lines (1102) of FIG. 11a. Referring to the cross-sectional views, in (a), polymer A (or polymer component A) is formed on the ILD lines (1104), and polymer B (or polymer component B) is formed on the metal lines (1102). In (b), polymer A (or polymer component A) is formed on an additional film (1106) formed on the ILD lines (1104), while polymer B (or polymer component B) is formed on the metal lines (1102). In (c), polymer A (or polymer component A) is formed on the ILD lines (1104), while polymer B (or polymer component B) is formed on an additional film (1108) formed on the metal lines (1102). In (d), polymer A (or polymer component A) is formed on an additional film (1106) formed on the ILD lines (1104), and polymer B (or polymer component B) is formed on an additional film (1108) formed on the metal lines (1102).

[0172] Referring again to FIG. 11b, in one embodiment, once the surface of the underlying structure (e.g., the structure (1100) of FIG. 11a) is prepared, a 50-50 diblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated and annealed on the substrate to promote self-assembly, reaching the polymer A / polymer B layer of the structure (1110) of FIG. 11b. In such an embodiment, depending on appropriate surface energy conditions, the block copolymers are separated based on the material underlying the structure (1100). For example, in a specific embodiment, the polystyrene is optionally aligned with the underlying metal lines (1102) (or the corresponding metal line cap or hard mask material). Meanwhile, the polymethyl methacrylate is optionally aligned with the ILD lines (1104) (or the corresponding metal line cap or hard mask material).

[0173] Accordingly, in one embodiment, the underlying metal and ILD grid are regenerated in a block copolymer (BCP, i.e., polymer A / polymer B). This may be particularly true when the BCP pitch corresponds to the underlying grating pitch. In one embodiment, the polymer grid (polymer A / polymer B) is robust against specific small deviations from a highly aligned grid. For example, a highly aligned polymer A / polymer B grid can still be achieved if small plugs effectively place oxides or similar materials where the highly aligned grid would have metal. However, since the ILD lines grating is an idealized grating structure that, in one embodiment, does not have metal blocks of the ILD backbone, it may be necessary to neutralize the ILD surface, because in such a case, both types of polymers (A and B) would be exposed to the ILD-like material, whereas only one type would be exposed to the metal.

[0174] In one embodiment, the thickness of the coated polymer (polymer A / polymer B) is approximately equal to or slightly thicker than the ultimate thickness of the ILD that is ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grid is not formed as an etching resist, but rather as a scaffolding for ultimately growing a permanent ILD layer around it. As such, the thickness of the polymer (A / B) may be important because this thickness can be used to define the ultimate thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 11b is eventually replaced by an ILD grating of approximately the same thickness.

[0175] In one embodiment, as previously mentioned, the grid of polymer A / polymer B in FIG. 11b is a block copolymer. In such an embodiment, the block copolymer molecules are the same as those previously described in relation to FIG. 10d. In one embodiment, as a first example (as shown in FIG. 11b), in two block copolymers, when the blocks are approximately the same length, a grid-like pattern of alternating polymer A lines and polymer B lines is created. In another embodiment, as a second example (not shown), in two block copolymers, when one of the blocks is longer than the other but not too long, vertical columnar structures may be formed. In the columnar structures, the block copolymer molecules may be aligned with their shorter polymer blocks that are microscopically separated into the interior of the columns and their longer polymer blocks that extend away from the columns and surround the columns. For example, if polymer block A is longer than polymer block B but not too long, columnar structures can be formed in which many block copolymer molecules align with their shorter polymer blocks B, thereby forming columnar structures surrounded by phases having longer polymer blocks A. When this occurs over an area of ​​sufficient size, a two-dimensional array of columnar structures, generally packed into hexagons, can be formed.

[0176] In one embodiment, the polymer A / polymer B grating is first applied as a portion of an unassembled block copolymer layer comprising a block copolymer material applied, for example by a brush or other coating process, as previously described in connection with FIG. 10d. In this embodiment, as previously described in connection with FIG. 10d, an annealing treatment is applied to the unassembled block copolymer to initiate, accelerate, improve the quality of, or otherwise promote microphase separation and / or self-assembly.

[0177] FIG. 11c illustrates a plan view and a corresponding cross-sectional view of the structure of FIG. 11b after the removal of one type of polymer, according to one embodiment of the present disclosure. Referring to FIG. 11c, polymer B is removed to re-expose the metal lines (1102) (or hard mask or cap layers formed on the metal lines (1102)), while polymer A is retained on the ILD lines (1104) to form the structure (1112). In one embodiment, deep ultra-violet (DUV) flood exposure and subsequent wet etching or selective dry etching are used to selectively remove polymer B. It should be recognized that instead of removing the polymer from the metal lines (1102) first (as depicted), removal from the ILD lines may be performed first instead.

[0178] FIG. 11d illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11c after the formation of a sacrificial material layer over the metal lines (1102) according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional view (b), the structure (1114) comprises a sacrificial B layer formed over or on the metal lines (1102) and between the polymer A lines on or on the ILD lines (1104). In one embodiment, referring to cross-sectional view (a), low-temperature deposition forms trenches between the polymer A lines, for example, an oxide (e.g., TiO₂) which is a conformal layer (1116). x) or other sacrificial material is filled. The conformal layer (1116) is then defined into regions on the metal lines (1102) by a dry etching or chemical mechanical planarization (CMP) process. In some embodiments, because the material is ultimately replaced by a permanent ILD material, the resulting layer is referred to herein as sacrificial B. However, it should be recognized that in other embodiments, a permanent ILD material may be formed at this stage instead. Where a sacrificial material is used, in one embodiment, the sacrificial material has the necessary deposition properties, thermal stability, and etching selectivity over other materials used in the process.

[0179] FIG. 11e illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11d after replacing polymer A with a permanent interlayer dielectric (ILD) material, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional view (c), the structure (1118) includes permanent interlayer dielectric (ILD) lines (1120) on or above the ILD lines (1104) and between the sacrificial B material lines. In one embodiment, the polymer A lines are removed as depicted in cross-sectional view (a). Then, referring to cross-sectional view (b), an ILD material layer (1119) is conformally formed on the resulting structure. The conformal layer (1119) is then defined in regions above the ILD lines (1104) by a dry etching or chemical mechanical planarization (CMP) process. In one embodiment, the structure (1118) effectively replaces the polymer (A / B) grating of FIG. 11b with a very thick material grating (e.g., permanent ILD (1120) and sacrificial B) that corresponds to and is aligned with the metal grating below. As described in more detail below, two different materials may be used to ultimately define possible locations for plugs and vias.

[0180] FIG. 11f illustrates a plan view and corresponding cross-sectional views of a structure of FIG. 11e after selective hard mask formation on permanent ILD lines according to one embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional view (c), the structure (1122) comprises a hard mask layer (1124) formed on permanent interlayer dielectric (ILD) lines (1120). In one embodiment, referring to cross-sectional view (c), a selective growth process is used to form the hard mask layer (1124) as defined on the surfaces of the permanent ILD lines (1120). In another embodiment, a conformal material layer (1123) is first formed on the structure having reset permanent ILD lines (1120) (cross-sectional view (a)). The conformal layer (1123) is then subjected to a timed etch and / or CMP process to form a hard mask layer (1124) (cross-sectional view (b)). In the latter case, the ILD lines (1120) are reset relative to the sacrificial B material, and then a non-conformal (flattened) hard mask (1123) is deposited on the resulting grating. The material (1123) is thinner on the sacrificial B lines than on the reset ILD lines (1120) so that the timed etching or polishing operation of the hard mask selectively removes the material (1123) from the sacrificial B material.

[0181] FIG. 11g illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11f after the removal of sacrificial B lines and their replacement with permanent ILD lines (1128) according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional view (c), the structure (1126) includes permanent ILD lines (1128) in place of the sacrificial B lines of FIG. 11f, that is, on the metal lines (1102) and aligned therewith. In one embodiment, for example, by the deposition of a conformal layer and subsequent timed etching or CMP processing (cross-sectional view (b)), the sacrificial B material is removed (cross-sectional view (a)) and replaced with permanent ILD lines (1128) (cross-sectional view (c)). In one embodiment, the resulting structure (1126) comprises a uniform ILD material (permanent ILD lines (1120) + permanent ILD lines (1128)), wherein the locations of all possible plugs are covered by a hard mask (1124) and all possible vias are in the areas of the exposed permanent ILD lines (1128). In such an embodiment, the permanent ILD lines (1120) and the permanent ILD lines (1128) are composed of the same material. In another such embodiment, the permanent ILD lines (1120) and the permanent ILD lines (1128) are composed of different ILD materials. In either case, in a particular embodiment, a distinction such as a seam between the materials of the permanent ILD lines (1120) and the permanent ILD lines (1128) may be observed in the final structure (1126). An exemplary seam (1199) is shown in FIG. 11g for illustrative purposes.

[0182] FIG. 11h illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11g after trench formation (e.g., grating definition) according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken respectively along the a-a', b-b', cc', and dd' axes, the grating in the structure (1130) for ultimately defining the regions between the patterns of metal lines is defined by forming trenches (1132) in the structure of FIG. 11g that are perpendicular to the grating of FIG. 11g. In one embodiment, the trenches (1132) are formed by patterning the grating pattern and etching it into the sacrificial grating of the previous structures. In one embodiment, a grid is effectively formed that defines the location of all the spaces between the ultimately formed metal lines, along with all the plugs and vias. In one embodiment, the trenches (1132) expose portions of the ILD lines (1104) and metal lines (1102) below.

[0183] FIG. 11i illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11h after forming a sacrificial material grating in the trenches of FIG. 11h according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) through (d) taken respectively along the a-a', b-b', cc', and dd' axes, a material layer (1134), which is an interlayer dielectric layer or a sacrificial layer, is formed in the trenches (1132) of the structure of FIG. 11h. In one embodiment, the material layer (1134) is formed as a permanent ILD material or a sacrificial layer (e.g., which can be later removed if an air gap is to be manufactured) by conformal deposition and subsequent timed etching or CMP. In the former case, the material layer (1134) ultimately becomes an ILD material between subsequently formed parallel metal lines on the same metal layer. In the latter case, the material may be referred to as a sacrificial C material, as described. In one embodiment, the material layer (1134) has high etching selectivity for other ILD materials and for the hard mask layer (1128).

[0184] FIG. 11j illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11i following the formation and patterning of a mask and subsequent etching of via locations, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the aa' and bb' axes, a mask (1136) is formed on the structure of FIG. 11i. The mask is patterned, for example, by a lithography process, so that openings (1137) are formed therein. In one embodiment, the openings are determined based on the desired via patterning. That is, at this stage, all possible vias and plugs (e.g., as placeholders) are patterned and self-aligned with the ultimate metal layers above and below. Here, a subset of via and plug locations for preservation is selected, such as locations for etching metal line locations. In one embodiment, an ArF or EUV or e-beam resist is used to cut or select vias to be etched at locations of the exposed portions of the metal lines (1102). It should be recognized that the hard mask (1124) and the material layer (1134) function as actual etching masks that determine the shape and location of the vias. The mask (1136) serves only to block the remaining vias from being etched. As such, the tolerance for the size of the openings (1137) is mitigated because the surrounding materials of the selected via locations (e.g., the hard mask (1124) and the material layer (1134)) (i.e., the portions of the openings (1137) immediately above the exposed portions of the metal lines (1102)) withstand the etching process used to remove the ILD line (1128) above the selected portions of the metal lines (1102) for the ultimate via fabrication. In one embodiment, the mask (1136) is composed of a topographic masking portion (1136C), an anti-reflective coating (ARC) layer (1136B), and a photoresist layer (1136A).In a particular embodiment, the topography masking portion (1136C) is a carbon hard mask (CHM) layer and the anti-reflective coating layer (1136B) is a silicon ARC layer.

[0185] FIG. 11k illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11j after mask and hard mask removal and subsequent plug patterning and etching, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b) taken respectively along the aa' and bb' axes, the mask (1136) shown in FIG. 11j is removed after via location patterning. Subsequently, a second mask (1138) is formed and patterned to cover selected plug locations. Specifically, in one embodiment, and as depicted in FIG. 11k, portions of the hard mask (1124) are preserved at the locations where plugs are ultimately formed. That is, at this stage, all possible plugs in the form of hard mask plugs exist. The patterning operation of FIG. 11k serves to remove all portions of the hard mask (1124) except those selected for plug preservation. Patterning effectively exposes a significant portion of the ILD lines (1120 and 1128), for example, as an integrated dielectric layer.

[0186] FIG. 11L illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11K after mask removal and metal line trench etching according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the aa' and bb' axes, the mask (1138) shown in FIG. 11K is removed after via location patterning. Subsequently, partial etching of the exposed portions of the ILD lines (1120 and 1128) is performed to provide recessed ILD lines (1120' and 1128'). The degree of recessing may be based on a time-set etching process aimed at a depth of the desired metal line thickness. As depicted in FIG. 11L, portions of the ILD lines (1120) protected by the preserved hard mask (1124) portions are not recessed by etching. Additionally, the material layer (1134), which may be a sacrificial material or a permanent ILD material, is also not etched or reset. It should be recognized that lithography is not required for the process illustrated by FIG. 11l because the via locations (in the exposed portions of the metal lines (1102)) have already been etched and the plugs (in the locations where the hard mask (1124) is preserved) are present.

[0187] FIG. 11m illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 11l after metal line deposition and polishing according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the aa' and bb' axes, metal for forming metal interconnect lines is conformally formed on the structure of FIG. 11l. The metal is then flattened, for example, by CMP, to provide metal lines (1140). The metal lines are coupled to the metal lines below through predetermined via locations and isolated by retained plugs (1142 and 1144). The metal (e.g., copper and associated barrier and seed layers) deposition and flattening process may be a standard BEOL dual damascene processing process. It should be recognized that in subsequent manufacturing operations, the material layer lines (1134) can be removed to provide air gaps between the resulting metal lines (1140).

[0188] The structure of FIG. 11m can subsequently be used as a basis for forming subsequent metal lines / vias and ILD layers. Alternatively, the structure of FIG. 11m can represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations can be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. Furthermore, although the process flow focuses on applications of directed self-assembly (DSA), selective growth processes may instead be used at one or more locations in the process flow. In any case, the resulting structures enable the fabrication of vias centered directly on the underlying metal lines. That is, the vias may be wider, narrower, or have the same thickness as the underlying metal lines, for example, due to imperfect selective etching processing. Nevertheless, in one embodiment, the centers of the vias are directly aligned (matched up) with the centers of the metal lines. As such, in one embodiment, the offset resulting from conventional lithography / dual damascene patterning, which must be allowed in a different way, is not a factor for the resulting structures described herein.

[0189] According to one embodiment of the present disclosure, self-aligned DSA triblock bottom-up approaches are described. One or more embodiments described herein relate to triblock copolymers for self-aligned vias or contacts. Through the use of more advanced block copolymers and guided self-assembly strategies, alignment to an underlying dense metal layer can be achieved. The embodiments described herein can be implemented to improve cost, scalability, pattern placement error, and variability.

[0190] Generally, one or more embodiments described herein involve using three phases of a triblock copolymer material to perform phase separation into "self-aligned photobuckets," for example, using a self-aligned triblock copolymer to produce aligned photobuckets is described. Additional embodiments regarding the manufacture and use of photobuckets are described in more detail below in embodiments other than those of FIGS. 12a through 12k. However, it should also be recognized that the embodiments are not limited to the concept of photobuckets and have a wide range of applications, including structures having pre-formed features manufactured using a bottom-up and / or directed self-assembly (DSA) approach.

[0191] FIGS. 12a through 12c illustrate inclined cross-sectional views illustrating various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure.

[0192] Referring to FIG. 12a, the semiconductor structure layer (1200) has a grating pattern of alternating metal lines (1202) and interlayer dielectric (ILD) lines (1204). The structure (1200) can be processed by a first molecular brush operation (i) using a first molecular species (1206). The structure (1200) can also be processed by a second molecular brush operation (ii) using a second molecular species (1208). It should be recognized that the order of operations (i) and (ii) can be reversed, or even performed substantially simultaneously.

[0193] Referring to FIG. 12b, molecular brush operations may be performed to alter or provide derivative surfaces for alternating metal lines (1202) and ILD lines (1204). For example, the surface of the metal lines (1202) may be treated to have an A / B surface (1210) on the metal lines (1202). The surface of the ILD lines (1204) may be treated to have a C surface (1212) on the ILD lines (1204).

[0194] Referring to FIG. 12c, the structure of FIG. 12b may be processed by a process operation (iii) involving the application of a triblock block copolymer (triblock BCP) (1214) and possible subsequent separation treatment to form a separation structure (1220). The separation structure (1220) includes first regions (1222) of the separation triblock BCP over the ILD lines (1204). Alternating second regions (1224) and third regions (1226) of the separation triblock BCP are over the metal lines (1202). The ultimate arrangement of the three blocks of the triblock copolymer (1214) is based on chemoepitaxy, because only the pattern below (not the coplanar pattern as used in graphoepitaxy) is used to induce the assembly of the triblock copolymer (1214) to form a separation structure (1220).

[0195] Referring collectively to FIGS. 12a through 12c, in one embodiment, a structure (1220) for the inductive self-assembly of a back-end-of-line (BEOL) semiconductor structure metallization layer comprises a substrate (not shown, but described below and recognized as being below the ILD lines (1204) and metal lines (1202)). The lower metallization layer comprises alternating metal lines (1202) and dielectric lines (1204) disposed on the substrate. A triblock copolymer layer (1214) is disposed on the lower metallization layer. The triblock copolymer layer comprises a first segregated block component (1222) disposed above the dielectric lines (1204) of the lower metallization layer. The triblock copolymer layer includes alternating second (1224) and third (1226) separating block components positioned above the metal lines (1202) of the lower metallization layer.

[0196] In one embodiment, the third separation block (1226) component of the triblock copolymer layer (1214) is photosensitive. In one embodiment, the triblock copolymer layer (1214) is formed with a thickness in the range of approximately 5 to 100 nanometers. In one embodiment, the triblock copolymer layer (1214) comprises a triblock copolymer species selected from any three of the group consisting of polystyrene and other polyvinylarenes, polyisoprene and other polyolefins, polymethacrylate and other polyesters, polydimethylsiloxane (PDMS) and related Si-based polymers, polyferrocenylsilanes, polyethylene oxide (PEO) and related polyethers, and polyvinylpyridine. In one embodiment, the alternating second (1224) and third (1226) separation block components have a ratio of approximately 1:1 as depicted in FIG. 21c (and as described below in connection with FIG. 12h). In another embodiment, the alternating second (1224) and third (1226) separation block components have a ratio of second separation block component (1224) to third separation block component (1226) of X:1, where X is greater than 1, and the third separation block component (1226) has a columnar structure surrounded by the second separation block component, as described below in connection with FIG. 12i. In another embodiment, the triblock copolymer layer (1214) is a blend of homopolymers of A, B, and / or C or biblock BCPs of AB, BC, or AC components to achieve the desired morphology.

[0197] In one embodiment, the structure (1220) further comprises a first molecular brush layer (1212) disposed on dielectric lines (1204) of a lower metallization layer. In that embodiment, a first separation block component (1222) is disposed on the first molecular brush layer. In one embodiment, the structure (1220) also comprises a second different molecular brush layer (1210) disposed on metal lines (102) of a lower metallization layer. Alternating second (1224) and third (1226) separation block components are disposed on the second molecular brush layer (1210). In one embodiment, the first molecular brush layer (1212) comprises a molecular species (1208) comprising polystyrene having a head group selected from the group consisting of -SH, -PO3H2, -CO2H, -NRH, -NRR', and -Si(OR)3, and the second molecular brush layer (1210) comprises a molecular species (1206) comprising polymethacrylate having a head group selected from the group consisting of -SH, -PO3H2, -CO2H, -NRH, -NRR', and -Si(OR)3.

[0198] In one embodiment, the alternating metal lines (1202) and dielectric lines (1204) of the lower metallization layer have a grating pattern having a constant pitch. In one embodiment, the third separation block component (1226) of the triblock copolymer layer (1214) defines all possible via locations for the metallization layer on the lower metallization layer. In one embodiment, the third separation block component (1226) of the triblock copolymer layer (1214) is photosensitive to an extreme ultraviolet (EUV) source or an e-beam source.

[0199] FIG. 12d illustrates an inclined cross-sectional view illustrating an operation in a method using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure.

[0200] Referring to FIG. 12d, all parts of the third separation block component (1226) of the structure (1220) of FIG. 12c are removed. In such an embodiment, the removal of all parts of the third separation block component (1226) opens all possible via locations that can be formed on the underlying metallization layer. Ultimately, the openings can be filled with a photoresist layer to enable the selection of only those via locations required for a specific design. In the case of FIG. 12d, since the removal of all parts of the third separation block component (1226) of the structure (1220) of FIG. 12c can be performed by selective etching only (e.g., selective for the first separation block component (1222) and the second separation block component (1224)), it should be recognized that the third separation block component (1226) of the structure (1220) may be photosensitive, but does not need to be photosensitive. In one such embodiment, selective etching may be performed using selective dry etching or selective wet etching or both.

[0201] FIG. 12e illustrates an inclined cross-sectional view illustrating work in another method using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to another embodiment of the present disclosure.

[0202] Referring to FIG. 12e, only selected portions of the third separation block component (1226) of the structure (1220) of FIG. 12c are removed. In such an embodiment, the removal of only selected portions of the third separation block component (1226) opens the via locations on the underlying metallization layer required for a specific design. In the case of FIG. 12e, it should be recognized that the third separation block component (1226) of the structure (1220) is photosensitive, and that the location selection is performed using localized but highly tolerant lithographic exposure. The exposure may be described as tolerant because the neighboring materials (1222 and 1224) adjacent to the locations (1226) are not photosensitive to the lithography used to select the locations for the portions of the component (1226) to be removed, in one embodiment.

[0203] FIG. 12f illustrates a triblock copolymer for forming self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure.

[0204] Referring to FIG. 12f, the separated triple-block BCP (1250) can be partitioned along the axis (1252) by parts (1222, 1224, 1226). It should be recognized that other partitioning arrangements, such as asymmetric arrangements, may be possible. In one embodiment, there is an etching selectivity between the components (1222, 1224, and 1226) which may be an etching selectivity of 10:1 of one component to the other two components. In one embodiment, the use of the triple-block BCP (1250) can improve pattern fidelity and reduce critical dimension (CD) variation. In one embodiment, the separated triple-block BCP (1250) can be implemented to enable a self-alignment strategy that complements a 193-nanometer immersion lithography (193i) or extreme ultraviolet lithography (EUVL) process.

[0205] Typically, it should be recognized that each block of a triblock copolymer may possess different chemical properties. For example, one of the blocks may be relatively more hydrophobic (e.g., water-repellent) while two of the blocks may be relatively more hydrophilic (water-absorbent), or vice versa. At least conceptually, one of the blocks may be relatively more oil-like and the other two blocks may be relatively more water-like, or vice versa. Such differences in chemical properties between the different polymer blocks, whether hydrophilicity-hydrophobicity differences or others, can cause the block copolymer molecules to self-assemble. For example, self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water, which are generally immiscible.

[0206] Similarly, differences in hydrophilicity between polymer blocks can cause roughly similar microphase separation when different polymer blocks attempt to "separate" from each other due to chemical incompatibility. However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot be completely separated macroscopically. Rather, polymer blocks of a given type may tend to separate or aggregate with polymer blocks of other molecules of the same type in extremely small (e.g., nano-sized) regions or phases. The specific size and shape of those regions or microphases generally depend at least partially on the relative lengths of the polymer blocks. In one embodiment, as an example, FIGS. 12g, 12h, and 12i depict possible assembly schemes for a triblock copolymer.

[0207] It should be recognized that the patterns required to open pre-formed via or plug locations can be made relatively small, which can enable an increase in the overlay margin of the lithography process. Pattern features can be made of uniform size, which can reduce scan time for direct write e-beams and / or optical proximity correction (OPC) complexity associated with optical lithography. Pattern features can also be made shallow, which can improve patterning resolution. The subsequent etching process can be isotropic chemically selective etch. Such an etching process alleviates issues otherwise associated with profile and critical dimensions and mitigates anisotropy issues typically associated with dry etching approaches. Such an etching process is also relatively much cheaper in terms of equipment and throughput compared to other selective removal approaches.

[0208] The following describes portions of integrated circuit layers representing various operations in a method of self-aligning vias and metal patterning. In particular, FIGS. 12g and FIGS. 12h illustrate plan views and corresponding cross-sectional views representing various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure.

[0209] FIG. 12g illustrates a plan view and corresponding cross-sectional views taken along the aa' axis of options for a prior layer metallized structure according to one embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional view option (a), the start structure (1260) includes a pattern of metal lines (1262) and interlayer dielectric (ILD) lines (1264). The start structure (1260) may be patterned into a grating-like pattern having metal lines spaced at a constant pitch and having a constant width, as depicted in FIG. 12g, when self-assembly materials are ultimately formed thereon. In the case of cross-sectional view (a), the pattern of metal lines (1262) and interlayer dielectric (ILD) lines (1264) is planar with respect to each other. Some of the lines may be associated with underlying vias, such as line (1262') shown as an example in the cross-sectional views.

[0210] Referring again to FIG. 12g, alternative options (b) through (f) address situations in which an additional film is formed (e.g., deposited, grown, or left as an artifact remaining from a previous patterning process) on the surface of one or both of the metal lines (1262) and the interlayer dielectric lines (1264). In example (b), an additional film (1266) is placed on the interlayer dielectric lines (1264). In example (c), an additional film (1268) is placed on the metal lines (1262). In example (d), an additional film (1266) is placed on the interlayer dielectric lines (1264), and an additional film (1268) is placed on the metal lines (1262). Furthermore, although the metal lines (1262) and interlayer dielectric lines (1264) are depicted as coplanar in (a), in other embodiments they are not coplanar. For example, in (e), the metal lines (1262) protrude over the interlayer dielectric lines (1264). In example (f), the metal lines (1262) are recessed under the interlayer dielectric lines (1264).

[0211] Referring again to Examples (b) through (d), an additional layer (e.g., layer (1266 or 1268)) may be used as a hard mask (HM) or a protective layer, or may be used to enable the self-assembly described below in relation to subsequent processing operations. Such additional layers may also be used to protect the ILD lines from further processing. In addition, optionally depositing other materials over the metal lines may be beneficial for similar reasons. Referring again to Examples (e) and (f), it may also be possible to reset either the ILD lines or the metal lines having any combination of protective / HM materials on either one or both surfaces. Overall, there are numerous options at this stage for ultimately preparing the underlying surfaces for the inductive self-assembly process.

[0212] Referring to FIG. 12h, a triblock copolymer layer (1270) is formed on the structure of FIG. 12g (e.g., plan view and cross-sectional structure (a)). The triblock copolymer layer (1270) is separated to have regions (1272) formed over the ILD lines (1264), and alternating second regions (1274) and third regions (1276) formed over the metal lines (1262).

[0213] Referring to the cross-sectional view along the bb' axis of FIG. 12h, the third regions (1276) are shown above the metal lines (1262), and the first regions (1272) are shown above the ILD lines (1264). According to one embodiment, a layer (1280) which may be a remnant of the molecular brush layer is also shown between the first regions (1272) and the ILD lines (1264). However, it should be recognized that the layer (1280) may not be present. According to one embodiment, the third regions (1276) are shown as being formed directly above the metal lines (1262). However, it should be recognized that remnants of the molecular brush layer may be between the third regions (1276) and the metal lines (1262).

[0214] Referring to the cross-sectional view along the cc' axis of FIG. 12h, the second regions (1274) are shown on the metal lines (1262), and the first regions (1272) are shown on the ILD lines (1264). According to one embodiment, a layer (1280), which may be a residue of the molecular brush layer, is also shown between the first regions (1272) and the ILD lines (1264). However, it should be recognized that the layer (1280) may not be present. According to one embodiment, a layer (1282), which may be a residue of the molecular brush layer, is also shown between the second regions (1274) and the metal lines (1262). However, it should be recognized that the layer (1282) may not be present. It should also be recognized that the regions (1276) may be formed as photosensitive or replaced with a photosensitive material.

[0215] Accordingly, in one embodiment, the underlying metal and ILD grid is regenerated into a block copolymer (BCP). This may be particularly true when the BCP pitch corresponds to the underlying grating pitch. In one embodiment, the polymer grid is robust against specific small deviations from such a highly aligned grid. For example, if small plugs effectively place oxide or similar material where the highly aligned grid would have metal, an essentially highly aligned block copolymer grid can still be achieved.

[0216] In one embodiment, referring again to FIG. 12h, the thickness of the coated triblock copolymer layer (1270) is approximately equal to or slightly thicker than the ultimate thickness of the ILD that is ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grid is not formed as an etching resist, but rather as a scaffolding to ultimately grow a permanent ILD layer around it. As such, the thickness of the triblock copolymer layer (1270) may be important because this thickness can be used to define the ultimate thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 12h is eventually replaced by an ILD / metal line grating of approximately the same thickness.

[0217] In one embodiment, the triblock copolymer layer (1270) molecule is a polymer molecule formed from a chain of covalently bonded monomers. In the triblock copolymer, there are three different types of monomers, and these different types of monomers are mainly contained within different blocks or consecutive sequences of monomers. In one embodiment, the triblock copolymer layer (1270) is first applied as a portion of an unassembled block copolymer layer comprising a block copolymer material applied, for example, by a brush or other coating process. The unassembled mode refers to scenarios in which, at deposition, the block copolymer is not yet substantially phase-separated and / or self-assembled to form nanostructures. In this unassembled mode, the block polymer molecules are relatively highly randomized, and the different polymer blocks are relatively highly randomly oriented and positioned, in contrast to the assembled triblock copolymer layer (1270) discussed in relation to the resulting structure of FIG. 12h. The unassembled block copolymer layer portion can be applied in various different ways. For example, the block copolymer can be dissolved in a solvent and then spin-coated onto the surface. Alternatively, the unassembled block copolymer can be spray-coated, dip-coated, immersed, or coated or applied onto the surface in other ways. Other methods of applying block copolymers, as well as other methods known in the art for applying similar organic coatings, may potentially be used. Subsequently, the unassembled layer can form an assembled block copolymer layer portion, for example, by microphase separation and / or self-assembly of the unassembled block copolymer layer portion. Microphase separation and / or self-assembly occurs through the rearrangement and / or rearrangement of block copolymer molecules to form a triblock copolymer layer (1270), and in particular through the rearrangement and / or rearrangement of different polymer blocks of block copolymer molecules.

[0218] In one such embodiment, an annealing treatment may be applied to an unassembled block copolymer to initiate, accelerate, improve the quality of, or otherwise promote microphase separation and / or self-assembly to form a triblock copolymer layer (1270). In some embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. Examples of such treatments include baking the layer, heating the layer in an oven or under a heat lamp, applying infrared radiation to the layer, or otherwise applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and / or self-assembly of the block copolymer without damaging any other important materials or structures of the block copolymer or integrated circuit board. Typically, the heating may be in the range of about 50°C to about 300°C, or about 75°C to about 250°C, but does not exceed the thermal degradation limits of the block copolymer or integrated circuit board. Heating or annealing can help provide energy to block copolymer molecules to make them more mobile / flexible, in order to increase the rate of microphase separation and / or improve the quality of microphase separation. Such microphase separation or rearrangement / rearrangement of block copolymer molecules can lead to self-assembly to form extremely small (e.g., nano-scale) structures. Self-assembly can occur under the influence of forces such as surface tension, molecular likes and dislikes, and other surface-related and chemical-related forces.

[0219] In any case, in some embodiments, the self-assembly of block copolymers can be used to form extremely small periodic structures (e.g., nano-scale structures or lines at precise intervals) in the form of a triblock copolymer layer (12720), whether based on hydrophobic-hydrophilic differences or in other ways. In some embodiments, these can be used to form nano-scale lines or other nano-scale structures that can ultimately be used to form via openings. In some embodiments, the induced self-assembly of block copolymers can be used to form vias that self-align with interconnects, as described in more detail below.

[0220] It should be recognized that the two components of the triblock copolymer structure formed on the metal lines do not need to have a 1:1 ratio (the 1:1 ratio is illustrated in FIG. 12c and FIG. 12h). For example, the third separating block component may be present in a smaller amount than the second component and may have a columnar structure surrounded by the second separating block component. FIG. 12i through 12l illustrate plan views and corresponding cross-sectional views illustrating various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure.

[0221] Referring to FIG. 12i, the plan view and the corresponding cross-sectional view taken along the dd' axis illustrate a third component (1276) with a smaller amount than the second component (1274). The third separating block component (1276) has a columnar structure surrounded by the second separating block component (1274).

[0222] Referring to FIG. 12j, the plan view illustrates that a lithographic selection (1290) of specifics (1292) of the third separation block component (1276) is performed to ultimately provide via locations for the upper metallized structure.

[0223] It should be recognized that while FIG. 12i effectively illustrates a non-exposed photosensitive DSA structure, FIG. 12j illustrates an exposed photosensitive DSA structure. Unlike FIG. 12h, FIG. 12i and FIG. 12j show an example of a columnar structure that can be formed when many block copolymer molecules are aligned with their shorter blocks of one of the polymer-forming columnar structures surrounded by a phase having longer blocks of another polymer. According to one embodiment of the present disclosure, the photoactive properties of the DSA structure provide the ability to effectively "plug" or "cut" a type of DSA polymer region using, for example, an e-beam or EUV exposure.

[0224] Referring to FIG. 12k, the plan view illustrates the exposed / chemically amplified regions (1294) within the exposure zones. By selectivity, the only active modification is to the material of the exposed portions of the third separation block component (1276). Although shown as already cleared in FIG. 12k, it should be recognized that the selected regions may not yet be cleared.

[0225] Referring to FIG. 12L, a plan view and a corresponding cross-sectional view taken along the ee' axis illustrate a post-lithographic development to provide cleared regions (1294). The cleared regions (1294) can ultimately be used for via formation.

[0226] The resulting patterned DSA structure of FIG. 12l (or FIG. 12c, FIG. 12d, FIG. 12e, or FIG. 12h) described above can ultimately be used as a scaffold on which permanent layers are ultimately formed. That is, none of the DSA materials are present in the final structure, but rather may be used to induce the fabrication of the finished interconnect structure. In one such embodiment, a permanent ILD replaces one or more regions of the DSA material, and subsequent processing (such as metal line fabrication) is completed. That is, it is possible for all DSA components to ultimately be removed for the formation of final self-aligned vias and plugs. In other embodiments, at least some of the DSA material may remain in the final structure.

[0227] Referring again to FIGS. 12a through 12c, FIGS. 12g, FIGS. 12h, and FIGS. 12i through 12l, in one embodiment, a method for manufacturing an interconnect structure for a semiconductor die comprises the step of forming a lower metallization layer having alternating metal lines and dielectric lines on a substrate. A triblock copolymer layer is formed on the lower metallization layer. The triblock copolymer layer is separated to form a first separation block component above the dielectric lines of the lower metallization layer, and to form alternating second and third separation block components disposed above the metal lines of the lower metallization layer. The third separation block component is photosensitive. The method also comprises the step of irradiating and developing selected locations of the third separation block component to provide via openings above the metal lines of the lower metallization layer.

[0228] In one embodiment, the alternating second and third separated block components have a ratio of approximately 1:1, as described in relation to FIG. 12c and FIG. 12h. In another embodiment, the alternating second and third separated block components have a ratio of the second separated block component to the third separated block component of X:1, where X is greater than 1. In that embodiment, as described in relation to FIG. 12i, the third separated block component has a columnar structure surrounded by the second separated block component.

[0229] In one embodiment, the method further comprises, following the step of investigating and developing selected locations of a third separation block component to provide via openings, the step of forming a second level of alternating metal lines and dielectric lines on top of a first level of alternating metal lines and dielectric lines, coupled thereto and orthogonally thereto, using the resulting patterned triblock copolymer layer as a scaffold. In one embodiment, one or more components of the triblock copolymer layer are retained in the final structure. However, in other embodiments, all components of the triblock copolymer layer are ultimately sacrificial in that none of the materials are retained in the final product. An exemplary embodiment of one embodiment of the latter example is described below in conjunction with FIG. 13.

[0230] In one embodiment, the method further comprises, before forming the triblock copolymer layer, the step of forming a first molecular brush layer on the dielectric lines of the lower metallization layer and the step of forming a second different molecular brush layer on the metal lines of the lower metallization layer, exemplary embodiments thereof have been described above in connection with FIGS. 12a through 12c. In one embodiment, the step of irradiating and developing selected locations of the third separation block component comprises the step of exposing the selected locations of the third separation block component to an extreme ultraviolet (EUV) source or an e-beam source.

[0231] As provided merely as an example of a final structure that can ultimately be obtained, FIG. 13 illustrates a plan view and corresponding cross-sectional views of a self-aligned via structure after the formation of metal lines, vias, and plugs according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the ff' and gg' axes, the upper level of the metal lines (1302) is provided on a dielectric framework (e.g., on a dielectric layer (1304) and adjacent to the dielectric lines (1314). The metal lines (1302) are coupled to the metal lines (1262) below through predetermined via locations (an example thereof (1306) is shown in cross-sectional view (a)) and isolated by plugs (examples thereof include plugs (1308 and 1310)). The lines below (1262 and 1264) may be as previously described in connection with FIG. 12g, as formed in a direction orthogonal to the metal lines (1302). It should be recognized that in subsequent manufacturing operations, the dielectric lines (1314) may be removed to provide air gaps between the resulting metal lines (1302).

[0232] The resulting structure, such as that described in connection with FIG. 13, can subsequently be used as a basis for forming subsequent metal lines / vias and ILD layers. Alternatively, the structure of FIG. 13 may represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations may be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. In any case, the resulting structures enable the fabrication of vias centered directly on the metal lines below. That is, the vias may be wider, narrower, or have the same thickness as the metal lines below, for example, due to imperfect selective etching processing. Nevertheless, in one embodiment, the centers of the vias are directly aligned (matched up) with the centers of the metal lines. As such, in one embodiment, offsets resulting from conventional lithography / dual damascene patterning, which must be allowed in other ways, are not a factor for the resulting structures described herein. It should be recognized that the above examples focus on via / contact formation. However, in other embodiments, similar approaches may be used to preserve or form regions (plugs) for line end termination within the metal line layer.

[0233] It should be recognized that while the process flows described herein may be described primarily as DSA-based (such as some of the process schemes described above), other process flows may be primarily etching-based. According to one embodiment of the present disclosure, a deep subtractive approach is implemented for BEOL processing. One or more embodiments described herein relate to subtractive approaches for self-aligned via and plug patterning, and structures resulting therefrom. In one embodiment, the processes described herein enable the realization of self-aligned metallization for back-end of line (BEOL) feature fabrication. Overlay problems anticipated for next-generation via and plug patterning can be resolved by one or more approaches described herein. Generally, one or more embodiments described herein involve the use of a subtractive method to pre-form all vias and plugs using already etched trenches. An additional operation is then used to select which of the vias and plugs to retain.

[0234] FIGS. 14a through 14n illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via and plug patterning according to one embodiment of the present disclosure. In each example of each described operation, an inclined three-dimensional cross-sectional view is provided.

[0235] FIG. 14a illustrates a starting point structure (1400) for a subtractive via and plug process following the manufacture of a deep metal line according to one embodiment of the present disclosure. Referring to FIG. 14a, the structure (1400) comprises metal lines (1402) having interposed interlayer dielectric (ILD) lines (1404). The ILD lines (1404) comprise a plug cap layer (1406). In one embodiment, as described in more detail below in conjunction with FIG. 14e, the plug cap layer (1406) is later patterned to ultimately define all possible locations for later plug formation.

[0236] In one embodiment, the grating structure formed by the metal lines (1402) is a dense pitch grating structure. In such an embodiment, the dense pitch is not directly achievable through conventional lithography. For example, a pattern based on conventional lithography may be formed first, but the pitch may be divided into two by the use of spacer mask patterning. Furthermore, the original pitch may be divided into four by a second round of spacer mask patterning. Accordingly, the grating-like pattern of FIG. 14a may have metal lines that are spaced at a constant pitch and have a constant width. The pattern may be manufactured by a pitch-divided or pitch-divided approach. It should also be recognized that some of the lines (1402) may be associated with vias below to be coupled to a previous interconnect layer.

[0237] In one embodiment, metal lines (1402) are formed by patterning trenches in an ILD material (e.g., the ILD material of the lines (1404)) on which a plug cap layer (1406) is formed. The trenches are then filled with metal and, if necessary, flattened to the plug cap layer (1406). In one embodiment, the metal trench and filling process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of the metal line height (h) to the metal line width (w) is in the range of approximately 5 to 10.

[0238] FIG. 14b illustrates the structure of FIG. 14a after resetting the metal lines according to one embodiment of the present disclosure. Referring to FIG. 14b, the metal lines (1402) are optionally reset to provide first-level metal lines (1408). Resetting is optionally performed on the ILD lines (1404) and the plug cap layer (1406). Resetting may be performed by etching through dry etching, wet etching, or a combination thereof. The degree of resetting may be determined by the target thickness (th) of the first-level metal lines (1408) for use as suitable conductive interconnect lines within the BEOL (back end of line) interconnect structure.

[0239] FIG. 14c illustrates the structure of FIG. 14b after hard mask filling in the recessed regions of the recessed metal lines according to one embodiment of the present disclosure. Referring to FIG. 14c, a hard mask layer (1410) is formed in the regions formed during recessing to form the first level metal lines (1408). The hard mask layer (1410) may be formed up to the level of the plug cap layer (1406) by a material deposition and chemical mechanical planarization (CMP) process, or by a controlled bottom-up only growth process. In one particular embodiment, the hard mask layer (1410) is composed of a carbon-rich material.

[0240] FIG. 14d illustrates the structure of FIG. 14c after the deposition and patterning of a hard mask layer according to one embodiment of the present disclosure. Referring to FIG. 14d, a second hard mask layer (1412) is formed on or above the hard mask layer (1410) and the plug cap layer (1406). In such an embodiment, as depicted in FIG. 14d, the second hard mask layer (1412) is formed with a grating pattern orthogonal to the grating pattern of the first level metal lines (1408) / ILD lines (1404). In one specific embodiment, the second hard mask layer (1412) is composed of a silicon-based anti-reflective coating material. In one embodiment, the grating structure formed by the second hard mask layer (1412) is a dense pitch grating structure. In such an embodiment, the dense pitch is not directly achievable through conventional lithography. For example, a pattern based on conventional lithography may be formed first, but as is known in the art, the pitch may be divided into two by using spacer mask patterning. Furthermore, the original pitch may be divided into four by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the second hard mask layer (1412) of FIG. 14d may have hard mask lines that are spaced at a constant pitch and have a constant width.

[0241] FIG. 14e illustrates a structure of FIG. 14d after trench formation defined using the pattern of the hard mask of FIG. 14d, according to one embodiment of the present disclosure. Referring to FIG. 14e, exposed areas of the hard mask layer (1410) and the plug cap layer (1406) (i.e., not protected by 1412) are etched to form trenches (1414). The etching stops on the top surfaces of the first level metal lines (1408) and ILD lines (1404) to expose the top surfaces.

[0242] FIG. 14f illustrates a structure of FIG. 14e after the formation of ILD in the trenches of FIG. 14e and the removal of the second hard mask, according to one embodiment of the present disclosure. Referring to FIG. 14f, second ILD lines (1416) are formed in the trenches (1414) of FIG. 14e. In one embodiment, a fluid ILD material is used to fill the trenches (1414). In one embodiment, the trenches (1414) are filled and the filling material is subsequently flattened. As depicted in FIG. 14f, flattening may be further used to remove the second hard mask layer (1412) to re-expose the hard mask layer (1410) and the plug cap layer (1406).

[0243] Referring again to FIG. 14f, in one embodiment, the resulting structure comprises a uniform ILD structure (ILD lines (1404) + ILD lines (1416)). All possible plug locations are occupied by the remaining portions of the plug cap layer (1406), while all possible via locations are occupied by the remaining portions of the hard mask layer (1410). In such an embodiment, the ILD lines (1404) and the ILD lines (1416) are composed of the same material. In another such embodiment, the ILD lines (1404) and the ILD lines (1416) are composed of different ILD materials. In either case, in a particular embodiment, a seam-like distinction between the materials of the ILD lines (1404) and the ILD lines (1416) may be observed in the final structure. In addition, in one embodiment, unlike conventional single or dual damascene patterning, there is no distinct etching stop layer where the ILD lines (1404) and ILD lines (1416) meet.

[0244] FIG. 14g illustrates a structure of FIG. 14f after the removal of the remaining portions of the hard mask layer occupying all possible via locations, according to one embodiment of the present disclosure. Referring to FIG. 14g, the remaining portions of the hard mask layer (1410) are optionally removed to form openings (1418) for all possible via locations. In such an embodiment, the hard mask layer (1410) is substantially composed of carbon and is optionally removed through an ashing process.

[0245] Generally, one or more embodiments described herein involve the use of a subtractive method to pre-form all vias and plugs using already etched trenches. An additional operation is then used to select which of the vias and plugs to retain. Such operations may be exemplified using "photobuckets," but the selection process may also be performed using more conventional resist exposure and ILD backfill approaches. It should also be recognized that the embodiments are not limited to the concept of photobuckets and have a wide range of applications, extending to structures having pre-formed features manufactured using bottom-up and / or directed self-assembly (DSA) approaches. Additional embodiments regarding the manufacture and use of photobuckets are described in more detail below in embodiments other than the present embodiments of FIGS. 14a through 14n and FIGS. 15a through 15d.

[0246] FIG. 14h illustrates the structure of FIG. 14g after the formation of photobuckets at all possible via locations according to one embodiment of the present disclosure. Referring to FIG. 14h, photobuckets (1420) are formed at all possible via locations on the exposed portions of the first level metal lines (1408). In one embodiment, the openings (1418) of FIG. 14g are filled with ultrafast photoresist, e-beam resist, or other photosensitive material. In such an embodiment, thermal reflow of the polymer into the openings (1418) is used after spin coat application. In one embodiment, the ultrafast photoresist is prepared by removing a quencher from the existing photoresist material. In another embodiment, the photobuckets (1420) are formed by an etch-back process and / or a lithography / reduction / etching process. It should be recognized that as long as the material functions as a photosensitive switch, the photobuckets do not need to be filled with actual photoresist.

[0247] FIG. 14i illustrates a structure of FIG. 14h following via location selection according to one embodiment of the present disclosure. Referring to FIG. 14i, photobuckets (1420) from FIG. 14h at the selected via locations are removed. At locations not selected for via formation, the photobuckets (1420) are retained, converted to permanent ILD material, or replaced with permanent ILD material. As an example, FIG. 14i illustrates a via location (1422) in which the corresponding photobucket (1420) is removed to expose a portion of one of the first level metal lines (1408). Other locations previously occupied by the photobuckets (1420) are now illustrated as regions (1424) in FIG. 14i. The locations (1424) are not selected for via formation and instead constitute part of the final ILD structure. In one embodiment, the material of the photobuckets (1420) is maintained at locations (1424) as the final ILD material. In another embodiment, the material of the photobuckets (1420) is modified at locations (1424), for example, by cross-linking, to form the final ILD material. In yet another embodiment, the material of the photobuckets (1420) at locations (1424) is replaced with the final ILD material.

[0248] Referring again to FIG. 14i, lithography is used to expose a corresponding photobucket (1420) to form via locations (1422). However, lithography constraints can be relaxed and misalignment tolerances can be high because the photobucket (1420) is surrounded by non-photodegradable materials. Furthermore, in one embodiment, instead of exposing at, for example, 30 mJ / cm2, such a photobucket can be exposed at, for example, 3 mJ / cm2. Typically, this would result in very poor CD control and roughness. However, in this case, CD and roughness control will be defined by the photobucket (1420), which can be very well controlled and defined. Accordingly, the photobucket approach can be used to avoid the imaging / dose trade-off that limits the throughput of next-generation lithography processes.

[0249] Referring again to FIG. 14i, in one embodiment, the resulting structure comprises a uniform ILD structure (ILD (1424) + ILD lines (1404) + ILD lines (1416)). In such an embodiment, two or all of the ILD (1424), ILD lines (1404), and ILD lines (1416) are composed of the same material. In another such embodiment, the ILD (1424), ILD lines (1404), and ILD lines (1416) are composed of different ILD materials. In either case, in a particular embodiment, a distinction such as a seam between the materials of the ILD (1424) and ILD lines (1404) (e.g., seam (1497)) and / or a seam between the materials of the ILD (1424) and ILD lines (1416) (e.g., seam (1498)) is observed in the final structure.

[0250] FIG. 14j illustrates a structure of FIG. 14i after hard mask filling in the openings of FIG. 14i, according to one embodiment of the present disclosure. Referring to FIG. 14j, a hard mask layer (1426) is formed at via locations (1422) and over ILD locations (1424). The hard mask layer (1426) can be formed by deposition and subsequent chemical mechanical planarization.

[0251] FIG. 14k illustrates the structure of FIG. 14j after the removal of the plug cap layer and the formation of a second plurality of photobuckets, according to one embodiment of the present disclosure. Referring to FIG. 14k, the plug cap layer (1406) is removed, for example, by a selective etching process. Photobuckets (1428) are subsequently formed at all possible plug locations on the exposed portions of the ILD lines (1404). In one embodiment, the openings formed upon the removal of the plug cap layer (1406) are filled with ultrafast photoresist, e-beam resist, or other photosensitive material. In such an embodiment, thermal reflow of the polymer into the openings is used after spin coat application. In one embodiment, the high-speed photoresist is prepared by removing quencher from a conventional photoresist material. In another embodiment, the photobuckets (1428) are formed by an etch-back process and / or a lithography / reduction / etching process. It should be recognized that as long as the material functions as a photosensitive switch, the photobuckets do not need to be filled with actual photoresist.

[0252] FIG. 14l illustrates a structure of FIG. 14k after plug location selection according to one embodiment of the present disclosure. Referring to FIG. 14l, photobuckets (1428) from FIG. 14k that are not located in the selected plug locations are removed. In the locations selected for the formation of plugs, the photobuckets (1428) are retained, converted to permanent ILD material, or replaced with permanent ILD material. As an example, FIG. 14l illustrates non-plug locations (1430) in which the corresponding photobuckets (1428) are removed to expose a portion of the ILD lines (1404). Other locations previously occupied by photobuckets (1428) are now illustrated as regions (1432) in FIG. 14l. Region (1432) is selected for plug formation and constitutes part of the final ILD structure. In one embodiment, the material of the corresponding photobucket (1428) is retained in the region (1432) as the final ILD material. In another embodiment, the material of the photobucket (1428) is modified in the region (1432), for example, by cross-linking, to form the final ILD material. In yet another embodiment, the material of the photobucket (1428) in the region (1432) is replaced with the final ILD material. In either case, the region (1432) may also be referred to as a plug (1432).

[0253] Referring again to FIG. 14l, lithography is used to expose corresponding photobuckets (1428) to form apertures (1430). However, lithography constraints can be relaxed and misalignment tolerances can be high because the photobuckets (1428) are surrounded by non-photodegradable materials. Furthermore, in one embodiment, instead of exposing at, for example, 30 mJ / cm2, such photobuckets can be exposed at, for example, 3 mJ / cm2. Typically, this would result in very poor CD control and roughness. However, in this case, CD and roughness control will be defined by the photobuckets (1428), which can be very well controlled and defined. Accordingly, the photobucket approach can be used to avoid the imaging / dose trade-off that limits the throughput of next-generation lithography processes.

[0254] Referring again to FIG. 14l, in one embodiment, the resulting structure comprises a uniform ILD structure (plug (1432) + ILD (1424) + ILD lines (1404) + ILD lines (1416)). In such an embodiment, two or more of the plug (1432), ILD (1424), ILD lines (1404), and ILD lines (1416) are composed of the same material. In another such embodiment, the plug (1432), ILD (1424), ILD lines (1404), and ILD lines (1416) are composed of different ILD materials. In any case, in a particular embodiment, a distinction such as a core (e.g., core (1499)) between the materials of the plug (1432) and the ILD lines (1404) and / or a core (e.g., core (1496)) between the materials of the plug (1432) and the ILD lines (1416) is observed in the final structure.

[0255] FIG. 14m illustrates a structure of FIG. 14l after the removal of the hard mask layer of FIG. 14l according to one embodiment of the present disclosure. Referring to FIG. 14m, the hard mask layer (1426) is optionally removed to form metal lines and via openings (1434). In such an embodiment, the hard mask layer (1426) is substantially composed of carbon and is optionally removed through an ashing process.

[0256] FIG. 14n illustrates the structure of FIG. 14m after the formation of metal lines and vias according to one embodiment of the present disclosure. Referring to FIG. 14n, metal lines (1436) and vias (one shown as 1438) are formed during the metal filling of the openings (1434) of FIG. 14m. The metal lines (1436) are coupled to the metal lines (1408) below by the vias (1438) and interrupted by plugs (1432). In one embodiment, the openings (1434) are filled using a damascene approach, wherein the metal is used to overfill the openings and then flattened again to provide the structure shown in FIG. 14n. Accordingly, the metal (e.g., copper and associated barrier and seed layers) deposition and flattening process for forming metal lines and vias using the above approach may be typically used for standard BEOL (back end of line) single or dual damascene processing. In one embodiment, in subsequent manufacturing operations, the ILD lines (1416) may be removed to provide air gaps between the resulting metal lines (1436).

[0257] The structure of FIG. 14n can subsequently be used as a basis for forming subsequent metal line / via and ILD layers. Alternatively, the structure of FIG. 14n can represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations can be performed in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. In any case, the resulting structures enable the fabrication of vias centered directly on the underlying metal lines. That is, the vias may be wider, narrower, or have the same thickness as the underlying metal lines, for example, due to imperfect selective etching processing. Nevertheless, in one embodiment, the centers of the vias are directly aligned (matched up) with the centers of the metal lines. Furthermore, the ILD is used to select which plugs and vias are likely to be very different from the primary ILD and highly self-aligned in both directions. As such, in one embodiment, the offset resulting from conventional lithography / dual damascene patterning, which must be allowed in a different way, is not a factor for the resulting structures described herein. Referring again to FIG. 14n, self-aligning fabrication by a subtractive approach may then be completed at this stage. The next layer fabricated in a similar manner may involve performing the described process once more. Alternatively, other approaches, such as conventional dual or single damascene approaches, may be used at this stage to provide additional interconnect layers.

[0258] The process flow described above involves the use of deep trench etching. In another embodiment, a shallower approach involves a plug-only self-aligned subtractive processing scheme. As an example, FIGS. 15a through 15d illustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned plug patterning according to another embodiment of the present disclosure. In each example of each described operation, plan views are shown at the top, and corresponding cross-sectional views are shown at the bottom. These drawings will be referred to herein as corresponding cross-sectional views and plan views.

[0259] FIG. 15a illustrates a plan view and corresponding cross-sectional views of a start plug grid according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the aa' and bb' axes, the start plug grid structure (1500) comprises an ILD layer (1502) on which a first hard mask layer (1504) is disposed. A second hard mask layer (1508) is disposed on the first hard mask layer (1504) and patterned to have a grating structure. A third hard mask layer (1506) is disposed on the second hard mask layer (1508) and on the first hard mask layer (1504). Additionally, openings (1510) remain between the grating structure of the second hard mask layer (1508) and the grating structure of the third hard mask layer (1506).

[0260] FIG. 15b illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 15a after photobucket filling, exposure, and development according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the aa' and bb' axes, photobuckets (1512) are formed in the openings (1510) of FIG. 15a. Subsequently, as depicted in FIG. 15b, selected photobuckets are exposed and removed to provide selected plug positions (1514).

[0261] FIG. 15c illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 15b after plug formation, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b), respectively taken along the aa' and bb' axes, plugs (1516) are formed in the openings (1514) of FIG. 15b. In one embodiment, the plugs (1516) are formed by a spin-on approach and / or a deposition and etch-back approach.

[0262] FIG. 15d illustrates a plan view and corresponding cross-sectional views of the structure of FIG. 15c after the removal of the hard mask layer and the remaining photobuckets, according to one embodiment of the present disclosure. Referring to the plan view and the corresponding cross-sectional views (a) and (b) taken respectively along the aa' and bb' axes, the third hard mask layer (1506) is removed, leaving the second hard mask layer (1508) and plugs (1516). The resulting pattern (the second hard mask layer (1508) and plugs (1516)) can subsequently be used to pattern the hard mask layer (1504) for the ultimate patterning of the ILD layer (1502). In one embodiment, the third hard mask layer (1506) is substantially composed of carbon and is removed by performing an ashing process.

[0263] Accordingly, the structure of FIG. 15d can subsequently be used as a basis for forming ILD lines and plug patterns. It should be recognized that the process operations may be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. In any case, the resulting structures enable the manufacture of self-aligning plugs. As such, in one embodiment, the offset resulting from conventional lithography / dual damascene patterning, which must be allowed in a different way, is not a factor for the resulting structures described herein.

[0264] According to one embodiment of the present disclosure, dielectric helmet-based approaches and / or hardmask selectivity-based approaches for the fabrication of back-end-of-line (BEOL) interconnects, and resulting structures are described. One or more embodiments described herein relate to methods using a dielectric helmet for directed self-assembly (DSA) or selective growth that enable the fabrication of self-aligned interconnects. The embodiments may address or implement one or more of the use of a dielectric helmet, inductive self-assembly, selective deposition, self-alignment, or patterning interconnects with a dense pitch. The embodiments may be implemented to provide improved via shorting margins by self-alignment using "coloring" via selective deposition and subsequent inductive self-assembly, for example, for sub-10 nm technology nodes.

[0265] To provide context, current solutions for improving short-circuit margins may include: (1) using metal recesses to fill alternating metal trenches with different hard masks, (2) using different "colored" metal caps as templates for directed self-assembly (DSA) or selective growth, or (3) resetting metal or ILD to "steer" vias toward lines of interest. Overall, the general process flows for improving via short-circuit margins require metal resetting. However, resetting metal to an acceptable uniformity has been found to be a challenge in many such processing schemes.

[0266] According to one embodiment of the present disclosure, one or more of the above issues are resolved by implementing a method of depositing a non-conformal dielectric cap on half of a group of interconnects. The non-conformal dielectric cap is used as a template for selective growth or induced self-assembly. In one such embodiment, such an approach may be applied to any interconnect metal layer and, perhaps, to gate contacts. In certain embodiments, the need for metal recesses as seen in prior art approaches is effectively eliminated from the processing schemes described herein.

[0267] As a general overview of the concepts included in this specification, FIGS. 16a through 16d illustrate cross-sectional views of portions of integrated circuit layers representing various operations in a method involving the formation of a dielectric helmet for manufacturing a back end of line (BEOL) interconnect according to one embodiment of the present disclosure.

[0268] Referring to FIG. 16a, a starting point structure (1600) is provided as a starting point for manufacturing a new metallization layer. The starting point structure (1600) includes a hard mask layer (1604) disposed on an interlayer dielectric (ILD) layer (1602). As described below, the ILD layer may be disposed on a substrate and, in one embodiment, is disposed above the metallization layer below. Openings corresponding to trenches formed in the ILD layer (1602) are formed in the hard mask layer (1604). Alternating trenches among the trenches are filled with a conductive layer to provide first metal lines (1606) (and, in some cases, corresponding conductive vias (1607)). The remaining trenches are not filled to provide open trenches (1608). In one embodiment, the start structure (1600) is manufactured by patterning the hard mask and ILD layers and then metallizing half of a group of metal trenches (e.g., alternating trenches among the trenches) while leaving the other half of the group open. In one embodiment, the trenches within the ILD are patterned using a pitch-divided patterning process flow. It should be recognized that the process operation described below may or may not first involve pitch division. In either case, but particularly when pitch division is also used, the embodiments may enable continued scaling of the pitch of the metal layers beyond the resolution capabilities of the prior art lithography equipment.

[0269] FIG. 16b illustrates the structure of FIG. 16a after the deposition of a non-conformal dielectric cap layer (1610) on the structure (1600). The non-conformal dielectric cap layer (1610) comprises a first portion (1600A) covering the exposed surfaces of the hard mask layer (1604) and the metal lines (1606). The non-conformal dielectric cap layer (1610) comprises a second portion (1610B) continuous with the first portion (1610A). The second portion (1610B) of the non-conformal dielectric cap layer (1610) is formed in the open trenches (1608) along the sidewalls (1608A) and bottom (1608B) of the open trenches (1608). In one embodiment, as depicted in FIG. 16b, the second portion (1610B) of the non-conformal dielectric cap layer (1610) is substantially thinner than the first portion (1610A). In other embodiments, the portion (1610B) is absent or discontinuous. In this way, because the thickness of the non-conformal dielectric cap layer (1610) is not the same at all locations, the deposition of the non-conformal dielectric cap layer (1610) is considered non-conformal deposition. The resulting geometry may be referred to as a helmet shape for the non-conformal dielectric cap layer (1610) because the uppermost portions of the ILD layer (1602) have the thickest portion of the non-conformal dielectric cap layer (1610) on them and are therefore protected to a greater degree than other regions. In one embodiment, the non-conformal dielectric cap layer (1610) is a dielectric material such as, but not limited to, silicon nitride or silicon oxynitride. In one embodiment, the non-conformal dielectric cap layer (1610) is formed using a plasma-enhanced chemical vapor deposition (PECVD) process, or, in another embodiment, using physical vapor deposition (PVD).

[0270] FIG. 16c illustrates the structure of FIG. 16b after via patterning, metallization, and planarization of the second half of the metal lines. In one embodiment, a metal filling process is performed to provide the second metal lines (1612). However, in one embodiment, prior to metal filling, via locations are first selected and opened. Subsequently, during metal filling, vias (1613) are formed in association with specifics of the second metal lines (1612). In such an embodiment, via openings are formed by extending specifics of the open trenches (1608) by etching through a non-conformal dielectric cap layer (1610) at the bottom of the selected trench (1608) and then extending the trench through the dielectric layer (1602). The result is a discontinuity of the continuity of the non-conformal dielectric cap layer (1610) at the via locations of the second metal lines (1612), as depicted in FIG. 16c.

[0271] In one embodiment, the metal filling process used to form the second metal lines (1612) and the conductive vias (1613) is performed using a subsequent planarization processing scheme, such as a metal deposition and chemical mechanical planarization (CMP) process. The planarization process exposes but does not remove the non-conformal dielectric cap layer (1610), as depicted in FIG. 16c. In one embodiment, since the second metal lines (1612) (and the corresponding conductive vias (1613)) are formed in a later process than the process used to manufacture the first metal lines (1606) (and the corresponding conductive vias (1607)), it should be recognized that the second metal lines (1612) may be manufactured using a different material than that used to manufacture the first metal lines (1606). In such an embodiment, the metallization layer ultimately comprises conductive interconnects of different first and second compositions that alternate. However, in another embodiment, the metal lines (1612 and 1606) are made of substantially the same material.

[0272] In one embodiment, the first metal lines (1606) are spaced apart by a certain pitch, and the second metal lines (1612) are spaced apart by the same pitch. In other embodiments, the lines are not necessarily spaced apart by a certain pitch. However, by including a non-conformal dielectric cap layer (1610) or a dielectric helmet, only the surfaces of the second metal lines (1612) are exposed. As a result, the pitch between adjacent first and second metal lines that would otherwise have been exposed is relaxed to only the pitch of the second metal lines. Accordingly, the exposed dielectric surfaces of the alternating non-conformal dielectric cap layers (1610) and the exposed surfaces of the second metal lines (1612) provide surfaces differentiated by the pitch of the second metal lines (1612).

[0273] FIG. 16d illustrates the structure of FIG. 16c following an inductive self-assembly or selective deposition approach to ultimately form two different, alternating first and second hardmask layers (1614 and 1616), respectively. In one embodiment, the materials of the hardmask layers (1614, 1616) exhibit different etching selectivity relative to one another. The first hardmask layer (1614) is aligned with the exposed regions of the non-conformal dielectric cap layer (1610). The second hardmask layer (1616) is aligned with the exposed regions of the second metal lines (1612). As described in more detail below, inductive self-assembly or selective growth can be used to selectively align the first and second hardmask layers (1614 and 1616), respectively, with respect to dielectric and metal surfaces.

[0274] In a first general embodiment, a direct self-assembly (DSA) block copolymer deposition and polymer assembly process is performed to ultimately form the first and second hard mask layers (1614 and 1616). In one embodiment, the DSA block copolymer is coated on a surface and annealed to separate the polymer into first blocks and second blocks. In one embodiment, the first polymer blocks are preferentially attached to the non-conformal dielectric cap layer (1610). The second polymer blocks are attached to the second metal lines (1612). In one embodiment, the block copolymer molecule is a polymer molecule formed from a chain of covalently bonded monomers, examples thereof have been described above.

[0275] Referring again to FIG. 16d, in the case of the DSA process, in the first embodiment, the first and second hard mask layers (1614 and 1616) are, respectively, the first and second block polymers. However, in the second embodiment, each of the first and second block polymers is sequentially replaced with the materials of the first and second hard mask layers (1614 and 1616). In such an embodiment, an optional etching and deposition process is used to replace the first and second block polymers with, respectively, the materials of the first and second hard mask layers (1614 and 1616).

[0276] In a second general embodiment, to ultimately form the first and second hardmask layers (1614 and 1616), a selective growth process is used instead of the DSA approach. In such an embodiment, the material of the first hardmask layer (1614) is grown over the exposed portions of the underlying non-conformal dielectric cap layer (1610). The second different material of the second hardmask layer (1616) is grown over the exposed portions of the underlying second metal lines (1612). In one embodiment, selective growth is achieved by a deposition-etch-deposition-etch approach for each of the first and second materials, resulting in multiple layers of each of the materials. Such an approach may be advantageous compared to conventional selective growth techniques that can form "mushroom cap" shaped films. The tendency for mushroom cap film growth can be reduced through an alternating deposition / etch / deposition (dep-etch-dep-etch) approach. In another embodiment, a film is selectively deposited on top of a metal and then a different film is selectively deposited on top of the ILD (or vice versa), and this is repeated several times to create a sandwich-like stack. In another embodiment, both materials, which are selectively grown on each exposed area of ​​the substrate below, are grown simultaneously in a reaction chamber (e.g., by a CVD-style process).

[0277] As described in more detail below, in one embodiment, the resulting structure of FIG. 16d enables an improved via short-circuit margin when via layers are subsequently fabricated on the structure of FIG. 16d. In one embodiment, an improved short-circuit margin is achieved because fabricating the structure using alternating "color" hard masks reduces the risk of via short-circuiting to incorrect metal lines. In one embodiment, self-alignment is achieved because the alternating color hard masks self-align with the metal trenches below. In one embodiment, the need for metal recesses is removed from the processing scheme, which can reduce process variation.

[0278] In a first more detailed exemplary process flow, FIGS. 16e through 16p illustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving the formation of a dielectric helmet for manufacturing a back end of line (BEOL) interconnect according to one embodiment of the present disclosure.

[0279] Referring to FIG. 16e, a starting point structure (1630) is provided after a first pass metal processing as a starting point for manufacturing a new metallization layer. The starting point structure (1630) comprises a hard mask layer (1634) (e.g., silicon nitride) disposed on an interlayer dielectric (ILD) layer (1632). As described below, the ILD layer may be disposed on a substrate and, in one embodiment, is disposed above the metallization layer below. First metal lines (1636) (and, in some cases, corresponding conductive vias (1637)) are formed on the ILD layer (1632). Protrusions (1636A) of the metal lines (1636) have adjacent dielectric spacers (1638). A sacrificial hard mask layer (1640) (e.g., amorphous silicon) is included between the adjacent dielectric spacers (1638). Although not described, in one embodiment, metal lines (1636) are formed by first removing the second sacrificial hard mask material between the dielectric spacers (1638) to form trenches that are later filled in the metallization process, and then etching the hard mask layer (1634) and the ILD layer (1632).

[0280] FIG. 16f illustrates the structure of FIG. 16e up to or after a second pass metal processing including trench etching. Referring to FIG. 16f, the sacrificial hard mask layer (1640) is removed to expose the hard mask layer (1634). The exposed portions of the hard mask layer (1634) are removed, and trenches (1642) are formed in the ILD layer (1632).

[0281] FIG. 16g illustrates the structure of FIG. 16f after the sacrificial material filling. The sacrificial material (1644) is formed in the trenches (1642) and on top of the spacers (1638) and metal lines (1636). In one embodiment, as depicted in FIG. 16g, the sacrificial material (1644) is formed in a spin-on process, leaving a substantially flat layer.

[0282] FIG. 16h illustrates the structure of FIG. 16g after a planarization process for re-exposing the hard mask layer (1634), removing the dielectric spacers (1638), and removing the protrusions (1636A) of the metal lines (1636). Additionally, the planarization process confined the sacrificial material (1644) to the trenches (1642) formed in the dielectric layer (1632). In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

[0283] FIG. 16i illustrates the structure of FIG. 16h after the removal of the sacrificial material. In one embodiment, the sacrificial material (1644) is removed from the trenches (1642) using a wet etching or dry etching process.

[0284] FIG. 16j illustrates the structure of FIG. 16i after the deposition of a non-conformal dielectric cap layer (1646), which may be referred to as a dielectric helmet. In one embodiment, the non-conformal dielectric cap layer (1646) is formed using a chemical vapor deposition (CVD) process, such as a physical vapor deposition (PVD) or plasma-enhanced CVD (PECVD) process. The non-conformal dielectric cap layer (1646) may be as previously described in relation to the non-conformal dielectric cap layer (1610).

[0285] FIG. 16k illustrates the structure of FIG. 16j after the deposition of a sacrificial cap layer. The sacrificial cap layer (1648) may be formed on the upper surfaces of a non-conformal dielectric cap layer (1646) and implemented to protect the non-conformal dielectric cap layer (1646) during a subsequent etching or CMP process. In one embodiment, the sacrificial cap layer (1648) is a titanium nitride (TiN) layer formed, for example, by PVD or CVD processing.

[0286] FIG. 16l illustrates the structure of FIG. 16k after via lithography and etching processing. Selected trenches among the trenches (1638) are exposed and undergo an etching process to extend the trenches to cut off the non-conformal dielectric cap layer (1646) at location (1650) and provide a via location (1652), as previously described.

[0287] FIG. 16m illustrates the structure of FIG. 16l after the manufacture of the second metal line. In one embodiment, the second metal lines (1654) (and, in some cases, the associated conductive vias (1656)) are formed by performing a metal filling and polishing process. The polishing process may be a CMP process that further removes the sacrificial cap layer (1648).

[0288] FIG. 16n illustrates a structure of FIG. 16m after directed self-assembly (DSA) or selective growth to provide, for example, first and second alternating placeholder materials (1658 and 1660) (or, as described in relation to FIG. 16d, permanent materials).

[0289] FIG. 16o illustrates the structure of FIG. 16n after replacing the first and second alternating placeholder materials (1658 and 1660) with permanent first and second hardmask layers (1662 and 1664), respectively. Processing for FIG. 16n and FIG. 16o may be as described in connection with FIG. 16d.

[0290] FIG. 16p illustrates the structure of FIG. 16o after the next layer via patterning. An upper ILD layer (1666) is formed over the first and second hard mask layers (1662 and 1664). An opening (1668) is formed in the upper ILD layer (1666). In one embodiment, the opening (1668) is formed wider than the via feature size. Selected locations among the exposed first and second hard mask layers (1662 and 1664) are selected for selective removal, for example, by a selective etching process. In this case, the first hard mask (1662) region is selectively removed for the exposed portions of the second hard mask layer (1664). Conductive vias (1670) are subsequently formed in the opening (1668) and in the regions where the first hard mask (1662) region was removed. A conductive via (1670) contacts one of the first metal lines (1636). In one embodiment, the conductive via (1670) contacts one of the first metal lines (1636) without short-circuiting to one of the adjacent second metal lines (1654). In a specific embodiment, a portion (1672) of the conductive via (1670) is placed on a portion of the second hard mask layer (1664) without contacting the second metal line (1654) below, as depicted in FIG. 16p. In one embodiment, an improved short-circuit margin is then realized.

[0291] In one embodiment, as described in the above embodiment, a first hard mask (1662) region is removed for manufacturing a via (1670). In this case, forming an opening upon removal of the selected first hard mask (1662) region requires additional etching through the uppermost portion of the non-conformal dielectric cap layer (1646). However, in another embodiment, a second hard mask (1664) region is removed for manufacturing a via (1670). In this case, forming an opening upon removal of such selected second hard mask (1664) region directly exposes the metal line (1654) to which the via (1670) is connected.

[0292] In a second, more detailed exemplary process flow involving a first via etching approach, FIGS. 17a through 17j illustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving the formation of a dielectric helmet for manufacturing a back end of line (BEOL) interconnect according to one embodiment of the present disclosure.

[0293] Referring to FIG. 17a, a starting point structure (1700) is provided after a first pass metal processing as a starting point for manufacturing a new metallization layer. The starting point structure (1700) comprises a hard mask layer (1704) (e.g., silicon nitride) disposed on an interlayer dielectric (ILD) layer (1702). As described below, the ILD layer may be disposed on a substrate and, in one embodiment, is disposed above the metallization layer below. First metal lines (1706) (and, in some cases, corresponding conductive vias (1707)) are formed on the ILD layer (1702). Protrusions (1706A) of the metal lines (1706) have adjacent dielectric spacers (1708). A sacrificial hard mask layer (1710) (e.g., amorphous silicon) is included between the adjacent dielectric spacers (1708). Although not described, in one embodiment, metal lines (1706) are formed by first removing the second sacrificial hard mask material between the dielectric spacers (1708) to form trenches that are later filled in the metallization process, and then etching the hard mask layer (1704) and the ILD layer (1702).

[0294] FIG. 17b illustrates the structure of FIG. 17a up to or after a second pass metal processing including trench and via location etching. Referring to FIG. 17b, the sacrificial hard mask layer (1710) is removed to expose the hard mask layer (1704). The exposed portions of the hard mask layer (1704) are removed, and trenches (1712) are formed in the ILD layer (1702). In addition, in one embodiment, via locations (1722) are formed at selected locations using a via lithography and etching process, as depicted in FIG. 17b.

[0295] FIG. 17c illustrates the structure of FIG. 17b after the sacrificial material filling. The sacrificial material (1714) is formed in the trenches (1712) and on the spacers (1708) and metal lines (1706). In one embodiment, as depicted in FIG. 17c, the sacrificial material (1714) is formed in a spin-on process, leaving a substantially flat layer.

[0296] FIG. 17d illustrates the structure of FIG. 17c after a planarization process for re-exposing the hard mask layer (1704), removing the dielectric spacers (1708), and removing the protrusions (1706A) of the metal lines (1706). Additionally, the planarization process confined the sacrificial material (1714) to the trenches (1712) formed in the dielectric layer (1702). In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

[0297] FIG. 17e illustrates the structure of FIG. 17d after partial removal of the sacrificial material (1714) to provide the recessed sacrificial material (1715). In one embodiment, the sacrificial material (1714) is recessed within the trenches (1712) using a wet etching or dry etching process. The recessed sacrificial material (1715) may be retained at this point to protect the metal layer below the via location (1722).

[0298] FIG. 17f illustrates the structure of FIG. 17e after the deposition of a non-conformal dielectric cap layer (1716), which may be referred to as a dielectric helmet. In one embodiment, the non-conformal dielectric cap layer (1716) is formed using a chemical vapor deposition (CVD) process such as physical vapor deposition (PVD), a selective growth process, or a plasma-enhanced CVD (PECVD) process. The non-conformal dielectric cap layer (1716) may be as previously described in relation to the non-conformal dielectric cap layer (1710). Alternatively, the non-conformal dielectric cap layer (1716) may comprise only upper portions (1716A), and, as depicted in FIG. 17f, essentially no portion of the non-conformal dielectric cap layer (1716) is formed in the trenches (1712).

[0299] FIG. 17g illustrates the structure of FIG. 17f after the manufacture of the second metal line. In one embodiment, the second metal lines (1724) (and, in some cases, associated conductive vias (1726)) are formed by performing a metal filling and polishing process after the removal of the reset sacrificial material (1715). The polishing process may be a CMP process.

[0300] FIG. 17h illustrates a structure of FIG. 17g after directed self-assembly (DSA) or selective growth to provide, for example, first and second alternating placeholder materials (1728 and 1730) (or, as described in relation to FIG. 16d, permanent materials).

[0301] FIG. 17i illustrates the structure of FIG. 17h after replacing the first and second alternating placeholder materials (1728 and 1730) with permanent first and second hardmask layers (1732 and 1734), respectively. The processing for FIG. 17h and FIG. 3i may be as described in relation to FIG. 16d.

[0302] FIG. 17j illustrates the structure of FIG. 17i after the next layer via patterning. An upper ILD layer (1736) is formed over the first and second hard mask layers (1732 and 1734). An opening (1738) is formed in the upper ILD layer (1736). In one embodiment, the opening (1738) is formed wider than the via feature size. Selected locations among the exposed first and second hard mask layers (1732 and 1734) are selected for selective removal, for example, by a selective etching process. In this case, the first hard mask (1732) region is selectively removed for the exposed portions of the second hard mask layer (1734). Conductive vias (1740) are subsequently formed in the opening (1738) and in the regions where the first hard mask (1732) region was removed. A conductive via (1740) contacts one of the first metal lines (1706). In one embodiment, the conductive via (1740) contacts one of the first metal lines (1706) without short-circuiting to one of the adjacent second metal lines (1724). In a specific embodiment, a portion (1742) of the conductive via (1740) is placed on a portion of the second hard mask layer (1734) without contacting the second metal line (1724) below, as depicted in FIG. 17j. In one embodiment, an improved short-circuit margin is then realized.

[0303] In one embodiment, as described in the above embodiment, a first hard mask (1732) region is removed for manufacturing a via (1740). In this case, forming an opening upon removal of the selected first hard mask (1732) region requires additional etching through the uppermost portion of the non-conformal dielectric cap layer (1716). However, in another embodiment, a second hard mask (1734) region is removed for manufacturing a via (1740). In this case, forming an opening upon removal of such selected second hard mask (1734) region directly exposes the metal line (1724) to which the via (1740) is connected.

[0304] Referring again to FIGS. 16p and FIGS. 17j, by cross-sectional analysis, a dielectric helmet may be visible across half of the metal groups. Additionally, hard masks of different materials are self-aligned to the dielectric helmet. Such structures may include one or more of conductive vias with improved short-circuit margins, alternating hard mask materials, and the presence of the dielectric helmet. The resulting structures, such as those described in relation to FIGS. 16p or FIGS. 17j, may subsequently be used as a basis for forming subsequent metal lines / vias and ILD layers. Alternatively, the structures of FIGS. 16p or FIGS. 17j may represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations may be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed.

[0305] According to one embodiment of the present disclosure, pattern accumulation layers for vias and plugs are described. One or more embodiments described herein relate to process schemes for via critical dimension (CD) control. The embodiments may include improvements related to via CD control, via CD uniformity, edge placement error (EPE), and via self-alignment. The embodiments may improve edge placement error (EPE) in semiconductor patterning of vias and enable self-alignment of multiple via lithography passes. In one embodiment, all via edges are defined by gratings instead of standard resist edges. A sacrificial grating is created under the via resist in the same direction as the metal on which the vias are landing. The vias are patterned with standard photoresist. However, during subsequent etchings through the sacrificial grating and the self-aligned via (SAV) metal grating (e.g., two intersecting gratings), all via edges are defined by the gratings. In one embodiment, variability from the via resist edge is not transferred to the substrate, and the resulting process capability enables better control of via CDs and improves yield and process capability.

[0306] To provide context for the embodiments described below, currently known solutions involve using resist edges to define via edges that determine the short-circuit margin for the metal below. However, standard via resist patterning is known to have much higher edge placement errors than grating patterning. In contrast, according to the embodiments described herein, using a sacrificial grating to define via edges improves control of via edges and significantly reduces the risk of short-circuiting to the wrong metal.

[0307] According to the embodiments described herein, a pattern accumulation flow for a plurality of via patterns having a sacrificial grating in a stack to define via edge post-etch is described. A "sieve" stack is constructed by coating a hard mask on a patterned upper metal (M1) interlayer dielectric layer where plugs already exist. The hard mask flattens the wafer for subsequent processing. The next layer formed can be used as an etch stop, followed by the formation of an accumulation layer. In this stage, the grating can be created at twice the pitch of the lower metal (M0) layer below and in the same direction as the M0 grating. This grating effectively blocks every other M0 line below and ultimately defines the critical dimension (CD) of the via post-etch. In one embodiment, since the grating is twice the pitch of the M0 below, a significant amount of hard mask (+ / - 20 nm) is included between the vias to account for the edge placement error (EPE) of the resist feature above.

[0308] Next, multiple via mask patterns are accumulated through the grating and on the accumulation layer. After accumulation, the grating is inverted without additional lithography to expose other underlying metal (M0) lines and protect the already created vias. A liner is added between the gratings to prevent vias on adjacent M0 lines from merging. The spacing between vias can be modulated using the thickness of the liner.

[0309] Finally, to complete the patterning in the accumulation of all derived vias, via patterns ranging from one mask to several via masks can be accumulated through an inverted grating. The grating is then removed, and the accumulated via pattern in the accumulation layer is etched through the upper metal (M1) hard mask grating into the interlayer dielectric below the M1 lines and down to M0 below. The stack on the M1 grating and the hard mask layer above it are removed. Subsequently, the trenches and vias are metallized and then polished. The result is very good CD control of the formed vias in both directions, and self-alignment of all vias relative to each other.

[0310] In one aspect, subsequently, one or more embodiments described herein relate to an approach utilizing a metal grating structure below or a pair of such orthogonal structures as a template for constructing conductive vias above. In an exemplary processing scheme, FIGS. 18a through 18w illustrate plan views (upper parts of the drawings) and corresponding inclined cross-sectional views (middle parts of the drawings) and cross-sectional views (lower parts of the drawings) illustrating various operations in metal via processing schemes for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure.

[0311] Referring to FIG. 18a, a starting structure (1800) is provided as a starting point for manufacturing a new metallization layer. The starting structure (1800) comprises an array of alternating metal lines (1802) and dielectric lines (1804). The metal lines (1802) have upper surfaces that are approximately coplanar with the upper surfaces of the dielectric lines (1804). As depicted in FIG. 18b, an etching stop layer (1806) is subsequently formed on the starting structure (1800).

[0312] Referring to FIG. 18c, an interlayer dielectric layer (1808) is formed on the structure of FIG. 18b. As depicted in FIG. 18d, a patterned hard mask (1810) is subsequently formed on the structure of FIG. 18c, and the pattern of the patterned hard mask (1810) is partially transferred to the interlayer dielectric layer (1808) to form a patterned interlayer dielectric layer (1812) in which metal line regions (1814) are formed internally. In one embodiment, the patterned hard mask (1810) has a grating-type pattern as depicted. In a specific embodiment, the patterned hard mask (1810) is composed of titanium nitride (TiN).

[0313] Referring to FIG. 18e, a hard mask layer (1816) is formed on the structure of FIG. 18d. In one embodiment, the bottom surface of the hard mask layer (1816) is conformal to the topography of the structure of FIG. 18d, while the top surface of the hard mask layer (1816) is flattened. In a specific embodiment, the hard mask layer (1816) is a carbon hard mask (CHM) layer. As depicted in FIG. 18f, an etching stop layer (1818) is subsequently formed on the structure of FIG. 18e. In a specific embodiment, the etching stop layer (1818) is composed of silicon oxide (SiOx or SiO2).

[0314] Referring to FIG. 18g, a pattern accumulation layer (1820) is subsequently formed on the structure of FIG. 18f. In one embodiment, the pattern accumulation layer (1820) is a layer on which more than one pattern is ultimately accumulated, for example, for final via patterning. In a specific embodiment, the pattern accumulation layer (1820) is composed of amorphous silicon (a-Si). As depicted in FIG. 18h, a patterned hard mask (1822) is subsequently formed on the structure of FIG. 18g. In one embodiment, the patterned hard mask (1822) has a grating-type pattern as depicted. In such an embodiment, the grating-type pattern is orthogonal to the grating of the patterned hard mask (1810) and parallel to the grating of the metal lines (1802). However, in one embodiment, from a top-down perspective, as depicted in FIG. 18h, the patterned hard mask (1822) exposes only one metal line (e.g., metal line (1802(A))) by skipping one of the metal lines (1802) and blocks the alternating metal lines (e.g., metal line (1802(B))) of the metal lines (1802). In a specific embodiment, the patterned hard mask (1822) is composed of silicon nitride (SiN).

[0315] Referring to FIG. 18i, a hard mask (1824) is subsequently formed on the structure of FIG. 18h. In a specific embodiment, the hard mask (1824) is a carbon hard mask (CHM). As depicted in FIG. 18j, the hard mask (1824) is subsequently patterned (e.g., by a lithography process using a single or multiple layer resist structures) and the pattern is transferred to portions of the pattern accumulation layer (1820) exposed by the patterned hard mask (1822) to form a once-patterned memory layer (1826). In one embodiment, the pattern is transferred to portions of the pattern accumulation layer (1820) by an etching process using an etching stop layer (1818) as an endpoint. In one embodiment, as also depicted in FIG. 18j, the hard mask (1824) is removed following the formation of the patterned memory layer (1826). It should be recognized that this process may be repeated for several different masking operations.

[0316] Referring to FIG. 18k, a blocking line (1828) is subsequently formed by filling an opening in the patterned hard mask (1822) of the structure of FIG. 18j with a blocking material layer. In a specific embodiment, the blocking material layer is a fluid silicon oxide material. In other embodiments, the blocking material layer is any of a number of other suitable materials. As depicted in FIG. 18l, the patterned hard mask (1822) is subsequently removed from the structure of FIG. 18k so that the blocking line (1828) remains.

[0317] Referring to FIG. 18m, an insulating spacer forming material layer (1830) is subsequently formed on the structure of FIG. 18l conformally with the blocking line (1828). In one embodiment, the insulating spacer forming material layer (1830) is composed of a dielectric material. In one embodiment, the spacer forming material layer (1830) is composed of silicon oxide (SiOx or SiO2). As depicted in FIG. 18n, the spacer forming material layer (1830) is subsequently patterned to form spacers (1832) adjacent to the sidewalls of the blocking line (1828). In one embodiment, the spacer forming material layer (1830) is patterned using an anisotropic dry etching process to form the spacers (1832).

[0318] Referring to FIG. 18o, a collective pattern of the protection regions of the patterning mask formed after the blocking lines (1828), spacers (1832), and spacers (1832) are formed to form a twice-patterned memory layer (1834) is subsequently transferred to a once-patterned memory layer (1826). In one embodiment, the pattern is transferred to the once-patterned memory layer (1826) by an etching process using an etching stop layer (1818) as an endpoint. As depicted in FIG. 18p, the blocking lines (1828), spacers (1832), and any additional mask material of the structure of FIG. 18o are subsequently removed to expose the twice-patterned memory layer (1834).

[0319] Referring to FIG. 18q, in order to form a patterned etching stop layer (1836) and to expose a portion of the hard mask layer (1816), the pattern of the double-patterned memory layer (1834) of the structure of FIG. 18p is subsequently transferred to the etching stop layer (1818). In one embodiment, the pattern of the double-patterned memory layer (1834) is transferred to the etching stop layer (1818) using a dry etching process. As depicted in FIG. 18r, the double-patterned memory layer (1834) of the structure of FIG. 18q is subsequently removed.

[0320] Referring to FIG. 18s, to form a patterned hard mask layer (1838), the pattern of the patterned etching stop layer (1836) of the structure of FIG. 18r is subsequently transferred to the hard mask layer (1816). The patterned hard mask layer (1838) exposes portions of the line regions (1814) of the patterned interlayer dielectric layer (1812) and portions of the patterned hard mask (1810). That is, although the patterned hard mask layer (1838) exposes areas wider than the line regions (1814) of the patterned interlayer dielectric layer (1812), the patterned hard mask (1810) protects the "exposed" areas of the patterned interlayer dielectric layer (1812) outside the line regions (1814). As depicted in FIG. 18t, in order to form a twice-patterned interlayer dielectric layer (1840) and to expose an etching stop layer (1806), the pattern of the patterned hard mask layer (1838) of the structure of FIG. 18s is subsequently transferred to the patterned interlayer dielectric layer (1812). However, in one embodiment, as also depicted in FIG. 18t, the patterned hard mask (1810) suppresses the total transfer pattern. In one embodiment, the pattern of the patterned hard mask layer (1838) is transferred to the patterned interlayer dielectric layer (1812) by an etching process using the etching stop layer (1806) as an endpoint.

[0321] Referring to FIG. 18u, exposed portions of the etching stop layer (1806) of the structure of FIG. 18t are removed to form a patterned etching stop layer (1842) and to expose via locations (1844) for metal lines (1802). As depicted in FIG. 18v, the patterned etching stop layer (1836), patterned hard mask layer (1838), and patterned hard mask (1810) of the structure of FIG. 18u are subsequently removed. This removal exposes the double-patterned interlayer dielectric layer (1840) and via locations (1844) for the metal lines (1802), as well as locations (1846) for the upper metal lines. In one embodiment, the patterned etching stop layer (1836), the patterned hard mask layer (1838), and the patterned hard mask (1810) are removed using an optional wet etching process.

[0322] Referring to FIG. 18w, an upper metallization layer is formed for the structure of FIG. 18v. Specifically, a metal filling process is performed to provide metal vias (1848) and metal lines (1850). In one embodiment, the metal filling process is performed using a subsequent planarization processing scheme, such as metal deposition and a chemical mechanical planarization (CMP) process. In one embodiment, the surface of the formed structure of FIG. 18w is substantially the same as, but orthogonal to, the surface of the starting structure (1800) of FIG. 18a. Thus, in one embodiment, the process described in relation to FIG. 18b through FIG. 18w may be repeated for the structure of FIG. 18w to form the next metallization layer, etc.

[0323] The resulting structure, such as that described in relation to FIG. 18w, can subsequently be used as a basis for forming subsequent metal line / via and ILD layers. Alternatively, the structure of FIG. 18w may represent a final metal interconnect layer in an integrated circuit. It should be recognized that the process operations may be carried out in alternative sequences, that not all operations need to be performed, and / or that additional process operations may be performed. It should also be recognized that the examples focus on via / contact formation. However, in other embodiments, similar approaches may be used to preserve or form regions (plugs) for line end terminations within the metal line layer.

[0324] According to one embodiment of the present disclosure, grid-based via and plug patterning approaches are described. One or more embodiments described herein relate to grid self-aligned and super self-aligned metal via processing schemes. The embodiments described herein may be implemented to provide a self-aligned methodology for metal / via layers. By implementing the approaches described herein, almost any plug and via geometry becomes possible. Additionally, the final via critical dimension (CD) may be independent of the lithography implemented for patterning. Furthermore, the approaches described herein may provide a "circular flow" in that the end of the process flow has the same or substantially the same layer stack and layout as the beginning of the process flow. Accordingly, once each operation in the process flow is performed, the process flow may be repeated as many times as necessary to add the required number of metal / via layers. In one or more embodiments, overlap between vertical grids is used to define the arrangement of vias and metal lines. The size of the via can be determined by the overlapping areas between the two grids.

[0325] To provide context for the embodiments described below, compared to currently known approaches for via self-alignment, the approaches described herein can provide almost any available plug and via placement. The approaches described herein may require fewer selective etchings. The approaches described herein can provide final plugs and via CDs independent of the lithography used. In one embodiment, subsequently, one or more embodiments described herein relate to an approach that utilizes a metal grating structure below as a template for constructing conductive vias above. It should be recognized that similar approaches may be implemented to manufacture non-conductive spaces or interruptions (plugs) between metals.

[0326] In an exemplary processing scheme, FIGS. 19a through 19l illustrate plan views (upper parts of the drawings) and corresponding inclined cross-sectional views (lower parts of the drawings) illustrating various operations in grid self-aligned metal via processing schemes for back-end-of-line (BEOL) interconnects according to one embodiment of the present disclosure. It should be recognized that, although not in reality, different metallization layers are depicted as separated (upper and lower) in the inclined cross-sectional views for clarity.

[0327] Referring to FIG. 19a, a starting point structure (1900) is provided as a starting point for manufacturing a new metallization layer. The starting point structure (1900) comprises an array of alternating metal lines (1902) and dielectric lines (1904). The metal lines (1902) are recessed under the dielectric lines (1904). A hard mask layer (1906) is placed alternately over the metal lines (1902) and the dielectric lines (1904). In one embodiment, the dielectric lines (1904) are composed of silicon nitride (SiN), and the hard mask layer (1906) is composed of silicon carbide (SiC) or silicon oxide (SiO2). As depicted in FIG. 19b, a next patterning layer (1908) is subsequently manufactured over the starting point structure (1900). In one embodiment, the next patterning layer (1908) comprises an etching stop layer (1910), a dielectric layer (1912), and a grating structure (1914). In one embodiment, the etching stop layer (1910) is composed of silicon oxide (SiO), the dielectric layer (1912) is composed of silicon nitride (SiN), and the grating structure (1914) is composed of silicon oxide (SiO). In one embodiment, the grating structure (1914) is formed using a pitch 2-part or pitch 4-part scheme, for example, by spacer patterning.

[0328] Referring to FIG. 19c, the pattern of the grating structure (1914) is transferred to the dielectric layer (1912) to form a patterned dielectric layer (1916). In one embodiment, the pattern of the grating structure (1914) is transferred to the dielectric layer (1912) using an etching process that utilizes the etching stop layer (1910) as the endpoint for the etching process. As illustrated in FIG. 19d, a breakthrough etch is subsequently performed to remove exposed portions of the etching stop layer (1910) to form a patterned etching stop layer (1918). In one embodiment, the breakthrough etch exposes all possible via locations (1920) that may potentially be formed in the structure (1900).

[0329] Referring to FIG. 19e, plug patterning is subsequently performed by forming a patterned hard mask (1922) on the structure of FIG. 19d at locations where plugs are to be preserved. As depicted in FIG. 19f, an integrated pattern of the patterned hard mask (1922) and the grating structure (1914) is subsequently transferred to the structure (1900) to form a structure (1900') having regions (1924) for forming metal lines within the structure (1900). In one embodiment, the integrated pattern of the patterned hard mask (1922) and the grating structure (1914) is transferred to the structure (1900) using an etching process. As also depicted in FIG. 19f, such an etching process can etch both layers (1904 and 1906) at substantially the same rate (or can be performed as several etching operations), and a cleaning process may follow to remove the patterned hard mask (1922).

[0330] Referring to FIG. 19g, via patterning is subsequently performed by forming a patterned lithography mask (1926) on the structure of FIG. 19f, and the patterned lithography mask (1926) exposes locations where vias are to be formed (e.g., via selection process). As depicted in FIG. 19h, the combined pattern of the patterned lithography mask (1926) and the grating structure (1914) is subsequently transferred to a structure (1900') to form a structure (1900) having regions (1928) for forming metal vias within the structure (1900'). In one embodiment, the combined pattern of the patterned lithography mask (1926) and the grating structure (1914) is transferred to the structure (1900') using an etching process. As also depicted in FIG. 19h, such an etching process may optionally etch the layer (1906) with respect to the layer (1904), and a cleaning process may follow to remove the patterned lithography mask (1926).

[0331] Referring to FIG. 19i, a metal filling process is performed on the structure of FIG. 19i to provide a structure (1930) below. The metal filling process forms metal vias (1932) and metal lines (1934) in the structure (1930). As depicted in FIG. 19i, the metal filling process may also fill the areas between the grating structures (1914) with metal lines (1936). In one embodiment, the metal filling process is performed using a metal deposition and subsequent flattening processing scheme. As depicted in FIG. 19j, the structure of FIG. 19i may subsequently be reduced in thickness to remove the grating structures (1914), to expose the patterned dielectric (1916), and to provide metal lines (1938) with reduced thickness from the metal lines (1936). In one embodiment, the thickness of the structure of FIG. 19i can then be reduced using a planarization process such as a chemical mechanical planarization (CMP) process.

[0332] Referring to FIG. 19k, metal lines (1938) are removed from the structure of FIG. 19j, leaving a patterned dielectric layer (1916) and a patterned etching stop layer (1918). The metal lines (1938) may be removed by an optional etching process that also ensures that the metal lines (1938) are removed and that the metal is not left at any height above the material layers (1904 and 1906) (i.e., that the metal is not left above the plug regions of the structure (1930). As depicted in FIG. 19l, a hard mask layer (1940) is subsequently formed between the lines of the patterned dielectric layer (1916) on the structure of FIG. 19k. In one embodiment, the hard mask layer (1940) is composed of silicon carbide (SiC) or silicon oxide (SiO2) and is formed using a deposition and flattening processing scheme. In one embodiment, the hard mask layer (1940) is composed of the same material as the hard mask layer (1906). In one embodiment, the surface of the structure formed by the patterned dielectric layer (1916) and the hard mask layer (1940) is substantially the same as the surface of the starting structure (1900) of FIG. 19a, but orthogonal to it. Thus, in one embodiment, the process described in relation to FIG. 19b through FIG. 19l can be repeated for the structure of FIG. 19l to form the next metallization layer, etc.

[0333] It should be recognized that the process described in relation to FIG. 19b through 19l, as repeated for the structure of FIG. 19l to form the next metallization layer, may be referred to as a cyclic flow in that the end of the process flow has the same or substantially the same layer stack and layout as the beginning of the process flow. In one embodiment, forming an additional metallization layer involves using such a cyclic flow. However, it should also be recognized that the cyclic or iterative flow may be implemented only for selected metallization layers. Other metallization layers in the resulting stack (e.g., layers above, below, or between layers manufactured using the processing scheme of FIG. 19b through 19l) may be manufactured using conventional dual damascene or other approaches.

[0334] The resulting structure described in relation to FIG. 19l can subsequently be used as a basis for forming subsequent metal line / via and ILD layers. Alternatively, the structure of FIG. 19l can represent a final metal interconnect layer in an integrated circuit. It should also be recognized that in subsequent fabrication operations, dielectric lines may be removed to provide air gaps between the resulting metal lines. It should be recognized that the above examples focus on via / contact formation. However, in other embodiments, similar approaches may be used to preserve or form regions (plugs) for line end terminations within the metal line layer.

[0335] According to one embodiment of the present disclosure, grating-based via and plug patterning is described. One or more embodiments described herein relate to grating-based plugs and cuts for forming feature ends. The embodiments may involve one or more of lithographic patterning, associated line end CD generation, and spacer-based patterning. The embodiments utilize methods for generating plugs and cuts having placement control and uniformity of one-dimensional (1D) features. It should be recognized that there is a trade-off between better control over line ends (plugs) or via placements in the sense that vias and line ends are placed at more restricted locations.

[0336] To provide context for the embodiments described herein, grating and plug or grating and cut approaches are being applied to more layers to enable the patterning of denser pitch features in semiconductor manufacturing. As feature dimensions continue to shrink, the ability to robustly pattern cuts and plugs can limit scaling and yield. Cut and plug features are generally defined directly by lithographic operations primarily on two-dimensional (2D) features. Such 2D features have much higher variability and non-uniformity than one-dimensional (1D) features.

[0337] With reference to FIGS. 20a through 20g described below, in one embodiment, an overview of a simplified patterning process for creating grating-defined plugs is presented. A sacrificial 1D pattern orthogonal to the primary direction of the layer being patterned is created. A selection mask is then used to cut or keep portions of the 1D pattern that will ultimately be used to cut or keep portions of the primary grating. The final edges of the cut / keep on the primary pattern are thus defined by the edges of the 1D sacrificial grating, having much better control and uniformity. FIGS. 20a through 20g illustrate plan views (top) and corresponding cross-sectional views (middle and bottom) illustrating various operations in a method for manufacturing grating-based plugs and cuts for forming feature ends for back end of line (BEOL) interconnects according to one embodiment of the present disclosure.

[0338] Referring to FIG. 20a, a starting point structure (2000) is provided as a starting point for manufacturing a new metallization layer. The starting point structure (2000) comprises an interlayer dielectric (ILD) material layer (2002) on which a first hard mask layer (2004) is formed. A second hard mask layer (2006) is formed on the first hard mask layer (2004). The second hard mask layer (2006) has a grating pattern, which can be viewed as a one-dimensional (1D) grating pattern. In one embodiment, the grating pattern of the second hard mask (2006) is ultimately used to define 1D locations of the final layer to be patterned, but the ends of the feature locations are not yet patterned thereon. The first hard mask layer (2004) and / or the second hard mask layer (2006) may be made of a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO2), titanium nitride (TiN), or silicon (Si). In one embodiment, the first hard mask layer (2004) and the second hard mask layer (2006) are made of different materials.

[0339] Referring to FIG. 20b, a third hard mask layer (2008) is formed on the structure of FIG. 20a. In one embodiment, the third hard mask layer (2008) has a grating pattern that can be viewed as a primarily one-dimensional (1D) grating pattern orthogonal to the 1D grating pattern of the second hard mask layer (2006). The third hard mask layer (2008) may be made of a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO2), titanium nitride (TiN), or silicon (Si). In one embodiment, the third hard mask layer (2008) is made of a material different from the materials of the first hard mask layer (2004) and the second hard mask layer (2006). It should be recognized that any of the hard mask layers described above may actually comprise a plurality of sublayers, for example, to provide improved etching selectivity.

[0340] In one embodiment, the grating pattern of the third hard mask layer (2008) and the grating pattern of the second hard mask layer (2006) together define all allowable line end positions for the metal line metallization layer. In such an embodiment, the grating pattern of the third hard mask layer (2008) and the grating pattern of the second hard mask layer (2006) together define line end positions at locations where the lines of the grating patterns overlap. In another such embodiment, the grating pattern of the third hard mask layer (2008) and the grating pattern of the second hard mask layer (2006) together define line end positions at locations where the spaces between the lines of the grating patterns are exposed.

[0341] Referring to FIG. 20c, regions of a lithography patterning mask (2010) are formed on the structure of FIG. 20b. The regions of the lithography patterning mask (2010) may be formed of a photoresist layer or layers, or a similar lithography patterning mask. In one embodiment, the regions of the lithography patterning mask (2010) provide a pattern of cutting / holding regions on a sacrificial grating formed of a second hard mask layer (2006) and a third hard mask layer (2008). In one embodiment, a lithography process is subsequently used to select (cutting or holding) portions of the sacrificial grating that will finally define the end positions of the primary pattern of metal lines. In such an embodiment, 193 nm or EUV lithography is used with the etching transfer of the resist pattern to the underlying layers before etching the sacrificial grating pattern. In one embodiment, the lithography process involves multiple exposures or depositi...

Claims

Claim 1 A method for manufacturing an integrated circuit structure, comprising: forming a plurality of backbone features on a substrate; forming a first spacer set along the sidewalls of each of the plurality of backbone features, wherein the first spacer set has a first material composition different from the material composition of the plurality of backbone features; forming a second spacer set along the sidewalls of each spacer of the first spacer set, wherein the second spacer set has a second material composition different from the first material composition and different from the material composition of the plurality of backbone features; forming a third spacer set along the sidewalls of each spacer of the second spacer set, wherein the third spacer set has a third material composition different from the first material composition, different from the second material composition, and different from the material composition of the plurality of backbone features; and forming a fourth spacer set along the sidewalls of each spacer of the third spacer set, wherein the fourth spacer set is the second material having a composition -; forming a fifth spacer set laterally adjacent to the sidewalls of each spacer of the fourth spacer set - the fifth spacer set has the first material composition -; removing the plurality of backbone features after forming the fifth spacer set; forming a sixth spacer set along the sidewalls of each spacer of the first spacer set and along the sidewalls of each spacer of the fifth spacer set after removing the plurality of backbone features - the sixth spacer set has the second material composition -; forming a final feature in each opening between adjacent pairs of spacers in the sixth spacer set; flattening the first spacer set, the second spacer set, the third spacer set, the fourth spacer set, the fifth spacer set, the sixth spacer set, and the final features to form a target base layer;A method comprising the step of forming a metallized layer of a semiconductor structure using the target base layer. Claim 2 A method according to claim 1, wherein the step of forming the plurality of backbone features includes the step of using a standard lithography operation. Claim 3 A method according to claim 1, wherein the step of forming the plurality of backbone features comprises the step of forming the plurality of features including a material selected from the group consisting of silicon nitride, silicon oxide, and silicon carbide. Claim 4 The method of claim 1, wherein the step of forming the first spacer set comprises: the step of depositing the material of the first spacer set conformally with the plurality of backbone features using an atomic layer deposition (ALD) process; and the step of anisotropically etching the material of the first spacer set to form the first spacer set along the sidewalls of each of the plurality of backbone features. Claim 5 A method according to claim 1, wherein the step of forming the first spacer set comprises the step of selectively growing the material of the first spacer set along the sidewalls of each of the plurality of backbone features. Claim 6 A method according to claim 1, wherein each final feature has a lateral width greater than the lateral width of each spacer from the first spacer set, the second spacer set, the third spacer set, the fourth spacer set, the fifth spacer set, and the sixth spacer set. Claim 7 A method according to claim 1, wherein each final feature is formed by the merging of material growth formed along adjacent pairs of spacers of the sixth spacer set. Claim 8 A method according to claim 1, wherein each final feature comprises the third material composition. Claim 9 The method of claim 1, wherein the step of forming a metallized layer of the semiconductor structure using the target base layer comprises: removing all portions of the first material composition to form a first plurality of trenches; and forming a first plurality of conductive lines in the first plurality of trenches. Claim 10 In claim 9, the step of forming a metallized layer of the semiconductor structure using the target base layer comprises: removing all portions of the third material composition to form a second plurality of trenches; and forming a second plurality of conductive lines in the second plurality of trenches. Claim 11 A method according to claim 10, wherein the first plurality of conductive lines and the second plurality of conductive lines have the same composition. Claim 12 A method according to claim 10, wherein the first plurality of conductive lines and the second plurality of conductive lines have different compositions. Claim 13 A method according to claim 1, further comprising the step of forming an additional 20 to 200 sets of spacers between the step of forming the fifth set of spacers and the step of forming the sixth set of spacers, and before removing the plurality of backbone features. Claim 14 As a target structure for manufacturing an integrated circuit structure, a first spacer set located on a hard mask layer on a substrate - said first spacer set has a first material composition -; a second spacer set located along the outer sidewalls of each spacer of said first spacer set - said second spacer set has a second material composition different from said first material composition -; a third spacer set located along the sidewalls of each spacer of said second spacer set - said third spacer set has a third material composition different from said first material composition and different from said second material composition -; a fourth spacer set located along the sidewalls of each spacer of said third spacer set - said fourth spacer set has said second material composition -; a fifth spacer set laterally adjacent to the sidewalls of each spacer of said fourth spacer set - said fifth spacer set has said first material composition -; said A target structure comprising: a sixth spacer set along the inner sidewalls of each spacer of the first spacer set and along the sidewalls of each spacer of the fifth spacer set—the sixth spacer set having the second material composition—; and a final feature within each opening between adjacent pairs of spacers of the sixth spacer set, wherein each final feature has a lateral width greater than the lateral width of each spacer from the first spacer set, the second spacer set, the third spacer set, the fourth spacer set, the fifth spacer set, and the sixth spacer set. Claim 15 In paragraph 14, the first spacer set, the second spacer set, the third spacer set, the fourth spacer set, the fifth spacer set, the sixth spacer set, and the final features are substantially coplanar with each other, a target structure. Claim 16 delete Claim 17 In claim 14, the target structure, wherein the lateral width of each final feature is in the range of 6 to 12 nanometers. Claim 18 As a target structure for manufacturing an integrated circuit structure, a first spacer set located on a hard mask layer on a substrate - said first spacer set has a first material composition -; a second spacer set located along the outer sidewalls of each spacer of said first spacer set - said second spacer set has a second material composition different from said first material composition -; a third spacer set located along the sidewalls of each spacer of said second spacer set - said third spacer set has a third material composition different from said first material composition and different from said second material composition -; a fourth spacer set located along the sidewalls of each spacer of said third spacer set - said fourth spacer set has said second material composition -; a fifth spacer set laterally adjacent to the sidewalls of each spacer of said fourth spacer set - said fifth spacer set has said first material composition -; said A target structure comprising: a sixth spacer set along the inner sidewalls of each spacer of the first spacer set and along the sidewalls of each spacer of the fifth spacer set—the sixth spacer set having the second material composition—; and a final feature within each opening between adjacent pairs of spacers of the sixth spacer set, wherein each final feature has a centering seam within the final feature. Claim 19 In paragraph 14, each final feature is a target structure comprising the above-mentioned third material composition.

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