Storage device for high speed link startup and storage system including the same

Abstract

A storage device performing a high-speed link startup and a storage system including the same are disclosed. After the initialization operation is completed, the storage device transmits a high-speed link up to a host via a connected transmission lane. Based on the high-speed link up of the storage device, the storage device and the host perform a link startup sequence in high-speed mode. The host initializes in high-speed mode and waits for the high-speed link up to be received from the storage device within a set time from the release of the reset signal. The high-speed link up of the storage device is transmitted to the host using the length of the activation interval of the connected transmission lane, the length of the line-reset interval, or a high-speed link startup primitive.

Description

Technology Field

[0001] The present invention relates to apparatuses and methods, and more specifically, to a storage device for performing high-speed link startup and a storage system including the same. Background Technology

[0002] A storage system includes a host and a storage device. The host and the storage device are connected via various standard interfaces such as UFS (Universal Flash Storage), SATA (Serial ATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), and eMMC (embedded Multi-Media Card). When a storage system is used in a mobile device, high-speed operation between the host and the storage device is critical, and rapid link startup between the host and the storage device is required. The problem to be solved

[0003] The objective of the present invention is to provide a storage device capable of performing link startup in high-speed mode between a storage device and a host, and a storage system including the same. means of solving the problem

[0004] A link startup method between a host and a storage device connected through at least one lane according to embodiments of the present invention comprises: performing an initialization operation on the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the at least one lane; transmitting a high-speed link up to the host through the connected transmission lane of the storage device; and performing a link startup in high-speed mode through the connected transmission lane of the storage device and the connected reception lane of the host based on the high-speed link up of the storage device.

[0005] A link startup method between a host and a storage device connected through at least one lane according to embodiments of the present invention comprises: initializing the host in a high-speed mode; establishing data communication through a connected transmission lane and a connected reception lane among the at least one lanes; determining whether a high-speed link up is received from the storage device through the connected reception lane of the host; recognizing the connected reception lane through which the high-speed link up is received from the storage device as a result of the determination; and, as the connected reception lane through which the high-speed link up is received is recognized, performing a link startup in a high-speed mode through the connected transmission lane of the storage device and the connected reception lane of the host.

[0006] A storage device according to embodiments of the present invention comprises an interconnect unit including at least one receiver and at least one transmitter, wherein the interconnect unit communicates data through a transmitting lane and a receiving lane among at least one lane connected between a host device and the storage device; a non-volatile memory; and a storage controller that controls the non-volatile memory, wherein the storage controller is configured such that the at least one transmitter transmits a high-speed link-up to the host device through the transmitting lane, and if a low-speed link-up is not received from the host device through the receiving lane within a set time from the transmission of the high-speed link-up, the storage controller is configured to perform a link startup in a high-speed mode through the transmitting lane and the receiving lane based on the high-speed link-up.

[0007] A host device according to embodiments of the present invention includes an interconnect unit comprising at least one receiver and at least one transmitter, wherein the interconnect unit communicates data through a transmitting lane and a receiving lane among at least one lane connected between the host device and a storage device; and the host device is configured to determine whether the at least one receiver receives a high-speed link-up from the storage device through the receiving lane, and, as a result of the determination, when the high-speed link-up is received from the storage device, to perform a link startup in high-speed mode through the receiving lane and the transmitting lane. Effects of the invention

[0008] According to embodiments of the present invention, by transmitting a high-speed link-up through a connected transmission lane after the initialization operation is completed in the storage device, the storage device can be linked up quickly with the host without waiting for the high-speed link-up of the host and without the host retrying operation, thereby improving the performance of the storage system. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a storage system according to embodiments of the present invention. Figure 2 is a diagram illustrating the interface between the host and the storage device of Figure 1. Figure 3 is a diagram illustrating the line state of Figure 2. FIG. 4 is a diagram illustrating high-speed link-up by a storage device according to embodiments of the present invention. Figure 5 is a diagram illustrating a high-speed link-up by a host as a comparative example of Figure 4. FIG. 6 is a flowchart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 7 is a chart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 8 is a flowchart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 9 is a flowchart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 10 is a flowchart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 11 is a chart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 12 is a flowchart illustrating a link startup sequence according to embodiments of the present invention. FIG. 13 is a drawing illustrating a system to which a storage device according to one embodiment of the present invention is applied. FIG. 14 is a drawing for explaining a UFS system according to one embodiment of the present invention. FIGS. 15a to 15c are drawings for explaining the form factor of a UFS card. FIG. 16 is a block diagram showing a non-volatile storage according to one embodiment of the present invention. FIG. 17 is a block diagram showing a non-volatile storage according to one embodiment of the present invention. FIG. 18 is an exemplary block diagram showing the memory device of FIG. 17. FIG. 19 is a drawing for explaining a 3D V-NAND structure that can be applied to a UFS device according to one embodiment of the present invention. FIG. 20 is a drawing for explaining a BVNAND structure that can be applied to a UFS device according to one embodiment of the present invention. Specific details for implementing the invention

[0010] FIG. 1 is a block diagram showing a storage system according to embodiments of the present invention.

[0011] Referring to FIG. 1, the storage system (10) may include a host (20) and a storage device (30). The host (20) and the storage device (30) may be connected according to an interface protocol defined in the Universal Flash Storage (UFS) specification, and accordingly, the storage device (30) may be a UFS storage device and the host (20) may be a UFS host. However, the present invention is not limited thereto, and the storage device (30) and the host (20) may be connected according to various standard interfaces.

[0012] The host (20) can control data processing operations for the storage device (30), such as data reading operations or data writing operations. The host (20) may refer to a data processing device capable of processing data, such as a CPU (Central Processing Unit), a processor, a microprocessor, or an application processor (AP). The host (20) may execute an operating system (OS) and / or various applications. In one embodiment, the storage system (10) may be included in a mobile device, and the host (20) may be implemented as an application processor (AP). In one embodiment, the host (20) may be implemented as a System-On-a-Chip (SoC) and, accordingly, embedded in an electronic device.

[0013] In this embodiment, a number of conceptual hardware configurations included in the host (20) and the storage device (30) are illustrated, but are not limited thereto and other configurations are also possible. The host (20) may include an interconnect section (22) and a host controller (24). The interconnect section (22) may provide an interface (40) between the host (20) and the storage device (30). The interconnect section (22) may include a physical layer and a link layer. The physical layer of the interconnect section (22) may include physical configurations for exchanging data with the storage device (30), and may include at least one transmitter (TX) and at least one receiver (RX), etc. The interconnect section (22) of the host (20) may include, for example, four transmitters (TX1-TX4) and four receivers (RX1-RX4). The link layer of the interconnect section (22) can manage the transmission and / or composition of data, and can also manage the integrity and error of the data.

[0014] The storage device (30) may include an interconnect section (32), a storage controller (34), and a non-volatile memory (36). The storage controller (34) may control the non-volatile memory (36) to write data to the non-volatile memory (36) in response to a write request from the host (20), or control the non-volatile memory (36) to read data stored in the non-volatile memory (36) in response to a read request from the host (20).

[0015] The interconnect section (32) may provide an interface (40) between the storage device (30) and the host (20). For example, the interconnect section (32) may include a physical layer and a link layer. The physical layer of the interconnect section (32) may include physical configurations for exchanging data with the host (20), and may include at least one receiver (RX) and at least one transmitter (TX), etc. The interconnect section (32) of the storage device (30) may include, for example, four receivers (RX1-RX4) and four transmitters (TX1-TX4). The link layer of the interconnect section (32) may manage the transmission and / or combination of data, and may also manage data integrity and errors.

[0016] In one embodiment, when the storage system (10) is a mobile device, the physical layers of the interconnect sections (22, 32) may be defined by the "M-PHY" specification, and the link layers may be defined by the "UniPro" specification. M-PHY and UniPro are interface protocols proposed by the MIPI (Mobile Industry Processor Interface) Alliance. The link layers of the interconnect sections (22, 32) may each include a Physical Adapted Layer, which can control the physical layers, such as managing data symbols or managing power.

[0017] A transmitter (TX) included in the interconnect section (22) of the host (20) and a receiver (RX) included in the interconnect section (32) of the storage device (30) can form a single lane, as shown in FIG. 2. Additionally, a transmitter (TX) included in the interconnect section (32) of the storage device (30) and a receiver (RX) included in the interconnect section (22) of the host (20) can also form a single lane. In this embodiment, the number of transmitters (TX1-TX4) and receivers (RX1-RX4) included in the interconnect section (22) of the host (20) is shown to be the same as the number of receivers (RX1-RX4) and transmitters (TX1-TX4) included in the interconnect section (32) of the storage device (30). According to exemplary embodiments, the number of transmitters (TX) and receivers (RX) included in the interconnect section (22) of the host (20) may differ from the number of transmitters (TX) and receivers (RX) included in the interconnect section (32) of the storage device (30). Additionally, the capability of the host (20) may differ from the capability of the storage device (30).

[0018] The host (20) and the storage device (30) can perform processing, such as link startup, to recognize physically connected lanes and receive information from the other device. The host (20) and the storage device (30) can perform a link startup sequence before exchanging data. By performing the link startup sequence, the host (20) and the storage device (30) can exchange and recognize information regarding the number of transmitters (TX) and receivers (RX), information regarding physically connected lanes, and information regarding the performance of the other device. After the link startup sequence is completed, the host (20) and the storage device (30) can be set to a linkup state in which they can reliably exchange data with each other.

[0019] The link startup sequence may be performed during the initialization operation performed when the storage system (10) is first used, or during the booting operation of the storage system (10). Furthermore, the link startup sequence may also be performed during the recovery operation for errors in the link-up state. Since the link startup sequence requires the exchange of a large amount of information regarding the host (20) and the storage device (30), it may take a long time to perform the link startup sequence. Moreover, if the link startup sequence is performed in a low-speed mode between the host (20) and the storage device (30), the time required for the link startup operation may be even longer. To reduce the link startup time, the host (20) may perform the link startup operation in a high-speed mode.

[0020] Meanwhile, the host (20) can transmit a high-speed link startup to the storage device (30) when the storage device (30) is not ready to perform a link startup. In this case, the host (20) does not receive a link startup reception response from the storage device (30) and performs a retry operation to retry the high-speed link startup. The link startup time may be prolonged due to the retry operation of the host (20). Accordingly, if the high-speed link startup can be transmitted after the initialization operation is completed at the storage device (30), and if such a facility is possible, the storage device (30) can perform the high-speed link startup without waiting for the high-speed link startup of the host (20), and the host (20) can perform the high-speed link startup without a retry operation, which would be beneficial for reducing the link startup time.

[0021] The storage controller (34) can perform data communication through the connected transmission lane and the connected reception lane among the multiple lanes included in the interconnect section (32). The storage controller (34) can control the transmission of high-speed link up to the host (20) by issuing an activation section or an activation section and a line reset section through the connected transmission lane. Accordingly, the storage device (30) can perform link startup with the host (20) in high-speed mode.

[0022] The host controller (24) can control data communication to be performed through a connected transmission lane and a connected reception lane among a plurality of lanes included in the interconnect section (22). The host controller (24) can control the host (20) to perform high-speed link startup by receiving an activation section or receiving an activation section and a line reset section through the connected reception lane. Accordingly, the host (20) can perform link startup with the storage device (30) in high-speed mode.

[0023] The non-volatile memory (36) may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. In one embodiment, the plurality of memory cells may be NAND flash memory cells. However, the present invention is not limited thereto, and in other embodiments, the plurality of memory cells may be resistive memory cells such as ReRAM (resistive RAM), PRAM (phase change RAM), or MRAM (magnetic RAM).

[0024] In some embodiments, the storage device (30) may be implemented as a DRAM-less device, and a DRAM-less device may refer to a device that does not include a DRAM cache. In this case, the storage controller (34) may not include a DRAM controller. For example, the storage device (30) may use a portion of the non-volatile memory (36) as a buffer memory.

[0025] In some embodiments, the storage device (30) may be an internal memory embedded in an electronic device. For example, the storage device (30) may be an embedded Universal Flash Storage (UFS) memory device, an embedded Multi-Media Card (eMMC), or a Solid State Drive (SSD). However, the present invention is not limited thereto, and the storage device (30) may be a non-volatile memory (e.g., One Time Programmable ROM (OTPROM), Programmable ROM (PROM), Erasable and Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Mask ROM, Flash ROM, etc.). In some embodiments, the storage device (30) may be an external memory that is detachable from the electronic device. For example, the storage device (30) may include at least one of a UFS memory card, CF (Compact Flash), SD (Secure Digital), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (extreme Digital) and Memory Stick.

[0026] The storage system (10) can be implemented as an electronic device such as, for example, a PC (personal computer), a laptop computer, a mobile phone, a smartphone, a tablet PC, a PDA (personal digital assistant), an EDA (enterprise digital assistant), a digital still camera, a digital video camera, an audio device, a PMP (portable multimedia player), a PND (personal navigation device or portable navigation device), an MP3 player, a handheld game console, or an e-book. Additionally, the storage system (10) can be implemented as various types of electronic devices such as a wristwatch or a wearable device such as an HMD (Head-Mounted Display).

[0027] FIG. 2 is a diagram illustrating an interface (40) between a host (20) and a storage device (30) of FIG. 1. Concepts of LANE, LINE, and LINK are explained in the interface (40) of FIG. 2. Hereinafter, for convenience of explanation, among the plurality of transmitters and receivers included in the interconnect parts (22, 32) of FIG. 1, the transmitter (TX1) of the interconnect part (32) of the storage device (30) and the receiver (RX1) of the interconnect part (22) of the host (20) are described as representative.

[0028] Referring to FIG. 2, the interface (40) may support multiple lanes (LANEs). Each lane (LANE) is a unidirectional, single-signal, information-carrying transmission channel. A lane (LANE) may consist of a transmitter (TX1), a receiver (RX1), and a line connecting the transmitter (TX1) and the receiver (RX1) point-to-point. The transmitter (TX1) or the receiver (RX1) has a single differential output or input line interface corresponding to two signaling pins (PINs). The pins (PINs) are individually labeled with DP, representing the positive node of the differential signal, and DN, representing the negative node of the differential signal. The DP and DN of the pins (PINs) may each be labeled with an optional prefix TX or RX to indicate that they are the transmitter (TX1) pin or the receiver (RX1) pin. The line consists of two differentially routed wires connecting the PINs of the transmitter (TX1) and the receiver (RX1). These wires are the transmission lines.

[0029] The interface (40) includes at least one lane (LANE) in each direction. The number of lanes (LANEs) in each direction does not need to be symmetrical. The link may include one or more lanes (LANEs) in each direction and lane management units (21, 32) that provide bidirectional data transmission functions. Although FIG. 2 is illustrated as having lane management units (21, 32) and controllers (24, 34) separated individually, it is not limited thereto, and lane management units (21, 32) may be included in the controllers (24, 34).

[0030] Figure 3 is a diagram illustrating the state of the line in Figure 2.

[0031] Referring to FIGS. 2 and 3, the line may have a DIF-Z state with a near-zero differential line voltage, a DIF-N state with a negative differential line voltage, or a DIF-P state with a positive differential line voltage. Alternatively, although not shown in FIG. 3, the line may have a DIF-Q state indicating a high impedance state, or a DIF-X state that is neither DIF-N nor DIF-P. Here, the differential line voltage may be defined as the value obtained by subtracting the voltage of the line connected to the negative node from the voltage of the line connected to the positive node.

[0032] In the line (LINE) between the transmitter (TX1) and the receiver (RX1), while the transmitter (TX1) is in a hibernation state (hereinafter referred to as "HIBERN8 state"), which is an ultra-low power power-saving state, the receiver (RX1) can maintain the line (LINE) in the DIF-Z state. During the DIF-Z state from time T1 to time T2, the line (LINE) is in the HIBERN8 state. The time between time T1 and time T2 is the hibernation interval (T HIBERN8 It is called ).

[0033] At time T2, the transmitter (TX1) may transition the line (LINE) to the DIF-N state to signal the escape from the HIBERN8 state. At this time, the receiver (RX1) detects the DIF-N state of the line (LINE) and recognizes that the link between both the transmitter (TX1) and the receiver (RX1) will be ready for use and will have the escaped HIBERN8 state. The time between time T2 and time T3, when the line is in the DIF-N state, is the activation interval (T ACTIVATE It is referred to as ). In one embodiment, the activation section (T ACTIVATE The length of ) may be less than approximately 0.9ms. In another embodiment, the activation interval (T ACTIVATE The length of ) can be less than about 1.6ms.

[0034] For example, the activation section (T) of the line ACTIVATE If the length of ) is less than 0.9ms, the transmitter (TX1) and receiver (RX1) can enter high-speed mode (HS-MODE). The activation period (T) of the line (LINE) ACTIVATE If the length of ) is 0.9ms or longer, the transmitter (TX1) and receiver (RX1) can enter low-speed mode (LS-MODE). Low-speed mode (LS-MODE) can correspond to Pulse Width Modulation (PWM) mode.

[0035] At time T3, the transmitter (TX1) may transition the line (LINE) to the DIF-P state to signal a line reset. At this time, the receiver (RX1) detects the DIF-P state of the line (LINE) and recognizes that both the transmitter (TX1) and the receiver (RX1) will prepare for and perform a line reset. The time between time T3 and time T4, when the line (LINE) is in the DIF-P state, is the line-reset interval (T LINE-RESET It is referred to as ). In one embodiment, the line-reset interval (T LINE-RESET The length of ) can be approximately 3.1ms or longer.

[0036] FIG. 4 is a diagram illustrating high-speed link-up by a storage device (30) according to embodiments of the present invention.

[0037] Referring to FIG. 4, the storage device (30) can perform an initialization operation (400) when power-up is detected during the booting of the storage system (10). The initialization operation of the storage device (30) may include an operation of reading initialization information stored in the non-volatile memory (36) built into the storage device (30) and setting it in a setting register. For example, the initialization information may include protection information regarding whether to prohibit programming / erasing, trimming data for trimming the operating voltage level in the operating mode, column repair information for rescuing failed bit lines, and bad block information including bad memory cells. The trimming data is data for setting voltage adjustments in the operating modes of the non-volatile memory (36), namely, read operation, program operation, and erase operation, as well as adjustments of the sense amplifier or page buffer or optimization of the reference cell.

[0038] After completing the initialization operation (400), the storage device (30) may transmit a line reset (410) to the host (20). The storage device (30) may generate a line reset (410), reset the transmitters (TXs) of the connected lanes, and transmit information to the host (20) indicating that the transmitters (TXs) have been reset. The host (20) may receive the line reset (412), reset the receivers (RXs) of the connected lanes, and transmit information to the storage device (30) indicating that the receivers (RXs) have been reset. The line reset (410, 412) may be configured to reset or clear all attributes of the physical layers of the interconnect parts (32, 22) to their default values. The storage device (30) and the host (20) may exchange line reset information with each other.

[0039] After performing a line reset (410), the storage device (30) can transmit a high-speed link up (420) to the host (20). The host (20) receives the high-speed link up (422) and can perform a link startup sequence in high-speed mode, including the exchange of trigger events, performance information, and control frames with the storage device (30). The link startup sequence will be described later with reference to FIG. 11.

[0040] When high-speed link-up is performed by the storage device (30), the link startup time (TLS1) between the storage device (30) and the host (20) is from the start of the line reset (410) of the storage device (30) to the end of the high-speed link-up (422) of the host (20). It can be seen that the link startup time (TLS1) by the storage device (30) is a relatively short time compared to the link startup time (TLS2) by the host (20) in FIG. 5. The link-up between the host (20) and the storage device (30) by the host (20) may take a relatively long time, as shown in FIG. 5.

[0041] FIG. 5 is a drawing illustrating a high-speed link-up by a host (20) as a comparative example of FIG. 4.

[0042] Referring to FIG. 5, the host (20) can generate a first line reset (510), reset the transmitters (TXs) of the connected lanes, and transmit information indicating that the transmitters (TXs) have been reset to the storage device (30). After performing the first line reset (510), the host (20) can transmit a first high-speed link up (520) to the storage device (30). After transmitting the first high-speed link up (520), the host (20) can expect to perform a link startup sequence with the storage device (30) in high-speed mode. However, while the host (20) transmits the first line reset (510) and the first high-speed link up (520) to the storage device (30), the storage device (30) may be performing an initialization operation (500). That is, the host (20) may attempt a first line reset (510) and a first high-speed link up (520) while not knowing whether the storage device (30) has completed the initialization operation (500) and / or while the storage device (30) is not ready to perform a link startup operation.

[0043] After the host (20) transmits the first high-speed link up (520), if the timeout period (TTIMEOUT) during which the link startup operation with the storage device (30) is not performed is exceeded, the host (20) may perform a retry operation by transmitting the second line reset (530) and the second high-speed link up (540). The storage device (30) receives the second line reset (532) and the second high-speed link up (542) and may perform a link startup sequence including the exchange of trigger events, performance information exchange, and control frame exchange with the host (20) in high-speed mode.

[0044] When high-speed link-up is performed by the host (20), the link startup time (TLS2) between the host (20) and the storage device (30) is from the time of the first line reset (510) of the host (20) to the time of the end of the second high-speed link-up (542) of the storage device (30). It can be seen that the link startup time (TLS2) by the host (20) is a relatively long time compared to the link startup time (TLS1) by the storage device (30) of FIG. 4.

[0045] FIG. 6 is a flowchart illustrating the operation method of a storage system according to embodiments of the present invention. FIG. 6 describes the operation of a storage device (30) in the storage system (10) of FIG. 1.

[0046] Referring to FIGS. 1, FIGS. 2, FIGS. 3 and FIGS. 6, in step S610, the storage device (30) can perform an initialization operation when a power-up is detected during the booting of the storage system (10). In the initialization operation, the storage device (30) can read initialization information stored in the non-volatile memory (36) and set it in the setting register.

[0047] After the storage device (30) performs the initialization operation of step S610, it may attempt to link up to the host (20) via the transmission lane (LANE) connected in step S620.

[0048] In step S630, the storage device (30) can determine whether a low-speed (LS) link-up is received through the connected receiving lane (LANE). The low-speed (LS) link-up is an activation period (T) in which the line (LINE) of the connected receiving lane (LANE) is in the DIF-N state from the DIF-Z state. ACTIVATE ) and line-reset interval in DIF-P state (T LINE-RESET Whether it is received as ) and the line-reset interval (T LINE-RESET The length of ) can be determined as being greater than or equal to the first time. For example, the first time can be set to about 3.1ms.

[0049] As a result of the determination in step S630, if a low-speed (LS) link-up is received through the connected receiving lane (LANE), steps S660 and S670 can be performed. After the storage device (30) is initialized to a low-speed (LS) mode state in step S660, a link startup sequence (LSS) in the low-speed (LS) mode can be performed in step S670. After that, the storage device (30) will be in a low-speed link-up state with the host (20).

[0050] If, as a result of the determination in step S630, a low-speed (LS) link-up is not received through the connected receiving lane (LANE), the process can proceed to steps S640 and S650. In step S640, the storage device (30) can perform a link startup sequence (LSS) with the host (20) in high-speed (HS) mode. In step S650, the storage device (30) determines whether the high-speed link-up status with the host (20) is successful, and if, as a result of the determination, it is not successful, the process can proceed to step 620 to retry the high-speed link-up with the host (20).

[0051] In this embodiment, when information required for link startup is exchanged between a storage device (30) and a host (20) through a lane (connected transmission lane (LANE) or connected reception lane (LANE)) in a low-speed mode link startup performed using a PWM method, bits representing information required for link startup can be expressed through the pulse width of a signal transmitted through the lane. In such a low-speed mode link startup using a PWM method, a Return to Zero (RZ) method may be applied, in which a logic low section must exist between each logic high section of the signal transmitted through the lane.

[0052] In contrast, in high-speed mode link startup, bits representing the information required for link startup can be expressed through the logic level of the signal transmitted through the lane. In high-speed mode link startup, a Non-Return to Zero (NRZ) method can be applied, where there is no need for logic low intervals between consecutive logic high intervals. Accordingly, high-speed mode link startup operations can be performed at a faster speed compared to low-speed mode link startup operations.

[0053] FIG. 7 is a chart illustrating the operation method of a storage system according to embodiments of the present invention.

[0054] Referring to FIGS. 6 and 7, while the storage device (30) transmits a high-speed link startup to the host (20) to attempt a high-speed link up in step S620, the host (20) may perform a low-speed link startup (S700) through the connected transmission lane. At this time, the host (20) may transmit a low-speed link startup primitive (LS_LinkStartUp.ind) indicating a low-speed link up to the storage device (30). The host (20) may transmit the low-speed link startup primitive (LS_LinkStartUp.ind) by including it in the first trigger event (TRG_UPR0) of the link startup sequence (LSS).

[0055] The host (20) can send a first trigger event (TRG_UPR0) containing a slow link startup primitive (LS_LinkStartUp.ind) through all transmission lanes (LANEs). The host (20) can continue to send the first trigger event (TRG_UPR0) until the lanes (LANEs) connected to the storage device (30), i.e., the available receiving lanes (LANEs), receive the first trigger event (TRG_UPR0) message. The slow link startup primitive (LS_LinkStartUp.ind) included in the first trigger event (TRG_UPR0) sent by the host (20) can be received by the storage device (30) through the connected receiving lane (S630).

[0056] The storage device (30) receives a low-speed link startup primitive (LS_LinkStartUp.ind) from a host (20) that has priority, initializes to a low-speed (LS) mode state (S660), and can perform a link startup sequence (LSS) in the low-speed (LS) mode (S670).

[0057] FIG. 8 is a flowchart illustrating a method of operation of a storage system according to embodiments of the present invention. FIG. 8 describes the operation of a storage device (30) in the storage system (10) of FIG. 1.

[0058] Referring to FIG. 8, the storage device (30) has an activation period (T) in which the line of the connected LANE in step S830 is in the DIF-N state compared to FIG. 6. ACTIVATE The length of ) is the second time (T HS There is a difference in that it determines whether it is shorter than ). Below, explanations that overlap with Fig. 6 are omitted.

[0059] The line of the lane (LANE) connected to the storage device (30) may be in a state other than DIF-N, for example, DIF-Z state, prior to step 830. The second time (T HS) can be, for example, 0.9ms. According to an exemplary embodiment, the second time (T HS ) can be set differently from 0.9ms. For example, the second time (T HS ) may have a value smaller than 0.9ms, or a value larger than 0.9ms (e.g., 1.6ms).

[0060] As a result of the judgment in step S830, the activation section (T) of the connected lane (LANE) ACTIVATE The length of ) is the second time (T HS If it is longer than ) it can proceed to steps S660 and S670.

[0061] As a result of the judgment in step S830, the activation section (T) of the connected lane (LANE) ACTIVATE If the length of ) is shorter than the second time (Ths), it can proceed to step S640 and step S650.

[0062] FIG. 9 is a flowchart illustrating a method of operation of a storage system according to embodiments of the present invention. FIG. 9 describes the operation of a host (20) in the storage system (10) of FIG. 1.

[0063] Referring to FIGS. 1, FIGS. 2 and FIGS. 9, in step S910, the host (20) can initialize to a High Speed ​​(HS) mode state and wait. In step S920, the host (20) can determine whether a High Speed ​​(HS) link-up is received through the connected receiving lane (LANE). The High Speed ​​(HS) link-up is an activation period (T) in which the line (LINE) of the connected receiving lane (LANE) is in the DIF-N state from the DIF-Z state. ACTIVATE ) and line-reset interval in DIF-P state (T LINE-RESET Whether it is received as ) and the line-reset interval (T LINE-RESET The length of ) can be determined as being greater than or equal to the first time. For example, the first time can be set to about 3.1ms.

[0064] If, as a result of the judgment in step S920, a high-speed (HS) link-up is received through the connected receiving lane (LANE), the process can proceed to steps S930 and S940. In step S930, the host (20) can perform a link startup sequence (LSS) with the storage device (30) in high-speed (HS) mode. In step S940, the host (20) can determine whether the high-speed link-up state with the storage device (30) is successful. If, as a result of the judgment in step S940, it is successful, the host (20) will be in a high-speed link-up state with the storage device (30). If, as a result of the judgment in step S940, it is not successful, the process can proceed to step 910 and wait in the high-speed (HS) mode state.

[0065] If, as a result of the judgment in step S920, a high-speed (HS) link-up is not received through the connected receiving lane (LANE), the process can proceed to steps S950 and S960. The host (20) attempts a low-speed link-up to the storage device (30) in step S660 and can perform a link startup sequence (LSS) in low-speed (LS) mode in step S960. Afterward, the host (20) will be in a low-speed link-up state with the storage device (30).

[0066] FIG. 10 is a flowchart illustrating a method of operation of a storage system according to embodiments of the present invention. FIG. 10 describes the operation of a host (20) in the storage system (10) of FIG. 1.

[0067] Referring to FIG. 10, the host (20) differs from FIG. 9 in that it determines whether a high-speed link startup primitive (HS_LinkStartUp.ind) is received through the connected lane (LANE) in step S1020. The following descriptions that overlap with FIG. 9 are omitted.

[0068] The host (20) waits in a high-speed (HS) mode state (S910) and can determine whether a high-speed link startup primitive (HS_LinkStartUp.ind) is received through the connected lane (LANE) in step S1020. The high-speed link startup primitive (HS_LinkStartUp.ind) indicates a high-speed link up and can be transmitted by the storage device (30) to the host (20).

[0069] As a result of the judgment in step S1020, if a high-speed link startup primitive (HS_LinkStartUp.ind) is received, the host (20) can recognize that the storage device (30) will attempt a high-speed link up. Subsequently, in step S930, the host (20) can perform a link startup sequence (LSS) with the storage device (30) in high-speed (HS) mode.

[0070] If, as a result of the judgment in step S1020, the high-speed link startup primitive (HS_LinkStartUp.ind) is not received, the host (20) can recognize that the storage device (30) has product specifications that cannot attempt a high-speed link up. Subsequently, the host (20) attempts a low-speed link up to the storage device (30) in step S950, and can perform a link startup sequence (LSS) in low-speed (LS) mode in step S960.

[0071] FIG. 11 is a chart illustrating the operation method of a storage system according to embodiments of the present invention.

[0072] Referring to FIGS. 10 and FIGS. 11, the reset signal (RESET_n) of the active row in the storage system (10) is released, and the line (LINE) of the lane (LANE) connected to the host (20) is in the HIBERN8 state of the DIF-Z state. The host (20) can exit the HIBERN8 state and wait after initializing to the high-speed (HS) mode state (S910). The host (20) can determine whether a high-speed link startup primitive (HS_LinkStartUp.ind) is received from the storage device (30) within a third time (THS-DEVICE-INITIAL) from the release of the reset signal (RESET_n) (S1020). The third time (THS-DEVICE-INITIAL) can be set as the time required for the storage device (30) to initialize to the high-speed (HS) mode state. That is, the storage device (30) can be initialized to a high-speed mode state within a third time (THS-DEVICE-INITIAL) and attempt a high-speed link-up. For example, the third time (THS-DEVICE-INITIAL) can be set to about 10 ms.

[0073] The storage device (30) can send a first trigger event (TRG_UPR0) containing a high-speed link startup primitive (HS_LinkStartUp.ind) through all transmission lanes (LANEs). The storage device (30) can continue to send the first trigger event (TRG_UPR0) until the lanes (LANEs) connected to the host (20), i.e., the available receiving lanes (LANEs), receive the first trigger event (TRG_UPR0) message. The high-speed link startup primitive (HS_LinkStartUp.ind) included in the first trigger event (TRG_UPR0) sent from the storage device (30) can be received by the host (20) through the connected receiving lane (S1020).

[0074] In step S1020, if a high-speed link startup primitive (HS_LinkStartUp.ind) is not received through the connected lanes (LANE), the host (20) may attempt a low-speed link up to the storage device (30) by sending a first trigger event (TRG_UPR0) containing a low-speed link startup primitive (LS_LinkStartUp.ind) through all transmitting lanes (LANEs) (S950). The host (20) may continue to send the first trigger event (TRG_UPR0) until the lanes (LANEs) connected to the storage device (30), i.e., the available receiving lanes (LANEs), receive the first trigger event (TRG_UPR0) message.

[0075] The storage device (30) receives a first trigger event (TRG_UPR0) containing a low-speed link startup primitive (LS_LinkStartUp.ind) and can perform a link startup sequence (LSS) with the host (20) in low-speed (LS) mode (S960, S1100).

[0076] FIG. 12 is a flowchart illustrating a link startup sequence (LSS) according to embodiments of the present invention. The link startup sequence (LSS) of FIG. 12 is performed in a multi-phase handskake manner that exchanges UniPro trigger events to establish initial link communication in both directions on connected lanes (LANEs), i.e., available lanes (LANEs).

[0077] Referring to FIGS. 1, 2 and 12, in step S1210, the storage device (30) may generate a LINE-RESET, reset the transmitters (TXs) of the connected lanes (LANEs), and transmit information indicating that the transmitters (TXs) have been reset. The host (20) may receive the LINE-RESET, reset the receivers (RXs) of the connected lanes (LANEs), and transmit information indicating that the receivers (RXs) have been reset. The LINE-RESET may be configured to reset or clear all attributes of the physical layers of the interconnect parts (32, 22) to their default values. The storage device (30) and the host (20) may exchange LINE-RESET information with each other. Step S1210 may be referred to as the LINE-RESET step (S1210). After the line reset step (S1210) is performed, the link startup sequence (LSS) can be started.

[0078] A link startup sequence (LSS) can be defined by a set of phases. A link startup sequence (LSS) uses a trigger event for each phase, and each trigger event can be sent multiple times.

[0079] In the first step (S1220) of the link startup sequence (LSS), the link startup sequence (LSS) may discover connected lanes (LANEs). To this end, the storage device (30) may send a first trigger event (TRG_UPR0) through all transmitting lanes (LANEs). The storage device (30) may continue to send the first trigger event (TRG_UPR0) until the lanes (LANEs) connected to the host (20), i.e., the available receiving lanes (LANEs), receive the first trigger event (TRG_UPR0) message. The first trigger event (TRG_UPR0) sent by the storage device (30) may include the physical lane number of the transmitting lane (LANE) of the storage device (30) to which the corresponding trigger is sent. Additionally, the first trigger event (TRG_UPR0) sent from the storage device (30) may include a high-speed link startup primitive (HS_LinkStartUp.ind) to attempt a high-speed link up to the host (20).

[0080] And, in the first step (S1220), the host (20) may send a first trigger event (TRG_UPR0) through all transmission lanes (LANEs). The host (20) may continue to send the first trigger event (TRG_UPR0) until the lanes (LANEs) connected to the storage device (30), i.e., the available receiving lanes (LANEs), receive the first trigger event (TRG_UPR0) message. The first trigger event (TRG_UPR0) sent by the host (20) may include the physical lane number of the transmission lane (LANE) of the host (20) to which the corresponding trigger is sent.

[0081] In the second step (S1230) of the link startup sequence (LSS), the link startup sequence (LSS) may realign the data lanes. To this end, the storage device (30) may send a second trigger event (TRG_UPR1) through all transmission lanes (LANEs). The storage device (30) may continue to send the second trigger event (TRG_UPR1) until the lanes (LANEs) connected to the host (20), i.e., the available receiving lanes (LANEs), receive the second trigger event (TRG_UPR1) message. The second trigger event (TRG_UPR1) sent by the storage device (30) may include information regarding the connected transmission lanes (LANEs) of the storage device (30).

[0082] And, in the second step (S1230), the host (20) may send a second trigger event (TRG_UPR1) through all transmission lanes (LANEs). The host (20) may continue to send the second trigger event (TRG_UPR1) until the lanes (LANEs) connected to the storage device (30), i.e., the available receiving lanes (LANEs), receive the second trigger event (TRG_UPR1) message. The second trigger event (TRG_UPR1) sent by the host (20) may include information regarding the connected transmission lanes (LANEs) of the host (20).

[0083] In the third step (S1240) of the link startup sequence (LSS), the link startup sequence (LSS) can reflect in the attributes of the physical layers of the interconnect parts (32, 22) how many lanes (LANEs), i.e., available lanes (LANEs), are connected between the storage device (30) and the host (20). To this end, the storage device (30) can send a third trigger event (TRG_UPR2) through the connected transmission lanes (LANEs), i.e., available transmission lanes (LANEs). The storage device (30) can continue to send the third trigger event (TRG_UPR2) until the reception lanes (LANEs), i.e., available reception lanes (LANEs), connected to the host (20) receive the third trigger event (TRG_UPR2) message. The third trigger event (TRG_UPR2) sent from the storage device (30) may include logical lane numbers regarding the connected transmission lanes (LANEs) of the storage device (30).

[0084] And, in the third step (S1240), the host (20) may send a third trigger event (TRG_UPR2) through the connected transmission lanes (LANEs), i.e., the available transmission lanes (LANEs). The host (20) may continue to send the third trigger event (TRG_UPR2) until the receiving lanes (LANEs) connected to the storage device (30), i.e., the available receiving lanes (LANEs), receive the third trigger event (TRG_UPR2) message. The third trigger event (TRG_UPR2) sent by the host (20) may include logical lane numbers regarding the connected transmission lanes (LANEs) of the host (20).

[0085] As the third step (S1240) of the link startup sequence (LSS) is performed, the storage device (30) and the host (20) may have matching logical lane numbers regarding available lanes (LANEs). At this point, the storage device (30) and the host (20) may terminate the link startup sequence (LSS) and perform a capability exchange.

[0086] In step S1250, the storage device (30) and the host (20) may exchange and recognize information regarding the performance (CAP) of the other device in order to communicate the architecture requirements of the interconnect parts (32, 22). The architecture requirements of the interconnect parts (32, 22) may include, for example, bandwidth, timers, speed gear, termination / untermination, scrambling, etc. Step S1250 may be referred to as the performance exchange step (S1250). By performing the performance exchange step (S1250), information regarding the performance (CAP) of the other device is collected in the interconnect parts (32, 22), and the attributes of the physical layers of the interconnect parts (32, 22) may be set according to the collected performance (CAP) information.

[0087] In step S1260, the storage device (30) and the host (20) may exchange an Automatic Control Frame (AFC) with each other to provide a reliable data link. To this end, the storage device (30) and the host (20) may send an initial data frame to the other device, and the device that received the data frame may send back an Automatic Control Frame (AFC) to the device that sent the data frame. The Automatic Control Frame (AFC) may be configured differently from the data frame and may be used to recognize that it has been correctly received by the transmitting device and to inform the available buffer space of the data link layer.

[0088] FIG. 13 is a diagram illustrating a system to which a storage device according to an embodiment of the present invention is applied. The system (1000) of FIG. 13 may basically be a mobile system such as a portable communication terminal (mobile phone), a smartphone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an IoT (Internet of Things) device. However, the system (1000) of FIG. 13 is not necessarily limited to a mobile system and may be an automotive device such as a personal computer, a laptop computer, a server, a media player, or a navigation device. Hereinafter, the subscripts attached to the reference numbers (e.g., a in 1200a, a in 1300a) are intended to distinguish multiple circuits that perform the same function.

[0089] Referring to FIG. 13, the system (1000) may include a main processor (1100), memory (1200a, 1200b) and storage devices (1300a, 1300b), and additionally may include one or more of an image capturing device (1410), a user input device (1420), a sensor (1430), a communication device (1440), a display (1450), a speaker (1460), a power supplying device (1470), and a connecting interface (1480).

[0090] The main processor (1100) can control the overall operation of the system (1000), more specifically, the operation of other components that make up the system (1000). Such a main processor (1100) can be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0091] The main processor (1100) may include one or more CPU cores (1110) and may further include a controller (1120) for controlling memory (1200a, 1200b) and / or storage devices (1300a, 1300b). According to an embodiment, the main processor (1100) may further include an accelerator block (1130), which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator block (1130) may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the main processor (1100).

[0092] The memory (1200a, 1200b) can be used as the main memory of the system (1000) and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) may also be implemented within the same package as the main processor (1100).

[0093] The storage device (1300a, 1300b) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memory (1200a, 1200b). The storage device (1300a, 1300b) may include a storage controller (1310a, 1310b) and a non-volatile memory (NVM) storage (1320a, 1320b) that stores data under the control of the storage controller (1310a, 1310b). The non-volatile storage (1320a, 1320b) may include V-NAND flash memory with a 2D (2-dimensional) or 3D (3-dimensional) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0094] The storage device (1300a, 1300b) may be included in the system (1000) in a state physically separated from the main processor (1100), or it may be implemented within the same package as the main processor (1100). Additionally, the storage device (1300a, 1300b) may have a form such as a memory card and may be detachably coupled to other components of the system (1000) through an interface such as the connection interface (1480) described later. Such storage device (1300a, 1300b) may be a device to which standard protocols such as UFS (universal flash storage) are applied, but it is not necessarily limited thereto.

[0095] The shooting device (1410) can take still images or video and may be a camera, camcorder and / or webcam, etc.

[0096] The user input device (1420) can receive various types of data input from a user of the system (1000) and may be a touch pad, keypad, keyboard, mouse and / or microphone, etc.

[0097] The sensor (1430) can detect various types of physical quantities that may be obtained from outside the system (1000) and convert the detected physical quantities into electrical signals. Such a sensor (1430) may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and / or a gyroscope, etc.

[0098] The communication device (1440) can transmit and receive signals between other devices outside the system (1000) according to various communication protocols. Such a communication device (1440) may be implemented including an antenna, a transceiver and / or a modem.

[0099] The display (1450) and speaker (1460) can function as output devices that output visual information and auditory information, respectively, to the user of the system (1000).

[0100] The power supply unit (1470) can appropriately convert power supplied from a battery (not shown) and / or an external power source built into the system (1000) and supply it to each component of the system (1000).

[0101] The connection interface (1480) can provide a connection between the system (1000) and an external device connected to the system (1000) that can exchange data with the system (1000). The connection interface (1480) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0102] FIG. 14 is a drawing for explaining a UFS system (2000) according to an embodiment of the present invention. The UFS system (2000) is a system that follows the UFS standard published by JEDEC (Joint Electron Device Engineering Council) and may include a UFS host (2100), a UFS device (2200), and a UFS interface (2300). The description of the system (1000) of FIG. 13 described above may also be applied to the UFS system (2000) of FIG. 14 to the extent that it does not conflict with the following description of FIG. 14.

[0103] Referring to FIG. 14, the UFS host (2100) and the UFS device (2200) can be interconnected via a UFS interface (2300). If the main processor (1100) of FIG. 13 is an application processor, the UFS host (2100) can be implemented as part of the application processor. The UFS host controller (2110) and the host memory (2140) can correspond to the controller (1120) and memory (1200a, 1200b) of the main processor (1100) of FIG. 13, respectively. The UFS device (2200) may correspond to the storage device (1300a, 1300b) of FIG. 13, and the UFS device controller (2210) and non-volatile storage (2220) may correspond to the storage controller (1310a, 1310b) and non-volatile storage (1320a, 1320b) of FIG. 13, respectively.

[0104] A UFS host (2100) may include a UFS host controller (2110), an application (2120), a UFS driver (2130), a host memory (2140), and a UIC (UFS interconnect) layer (2150). A UFS device (2200) may include a UFS device controller (2210), non-volatile storage (2220), a storage interface (2230), a device memory (2240), a UIC layer (2250), and a regulator (2260). The non-volatile storage (2220) may be composed of a plurality of storage units (2221), and such storage units (2221) may include V-NAND flash memory of a 2D or 3D structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM. The UFS device controller (2210) and the non-volatile storage (2220) can be connected to each other through a storage interface (2230). The storage interface (2230) can be implemented to comply with standard protocols such as Toggle or ONFI.

[0105] The application (2120) may refer to a program that wishes to communicate with the UFS device (2200) in order to use the functions of the UFS device (2200). The application (2120) may send an input-output request (IOR) to the UFS driver (2130) for input / output to the UFS device (2200). The input-output request (IOR) may refer to a data read request, a write request, and / or a discard request, but is not necessarily limited thereto.

[0106] The UFS driver (2130) can manage the UFS host controller (2110) through the UFS-HCI (host controller interface). The UFS driver (2130) can convert an I / O request generated by an application (2120) into a UFS command defined by the UFS standard and transmit the converted UFS command to the UFS host controller (2110). A single I / O request can be converted into multiple UFS commands. The UFS commands may be commands defined by the SCSI standard by default, but they may also be commands specific to the UFS standard.

[0107] The UFS host controller (2110) can transmit UFS commands converted by the UFS driver (2130) to the UIC layer (2250) of the UFS device (2200) through the UIC layer (2150) and the UFS interface (2300). In this process, the UFS host register (2111) of the UFS host controller (2110) can serve as a command queue (CQ).

[0108] The UIC layer (2150) on the UFS host (2100) side may include MIPI M-PHY (2151) and MIPI UniPro (2152), and the UIC layer (2250) on the UFS device (2200) side may also include MIPI M-PHY (2251) and MIPI UniPro (2252).

[0109] The UFS interface (2300) may include a line transmitting a reference clock (REF_CLK), a line transmitting a hardware reset signal (RESET_n) for the UFS device (2200), a pair of lines transmitting a differential input signal pair (DIN_t and DIN_c), and a pair of lines transmitting a differential output signal pair (DOUT_t and DOUT_c).

[0110] The frequency value of the reference clock (REF_CLK) provided from the UFS host (2100) to the UFS device (2200) may be one of four values: 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not necessarily limited thereto. The UFS host (2100) may change the frequency value of the reference clock (REF_CLK) even while in operation, that is, while data transmission and reception is being performed between the UFS host (2100) and the UFS device (2200). The UFS device (2200) may generate clocks of various frequencies from the reference clock (REF_CLK) provided from the UFS host (2100) using a phase-locked loop (PLL), etc. Additionally, the UFS host (2100) may set the value of the data rate between the UFS host (2100) and the UFS device (2200) through the frequency value of the reference clock (REF_CLK). That is, the value of the data rate may be determined based on the frequency value of the reference clock (REF_CLK).

[0111] The UFS interface (2300) may support multiple lanes, and each lane may be implemented as a differential pair. For example, the UFS interface may include one or more receive lanes and one or more transmit lanes. In FIG. 14, a pair of lines transmitting a differential input signal pair (DIN_T and DIN_C) may each constitute a receive lane, and a pair of lines transmitting a differential output signal pair (DOUT_T and DOUT_C) may each constitute a transmit lane. Although FIG. 14 shows one transmit lane and one receive lane, the number of transmit lanes and receive lanes may be changed.

[0112] The receiving lane and the transmitting lane can transmit data in a serial communication manner, and full-duplex communication between the UFS host (2100) and the UFS device (2200) is possible due to the structure in which the receiving lane and the transmitting lane are separated. That is, the UFS device (2200) can transmit data to the UFS host (2100) through the transmitting lane even while receiving data from the UFS host (2100) through the receiving lane. In addition, control data such as commands from the UFS host (2100) to the UFS device (2200), and user data that the UFS host (2100) intends to store in the non-volatile storage (2220) of the UFS device (2200) or read from the non-volatile storage (2220) can be transmitted through the same lane. Accordingly, there is no need to provide additional lanes for data transmission between the UFS host (2100) and the UFS device (2200) in addition to a pair of receiving lanes and a pair of transmitting lanes.

[0113] The UFS device controller (2210) of the UFS device (2200) can control the overall operation of the UFS device (2200). The UFS device controller (2210) can manage non-volatile storage (2220) through a logical unit (LU) (2211), which is a logical data storage unit. The number of LUs (2211) may be eight, but is not limited thereto. The UFS device controller (2210) may include a flash translation layer (FTL) and can convert a logical data address, such as a logical block address (LBA), transmitted from the UFS host (2100) into a physical data address, such as a physical block address (PBA), using the address mapping information of the FTL. A logical block for storing user data in the UFS system (2000) may have a size within a predetermined range. For example, the minimum size of a logical block can be set to 4Kbyte.

[0114] When a command from the UFS host (2100) is input to the UFS device (2200) through the UIC layer (2250), the UFS device controller (2210) performs an operation according to the input command, and when the operation is completed, it can send a completion response to the UFS host (2100).

[0115] For example, if a UFS host (2100) intends to store user data in a UFS device (2200), the UFS host (2100) may send a data storage command to the UFS device (2200). When the UFS host (2100) receives a response from the UFS device (2200) that the user data is ready to be transferred, the UFS host (2100) may transfer the user data to the UFS device (2200). The UFS device controller (2210) may temporarily store the transferred user data in the device memory (2240) and, based on the address mapping information of the FTL, store the user data temporarily stored in the device memory (2240) in a selected location of the non-volatile storage (2220).

[0116] As another example, when a UFS host (2100) intends to read user data stored in a UFS device (2200), the UFS host (2100) may transmit a data read command to the UFS device (2200). Upon receiving the command, the UFS device controller (2210) may read user data from the non-volatile storage (2220) based on the data read command and temporarily store the read user data in the device memory (2240). During this read process, the UFS device controller (2210) may detect and correct errors in the read user data using an embedded ECC (error correction code) circuit (not shown). Then, the UFS device controller (2210) may transmit the user data temporarily stored in the device memory (2240) to the UFS host (2100). In addition, the UFS device controller (2210) may further include an AES (advanced encryption standard) circuit (not shown), and the AES circuit can encrypt or decrypt data input to the UFS device controller (2210) using a symmetric-key algorithm.

[0117] The UFS host (2100) can store commands to be transmitted to the UFS device (2200) in order in a UFS host register (2111) that can function as a command queue, and can transmit commands to the UFS device (2200) in the said order. At this time, the UFS host (2100) can transmit the next command waiting in the command queue to the UFS device (2200) even if the previously transmitted command is still being processed by the UFS device (2200), that is, before receiving notification that the previously transmitted command has been completed by the UFS device (2200), and accordingly, the UFS device (2200) can also receive the next command from the UFS host (2100) even while processing the previously transmitted command. The maximum number of commands that can be stored in such a command queue (queue depth) may be, for example, 32. Additionally, the command queue can be implemented as a circular queue type, which indicates the start and end of the column of commands stored in the queue through a head pointer and a tail pointer, respectively.

[0118] Each of the plurality of storage units (2221) may include a memory cell array and a control circuit that controls the operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a single-level cell (SLC) that stores 1 bit of information, but may also be a cell that stores 2 bits or more of information, such as an MLC (multi-level cell), TLC (triple-level cell), or QLC (quadruple-level cell). The three-dimensional memory cell array may include a vertically oriented NAND string such that at least one memory cell is positioned above another memory cell.

[0119] VCC, VCCQ1, VCCQ2, etc., may be input as power voltages to the UFS device (2200). VCC is the main power voltage for the UFS device (2200) and may have a value of 2.4 to 3.6 V. VCCQ is a power voltage for supplying a low range of voltage, mainly for the UFS device controller (2210), and may have a value of 1.14 to 1.26 V. VCCQ2 is a power voltage for supplying a range of voltage lower than VCC but higher than VCCQ, mainly for an input / output interface such as MIPI M-PHY (2251), and may have a value of 1.7 to 1.95 V. The above power voltages may be supplied to each component of the UFS device (2200) through a regulator (2260). The regulator (2260) may be implemented as a set of unit regulators each connected to different of the aforementioned power voltages.

[0120] FIGS. 15a to 15c are drawings for explaining the form factor of a UFS card. When the UFS device (2200) described with reference to FIG. 13 is implemented in the form of a UFS card (4000), the external appearance of the UFS card (4000) may follow that shown in FIGS. 15a to 15c.

[0121] FIG. 15a illustrates an exemplary top view of a UFS card (4000). Referring to FIG. 15a, it can be seen that the UFS card (4000) follows a shark-shaped design overall. In relation to FIG. 15a, the UFS card (4000) may have dimension values ​​as described in Table 1 below, for example.

[0122] item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0123] FIG. 15b illustrates an exemplary side view of a UFS card (4000). In relation to FIG. 15b, the UFS card (4000) may have dimension values ​​as described in Table 2 below, for example.

[0124] item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

[0125] FIG. 15c illustrates an exemplary bottom view of a UFS card (4000). Referring to FIG. 15c, a plurality of pins for electrical contact with a UFS slot may be formed on the bottom surface of the UFS card (4000), and the function of each pin will be described later. Based on the symmetry between the top surface and the bottom surface of the UFS card (4000), some of the information regarding dimensions described with reference to FIG. 15a and Table 1 (e.g., T1 to T5 and T9) may also be applied to the bottom view of the UFS card (4000) as illustrated in FIG. 15c.

[0126] A plurality of pins may be formed on the bottom surface of the UFS card (4000) for electrical connection with the UFS host, and according to FIG. 15c, the total number of pins may be 12. Each pin may have a rectangular shape, and the signal name corresponding to the pin is as shown in FIG. 15c. For general information regarding each pin, refer to Table 3 below, and refer to the description above in relation to FIG. 14.

[0127] number Shin Ho-myeong explanation Dimensions (mm) 1 VSS Ground (GND) 3.00 × 0.72±0.05 2 DIN_C Differential input signal input from the host to the UFS card (4000) (DIN_C is the negative node, DIN_T is the positive node) 1.50 × 0.72±0.05 3 DIN_T 4 VSS Same as number 1 3.00 × 0.72±0.05 5 DOUT_C Differential output signal output from UFS card (4000) to host (DOUT_C ​​is negative node, DOUT_T is positive node) 1.50 × 0.72±0.05 6 DOUT_T 7 VSS Same as number 1 3.00 × 0.72±0.05 8 REF_CLK Reference clock provided from the host to the UFS card (4000) 1.50 × 0.72±0.05 9 VCCQ2 A power supply voltage having a relatively lower value compared to Vcc, primarily provided for PHY interfaces or controllers. 3.00 × 0.72±0.05 10 C / D(GND) Card Detection Signal 1.50 × 0.72±0.05 11 VSS Same as number 1 3.00 × 0.80±0.05 12 Vcc Main power supply voltage

[0128] FIG. 16 is a block diagram showing a non-volatile storage according to one embodiment of the present invention.

[0129] Referring to FIG. 16, the non-volatile storage (2220a) may include a memory device (2224) and a memory controller (2222). The non-volatile storage (2220a) may support a plurality of channels (CH1 to CHm), and the memory device (2224) and the memory controller (2222) may be connected through the plurality of channels (CH1 to CHm). For example, the non-volatile storage (2220a) may be implemented as a storage device such as a Solid State Drive (SSD).

[0130] The memory device (2224) may include a plurality of non-volatile memory devices (NVM11 to NVMmn). Each of the non-volatile memory devices (NVM11 to NVMmn) may be connected to one of a plurality of channels (CH1 to CHm) through a corresponding way. For example, the non-volatile memory devices (NVM11 to NVM1n) may be connected to a first channel (CH1) through ways (W11 to W1n), and the non-volatile memory devices (NVM21 to NVM2n) may be connected to a second channel (CH2) through ways (W21 to W2n). In an exemplary embodiment, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as any memory unit capable of operating according to individual commands from the memory controller (2222). For example, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as a chip or a die, but the present invention is not limited thereto.

[0131] The memory controller (2222) can transmit and receive signals to and from the memory device (2224) through multiple channels (CH1~CHm). For example, the memory controller (2222) can transmit commands (CMDa~CMDm), addresses (ADDRa~ADDRm), and data (DATAa~DATAm) to the memory device (2224) through the channels (CH1~CHm), or receive data (DATAa~DATAm) from the memory device (2224).

[0132] The memory controller (2222) can select one of the non-volatile memory devices connected to the corresponding channel through each channel and transmit and receive signals with the selected non-volatile memory device. For example, the memory controller (2222) can select a non-volatile memory device (NVM11) among the non-volatile memory devices (NVM11 to NVM1n) connected to the first channel (CH1). The memory controller (2222) can transmit a command (CMDa), an address (ADDRa), and data (DATAa) to the selected non-volatile memory device (NVM11) through the first channel (CH1), or receive data (DATAa) from the selected non-volatile memory device (NVM11).

[0133] The memory controller (2222) can transmit and receive signals to and from the memory device (2224) in parallel through different channels. For example, the memory controller (2222) can transmit a command (CMDb) to the memory device (2224) through a second channel (CH2) while transmitting a command (CMDa) to the memory device (2224) through a first channel (CH1). For example, the memory controller (2222) can receive data (DATAb) from the memory device (2224) through a second channel (CH2) while receiving data (DATAa) from the memory device (2224) through a first channel (CH1).

[0134] The memory controller (2222) can control the overall operation of the memory device (2224). The memory controller (2222) can control each of the non-volatile memory devices (NVM11–NVMmn) connected to the channels (CH1–CHm) by transmitting signals to the channels (CH1–CHm). For example, the memory controller (2222) can control one of the selected non-volatile memory devices (NVM11–NVM1n) by transmitting a command (CMDa) and an address (ADDRa) to the first channel (CH1).

[0135] Each of the non-volatile memory devices (NVM11 to NVMmn) can operate under the control of the memory controller (2222). For example, the non-volatile memory device (NVM11) can program data (DATAa) according to a command (CMDa), an address (ADDRa), and data (DATAa) provided through the first channel (CH1). For example, the non-volatile memory device (NVM21) can read data (DATAb) according to a command (CMDb) and an address (ADDRb) provided through the second channel (CH2), and transmit the read data (DATAb) to the memory controller (2222).

[0136] FIG. 16 illustrates that a memory device (2224) communicates with a memory controller (2222) through m channels, and that the memory device (2224) includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to one channel can be varied.

[0137] FIG. 17 is a block diagram illustrating a non-volatile storage according to an embodiment of the present invention. Referring to FIG. 17, the non-volatile storage (2220b) may include a memory device (2226) and a memory controller (2222). The memory device (2226) may correspond to one of the non-volatile memory devices (NVM11 to NVMmn) that communicate with the memory controller (2222) based on one of the plurality of channels (CH1 to CHm) of FIG. 16. The memory controller (2222) may correspond to the memory controller (2222) of FIG. 16.

[0138] The memory device (2226) may include first to eighth pins (P11 to P18), a memory interface circuit (2310), a control logic circuit (2320), and a memory cell array (2330).

[0139] The memory interface circuit (2310) can receive a chip enable signal (nCE) from the memory controller (2222) through the first pin (P11). The memory interface circuit (2310) can transmit and receive signals with the memory controller (2222) through the second to eighth pins (P12 to P18) according to the chip enable signal (nCE). For example, when the chip enable signal (nCE) is in an enable state (e.g., low level), the memory interface circuit (2310) can transmit and receive signals with the memory controller (2222) through the second to eighth pins (P12 to P18).

[0140] The memory interface circuit (2310) can receive a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) from the memory controller (2222) through the second to fourth pins (P12 to P14). The memory interface circuit (2310) can receive a data signal (DQ) from the memory controller (2222) or transmit a data signal (DQ) to the memory controller (2222) through the seventh pin (P17). A command (CMD), an address (ADDR), and data (DATA) can be transmitted through the data signal (DQ). For example, the data signal (DQ) can be transmitted through a plurality of data signal lines. In this case, the seventh pin (P17) may include a plurality of pins corresponding to the plurality of data signals.

[0141] The memory interface circuit (2310) can obtain a command (CMD) from a data signal (DQ) received during the enable period (e.g., high level state) of a command latch enable signal (CLE) based on the toggle timings of a write enable signal (nWE). The memory interface circuit (2310) can obtain an address (ADDR) from a data signal (DQ) received during the enable period (e.g., high level state) of an address latch enable signal (ALE) based on the toggle timings of a write enable signal (nWE).

[0142] In an exemplary embodiment, the write enable signal (nWE) may maintain a static state (e.g., high level or low level) and then toggle between the high level and the low level. For example, the write enable signal (nWE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory interface circuit (2310) may obtain a command (CMD) or an address (ADDR) based on the toggle timings of the write enable signal (nWE).

[0143] The memory interface circuit (2310) can receive a read enable signal (nRE) from the memory controller (2222) through the fifth pin (P15). The memory interface circuit (2310) can receive a data strobe signal (DQS) from the memory controller (2222) through the sixth pin (P16) or transmit a data strobe signal (DQS) to the memory controller (2222).

[0144] In the data (DATA) output operation of the memory device (2226), the memory interface circuit (2310) may receive a read enable signal (nRE) that toggles through the fifth pin (P15) before outputting the data (DATA). The memory interface circuit (2310) may generate a data strobe signal (DQS) that toggles based on the toggling of the read enable signal (nRE). For example, the memory interface circuit (2310) may generate a data strobe signal (DQS) that begins to toggle after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read enable signal (nRE). The memory interface circuit (2310) may transmit a data signal (DQ) containing data (DATA) based on the toggling timing of the data strobe signal (DQS). Accordingly, the data (DATA) can be aligned with the toggle timing of the data strobe signal (DQS) and transmitted to the memory controller (2222).

[0145] In the data (DATA) input operation of the memory device (2226), when a data signal (DQ) containing data (DATA) is received from the memory controller (2222), the memory interface circuit (2310) may receive a data strobe signal (DQS) that toggles along with the data (DATA) from the memory controller (2222). The memory interface circuit (2310) may acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS). For example, the memory interface circuit (2310) may acquire data (DATA) by sampling the data signal (DQ) at the rising edge and falling edge of the data strobe signal (DQS).

[0146] The memory interface circuit (2310) can transmit a ready / busy output signal (nR / B) to the memory controller (2222) through the eighth pin (P18). The memory interface circuit (2310) can transmit status information of the memory device (2226) to the memory controller (2222) through the ready / busy output signal (nR / B). When the memory device (2226) is in a busy state (i.e., when internal operations of the memory device (2226) are being performed), the memory interface circuit (2310) can transmit a ready / busy output signal (nR / B) indicating the busy state to the memory controller (2222). When the memory device (2226) is in a ready state (i.e., when internal operations of the memory device (2226) are not performed or are completed), the memory interface circuit (2310) may transmit a ready / busy output signal (nR / B) indicating the ready state to the memory controller (2222). For example, while the memory device (2226) reads data (DATA) from the memory cell array (2330) in response to a page read command, the memory interface circuit (2310) may transmit a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the memory controller (2222). For example, while the memory device (2226) programs data (DATA) into the memory cell array (2330) in response to a program command, the memory interface circuit (2310) may transmit a ready / busy output signal (nR / B) indicating a busy state to the memory controller (2222).

[0147] The control logic circuit (2320) can control various operations of the memory device (2226) overall. The control logic circuit (2320) can receive a command / address (CMD / ADDR) obtained from the memory interface circuit (2310). The control logic circuit (2320) can generate control signals to control other components of the memory device (2226) according to the received command / address (CMD / ADDR). For example, the control logic circuit (2320) can generate various control signals to program data (DATA) into the memory cell array (2330) or to read data (DATA) from the memory cell array (2330).

[0148] The memory cell array (2330) can store data (DATA) obtained from the memory interface circuit (2310) under the control of the control logic circuit (2320). The memory cell array (2330) can output the stored data (DATA) to the memory interface circuit (2310) under the control of the control logic circuit (2320).

[0149] The memory cell array (2330) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, or MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments of the present invention will be described with a focus on embodiments in which the memory cells are NAND flash memory cells.

[0150] The memory controller (2222) may include first to eighth pins (P21 to P28) and a controller interface circuit (2410). The first to eighth pins (P21 to P28) may correspond to the first to eighth pins (P11 to P18) of the memory device (2226).

[0151] The controller interface circuit (2410) can transmit a chip enable signal (nCE) to a memory device (2226) through the first pin (P21). The controller interface circuit (2410) can transmit and receive signals to and from the selected memory device (2226) through the second to eighth pins (P22~P28) via the chip enable signal (nCE).

[0152] The controller interface circuit (2410) can transmit a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) to the memory device (2226) through the second to fourth pins (P22 to P24). The controller interface circuit (2410) can transmit a data signal (DQ) to the memory device (2226) or receive a data signal (DQ) from the memory device (2226) through the seventh pin (P27).

[0153] The controller interface circuit (2410) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the memory device (2226) along with a toggling write enable signal (nWE). The controller interface circuit (2410) can transmit a data signal (DQ) containing a command (CMD) to the memory device (2226) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the memory device (2226) by transmitting an address latch enable signal (ALE) having an enable state.

[0154] The controller interface circuit (2410) can transmit a read enable signal (nRE) to the memory device (2226) through the fifth pin (P25). The controller interface circuit (2410) can receive a data strobe signal (DQS) from the memory device (2226) or transmit a data strobe signal (DQS) to the memory device (2226) through the sixth pin (P26).

[0155] In the data (DATA) output operation of the memory device (2226), the controller interface circuit (2410) can generate a toggling read enable signal (nRE) and transmit the read enable signal (nRE) to the memory device (2226). For example, the controller interface circuit (2410) can generate a read enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggling state before the data (DATA) is output. Accordingly, a toggling data strobe signal (DQS) can be generated in the memory device (2226) based on the read enable signal (nRE). The controller interface circuit (2410) can receive a data signal (DQ) containing data (DATA) along with the toggling data strobe signal (DQS) from the memory device (2226). The controller interface circuit (2410) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0156] In the data (DATA) input operation of the memory device (2226), the controller interface circuit (2410) can generate a toggling data strobe signal (DQS). For example, the controller interface circuit (2410) can generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the controller interface circuit (2410) can transmit a data signal (DQ) containing the data (DATA) to the memory device (2226).

[0157] The controller interface circuit (2410) can receive a ready / busy output signal (nR / B) from the memory device (2226) through the eighth pin (P28). The controller interface circuit (2410) can determine the status information of the memory device (2226) based on the ready / busy output signal (nR / B).

[0158] FIG. 18 is an exemplary block diagram illustrating the memory device of FIG. 17. Referring to FIG. 18, the memory device (2226) may include a control logic circuit (2320), a memory cell array (2330), a page buffer section (2340), a voltage generator (2350), and a row decoder (3394). Although not shown in FIG. 18, the memory device (2226) may further include a memory interface circuit (2310) shown in FIG. 18, and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0159] The control logic circuit (2320) can control various operations within the memory device (2226) overall. The control logic circuit (2320) can output various control signals in response to a command (CMD) and / or an address (ADDR) from the memory interface circuit (2310). For example, the control logic circuit (2320) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0160] The memory cell array (2330) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (2330) may be connected to a page buffer (2340) via bit lines (BL) and may be connected to a row decoder (3394) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0161] In an exemplary embodiment, the memory cell array (2330) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array (2330) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0162] The page buffer unit (2340) may include a plurality of page buffers (PB1 to PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1 to PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer unit (2340) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer unit (2340) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer unit (2340) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer unit (2340) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0163] The voltage generator (2350) can generate various types of voltages to perform program, readout, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (2350) can generate a program voltage, a readout voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0164] The row decoder (3394) can select one of a plurality of word lines (WL) and one of a plurality of string select lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (3394) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0165] FIG. 19 is a diagram illustrating a 3D V-NAND structure that can be applied to a UFS device according to an embodiment of the present invention. When the storage module of the UFS device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the storage module can be represented by an equivalent circuit as shown in FIG. 19.

[0166] The memory block (BLKi) illustrated in FIG. 19 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block (BLKi) may be formed in a direction perpendicular to the substrate.

[0167] Referring to FIG. 19, a memory block (BLKi) may include a plurality of memory NAND strings (NS11 to NS33) connected between bit lines (BL1, BL2, BL3) and a common source line (CSL). Each of the plurality of memory NAND strings (NS11 to NS33) may include a string select transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground select transistor (GST). FIG. 19 illustrates that each of the plurality of memory NAND strings (NS11 to NS33) includes eight memory cells (MC1, MC2, ..., MC8), but is not necessarily limited thereto.

[0168] A string select transistor (SST) can be connected to corresponding string select lines (SSL1, SSL2, SSL3). Multiple memory cells (MC1, MC2, ..., MC8) can each be connected to corresponding gate lines (GTL1, GTL2, ..., GTL8). The gate lines (GTL1, GTL2, ..., GTL8) may correspond to word lines, and some of the gate lines (GTL1, GTL2, ..., GTL8) may correspond to dummy word lines. A ground select transistor (GST) can be connected to corresponding ground select lines (GSL1, GSL2, GSL3). A string select transistor (SST) is connected to corresponding bit lines (BL1, BL2, BL3), and a ground select transistor (GST) can be connected to a common source line (CSL).

[0169] Word lines of the same height (e.g., WL1) are connected in common, and ground select lines (GSL1, GSL2, GSL3) and string select lines (SSL1, SSL2, SSL3) can be separated. FIG. 19 shows a memory block (BLK) connected to eight gate lines (GTL1, GTL2, ..., GTL8) and three bit lines (BL1, BL2, BL3), but is not necessarily limited thereto.

[0170] FIG. 20 is a diagram illustrating a BVNAND structure that can be applied to a UFS device according to an embodiment of the present invention. Referring to FIG. 20, the memory device (2226) may have a C2C (chip to chip) structure. A C2C structure may mean fabricating an upper chip including a cell region (CELL) on a first wafer, fabricating a lower chip including a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip to each other. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0171] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (2226) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0172] The peripheral circuit region (PERI) may include a first substrate (3210), an interlayer insulating layer (3215), a plurality of circuit elements (3220a, 3220b, 3220c) formed on the first substrate (3210), a first metal layer (3230a, 3230b, 3230c) connected to each of the plurality of circuit elements (3220a, 3220b, 3220c), and a second metal layer (3240a, 3240b, 3240c) formed on the first metal layer (3230a, 3230b, 3230c). In one embodiment, the first metal layer (3230a, 3230b, 3230c) may be formed of tungsten, which has relatively high resistance, and the second metal layer (3240a, 3240b, 3240c) may be formed of copper, which has relatively low resistance.

[0173] In this specification, only the first metal layer (3230a, 3230b, 3230c) and the second metal layer (3240a, 3240b, 3240c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (3240a, 3240b, 3240c). At least some of the one or more metal layers formed on the upper part of the second metal layer (3240a, 3240b, 3240c) may be formed of aluminum or the like, having a lower resistance than the copper forming the second metal layer (3240a, 3240b, 3240c).

[0174] The interlayer insulating layer (3215) is disposed on a first substrate (3210) to cover a plurality of circuit elements (3220a, 3220b, 3220c), a first metal layer (3230a, 3230b, 3230c), and a second metal layer (3240a, 3240b, 3240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0175] A lower bonding metal (3271b, 3272b) may be formed on the second metal layer (3240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (3271b, 3272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (3371b, 3372b) of the cell region (CELL) by a bonding method, and the lower bonding metal (3271b, 3272b) and the upper bonding metal (3371b, 3372b) may be formed of aluminum, copper, or tungsten, etc.

[0176] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (3310) and a common source line (3320). On the second substrate (3310), a plurality of word lines (3331-338; 330) may be stacked along a direction perpendicular to the upper surface of the second substrate (3310) (Z-axis direction). String selection lines and ground selection lines may be disposed on the upper and lower sides of each of the word lines (3330), and a plurality of word lines (3330) may be disposed between the string selection lines and the ground selection lines.

[0177] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction perpendicular to the upper surface of the second substrate (3310) and penetrate word lines (3330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer (3350c) and the second metal layer (3360c). For example, the first metal layer (3350c) may be a bitline contact, and the second metal layer (3360c) may be a bitline. In one embodiment, the bitline (3360c) may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (3310).

[0178] In one embodiment illustrated in FIG. 20, the area where the channel structure (CH) and the bit line (3360c) are placed may be defined as a bit line bonding area (BLBA). The bit line (3360c) may be electrically connected to circuit elements (3220c) that provide a page buffer (3393) in the peripheral circuit area (PERI) in the bit line bonding area (BLBA). For example, the bit line (3360c) may be connected to an upper bonding metal (3371c, 3372c) in the peripheral circuit area (PERI), and the upper bonding metal (3371c, 3372c) may be connected to a lower bonding metal (3271c, 3272c) that is connected to the circuit elements (3220c) of the page buffer (3393).

[0179] In the wordline bonding area (WLBA), wordlines (3330) may extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate (3310) and may be connected to a plurality of cell contact plugs (3341-347; 340). The wordlines (3330) and the cell contact plugs (3340) may be connected to each other at pads provided by extending at least some of the wordlines (3330) along the second direction at different lengths. A first metal layer (3350b) and a second metal layer (3360b) may be connected in sequence to the upper portion of the cell contact plugs (3340) connected to the wordlines (3330). The cell contact plugs (3340) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (3371b, 3372b) of the cell area (CELL) and the lower bonding metal (3271b, 3272b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0180] Cell contact plugs (3340) may be electrically connected to circuit elements (3220b) that provide a row decoder (3394) in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (3220b) that provide the row decoder (3394) may be different from the operating voltage of the circuit elements (3220c) that provide the page buffer (3393). For example, the operating voltage of the circuit elements (3220c) that provide the page buffer (3393) may be greater than the operating voltage of the circuit elements (3220b) that provide the row decoder (3394).

[0181] A common source line contact plug (3380) may be disposed in the external pad bonding area (PA). The common source line contact plug (3380) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to a common source line (3320). A first metal layer (3350a) and a second metal layer (3360a) may be sequentially laminated on top of the common source line contact plug (3380). For example, the area where the common source line contact plug (3380), the first metal layer (3350a), and the second metal layer (3360a) are disposed may be defined as the external pad bonding area (PA).

[0182] Meanwhile, input / output pads (3205, 3305) may be disposed in the external pad bonding area (PA). Referring to FIG. 20, a lower insulating film (3201) covering the lower surface of the first substrate (3210) may be formed on the lower surface of the first substrate (3210), and a first input / output pad (3205) may be formed on the lower insulating film (3201). The first input / output pad (3205) is connected to at least one of a plurality of circuit elements (3220a, 3220b, 3220c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (3203), and may be separated from the first substrate (3210) by the lower insulating film (3201). Additionally, a side insulating film is disposed between the first input / output contact plug (3203) and the first substrate (3210) to electrically separate the first input / output contact plug (3203) and the first substrate (3210).

[0183] Referring to FIG. 20, an upper insulating film (3301) covering the upper surface of the second substrate (3310) may be formed on the upper surface of the second substrate (3310), and a second input / output pad (3305) may be disposed on the upper insulating film (3301). The second input / output pad (3305) may be connected to at least one of a plurality of circuit elements (3220a, 3220b, 3220c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (3303).

[0184] According to the embodiments, the second substrate (3310) and common source line (3320), etc., may not be placed in the area where the second input / output contact plug (3303) is placed. Additionally, the second input / output pad (3305) may not overlap with the word lines (3330) in the third direction (Z-axis direction). Referring to FIG. 20, the second input / output contact plug (3303) is separated from the second substrate (3310) in a direction parallel to the upper surface of the second substrate (3310) and may be connected to the second input / output pad (3305) by penetrating the interlayer insulating layer (3315) of the cell area (CELL).

[0185] According to embodiments, the first input / output pad (3205) and the second input / output pad (3305) may be formed optionally. For example, the memory device (2226) may include only the first input / output pad (3205) disposed on the upper part of the first substrate (3210), or only the second input / output pad (3305) disposed on the upper part of the second substrate (3310). Alternatively, the memory device (2226) may include both the first input / output pad (3205) and the second input / output pad (3305).

[0186] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0187] The memory device (2226) may form a lower metal pattern (3273a) of the same shape as the upper metal pattern (3372a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (3372a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (3273a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, the memory device may form an upper metal pattern of the same shape as the lower metal pattern of the peripheral circuit region (PERI) on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern formed on the upper metal layer of the peripheral circuit region (PERI).

[0188] A lower bonding metal (3271b, 3272b) may be formed on the second metal layer (3240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (3271b, 3272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (3371b, 3372b) of the cell region (CELL) by a bonding method.

[0189] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (3392) of the same shape as the lower metal pattern (3252) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (3252) formed on the upper metal layer of the peripheral circuit area (PERI). A contact may not be formed on the upper metal pattern (3392) formed on the upper metal layer of the cell area (CELL).

[0190] Although the present invention has been described in relation to a limited number of embodiments illustrated in the drawings, this is merely illustrative and those skilled in the art will recognize that various modifications and variations and equivalent other embodiments are possible therefrom. Accordingly, the appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

Claims

Claim 1 A method for link startup between a host and a storage device connected through at least one lane, comprising: performing an initialization operation on the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the at least one lane; and transmitting a high-speed link up to the host through the connected transmission lane of the storage device. A method comprising the step of performing a link startup in high-speed mode through the connected transmission lane of the storage device and the connected reception lane of the host based on the high-speed link up of the storage device, wherein the step of transmitting the high-speed link up to the host through the connected transmission lane of the storage device comprises the step of transitioning the line of the connected transmission lane of the storage device from a zero differential line voltage (DIF-Z) to an activation interval (TACTIVATE) having a negative differential line voltage (DIF-N), wherein if the length of the activation interval (TACTIVATE) is less than a second time, the connected transmission lane of the storage device and the reception lane of the host enter a high-speed mode (HS-MODE), and if the length of the activation interval (TACTIVATE) is greater than or equal to the second time, the connected transmission lane of the storage device and the reception lane of the host enter a low-speed mode (LS-MODE). Claim 2 The method of claim 1 further comprises the steps of: receiving a low-speed link-up from the host through the connected receiving lane of the storage device; and performing a link startup in low-speed mode through the connected transmitting lane of the host and the connected receiving lane of the storage device based on the low-speed link-up of the host. Claim 3 In paragraph 2, the step of receiving the low-speed link-up from the host through the connected receiving lane of the storage device comprises the step of receiving a low-speed link-up indicating the low-speed link-up through the connected receiving lane of the storage device. Claim 4 A method according to paragraph 3, wherein the low-speed link startup primitive is received carried on a first trigger event of a link startup sequence, and the first trigger event of the link startup sequence is performed such that the physical lane number of the connected transmission lane of the host is transmitted to the connected reception lane of the storage device. Claim 5 In claim 1, the step of transmitting the high-speed link-up to the host through the connected transmission lane of the storage device comprises the step of transitioning the line of the connected transmission lane of the storage device from a zero differential line voltage (DIF-Z) to a negative differential line voltage (DIF-N), and then transitioning to a line-reset interval having a positive differential line voltage (DIF-P), and setting the length of the line-reset interval to be greater than or equal to a first time. Claim 6 In paragraph 5, the method wherein the first time is set to 3.1 ms. Claim 7 delete Claim 8 In claim 1, the method wherein the second time is set to 0.9 ms. Claim 9 In claim 1, the method wherein the second time is set to 1.6ms. Claim 10 A method according to claim 1, wherein the step of performing an initialization operation in the storage device includes the step of reading initialization information stored in a non-volatile memory embedded in the storage device and setting it in a setting register when the storage device boots up. Claim 11 A method according to claim 10, wherein the initialization information comprises at least one of protection information for prohibiting the programming / erasing of the non-volatile memory, trimming data for trimming the operating voltage level in the operating mode, column repair information for rescuing failed bitlines, or bad block information including bad memory cells. Claim 12 A method for link startup between a host and a storage device connected through at least one lane, comprising: initializing the host in a high-speed mode; establishing data communication through a connected transmitting lane and a connected receiving lane among the at least one lane; determining whether a high-speed link-up is received from the storage device through the connected receiving lane of the host; and, as a result of the determination, recognizing the connected receiving lane through which the high-speed link-up is received from the storage device. A method comprising the step of performing a link startup in high-speed mode through the connected transmission lane of the storage device and the connected reception lane of the host as the connected reception lane receiving the high-speed link-up is recognized, and the step of determining whether the high-speed link-up is received from the storage device through the connected reception lane of the host includes the step of transitioning the line of the connected transmission lane of the storage device from a zero differential line voltage (DIF-Z) to an activation section having a negative differential line voltage (DIF-N), wherein if the length of the activation section (TACTIVATE) is less than a second time, the connected transmission lane of the storage device and the reception lane of the host enter high-speed mode (HS-MODE), and if the length of the activation section (TACTIVATE) is greater than or equal to the second time, the connected transmission lane of the storage device and the reception lane of the host enter low-speed mode (LS-MODE). Claim 13 In claim 12, the step of determining whether the high-speed link-up is received from the storage device through the connected receiving lane of the host comprises the step of transitioning the line of the connected transmitting lane of the storage device from a zero differential line voltage (DIF-Z) to a negative differential line voltage (DIF-N), and then transitioning to a line-reset interval having a positive differential line voltage (DIF-P), and setting the length of the line-reset interval to be greater than or equal to a first time. Claim 14 In paragraph 13, the method wherein the first time is set to 3.1ms. Claim 15 delete Claim 16 In paragraph 12, the method in which the second time is set to 0.9ms. Claim 17 In paragraph 12, the method in which the second time is set to 1.6ms. Claim 18 In claim 12, the step of determining whether the high-speed link-up is received from the storage device through the connected receiving lane of the host comprises the step of receiving a high-speed link startup primitive indicating the high-speed link-up through the connected receiving lane of the host. Claim 19 A method according to claim 18, wherein the high-speed link startup primitive is received carried on a first trigger event of a link startup sequence, and the first trigger event of the link startup sequence is performed such that the physical lane number of the connected transmission lane of the storage device is received on the connected reception lane of the host. Claim 20 In claim 18, the step of recognizing the connected receiving lane in which the high-speed link-up is received from the storage device comprises the step of receiving the high-speed link startup primitive within a third time from the release of the reset signal at the host.

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