Memory device reducing power noise in refresh operation and Operating Method thereof

Abstract

A memory device that reduces power noise in a refresh operation and a method of operating the same are disclosed. A method of operation of a memory device according to one aspect of the technical concept of the present disclosure comprises: a step of performing a first normal refresh that simultaneously refreshes N word lines among a plurality of word lines at a first refresh timing in response to the reception of a first refresh command; a step of performing a first target refresh on a first weak word line adjacent to the most active maximum active word line among the plurality of word lines at a second refresh timing in response to the reception of the first refresh command; a step of performing a second normal refresh that simultaneously refreshes N other word lines among the plurality of word lines at a first refresh timing in response to the reception of a second refresh command; and a step of performing a second target refresh on a second weak word line adjacent to the maximum active word line at a second refresh timing in response to the reception of the second refresh command.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a memory device and a method of operating the same, and more specifically, to a memory device and a method of operating the same that reduces power noise in a refresh operation. Background Technology

[0002] Memory devices widely used in high-performance electronic systems are increasing in integration density and speed. When the access frequency of specific memory cells in memory devices such as DRAM (Dynamic Random Access Memory) increases, adjacent memory cells become stressed, and consequently, the data retention characteristics of adjacent memory cells deteriorate, leading to lower data reliability. For example, when a specific word line is intensively active, the data retention characteristics of memory cells connected to one or more word lines located adjacent to the specific word line may deteriorate; therefore, to ensure data reliability, a targeted refresh may be performed on the adjacent word lines.

[0003] However, as the integration density of memory devices increases, the number of word lines to be refreshed increases. There is a limit to the number of refresh timings within the refresh cycle required by DRAM specifications, and additionally, since target refreshes need to be performed within the refresh cycle, a large number of word lines may be refreshed simultaneously in a specific time interval, and in this case, there is a problem that power noise may increase. The problem to be solved

[0004] The problem that the technical concept of the present invention aims to solve is to provide a memory device and a method of operation thereof that can reduce power noise by optimally performing normal refresh and target refresh for a plurality of word lines. means of solving the problem

[0005] To achieve the above objectives, a method of operation of a memory device according to one aspect of the technical concept of the present disclosure comprises: a step of performing a first normal refresh that simultaneously refreshes N word lines among a plurality of word lines at a first refresh timing in response to the reception of a first refresh command; a step of performing a first target refresh on a first weak word line adjacent to the most active maximum word line among the plurality of word lines at a second refresh timing in response to the reception of the first refresh command; a step of performing a second normal refresh that simultaneously refreshes N other word lines among the plurality of word lines at a first refresh timing in response to the reception of a second refresh command; and a step of performing a second target refresh on a second weak word line adjacent to the maximum active word line at a second refresh timing in response to the reception of the second refresh command.

[0006] Meanwhile, a memory device according to one aspect of the technical concept of the present disclosure comprises a memory cell array including a plurality of word lines, a refresh controller that controls a refresh operation for the plurality of word lines and schedules a normal refresh operation and a target refresh operation for the plurality of word lines, and a control logic that determines at least one weak word line for which the target refresh is to be performed based on counting the number of actives for the plurality of word lines, wherein the refresh controller performs scheduling so that the normal refresh operation and the target refresh operation are performed together during a refresh interval defined in response to the reception of a refresh command, and wherein, during the refresh interval, the number of word lines refreshed simultaneously in the normal refresh operation is greater than the number of word lines refreshed in the target refresh operation.

[0007] Meanwhile, a memory system according to one aspect of the technical concept of the present disclosure comprises: a memory cell array including a plurality of word lines; a memory device including a refresh controller that controls a refresh operation for the plurality of word lines and schedules a normal refresh operation for the plurality of word lines and a target refresh operation for a weak word line; and a memory controller that controls access to the memory device by providing a command and an address for the memory device, wherein the memory device performs scheduling such that the normal refresh operation and the target refresh operation are performed together during a refresh interval defined in response to the reception of a refresh command from the memory controller, and wherein, during the refresh interval, the number of word lines refreshed simultaneously in the normal refresh operation is greater than the number of word lines refreshed in the target refresh operation. Effects of the invention

[0008] According to the memory device and the method of operation of the technical concept of the present invention, there is an effect of reducing power noise that may occur as a large number of word lines are refreshed over a relatively short period of time.

[0009] In addition, according to the memory device and method of operation of the technical concept of the present invention, since a target refresh is performed on weak word lines with a high probability of data loss, there is an effect of improving data reliability while minimizing the increase in power noise. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. Figure 2 is a diagram showing an example of a weak wordline where a target refresh is performed. FIG. 3 is a schematic diagram illustrating a 2-series refresh according to an exemplary embodiment of the present disclosure. FIG. 4 is a drawing illustrating an example of a refresh operation according to an exemplary embodiment of the present disclosure. FIG. 5 is a flowchart illustrating a method of operation of a memory device according to an exemplary embodiment of the present disclosure. FIG. 6 is a drawing illustrating an example of a refresh operation in any one bank according to an exemplary embodiment of the present disclosure. FIG. 7 is a block diagram showing a specific implementation example of a memory device according to an exemplary embodiment of the present disclosure. FIG. 8 is a drawing illustrating an example of a refresh operation of a memory device according to various embodiments of the present disclosure. FIG. 9 is a drawing showing an example of a refresh operation of a memory device according to another embodiment of the present disclosure. FIG. 10 is a flowchart illustrating a method of operation of a memory system including a memory device of the present disclosure. FIG. 11 is a block diagram showing a memory system of an exemplary embodiment of the present disclosure. FIG. 12 is a drawing showing an example of the operation of a memory device according to another embodiment of the present disclosure. FIG. 13 is a block diagram showing a data center including a system according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0012] FIG. 1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure.

[0013] Referring to FIG. 1, the memory system (10) may include a memory controller (100) and a memory device (200). The memory device (200) may include a memory cell array (210), a refresh controller (220), and control logic (230). Additionally, according to an exemplary embodiment of the present disclosure, the control logic (230) may include a weak wordline determiner (231). The control logic (230) may further include other components for controlling memory operations in addition to the weak wordline determiner (231). That is, the control logic (230) may be defined as a concept that includes various types of components within the memory device (200).

[0014] The memory controller (100) controls memory operations such as writing and reading by providing various signals to the memory device (200) through an interface circuit (not shown). For example, the memory controller (100) can access data (DATA) of the memory cell array (210) by providing a command (CMD) and an address (ADD) to the memory device (200). The command (CMD) may include commands for normal memory operations such as writing and reading data. Additionally, if the memory device (200) includes DRAM (Dynamic Random Access Memory) cells, the command (CMD) may include various operations unique to DRAM, such as a refresh command for refreshing memory cells.

[0015] The memory controller (100) can access the memory device (200) in response to a request from the host (HOST). The memory controller (100) can communicate with the host (HOST) using various protocols. The memory cell array (210) may include a plurality of memory cells, and for example, the memory cell array (210) may include a plurality of word lines, and a plurality of memory cells may be connected to each word line. For example, memory cells connected to a single word line may be referred to as rows. That is, the memory cell array (210) may include a plurality of rows. In describing exemplary embodiments of the present disclosure, performing a refresh on a word line may mean performing a refresh on memory cells (or rows) connected to a single word line, and accordingly, phrases such as refresh on a word line and refresh on a row may be used interchangeably.

[0016] Meanwhile, according to an exemplary embodiment of the present disclosure, when one wordline is intensively or frequently active (or accessed), the memory cells of a wordline located adjacent to the intensively active wordline (hereinafter referred to as a weak wordline) are subjected to electromagnetic interference, and in particular, as the integration density of the memory device (200) increases, the degree of interference received by the weak wordline may increase. Accordingly, the data of the memory cells connected to the weak wordline is more likely to be flipped, and in order to ensure data reliability in response to such phenomena, a target refresh for the weak wordline may be performed at a predetermined period or non-periodically.

[0017] Additionally, in the memory cell array (210), a plurality of wordlines may have a structure in which they are arranged side by side, and two wordlines located adjacent to both sides of the intensively accessed wordline may correspond to the aforementioned weak wordline. Alternatively, in an exemplary embodiment, as at least two wordlines adjacent to one side of the intensively accessed wordline correspond to the aforementioned weak wordline, three or more weak wordlines may be determined in relation to the intensively accessed wordline.

[0018] Meanwhile, the refresh controller (220) may perform a refresh on the word lines (or rows) of the memory cell array (210) in response to a refresh command from the memory controller (100). Alternatively, the refresh controller (220) may refresh the word lines of the memory cell array (210) in a self-refresh mode without intervention from the memory controller (100). Additionally, according to one embodiment, when a specific word line is accessed intensively, the refresh controller (220) may control a target refresh operation for one or more weak word lines adjacent to the intensively accessed word line based on the control of the control logic (230).

[0019] In an exemplary embodiment, the weak wordline determiner (231) can determine the wordline that is most active during a predetermined period based on the result of determining the number of active times for a plurality of wordlines, and can determine the location of one or more weak wordlines adjacent to the wordline that is most active. Additionally, information related to the determined weak wordlines may be provided to the refresh controller (220). However, the embodiments of the present disclosure are not limited thereto, and the components for determining the weak wordline may be implemented in various ways within the memory device (200), for example, the components for determining the weak wordline may be implemented outside the control logic (230).

[0020] According to an exemplary embodiment of the present disclosure, the refresh controller (220) can control a normal refresh operation and a target refresh operation. For example, a command (CMD) from the memory controller (100) may include a refresh command, and the refresh controller (220) may selectively perform a normal refresh operation and a target refresh operation in response to the refresh command. For example, the refresh controller (220) may include a scheduler (221), and the scheduler (221) may perform scheduling for a normal refresh operation and a target refresh operation.

[0021] According to an exemplary embodiment of the present disclosure, a memory device (200) may perform at least two refresh operations in response to a refresh command from a memory controller (100). For example, if a refresh operation is performed at N timings in response to a refresh command, this may be referred to as an N series refresh. For example, a time interval (e.g., refresh interval) in which a refresh is performed in response to a refresh command may be defined by the parameter tRFC, and N refresh operations may be performed sequentially within the refresh interval (tRFC). Additionally, all wordlines of the memory device (200) need to be refreshed at least once within a predetermined refresh cycle, and the interval in which a refresh command is received from the memory controller (100) (e.g., refresh reception interval) may be defined by the parameter tREFI.

[0022] Power noise may increase when multiple word lines are refreshed simultaneously or when refresh operations for many word lines are concentrated over a short period of time, which may cause a decrease in data reliability. However, according to an exemplary embodiment of the present disclosure, a scheduling operation may be performed so that a normal refresh operation and a target refresh operation are performed at appropriate timings, and accordingly, power noise may be reduced. For example, when a memory device (200) performs an N series refresh, based on the above-described scheduling operation, a normal refresh operation may be performed at some refresh timings and a target refresh operation may be performed at other refresh timings in response to a refresh command.

[0023] In order to improve the data retention characteristics in the memory device (200), a refresh cycle having a predetermined time is set, and as the density of the memory device (200) improves, the number of word lines provided in the memory cell array (210) may increase, and in this case, multiple word lines may be normal refreshed simultaneously at one refresh timing. On the other hand, in the case of a target refresh operation, since a refresh is selectively performed on one or two weak word lines adjacent to any one word line, one or a relatively small number of word lines may be refreshed at one refresh timing. In the embodiment of the present disclosure, since normal refresh and target refresh are performed together during one refresh interval (tRFC), the case in which a large number of word lines are refreshed during a short time interval can be reduced or prevented as the normal refresh operation is performed continuously during one refresh interval (tRFC), and accordingly, power noise can be reduced.

[0024] Meanwhile, in the above-described embodiment, the criteria for determining a weak wordline were described as including an operation to determine the most active wordline in a predetermined section, but the embodiments of the present disclosure are not limited thereto. A weak wordline may be determined by various criteria, and as an example, a wordline that has been continuously active above a predetermined threshold value may be determined, and one or more wordlines adjacent to the wordline that has been continuously active may be determined as the above-described weak wordline.

[0025] Meanwhile, the refresh controller (220) includes a counter (not shown) that generates an address (e.g., a normal address) for indicating a wordline where a normal refresh is to be performed, and the scheduler (221) can receive an address (e.g., a target address) for indicating a weak wordline where a target refresh is to be performed from the control logic (230) along with the normal address. Additionally, based on the control of the control logic (230), the scheduler (221) can output a normal refresh at the timing when a normal refresh is to be performed and output a target refresh at the timing when a target refresh is to be performed.

[0026] As target refresh is performed for weak wordlines, the number of normal refresh timings within one refresh cycle is reduced, and as a result, power noise may increase as a large number of wordlines are refreshed during a predetermined time interval (e.g., a short time interval). According to the embodiment of the present disclosure as described above, the number of cases where a large number of wordlines are refreshed within a short time interval can be reduced, and data reliability can be effectively improved in response to power noise.

[0027] Meanwhile, the memory device (200) may be a dynamic random access memory such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc. However, the embodiments of the present disclosure are not limited thereto, and the embodiments of the present disclosure may be applied to a memory device that performs a data retention operation corresponding to a refresh, such as a non-volatile memory such as MRAM (Magnetic RAM), FeRAM (Ferroelectric RAM), PRAM (Phase change RAM), and ReRAM (Resistive RAM), as an example.

[0028] Meanwhile, the memory device (200) may be a single memory chip, or a semiconductor package including two or more memory chips. Alternatively, the memory device (200) may be a memory module in which a plurality of memory chips are mounted on a module board. Alternatively, although the memory controller (100) and the memory device (200) are shown as being configured separately in FIG. 1, the memory device (200) of the present disclosure may be implemented as a memory system in which a memory control function and a memory cell array are integrated into a single semiconductor package.

[0029] Figure 2 is a diagram showing an example of a weak wordline where a target refresh is performed.

[0030] Referring to FIG. 2, the memory cell array (210) includes a plurality of word lines (WL1 to WLm), and the most active word line among the plurality of word lines (WL1 to WLm) can be determined according to a predetermined period. Assuming that the k-th word line (WLk) is the most active word line, at least one word line adjacent to the k-th word line may be subject to significant electromagnetic interference, and accordingly, said at least one adjacent word line may correspond to a weak word line.

[0031] Weak word lines may be located on both sides based on the k-th word line (WLk). For example, a weak word line located on one side of the k-th word line (WLk) may be referred to as the first weak word line (weak WL 1), and a weak word line located on the other side may be referred to as the second weak word line (weak WL 2). In an exemplary embodiment, a single word line located on one side based on the k-th word line (WLk) may be determined to be a weak word line, in which case the first weak word line (weak WL 1) may include a single word line. Alternatively, two or more word lines located on one side may be determined to be weak word lines, in which case the first weak word line (weak WL 1) may include two or more word lines.

[0032] In an exemplary embodiment, a target refresh may be performed for one wordline at a single refresh timing. Additionally, when N refreshes are performed in response to a single refresh command from a memory controller (where N is an integer greater than or equal to 2), some of the N refreshes may correspond to a target refresh. Accordingly, the case where a normal refresh is performed consecutively in response to a single refresh command may be prevented or reduced, and power noise may be reduced by preventing a large number of wordlines from being refreshed intensively over a short period of time.

[0033] FIG. 3 is a schematic diagram illustrating a 2-series refresh according to an exemplary embodiment of the present disclosure.

[0034] Referring to FIG. 3, multiple refresh commands may be provided from a memory controller to a memory device within a single refresh cycle, and a refresh interval (tRFC), which is defined as various parameters in the DRAM specification, may correspond to a time interval in which a refresh is performed within the memory device in response to a single refresh command. If two refresh operations are performed as there are two refresh timings during one refresh interval (tRFC), the memory device may be referred to as performing a two-series refresh operation. For example, whenever a refresh command is received from a memory controller, the memory device may determine any two points in time for a refresh to be performed within a refresh interval (tRFC) defined as a predetermined parameter, and may include components such as a counter circuit for determining the points in time.

[0035] In an exemplary embodiment, the memory device of the present disclosure may perform multiple types of refresh operations together within a single refresh interval (tRFC). For example, the refresh operation may include a normal refresh operation performed sequentially on multiple word lines and a target refresh operation performed selectively on specific word lines. Additionally, information on word lines with relatively low data retention characteristics may be stored in the memory system during the manufacturing or testing process of the memory device, and the refresh operation may further include a refresh operation for word lines with low characteristics (e.g., may be referred to as a care refresh for defective word lines). For example, the memory device of the present disclosure may perform at least two types of refresh operations among the various types of refresh operations described above together within a single refresh interval (tRFC).

[0036] In an exemplary embodiment, when the memory device performs a 2-series refresh operation, it may perform a normal refresh and a target refresh together in response to a single refresh command from the memory controller. Alternatively, in an exemplary embodiment, the memory device may perform a normal refresh and a care refresh together in response to a single refresh command from the memory controller. In addition, the memory device may perform various other types of refresh operations, and at least two types of refresh operations selected from among the various types of refresh operations may be performed together in a single refresh interval (tRFC).

[0037] FIG. 4 is a drawing illustrating an example of a refresh operation according to an exemplary embodiment of the present disclosure.

[0038] The number of word lines provided in the memory device may vary depending on the capacity of the memory device, and in the example of FIG. 4 (a), a case is exemplified in which a DRAM chip including a DRAM cell as a memory device has a capacity of 8Gb, 12Gb, 16Gb, and 24Gb. In one embodiment, the memory cell array of the DRAM chip includes a plurality of bank groups (BG), and each bank group (BG) may include four banks (BA), and a different number of word lines may be arranged in each bank according to the memory capacity of the DRAM chip. As an example, when the DRAM chip has a capacity of 8Gb, 32k word lines may be arranged in one bank; when it has a capacity of 12Gb, 48k word lines may be arranged; when it has a capacity of 16Gb, 64k word lines may be arranged; and when it has a capacity of 24Gb, 96k word lines may be arranged.

[0039] If the refresh cycle of the memory device is defined as 64ms and it is assumed that 8k refresh commands are provided from the memory controller to the memory device during the refresh cycle according to the refresh command reception interval (tREFI) at which refresh commands are received, then when the memory device performs 2 series refreshes, 16k refresh operations can be performed during one refresh cycle. In this case, if 32k word lines are placed in each bank as the memory capacity corresponds to 8Gb, then 2 word lines need to be refreshed simultaneously for every refresh operation (e.g., normal refresh operation).

[0040] Meanwhile, when the memory device performs a target refresh according to the above-described embodiment, the target refresh may be performed in some of the refresh operations among the 16k refresh operations described above. For example, if the normal refresh operation and the target refresh operation are performed in a 1:1 ratio, the normal refresh operation and the target refresh operation may each be performed 8k times within a single refresh cycle. In this case, in order for the normal refresh operation to be performed for all 32k word lines, it is necessary for 4 word lines to be refreshed simultaneously in each normal refresh operation.

[0041] FIG. 4(b) illustrates an example of a refresh operation in a memory device having a capacity of 8 Gb, and shows an example of a refresh operation when the first to fourth refresh commands (C_Ref 1 to C_Ref 4) are received. Additionally, in the first row of FIG. 4(b), an example is shown in which only a normal refresh operation (N) is performed without a target refresh operation (T) being performed; in the second row of FIG. 4(b), an example is shown in which a target refresh operation (T) and a normal refresh operation (N) are performed when the embodiment of the present disclosure is not applied; and in the third row of FIG. 4(b), an example is shown in which a target refresh operation (T) and a normal refresh operation (N) are performed according to an embodiment of the present disclosure. In addition, for the second and third rows of Fig. 4(b), the target refresh operation (T) and the normal refresh operation (N) are assumed to be performed in a 1:1 ratio.

[0042] As shown in the first row of FIG. 4(b), two refresh operations can be performed in response to each of the first to fourth refresh commands (C_Ref 1 to C_Ref 4), and according to the above-described embodiment, two word lines can be refreshed simultaneously in one refresh operation.

[0043] On the other hand, as illustrated in the second row of (b) of FIG. 4, only the same type of refresh operation is performed in response to each refresh command, and since a target refresh is performed at a refresh operation timing corresponding to half of the multiple refresh operations included in one refresh cycle, a refresh operation can be performed simultaneously for four word lines in one normal refresh operation (N). Additionally, the time interval (2 * tREFI) during which two refresh commands are received may correspond to a unit for determining the most active word line, and two word lines adjacent to both sides of the most active word line may be determined as weak word lines, and a target refresh for the two weak word lines may be performed during the cycle for determining the most active word line.

[0044] For example, in response to a first refresh command (C_Ref 1), two normal refresh operations may be performed, and four wordlines may be refreshed simultaneously in each normal refresh operation. Subsequently, in response to a second refresh command (C_Ref 2), two target refresh operations may be performed, and one weak wordline may be refreshed in each target refresh operation. The normal refresh operations (N) and target refresh operations (T) described above may be performed alternately whenever a refresh command is received.

[0045] Meanwhile, according to an embodiment of the present disclosure illustrated in the third row of FIG. 4(b), a normal refresh operation (N) and a target refresh operation (T) may be performed together in response to a refresh command. For example, in response to a first refresh command (C_Ref 1), four word lines may be normally refreshed simultaneously at the first refresh timing, and then a target refresh operation (T) for one weak word line may be performed at the next refresh timing. Similarly, in response to a second refresh command (C_Ref 2), four word lines may be normally refreshed simultaneously, and then a target refresh operation (T) for one weak word line may be performed. Meanwhile, although an example has been provided in which a normal refresh operation (N) is performed first in response to each refresh command and then a target refresh operation (T) is performed, in an exemplary embodiment of the present disclosure, the normal refresh operation (N) may be performed after the target refresh operation (T) is performed.

[0046] According to the exemplary embodiment of the present disclosure as described above, the number of word lines refreshed during a relatively short time interval (e.g., a refresh interval) can be reduced, and as shown in the third row of FIG. 4(b) as an example, the number of word lines refreshed simultaneously can be uniformized overall, thereby reducing power noise. In addition, in the exemplary embodiment of the present disclosure, when the capacity of the memory device is greater than a predetermined size, a large number of word lines corresponding to multiples of 4 can be normally refreshed simultaneously in a single refresh timing, but since the number of cases where normal refresh is performed continuously within a relatively short time interval can be reduced, power noise can be reduced.

[0047] FIG. 5 is a flowchart illustrating a method of operation of a memory device according to an exemplary embodiment of the present disclosure.

[0048] Referring to FIG. 5, the memory device may periodically receive a refresh command from a memory controller, and, for example, receive a first refresh command (S11). The memory device may perform an N-series refresh in response to the reception of each refresh command, and, for example, may perform a normal refresh for a plurality of first wordlines at each of some of the N refresh timings in response to the reception of the first refresh command (S12). Then, may perform a target refresh for a first target wordline at each of the other of the N refresh timings (S13), and, for example, the first target wordline may include at least one wordline.

[0049] Subsequently, the memory device may receive a second refresh command from the memory controller (S14), and may perform a normal refresh on a plurality of second wordlines at each of some of the N refresh timings in response to the reception of the second refresh command (S15). Then, may perform a target refresh on a second target wordline at each of the other of the N refresh timings (S16).

[0050] In an exemplary embodiment, a normal refresh operation may be performed based on a normal address that sequentially indicates a plurality of word lines, and the normal address may be generated based on a counting operation. Additionally, the plurality of first word lines may include two or more word lines located apart by a predetermined number of word lines in any bank of the memory cell array. Accordingly, the plurality of second word lines may include word lines located adjacent to the first word lines.

[0051] FIG. 6 is a diagram illustrating an example of a refresh operation in any one bank according to an exemplary embodiment of the present disclosure. FIG. 6 illustrates a case in which a memory device performs two series refreshes and also performs one normal refresh and one target refresh together in response to each refresh command.

[0052] First, upon receiving a first refresh command (C_Ref 1) from the memory controller, the memory device may perform two refresh operations within the refresh interval (tRFC), and as an example, may perform a normal refresh operation at the first refresh timing and a target refresh operation at the second refresh timing. Depending on the number of word lines provided in the memory device, multiple word lines may be refreshed simultaneously during the normal refresh operation, and as an example, a case in which four word lines are refreshed simultaneously during the first refresh timing is exemplified.

[0053] Meanwhile, the most active wordline during a predetermined time interval can be determined, and, for example, at least two weak wordlines can be determined based on the most active wordline determined during a predetermined interval prior to the reception of the first refresh command (for example, a time interval during which two refresh commands are received from the memory controller). If it is assumed that the most active wordline is the k-th wordline (WL k), a target refresh for the first weak wordline (weak WL 1) adjacent to one side of the k-th wordline (WL k) can be performed at the second refresh timing responding to the first refresh command.

[0054] Meanwhile, the memory device subsequently receives a second refresh command (C_Ref 2) from the memory controller, and a normal refresh may be performed at the first refresh timing in response to the second refresh command. As an example, as the normal refresh proceeds sequentially for word lines based on address counting, four word lines adjacent to the four word lines for which a normal refresh was performed in response to the preceding first refresh command may be refreshed simultaneously.

[0055] Meanwhile, a target refresh may be performed at a second refresh timing in response to a second refresh command (C_Ref 2), and a target refresh may be performed for a second weak wordline (weak WL 2) adjacent to the other side of the most active wordline determined earlier (e.g., the k-th wordline (WL k)). As such a target refresh operation is added to the refresh cycle, some wordlines may be refreshed at least twice within one refresh cycle.

[0056] FIG. 7 is a block diagram showing a specific implementation example of a memory device according to an exemplary embodiment of the present disclosure.

[0057] Referring to FIG. 7, the memory device (300) may include control logic (310), a refresh controller (320), refresh logic (330), and a memory cell array (340). The components illustrated in FIG. 7 are for one implementable embodiment, and some of the components within the refresh controller (320) illustrated in FIG. 7 may be described as being provided in the control logic (310) or as being located separately outside the refresh controller (320).

[0058] The control logic (310) can perform control related to the refresh operation according to the embodiments described above, and, as an example, can provide a normal refresh address (or normal address (ADD_N)) that can be generated based on the counting operation of a counter circuit (not shown) inside to the refresh controller (320). Additionally, the refresh controller (320) may include a first address buffer (321), a second address buffer (322), an address selector (323), a maximum active address generator (324), an address converter (325), and a refresh scheduler (326).

[0059] The maximum active address generator (324) may include a counter circuit (not shown) internally and may count the number of active times for each word line during a predetermined period and may generate the address of the most active word line based on the counting result. Additionally, the address converter (325) may perform an address conversion operation to generate the address of a weak word line adjacent to the most active word line, and as an example, by adding 1 to the address of the most active word line, a target address (ADD_T) indicating a weak word line adjacent to one side of the most active word line may be generated, and by subtracting 1 from the address of the most active word line, a target address (ADD_T) indicating a weak word line adjacent to the other side of the most active word line may be generated. Additionally, the normal address (ADD_N) is stored in the first address buffer (321), the target address (ADD_T) is stored in the second address buffer (322), and the normal address (ADD_N) and the target address (ADD_T) can be provided as inputs to the address selector (323).

[0060] Meanwhile, the address selector (323) can selectively output a normal address (ADD_N) or a target address (ADD_T) in response to a refresh control signal (Ctrl_R), and as a two-series refresh operation is performed based on the embodiments of the present disclosure, the address selector (323) can alternately output the normal address (ADD_N) and the target address (ADD_T) during one refresh interval. The normal address (ADD_N) or the target address (ADD_T) output from the address selector (323) can be provided to a refresh scheduler (326), and the refresh scheduler (326) can schedule the refresh timing. For example, in memory operation, the refresh operation may be performed a predetermined time earlier or delayed, and the refresh timing may be adjusted based on the control of the refresh scheduler (326).

[0061] Meanwhile, the refresh logic (330) can perform an operation to control the memory cell array (340) so that actual refresh is performed based on the control of the refresh scheduler (326), and as an example, can perform a control operation to activate the word line at the location indicated by the normal address (ADD_N) or the target address (ADD_T).

[0062] FIG. 8 is a diagram illustrating an example of a refresh operation of a memory device according to various embodiments of the present disclosure. FIG. 8 illustrates an example of a refresh operation in adjacent first and second banks (BA 1, BA 2). Additionally, a 2-series refresh is performed in response to each refresh command, and a normal refresh operation (N) and a target refresh operation (T) can be performed in a 1:1 ratio, and an example is provided in which four word lines are refreshed simultaneously in each normal refresh operation (N).

[0063] In the case where the embodiment of the present disclosure is not applied as in the first row of FIG. 8, a normal refresh operation (N) may be performed in each of the first and second banks (BA 1, BA 2) in response to a first refresh command (C_Ref 1), and as an example, four word lines per bank may be refreshed simultaneously at each of the first and second refresh timings of a single refresh interval. In this case, at one refresh timing, not only are eight word lines located in adjacent first and second banks (BA 1, BA 2) refreshed simultaneously, but a total of 16 word lines may be refreshed at the first and second refresh timings corresponding to a relatively short time interval.

[0064] Meanwhile, in response to the second refresh command (C_Ref 2), a target refresh operation (T) may be performed in each of the first and second banks (BA 1, BA 2), and at each refresh timing within a refresh interval, a target refresh operation (T) for one wordline in one bank may be performed. Similarly, in response to the third refresh command (C_Ref 3), a normal refresh operation (N) may be performed in each of the first and second banks (BA 1, BA 2), and in response to the fourth refresh command (C_Ref 4), a target refresh operation (T) may be performed in each of the first and second banks (BA 1, BA 2).

[0065] According to the above example of operation, in the refresh operation performed in response to the first refresh command (C_Ref 1) and the third refresh command (C_Ref 3), a very large number of word lines may be refreshed in a concentrated manner during a relatively short time interval, so performance degradation due to power noise may occur.

[0066] Meanwhile, when an embodiment of the present disclosure is applied as shown in the second row of FIG. 8, a normal refresh operation (N) and a target refresh operation (T) can be performed together in a single refresh interval. For example, four word lines can be normal refreshed simultaneously at one refresh timing of a single refresh interval, and one weak word line can be target refreshed at another refresh timing.

[0067] In an exemplary embodiment, at any one refresh timing, different types of refreshes may be performed for the first bank (BA 1) and the second bank (BA 2). For example, at the first refresh timing responding to the first refresh command (C_Ref 1), four wordlines may be refreshed simultaneously as a normal refresh operation (N) is performed in the first bank (BA 1), whereas one weak wordline may be refreshed as a target refresh operation (T) is performed in the second bank (BA 2). Additionally, at the second refresh timing in response to the first refresh command (C_Ref 1), one weak wordline is refreshed as a target refresh operation (T) is performed in the first bank (BA 1), while four wordlines can be normally refreshed simultaneously as a normal refresh operation (N) is performed in the second bank (BA 2).

[0068] Similarly, for each of the second refresh command (C_Ref 2) to the fourth refresh command (C_Ref 4), there may be two refresh timings in response to each refresh command, and at each refresh timing, a normal refresh operation (N) may be performed on one of the first and second banks (BA 1, BA 2), while a target refresh operation (T) may be performed on the other bank.

[0069] According to an exemplary embodiment of the present disclosure as described above, by applying different types of refresh operations at the same refresh timing to adjacent banks, the number of word lines refreshed simultaneously at each refresh timing can be equalized, thereby reducing power noise. For example, when a normal refresh operation (N) in which multiple word lines are refreshed simultaneously is applied to multiple adjacent banks, power noise may increase as a large number of word lines are refreshed simultaneously, whereas according to the embodiment of the present disclosure described above, the number of word lines refreshed simultaneously at each refresh timing can be reduced.

[0070] FIG. 9 is a diagram illustrating an example of a refresh operation of a memory device according to another embodiment of the present disclosure. In FIG. 9, in an exemplary embodiment of the present disclosure, a case is illustrated in which a 3-series refresh is performed in response to each refresh command.

[0071] In the case of the first row of FIG. 9, it indicates a case where a 2-series refresh is performed without applying an embodiment of the present disclosure and a target refresh operation (T) is not performed, and there are two refresh timings in response to each of the first refresh command (C_Ref 1) to the fourth refresh command (C_Ref 4), and a normal refresh operation (N) can be performed for four word lines at each refresh timing. Meanwhile, the second row of FIG. 9 represents a case where a 2-series refresh is performed and a target refresh operation (T) is performed without applying an embodiment of the present disclosure, and there are two refresh timings in response to each of the first refresh command (C_Ref 1) to the fourth refresh command (C_Ref 4), and in response to one of the refresh commands, only a normal refresh operation (N) is performed, whereas in response to the other refresh command, only a target refresh operation (T) can be performed. At this time, when the normal refresh operation (N) is performed, eight word lines can be refreshed simultaneously, and when the target refresh operation (T) is performed, a target refresh can be performed on one weak word line.

[0072] Meanwhile, when an embodiment of the present disclosure is applied as shown in the third row of FIG. 9, there are three refresh timings in one refresh interval, and a normal refresh operation (N) may be performed in some of the three refresh timings, and a target refresh operation (T) may be performed in other parts. For example, a case is exemplified in which two normal refresh operations (N) and one target refresh operation (T) are performed in response to one refresh command.

[0073] The number of times the normal refresh operation (N) and the target refresh operation (T) are performed can be set in a predetermined ratio, and according to an exemplary embodiment, the number of times the normal refresh operation (N) and the target refresh operation (T) are performed can be set in a ratio of 2:1. In this case, in one example of operation, in response to one refresh command, four word lines may be refreshed simultaneously in each normal refresh operation (N), whereas one weak word line may be refreshed in the target refresh operation (T). Also, in an exemplary embodiment, the normal refresh operation (N), the target refresh operation (T), and the normal refresh operation (N) may be performed sequentially in response to each refresh command.

[0074] According to the exemplary embodiment described above, the number of word lines that are refreshed simultaneously at each refresh timing may be reduced, and the number of word lines that are refreshed consecutively may be reduced. For example, the refresh command reception interval may be relatively long in time compared to a single refresh interval (e.g., tRFC), and accordingly, the time interval between the normal refresh operation (N) performed at the third refresh timing in response to the first refresh command (C_Ref 1) and the normal refresh operation (N) performed at the first refresh timing in response to the second refresh command (C_Ref 2) may be relatively long, so the number of word lines that are refreshed intensively during a short time interval may be reduced.

[0075] FIG. 10 is a flowchart illustrating a method of operation of a memory system including a memory device of the present disclosure.

[0076] Referring to FIG. 10, as the memory system is initially started, the initial operation of a memory device provided in the memory system is performed (S21), and various setting information for setting the operating environment of the memory device based on control from a memory controller may be stored in a set of mode registers provided in the memory device. For example, a different number of word lines may be provided in the memory device depending on the capacity of the memory device, and the operating environment according to the capacity of the memory device may be set by the initial operation based on control from the memory controller (S22).

[0077] According to the above-described operation environment settings, the refresh operation of the memory device can be controlled differently depending on whether its capacity is larger or smaller than a reference value (S23). For example, if the capacity of the memory device is larger than a predetermined reference value, it may indicate that the number of word lines provided in the memory device is relatively large, and in this case, the embodiments of the present disclosure may be applied to the refresh operation. That is, if the number of word lines is relatively large, the number of word lines refreshed simultaneously may be relatively large, and accordingly, the refresh operation may be controlled to be performed together with normal refresh and target refresh in response to a single refresh command to reduce power noise (S25).

[0078] On the other hand, if the capacity of the memory device is smaller than a predetermined reference value, it may indicate that the number of word lines provided in the memory device is relatively small, and in such cases, it may indicate that the number of word lines refreshed simultaneously is relatively small. Accordingly, normal refresh and target refresh may be performed separately in response to a single refresh command (S24). For example, multiple normal refreshes may be performed consecutively in response to one refresh command, and multiple target refreshes may be performed consecutively in response to another refresh command.

[0079] FIG. 11 is a block diagram illustrating a memory system of an exemplary embodiment of the present disclosure. FIG. 11 illustrates data access between an application processor (410) and a memory device (420), and the memory system (400) may be defined as a concept including the application processor (410) and the memory device (420), or the memory control module (411) within the application processor (410) and the memory device (420) may be defined as constituting the memory system (400). According to the above-described embodiment, the memory device (420) may include a memory cell array (421), a refresh controller (422), and control logic (424).

[0080] The application processor (410) can be implemented as a System on Chip (SoC). The System on Chip (SoC) may include a system bus (not shown) to which a protocol having a predetermined standard bus specification is applied, and may include various IPs (Intellectual Properties) connected to the system bus. As a standard specification for the system bus, the AMBA (Advanced Microcontroller Bus Architecture) protocol from ARM (Advanced RISC Machine) may be applied. Bus types of the AMBA protocol may include AHB (Advanced High-Performance Bus), APB (Advanced Peripheral Bus), AXI (Advanced eXtensible Interface), AXI4, ACE (AXI Coherency Extensions), etc. In addition, other types of protocols such as SONICs Inc.'s uNetwork, IBM's CoreConnect, or OCP-IP's Open Core Protocol may be applied.

[0081] In an exemplary embodiment, at least some of the control operations related to the refresh operation may be performed on the side of the application processor (410), and as an example, the memory control module (411) may include a weak wordline determiner (411_1). The memory control module (411) may provide a command / address (CMD / ADD) to the memory device (420), thereby determining whether the wordlines provided in the memory device (420) are active, and may determine a weak wordline based on the counting result of the number of active words.

[0082] The refresh controller (422) may include a scheduler (422_1) and may perform scheduling so that normal refresh and target refresh are performed together in any one of the refresh intervals according to the embodiments described above. As an example of operation, the memory control module (411) may provide a target address (ADD_T) representing at least one weak word line to the memory device (420) along with a refresh command, and the memory device (420) may perform a target refresh based on the target address (ADD_T) from the memory control module (411). For example, the memory device (420) may generate a normal address (not shown) to which a normal refresh is to be performed based on an internal counting operation, and may perform a refresh operation to which the embodiments of the present disclosure are applied through a scheduling operation using the normal address and the target address (ADD_T).

[0083] FIG. 12 is a diagram illustrating an example of operation of a memory device according to another embodiment of the present disclosure. FIG. 12 illustrates a case in which a target refresh is selectively performed based on the number of active wordslines that are most active in the target refresh according to embodiments of the present disclosure.

[0084] If the number of active wordslines that are most active within a given period does not exceed a threshold (Th), it corresponds to a case where there are no wordslines that have received significant electromagnetic interference, so the execution of the target refresh can be skipped. In this case, when two refresh operations are performed in a refresh interval (tRFC) that responds to one refresh command, only the normal refresh operation (N) can be performed consecutively.

[0085] On the other hand, if the number of active wordslines that are most active within a given period exceeds a threshold (Th), it corresponds to a case where one or more specific wordslines have been significantly affected by electromagnetic interference, and a target refresh may be performed accordingly. In this case, when two refresh operations are performed in a refresh interval (tRFC) responding to a single refresh command, a normal refresh operation (N) and a target refresh operation (T) may be performed sequentially.

[0086] FIG. 13 is a block diagram showing a data center (500) including a system according to an exemplary embodiment of the present disclosure. In some embodiments, the memory system described above with reference to the drawings may be included in an application server and / or storage server of the data center (500).

[0087] Referring to FIG. 13, the data center (500) may collect various data and provide services, and may also be referred to as a data storage center. For example, the data center (500) may be a system for operating a search engine and database, or a computing system used by a company or government agency such as a bank. As illustrated in FIG. 13, the data center (500) may include application servers (50_1 to 50_n) and storage servers (60_1 to 60_m) (m and n are integers greater than 1). The number of application servers (50_1 to 50_n) n and the number of storage servers (60_1 to 60_m) m may be selected in various ways according to the embodiment, and the number of application servers (50_1 to 50_n) n and the number of storage servers (60_1 to 60_m) m may be different.

[0088] The application server (50_1 to 50_n) may include at least one of a processor (51_1 to 51_n), memory (52_1 to 52_n), a switch (53_1 to 53_n), a network interface controller (NIC) (54_1 to 54_n), and a storage device (55_1 to 55_n). The processor (52_1 to 51_n) can control the overall operation of the application server (50_1 to 50_n) and can access the memory (52_1 to 52_n) to execute instructions and / or data loaded in the memory (52_1 to 52_n). Memory (52_1 to 52_n) may include, as a non-limiting example, DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, or NVMDIMM (Non-Volatile DIMM).

[0089] According to the embodiments, the number of processors and the number of memories included in the application servers (50_1 to 50_n) may be selected in various ways. In some embodiments, the processors (51_1 to 51_n) and the memories (52_1 to 52_n) may provide processor-memory pairs. In some embodiments, the number of processors (51_1 to 51_n) and memories (52_1 to 52_n) may differ. The processors (51_1 to 51_n) may include single-core processors or multi-core processors. In some embodiments, as shown by the dashed line in FIG. 13, the storage devices (55_1 to 55_n) in the application servers (50_1 to 50_n) may be omitted. The number of storage devices (55_1 to 55_n) included in the storage servers (50_1 to 50_n) may be selected in various ways according to the embodiments. Processors (51_1 to 51_n), memory (52_1 to 52_n), switch (53_1 to 53_n), NIC (54_1 to 54_n) and / or storage devices (55_1 to 55_n) can communicate with each other through the links described above with reference to the drawings.

[0090] The storage server (60_1 to 60_m) may include at least one of a processor (61_1 to 61_m), memory (62_1 to 62_m), switch (63_1 to 63_m), NIC (64_1 to 64_n), and storage device (65_1 to 65_m). The processor (61_1 to 61_m) and memory (62_1 to 62_m) may operate similarly to the processor (51_1 to 51_n) and memory (52_1 to 52_n) of the aforementioned application server (50_1 to 50_n).

[0091] The memories (52_1 to 52_n, 62_1 to 62_m) included in the application servers (50_1 to 50_n) and storage servers (60_1 to 60_m) may include memory devices according to the embodiments described above. For example, the memories (52_1 to 52_n, 62_1 to 62_m) may include volatile memory devices such as DRAM, and normal refresh operation and target refresh operation according to the embodiments described above may be performed when performing a refresh operation for a plurality of word lines.

[0092] Application servers (50_1 to 50_n) and storage servers (60_1 to 60_m) can communicate with each other through a network (70). In some embodiments, the network (70) may be implemented using Fibre Channel (FC) or Ethernet, etc. FC may be a medium used for relatively high-speed data transmission, and an optical switch providing high performance / high availability may be used. Depending on the access method of the network (70), the storage servers (60_1 to 60_m) may be provided as file storage, block storage, or object storage.

[0093] In some embodiments, the network (70) may be a storage-dedicated network such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN that utilizes an FC network and is implemented according to the FC Protocol (FCP). Alternatively, the SAN may be an IP-SAN that utilizes a TCP / IP network and is implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In some embodiments, the network (70) may be a general network such as a TCP / IP network. For example, the network (70) may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0094] In the following description, the application server (50_1) and the storage server (60_1) are primarily described, but it should be noted that the description of the application server (50_1) may also apply to other application servers (e.g., 50_n) and the description of the storage server (60_1) may also apply to other storage servers (e.g., 60_m).

[0095] The application server (50_1) can store data requested for storage by a user or client in one of the storage servers (60_1 to 60_m) via the network (70). Additionally, the application server (50_1) can obtain data requested for retrieval by a user or client from one of the storage servers (60_1 to 60_m) via the network (70). For example, the application server (50_1) can be implemented as a web server or a DBMS (Database Management System), etc.

[0096] The application server (50_1) can access memory (52_n) and / or storage device (55_n) contained in another application server (50_n) via the network (70), and / or access memory (62_1 to 62_m) and / or storage device (65_1 to 65_m) contained in storage servers (60_1 to 60_m) via the network (70). Accordingly, the application server (50_1) can perform various operations on data stored in the application servers (50_1 to 50_n) and / or storage servers (60_1 to 60_m). For example, the application server (50_1) can execute commands to move or copy data between the application servers (50_1 to 50_n) and / or storage servers (60_1 to 60_m). At this time, data may be moved from the storage devices (65_1 to 65_m) of the storage servers (60_1 to 60_m) to the memories (62_1 to 62_m) of the storage servers (60_1 to 60_m) or directly to the memories (52_1 to 52_n) of the application servers (50_1 to 50_n). In some embodiments, data moving through the network (70) may be encrypted data for security or privacy.

[0097] In the storage server (60_1), the interface (IF) can provide a physical connection between the processor (61_1) and the controller (CTRL) and a physical connection between the NIC (64_1) and the controller (CTRL). For example, the interface (IF) can be implemented in a Direct Attached Storage (DAS) manner, which directly connects the storage device (65_1) with a dedicated cable. In addition, for example, the interface (IF) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0098] In the storage server (60_1), the switch (63_1) can selectively connect the processor (61_1) and the storage device (65_1) or selectively connect the NIC (64_1) and the storage device (65_1) according to the control of the processor (61_1).

[0099] In some embodiments, the NIC (64_1) may include a network interface card, a network adapter, etc. The NIC (54_1) may be connected to a network (70) by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC (54_1) may include internal memory, a DSP, a host bus interface, etc. and may be connected to a processor (61_1) and / or a switch (63_1), etc., through the host bus interface. In some embodiments, the NIC (64_1) may be integrated with at least one of a processor (61_1), a switch (63_1), and a storage device (65_1).

[0100] In an application server (50_1 to 50_n) or a storage server (60_1 to 60_m), a processor (51_1 to 51_m, 61_1 to 61_n) can program or read data by transmitting commands to storage devices (55_1 to 55_n, 65_1 to 65_m) or memory (52_1 to 52_n, 62_1 to 62_m). At this time, the data may be data that has been error-corrected through an ECC (Error Correction Code) engine. The data may be data that has undergone Data Bus Inversion (DBI) or Data Masking (DM) processing and may include Cyclic Redundancy Code (CRC) information. The data may be data that has been encrypted for security or privacy.

[0101] The storage device (55_1 to 55_n, 65_1 to 65_m) can transmit a control signal and a command / address signal to a non-volatile memory device (e.g., a NAND flash memory device, NVM) in response to a read command received from the processor (51_1 to 51_m, 61_1 to 61_n). Accordingly, when reading data from the non-volatile memory device (NVM), the read enable signal can be input as a data output control signal and serve to output data to the DQ bus. A data strobe signal can be generated using the read enable signal. The command and address signals can be latched according to the rising edge or falling edge of the write enable signal.

[0102] The controller (CTRL) can control the overall operation of the storage device (65_1). In one embodiment, the controller (CTRL) may include Static Random Access Memory (SRAM). The controller (CTRL) can write data to the non-volatile memory device (NVM) in response to a write command, or read data from the non-volatile memory device (NVM) in response to a read command. For example, the write command and / or read command may be generated based on a request provided by a processor (61_1) in a host, such as a storage server (60_1), a processor (61_m) in another storage server (60_m), or a processor (51_1 to 51_n) in an application server (50_1 to 50_n). The buffer (BUF) may temporarily store (buffer) data to be written to the non-volatile memory device (NVM) or data read from the non-volatile memory device (NVM). In some embodiments, the buffer (BUF) may include DRAM. Additionally, the buffer (BUF) may store metadata, and the metadata may refer to user data or data generated by the controller (CTRL) to manage the non-volatile memory device (NVM). The storage device (65_1) may include a Secure Element (SE) for security or privacy.

[0103] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 A method of operation of a memory device, wherein the memory device comprises a plurality of word lines, and at a first refresh timing in response to the reception of a first refresh command, a step of performing a first normal refresh that simultaneously refreshes N word lines among the plurality of word lines (wherein N is an integer greater than or equal to 2); at a second refresh timing in response to the reception of the first refresh command, a step of performing a first target refresh on a first weak word line adjacent to the most active maximum word line among the plurality of word lines; at a first refresh timing in response to the reception of a second refresh command, a step of performing a second normal refresh that simultaneously refreshes N other word lines among the plurality of word lines; and at a second refresh timing in response to the reception of the second refresh command, a step of performing a second target refresh on a second weak word line adjacent to the maximum active word line. Claim 2 A method of operation of a memory device according to claim 1, wherein the first weak word line is the word line closest to the maximum active word line on one side, and the second weak word line is the word line closest to the maximum active word line on the other side. Claim 3 A method of operation of a memory device according to claim 1, wherein the first weak word line comprises at least two word lines adjacent to the maximum active word line on one side, and the second weak word line comprises at least two word lines adjacent to the maximum active word line on the other side. Claim 4 A method of operation of a memory device according to claim 1, wherein the maximum active wordline corresponds to the wordline most actively active during the time interval in which two refresh commands are received. Claim 5 A method of operation of a memory device according to claim 1, wherein the memory device comprises a first bank and a second bank, and at the first refresh timing in response to the reception of the first refresh command, N wordlines of the first bank are refreshed simultaneously and a target refresh is performed on any one of the weak wordlines of the second bank. Claim 6 A method of operation of a memory device according to claim 5, characterized in that, at the second refresh timing responding to the reception of the first refresh command, a target refresh is performed on any one of the weak wordlines of the first bank and N wordlines of the second bank are refreshed simultaneously. Claim 7 A method of operation of a memory device according to claim 1, wherein a refresh interval (tRFC) corresponding to a time interval in which a refresh is performed in response to the reception of the first refresh command is defined, and the first normal refresh and the first target refresh are performed within the refresh interval (tRFC). Claim 8 A method of operation of a memory device according to claim 1, characterized in that, in response to the reception of the first refresh command, the number of word lines simultaneously refreshed in the first normal refresh corresponds to a multiple of 4, and one weak word line is refreshed in the first target refresh. Claim 9 A memory device comprising: a memory cell array including a plurality of word lines; and a refresh controller that controls a refresh operation for the plurality of word lines and schedules a normal refresh operation and a target refresh operation for the plurality of word lines. The present invention comprises a control logic for determining at least one weak wordline on which the target refresh is to be performed based on counting the number of active occurrences for the plurality of wordlines, wherein the refresh controller performs scheduling such that the normal refresh operation and the target refresh operation are performed together during a first refresh interval defined in response to the reception of one refresh command, and the normal refresh operation and the target refresh operation are performed together during a second refresh interval defined in response to the reception of the next refresh command, wherein during the first refresh interval corresponding to the reception of the one refresh command, the target refresh operation is performed for a first weak wordline adjacent to a first wordline that is intensively accessed among the plurality of wordlines, and during the second refresh interval corresponding to the reception of the next refresh command, the target refresh operation is performed for a second weak wordline adjacent to the first wordline and different from the first weak wordline. A memory device that does. Claim 10 In claim 9, the memory device is characterized in that, in response to the reception of the one refresh command, it performs an N-series refresh including N refresh timings during the first refresh interval (wherein N is an integer greater than or equal to 2), and during the refresh interval, the number of times the normal refresh operation is performed and the number of times the target refresh operation is performed are the same. Claim 11 A memory device according to claim 9, wherein the first wordline is the most active wordline among the plurality of wordlines during a predetermined time interval, and the first weak wordline is a weak wordline adjacent to one side of the first wordline. Claim 12 A memory device according to claim 11, characterized in that the second weak wordline is a weak wordline adjacent to the other side of the first wordline. Claim 13 A memory device according to claim 9, wherein the refresh controller generates a normal address indicating word lines to be refreshed in the normal refresh operation, receives a target address indicating the weak word line from the control logic, outputs the normal address at the timing when the normal refresh is to be performed, and outputs the target address at the timing when the target refresh is to be performed. Claim 14 A memory device according to claim 9, wherein the memory cell array comprises a first bank and a second bank, the first refresh interval comprises a first refresh timing and a second refresh timing, and at the first refresh timing, the normal refresh operation is performed for a plurality of word lines of the first bank and the target refresh operation is performed for a weak word line of the second bank. Claim 15 A memory device according to claim 14, characterized in that, at the second refresh timing, the target refresh operation is performed for the weak wordline of the first bank, and the normal refresh operation is performed for a plurality of wordlines of the second bank. Claim 16 A memory device according to claim 9, wherein the weak wordline is a wordline adjacent to the most active wordline during the time interval in which two refresh commands are received. Claim 17 A memory system comprising: a memory cell array including a plurality of word lines; a memory device including a refresh controller that controls a refresh operation for the plurality of word lines and schedules a normal refresh operation for the plurality of word lines and a target refresh operation for a weak word line; and a memory controller that controls access to the memory device by providing a command and an address to the memory device, wherein the memory device performs scheduling such that the normal refresh operation and the target refresh operation are performed together during a refresh interval defined in response to the reception of a single refresh command from the memory controller, wherein during the refresh interval, the number of word lines refreshed simultaneously in the normal refresh operation is greater than the number of word lines refreshed in the target refresh operation, and wherein the memory device performs the normal refresh operation and the target refresh operation once each during the refresh interval in response to the reception of the single refresh command. Claim 18 delete Claim 19 A memory system according to claim 17, wherein the above-mentioned weak wordline includes a first weak wordline and a second weak wordline adjacent to both sides of the wordline most active during a predetermined interval, wherein a target refresh operation for the first weak wordline is performed in the target refresh operation corresponding to the reception of the one refresh command, and a target refresh operation for the second weak wordline is performed in the target refresh operation corresponding to the reception of the next refresh command. Claim 20 A memory system according to claim 17, wherein the memory controller determines the weak word line based on counting the number of active words lines of the memory device and transmits a target address indicating the weak word line to the memory device along with the refresh command.

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