Method of manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device according to the technical concept of the present invention comprises: forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; forming a plurality of first buried films having protrusions that extend to protrude onto the substrate while burying the plurality of first trenches; forming a spacer on the side wall of each protrusion of the plurality of first buried films so that a portion of the substrate is exposed between the plurality of first buried films; etching the substrate exposed through the spacer to form a plurality of second trenches around the plurality of first trenches; forming a plurality of second buried films that bury the plurality of second trenches and have an upper surface at the same level as the upper surface of the substrate; removing all of the plurality of first buried films and the spacer; forming a gate material layer that extends while conformally covering the inner wall of the plurality of first trenches; separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; and forming a third between the pair of gate structures in each of the plurality of first trenches. It includes the step of forming a landfill film.

Description

Technology Field

[0001] The technical field of the present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device using a self-alignment method. Background Technology

[0002] Semiconductor devices are becoming increasingly smaller in volume while requiring high-capacity data processing. Consequently, there is a need to increase the integration density of these devices and to miniaturize the patterns formed on them. As a result, there is a demand for the realization of fine patterns with minute widths and spacing that transcend the resolution limits of photolithography processes. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is that since trenches formed in a subsequent process are self-aligned with the trenches formed first, misalignment is prevented and the reliability of the semiconductor device is improved.

[0004] The problems that the technical concept of the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A method for manufacturing a semiconductor device according to the technical concept of the present invention comprises: forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; forming a plurality of first buried films that fill the plurality of first trenches and have protrusions that extend to protrude onto the substrate; forming a spacer on the side wall of the protrusion of each of the plurality of first buried films so as to expose a portion of the substrate between the plurality of first buried films; etching the substrate exposed through the spacer to form a plurality of second trenches around the plurality of first trenches; forming a plurality of second buried films that fill the plurality of second trenches and have an upper surface at the same level as the upper surface of the substrate; removing all of the plurality of first buried films and the spacer; and forming a gate material layer that extends to conformally cover the inner wall of the plurality of first trenches. The method includes the step of separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; and the step of forming a third buried film between the pair of gate structures in each of the plurality of first trenches.

[0006] A method for manufacturing a semiconductor device according to the technical concept of the present invention comprises: forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; forming a plurality of first filling films that fill the plurality of first trenches and have protrusions that extend to protrude onto the substrate; forming a spacer on the side wall of the protrusion of each of the plurality of first filling films so as to expose a portion of the substrate between the plurality of first filling films; etching the substrate exposed through the spacer to form a plurality of second trenches around the plurality of first trenches; forming a plurality of second filling films that fill the plurality of second trenches and have an upper surface at the same level as the upper surface of the substrate; removing all of the plurality of first filling films and the spacer; and forming a sacrificial material film that extends to conformally cover the inner wall of the plurality of first trenches. The method comprises the steps of: removing and separating a portion of the sacrificial material film from a plurality of first trenches so that a portion of the bottom surface of the plurality of first trenches is exposed; burying the plurality of first trenches and forming a plurality of third burial films in contact with the exposed bottom surface of the plurality of first trenches and the side wall of the sacrificial material film; removing all of the sacrificial material film; and forming a pair of gate structures in each of the plurality of first trenches in the empty space partitioned by the third burial film.

[0007] A method for manufacturing a semiconductor device according to the technical concept of the present invention comprises: forming a mask layer having a plurality of openings on a substrate; etching the substrate using the mask layer as an etching mask to form a plurality of first trenches that are spaced apart from each other in a first horizontal direction and extend in a second horizontal direction orthogonal to the first horizontal direction; removing the mask layer; forming a plurality of sacrificial films that fill the plurality of first trenches; removing the upper portion of the substrate by a predetermined thickness so that a portion of the plurality of sacrificial films protrudes onto the substrate; forming a spacer on the protruding sidewall of the plurality of sacrificial films; etching the substrate exposed through the spacer to form a plurality of second trenches around the plurality of first trenches; forming a plurality of device isolation films that fill the plurality of second trenches and have an upper surface at the same level as the upper surface of the substrate; removing all of the plurality of sacrificial films and the spacer; and forming a gate material layer that extends while conformally covering the inner walls of the plurality of first trenches. The method includes the step of separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; and the step of forming an epitaxial growth film between the pair of gate structures in each of the plurality of first trenches. Effects of the invention

[0008] The method for manufacturing a semiconductor device according to the technical concept of the present invention has the effect of preventing misalignment and improving the reliability of the semiconductor device, because trenches formed in a subsequent process are formed by self-aligning with trenches formed first. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention. FIG. 2 is a layout showing the main configurations of the cell region of a semiconductor device according to an embodiment of the technical concept of the present invention. FIGS. 3a to 3u are cross-sectional views shown in the order of process to explain a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention. FIG. 4 is a block diagram showing a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention. FIGS. 5a to 5k are cross-sectional views shown in the order of process to explain a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention. FIG. 6 is a layout showing the main configurations of a cell region of a semiconductor device according to an embodiment of the technical concept of the present invention, and FIG. 7 is a cross-sectional view showing the cross-sectional configuration of the line XX' of FIG. 6. FIG. 8 is a layout showing a semiconductor device according to an embodiment of the technical concept of the present invention, and FIG. 9 is a cross-sectional view showing the cross-sectional configuration of the XX' line and the YY' line of FIG. 8 together. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a block diagram showing a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention.

[0012] Referring to FIG. 1, the method for manufacturing a semiconductor device (S10) may include a process sequence of steps 1 to 9 (S110 to S190).

[0013] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the description.

[0014] A method for manufacturing a semiconductor device (S10) according to the technical concept of the present invention comprises: a first step (S110) of forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; a second step (S120) of forming a plurality of first buried films having protrusions that extend to protrude onto the substrate while burying the plurality of first trenches; a third step (S130) of forming spacers on the side walls of each of the protrusions of the plurality of first buried films so that a portion of the substrate is exposed between the plurality of first buried films; a fourth step (S140) of etching the substrate exposed through the spacers to form a plurality of second trenches around the plurality of first trenches; a fifth step (S150) of forming a plurality of second buried films having upper surfaces at the same level as the upper surface of the substrate while burying the plurality of second trenches; a sixth step (S160) of removing all of the plurality of first buried films and spacers; and conformally covering the inner walls of the plurality of first trenches. It may include a seventh step (S170) of forming an extended gate material layer, an eighth step (S180) of separating the gate material layer to form a pair of gate structures in each of a plurality of first trenches, and a ninth step (S190) of forming a third filling film between the pair of gate structures in each of the plurality of first trenches.

[0015] The technical features for each of the above-mentioned steps 1 to 9 (S110 to S190) will be explained in detail through FIGS. 3a to 3u described later.

[0016] FIG. 2 is a layout showing the main configurations of the cell region of a semiconductor device according to an embodiment of the technical concept of the present invention.

[0017] Referring to FIG. 2, the semiconductor device (10) may include a plurality of active regions (ACTs) arranged to have a long axis in the first horizontal direction (X direction).

[0018] A plurality of word lines (WL) may be extended parallel to each other along a second horizontal direction (Y direction) that is orthogonal to a first horizontal direction (X direction) across a plurality of active regions (ACT). A plurality of bit lines (BL) may be extended parallel to each other along the first horizontal direction (X direction) above (or below) the plurality of word lines (WL).

[0019] In a semiconductor device (10) according to the technical concept of the present invention, the long axis of a plurality of active regions (ACT) may be orthogonal to a plurality of word lines (WL). That is, the long axis of a plurality of active regions (ACT) may be parallel to a plurality of bit lines (BL).

[0020] Multiple bit lines (BL) may be connected to multiple active regions (ACT) through direct contacts (DC). In some embodiments, multiple berid contacts (not shown) may be formed between two adjacent bit lines (BL). Each of the multiple berid contacts (not shown) may extend to the top of either of the two adjacent bit lines (BL). In some embodiments, the multiple berid contacts (not shown) may be arranged in a line along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0021] The manufacturing method of the above main components of the cell region of the semiconductor device (10) will be examined in detail below.

[0022] FIGS. 3a to 3u are cross-sectional views shown in the order of process to explain a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention.

[0023] Specifically, FIGS. 3a to 3u are cross-sectional views corresponding to the cutting line X-X' of FIG. 2 described above.

[0024] Referring to FIG. 3a, a photolithography process is performed to form a mask layer (MP) having a plurality of openings on a substrate (100).

[0025] The substrate (100) may be a wafer containing silicon (Si). Alternatively, the substrate (100) may be a wafer containing a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), or InP (indium phosphide). Meanwhile, the substrate (100) may have a silicon-on-insulator (SOI) structure. Additionally, the substrate (100) may include a conductive region, for example, an impurity-doped well or an impurity-doped structure.

[0026] A mask layer (MP) having a plurality of openings can be formed on the upper surface of a substrate (100). In some embodiments, the mask layer (MP) having a plurality of openings can be formed through an ArF lithography process or an EUV lithography process.

[0027] Referring to FIG. 3b, an etching process is performed to form a plurality of first trenches (110T) in a substrate (100).

[0028] A plurality of first trenches (110T) can be formed by etching a substrate (100) using a mask layer (MP) having a plurality of openings as an etching mask. The etching process may be anisotropic etching, for example, plasma etching.

[0029] Referring to FIG. 3c, a process of removing a mask layer (MP, see FIG. 3b) having a plurality of openings on a substrate (100) is performed.

[0030] A mask layer having multiple openings (MP, see FIG. 3b) can be completely removed by an ashing and stripping process.

[0031] Thus, a plurality of first trenches (110T) can have a first width (W1) in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction). Additionally, adjacent plurality of first trenches (110T) can be spaced apart by a first separation distance (D1).

[0032] Referring to FIG. 3d, a sacrificial material film (111M) is formed conformally along the inner walls of a plurality of first trenches (110T).

[0033] The sacrificial material film (111M) can be formed, for example, by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The sacrificial material film (111M) can be made of silicon oxide, silicon nitride, or a combination thereof.

[0034] Referring to FIG. 3e, a plurality of first trenches (110T) are filled, and a first filled material film (113M) protruding onto the substrate (100) is formed.

[0035] A first filling material film (113M) is formed to completely fill a plurality of first trenches (110T) and cover a sacrificial material film (111M). The first filling material film (113M) can be formed, for example, by a chemical vapor deposition method or an atomic layer deposition method. The first filling material film (113M) can be made of titanium nitride, tantalum nitride, or a combination thereof. That is, the sacrificial material film (111M) and the first filling material film (113M) may contain different materials.

[0036] Referring to FIG. 3f, a first burial material film (113M, see FIG. 3e) is flattened so that the upper surface of the sacrificial material film (111M) is exposed, thereby forming a plurality of first burial films (113).

[0037] The planarization process of the first landfill material film (113M, see FIG. 3e) may be, for example, a Chemical Mechanical Polishing (CMP) process.

[0038] Through the above leveling process, a plurality of first filling membranes (113) are formed to fill a plurality of first trenches (110T). The upper surface of the plurality of first filling membranes (113) can be located at substantially the same level as the upper surface of the sacrificial material membrane (111M).

[0039] Referring to FIG. 3g, an etching process is performed to remove the upper part of the substrate (100) and a portion of the sacrificial material film (111M, see FIG. 3f).

[0040] By an etching process, only the material constituting the substrate (100) and the sacrificial material film (111M, see FIG. 3f) can be selectively removed. By the etching process, the sacrificial material film (111M, see FIG. 3f) is formed into a plurality of sacrificial films (111) located only on the inner walls of a plurality of first trenches (110T).

[0041] Each of the plurality of first embedding films (113) includes a protrusion (113P) that protrudes onto the substrate (100) having a predetermined height (H1). The height (H1) of the protrusion (113P) can determine the height of the spacer (115, see FIG. 3i) in the formation process of the spacer (115, see FIG. 3i) described later.

[0042] Referring to FIG. 3h, a spacer material film (115M) is formed to conformally cover the exposed surface of the substrate (100), the exposed surface of the sacrificial film (111), and the protrusions (113P) of the plurality of first buried films (113).

[0043] The spacer material film (115M) may be made of a material having a high etch selectivity with respect to the material constituting the substrate (100). Etch selectivity can be quantitatively expressed through the ratio of the etch rate of one material to the etch rate of another material.

[0044] The spacer material film (115M) may be made of titanium nitride, tantalum nitride, or a combination thereof. That is, the spacer material film (115M) and a plurality of first burial films (113) may contain the same material. Alternatively, the spacer material film (115M) may be made of silicon nitride.

[0045] An atomic layer deposition method may be used so that the spacer material film (115M) is formed with a uniform thickness (T1). The thickness (T1) of the spacer material film (115M) can be determined by the width of the second trench (120T) in the process of forming the second trench (120T) described later.

[0046] Referring to FIG. 3i, a spacer material film (115M, see FIG. 3h) is partially removed to form a spacer (115).

[0047] An etch-back process is performed so that the upper surface of the substrate (100) is partially exposed around the plurality of first buried films (113), thereby removing a portion of the spacer material film (115M, see FIG. 3h). Accordingly, spacers (115) are formed on both side walls of the protrusions (113P) in each of the plurality of first buried films (113).

[0048] The spacer (115) can be used as an etching mask to form the second trench (120T) described later. The exposed surface of the substrate (100) exposed by the spacer (115) may correspond to the size of the second trench (120T) described later.

[0049] Referring to FIG. 3j, a spacer (115) is used as an etching mask to etch an exposed substrate (100) and form a plurality of second trenches (120T).

[0050] During the etching process, the spacer (115) and the protrusion (113P) may also be partially etched, thereby reducing their height. Accordingly, the height of the protrusion (113P) and the height of the spacer (115) determined during the preceding process may be determined as a remaining thickness by taking into account the thickness removed during the etching process. For example, the greater the aspect ratio of the plurality of second trenches (120T), the higher the height of the protrusion (113P) and the height of the spacer (115) may be formed.

[0051] According to the technical concept of the present invention, since a plurality of second trenches (120T) are formed using spacers (115) formed on the side walls of a plurality of first burial membranes (113), they can be formed at regular intervals from a plurality of first burial membranes (113).

[0052] In addition, according to the technical concept of the present invention, the process of forming a plurality of second trenches (120T) does not use a photolithography process but uses a self-align method, so a plurality of second trenches (120T), which are deep trench patterns of fine size, can be formed with uniform dispersion without misalignment.

[0053] Referring to FIG. 3k, a plurality of second trenches (120T) are filled, and a second filling material film (102M) protruding over a plurality of first filling films (113) is formed.

[0054] In some embodiments, the second buried material film (102M) may be made of silicon oxide, silicon nitride, or a combination thereof. The second buried material film (102M) may be an insulating composite film composed of a buffer oxide film, a trench liner nitride film, and a buried oxide film.

[0055] In other embodiments, the second buried material film (102M) may be at least one selected from High Temperature Oxide (HTO), High Density Plasma (HDP) oxide, Tetra Ethyl Ortho Silicate (TEOS), Boro-Phospho-Silicate Glass (BPSG), or Undoped Silicate Glass (USG). After the process of forming the second buried material film (102M), an annealing process may be added to increase the density of the film.

[0056] Referring to FIG. 3L, a second buried material film (102M, see FIG. 3k) is flattened so that the upper surface of the substrate (100) is exposed, thereby forming a plurality of second buried films (102).

[0057] A flattening process may be performed on the second landfill material film (102M, see FIG. 3k). The flattening process may be, for example, a chemical mechanical polishing process.

[0058] By the above flattening process, a plurality of second filling films (102) are formed to fill a plurality of second trenches (120T). Additionally, by the above flattening process, the protrusions (113P) and spacers (115) are all removed from each of the plurality of first filling films (113). Accordingly, the upper surface of the plurality of second filling films (102) can be located at substantially the same level as the upper surface of the substrate (100).

[0059] In the present invention, a plurality of second buried membranes (102) can serve as device isolation membranes. For example, a plurality of second buried membranes (102) can form a shallow trench isolation (STI).

[0060] Referring to FIG. 3m, all of the multiple sacrificial membranes (111) and multiple first burial membranes (113) are removed within the multiple first trenches (110T).

[0061] By the above removal process, a plurality of first trenches (110T) surrounded by a plurality of second buried films (102) on the substrate (100) can be redefined.

[0062] Along the first horizontal direction (X direction), the first width (W1) of each of the plurality of first trenches (110T) is larger than the second width (W2) of each of the plurality of second burial membranes (102), and the first vertical level (LV1) of the bottom surface of each of the plurality of first trenches (110T) may be located higher than the second vertical level (LV2) of the bottom surface of each of the plurality of second burial membranes (102).

[0063] Here, the second width (W2) of each of the plurality of second burial membranes (102) and the second vertical level (LV2) of the bottom surface may correspond to the width of each of the plurality of second trenches (120T, see FIG. 3k) and the vertical level of the bottom surface.

[0064] Referring to FIG. 3n, a first insulating material film (121M) is formed that extends conformally along the upper surface of the substrate (100) and the inner walls of a plurality of first trenches (110T).

[0065] The first insulating material film (121M) can be formed, for example, by a chemical vapor deposition method or an atomic layer deposition method. The first insulating material film (121M) can be made of silicon oxide, silicon nitride, or a combination thereof.

[0066] Referring to FIG. 3o, a gate material layer (123M) is formed that extends conformally on a first insulating material film (121M) along a plurality of first trenches (110T).

[0067] The gate material layer (123M) can be formed, for example, by a physical vapor deposition (PVD), chemical vapor deposition, or atomic layer deposition method. The gate material layer (123M) can be made of a metal, a metal nitride, or doped polysilicon.

[0068] The gate material layer (123M) can be formed to have a predetermined thickness (T2). The thickness (T2) of the gate material layer (123M) can determine the width (W3) along the first horizontal direction (X direction) of the gate structure (123, see FIG. 3p) during the formation process of a pair of gate structures (123, see FIG. 3p) described later.

[0069] Referring to FIG. 3p, a portion of the first insulating material film (121M, see FIG. 30) and the gate material layer (123M, see FIG. 30) is removed so that the upper surface of the substrate (100) is exposed, thereby forming a plurality of first insulating films (121) and a plurality of gate structures (123).

[0070] In the interior of a plurality of first trenches (110T), a first insulating material film (121M, see FIG. 30) and a gate material layer (123M, see FIG. 30) can be separated by an anisotropic etching process to form a pair of gate structures (123) in each of the plurality of first trenches (110T).

[0071] For example, the gate material layer (123M, see FIG. 30) may be separated into two gate structures (123) respectively disposed on the first and second sidewalls facing each other of a plurality of first trenches (110T). Each of the plurality of gate structures (123) may have a width (W3) along a first horizontal direction (X direction).

[0072] A first insulating film (121) may be disposed between the inner wall of each of the plurality of first trenches (110T) and the gate structure (123). That is, the gate structure (123) and the substrate (100) may not come into direct contact.

[0073] Referring to FIG. 3q, a second insulating material film (125M) is formed that extends conformally along the upper surface and one side of a plurality of gate structures (123) and the bottom surface of a plurality of first trenches (110T).

[0074] The second insulating material film (125M) can be formed, for example, by a chemical vapor deposition method or an atomic layer deposition method. The second insulating material film (125M) can be made of silicon oxide, silicon nitride, or a combination thereof. That is, the first insulating film (121) and the second insulating material film (125M) can be composed of substantially the same material.

[0075] Referring to FIG. 3r, a portion of the second insulating material film (125M, see FIG. 3q) is removed so that the upper surface of the substrate (100) and the bottom surface of the plurality of first trenches (110T) are exposed, thereby forming a plurality of second insulating films (125).

[0076] A second insulating film (125M, see FIG. 3q) can be separated from each of the first trenches (110T) to form a second insulating film (125) on one of the two side walls of the gate structure (123) where the first insulating film (121) is not formed.

[0077] Referring to FIG. 3s, a third filling film (103) is formed between a pair of gate structures (123) in each of the plurality of first trenches (110T, see FIG. 3r).

[0078] The third buried film (103) can be formed by an epitaxial growth process. The third buried film (103) may be an epitaxial growth film grown using the bottom surface of a plurality of first trenches (110T, see FIG. 3r) below it as a seed. That is, the third buried film (103) can be formed to contain the same material as the substrate (100). For example, the third buried film (103) can be formed of silicon (Si) or silicon germanium (SiGe).

[0079] Referring to FIG. 3t, a plurality of gate structures (123) are partially etched to form a recess (123R).

[0080] A recessed portion (123R) that is recessed into the interior of a plurality of first trenches (110T, see FIG. 3r) may be formed on a plurality of gate structures (123). As a result, the upper surface of each of the plurality of gate structures (123) may be located at a lower level than the upper surface of the substrate (100).

[0081] Referring to FIG. 3u, a plurality of capping films (131) are formed to fill the recess portion (123R, see FIG. 3t) on a plurality of gate structures (123).

[0082] A plurality of capping films (131) formed on a plurality of gate structures (123) may be made of an insulating material. The plurality of capping films (131) may be, for example, silicon oxide, silicon nitride, or a combination thereof.

[0083] In some embodiments, each of the plurality of gate structures (123) may be a buried gate structure containing a conductive material. That is, each of the plurality of gate structures (123) may correspond to a word line (WL, see FIG. 2). In other embodiments, each of the plurality of gate structures (123) may be a vertical gate structure containing a conductive material. That is, each of the plurality of gate structures (123) may correspond to a gate electrode (440, see FIG. 8).

[0084] Through such a process, a semiconductor device (10) according to the technical concept of the present invention can be manufactured.

[0085] Ultimately, according to the method for manufacturing a semiconductor device (10) of the present invention, since trenches formed in a subsequent process are formed in self-alignment with the trenches formed first, misalignment can be prevented, and since the trenches have a uniform distribution, the reliability of the semiconductor device (10) is improved.

[0086] FIG. 4 is a block diagram showing a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention.

[0087] Referring to FIG. 4, the method for manufacturing a semiconductor device (S20) may include the process sequence of steps 1 to 6 (S210 to S260).

[0088] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the description.

[0089] A method for manufacturing a semiconductor device (S20) according to the technical concept of the present invention may include: a first step (S210) of forming a plurality of first trenches and a plurality of second buried films on a substrate; a second step (S220) of forming a sacrificial material film that extends and conformally covers the inner walls of the plurality of first trenches; a third step (S230) of removing and separating a portion of the sacrificial material film from the plurality of first trenches so that a portion of the bottom surface of the plurality of first trenches is exposed; a fourth step (S240) of forming a plurality of third buried films that are in contact with the exposed bottom surface of the plurality of first trenches and the side wall of the sacrificial material film while burying the plurality of first trenches; a fifth step (S250) of removing all of the sacrificial material films; and a sixth step (S260) of forming a pair of gate structures in the empty space partitioned by the third buried film in each of the plurality of first trenches.

[0090] The above first step (S210) may substantially include the first to sixth steps (S110 to S160, see FIG. 1) of the semiconductor device manufacturing method (S10, see FIG. 1) described above. Therefore, a detailed description thereof is omitted.

[0091] The technical features for each of the above-mentioned first to sixth steps (S210 to S260) will be explained in detail through FIGS. 5a to 5k described later.

[0092] FIGS. 5a to 5k are cross-sectional views shown in the order of process to explain a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention.

[0093] Specifically, FIGS. 5a to 5k are cross-sectional views corresponding to the cutting line X-X' of FIG. 2 described above.

[0094] Referring to FIG. 5a, a plurality of first trenches (110T) and a plurality of second buried films (102) are formed on a substrate (100).

[0095] In a method for manufacturing a semiconductor device (20, see FIG. 5k), the process of forming a plurality of first trenches (110T) and a plurality of second filling films (102) on a substrate (100) is substantially the same as described above in FIG. 3a to 3m. Therefore, a detailed description thereof is omitted.

[0096] Referring to FIG. 5b, a sacrificial material film (211M) is formed conformally along the inner walls of a plurality of first trenches (110T).

[0097] The sacrificial material film (211M) can be formed, for example, by a chemical vapor deposition method or an atomic layer deposition method. The sacrificial material film (211M) can be made of silicon oxide, silicon nitride, or a combination thereof.

[0098] Referring to FIG. 5c, a second sacrificial material film (213M) is formed that extends conformally on the first sacrificial material film (211M) along a plurality of first trenches (110T).

[0099] The second sacrificial material film (213M) can be formed, for example, by a chemical vapor deposition method or an atomic layer deposition method. The second sacrificial material film (213M) may be made of titanium nitride, tantalum nitride, or a combination thereof. That is, the first sacrificial material film (211M) and the second sacrificial material film (213M) may contain different materials.

[0100] Referring to FIG. 5d, a portion of the first sacrificial material film (211M, see FIG. 5c) and the second sacrificial material film (213M, see FIG. 5c) is removed so that the bottom surface of a plurality of first trenches (110T) is exposed, thereby forming a plurality of first sacrificial films (211) and a plurality of second sacrificial films (213).

[0101] A first sacrificial material film (211M, see FIG. 5c) and a second sacrificial material film (213M, see FIG. 5c) can be separated by an anisotropic etching process within a plurality of first trenches (110T), thereby forming an empty space in each of the plurality of first trenches (110T) that is partitioned by the sidewalls of the first sacrificial film (211) and the sidewalls of the second sacrificial film (213).

[0102] Referring to FIG. 5e, a third landfill material film (203M) is formed between a pair of second sacrificial films (213) in each of the plurality of first trenches (110T, see FIG. 5d).

[0103] The third buried material film (203M) may be formed, for example, by a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method. The third buried material film (203M) may be made of a metal, a metal nitride, or doped polysilicon. However, it is not limited thereto, and the third buried material film (203M) may be formed of an insulating material such as silicon oxide or silicon nitride.

[0104] Referring to FIG. 5f, the second sacrificial membrane (213) is completely removed so that the first sacrificial membrane (211) and the third landfill material membrane (203M) are exposed.

[0105] The third buried material film (203M) may be positioned to protrude from the upper surface of the substrate (100). Additionally, the third buried material film (203M) may be positioned to protrude from the upper surface of the first sacrificial film (211).

[0106] Referring to Fig. 5g, all of the first sacrificial membranes (211) are removed so that the inner walls of the plurality of first trenches (110T) are exposed.

[0107] During the above removal process, the third buried material film (203M, see FIG. 5f) may also be partially etched, and its height may be reduced. Accordingly, the height of the third buried material film (203M, see FIG. 5f) determined during the preceding process may be determined as a remaining thickness by taking into account the thickness removed during the above removal process.

[0108] A portion of the third landfill material film (203M, see FIG. 5f) is removed to form a third landfill film (203). The upper surface of the third landfill film (203) may be located at the same level as the upper surface of the substrate (100). Thus, a plurality of first trenches (110T) may form empty spaces partitioned by the third landfill film (203).

[0109] Referring to FIG. 5h, an insulating material film (221M) is formed that extends conformally along the inner wall of a plurality of first trenches (110T) and the outer wall of a plurality of third burial films (203).

[0110] The insulating material film (221M) can be formed, for example, by a chemical vapor deposition method or an atomic layer deposition method. The insulating material film (221M) can be made of silicon oxide, silicon nitride, or a combination thereof.

[0111] Referring to FIG. 5i, a plurality of first trenches (110T) are filled, and a gate material layer (223M) protruding onto the substrate (100) is formed.

[0112] A gate material layer (223M) is formed to completely fill a plurality of first trenches (110T) and cover an insulating material film (221M). The gate material layer (223M) may be formed, for example, by a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method. The gate material layer (223M) may be made of a metal, a metal nitride, or doped polysilicon.

[0113] Referring to FIG. 5j, a gate material layer (223M) is partially etched to form a plurality of gate structures (223).

[0114] A recessed portion (223R) that is recessed into the interior of a plurality of first trenches (110T, see FIG. 5h) may be formed on a plurality of gate structures (223). As a result, the upper surface of each of the plurality of gate structures (223) may be located at a lower level than the upper surface of the substrate (100).

[0115] Referring to FIG. 5k, a plurality of capping films (231) are formed to fill the recess portion (223R, see FIG. 5j) on a plurality of gate structures (223).

[0116] A plurality of capping films (231) formed on a plurality of gate structures (223) may be made of an insulating material. The plurality of capping films (231) may be, for example, silicon oxide, silicon nitride, or a combination thereof.

[0117] Through such a process, a semiconductor device (20) according to the technical concept of the present invention can be manufactured.

[0118] Ultimately, according to the method for manufacturing a semiconductor device (20) of the present invention, since trenches formed in a subsequent process are formed in self-alignment with the trenches formed first, misalignment can be prevented, and since the trenches have a uniform distribution, the reliability of the semiconductor device (20) is improved.

[0119] FIG. 6 is a layout showing the main configurations of a cell region of a semiconductor device according to an embodiment of the technical concept of the present invention, and FIG. 7 is a cross-sectional view showing the cross-sectional configuration of the line XX' of FIG. 6.

[0120] Most of the components constituting the semiconductor device (30) described below and the materials forming said components are substantially the same or similar as those previously described in FIG. 2 and FIG. 3a to FIG. 3u. Therefore, for the convenience of explanation, the explanation will focus on the differences from the semiconductor device (10) described above.

[0121] Referring to FIGS. 6 and FIGS. 7 together, the semiconductor device (30) may include a plurality of shield lines (SL) that extend parallel to each other in a second horizontal direction (Y direction).

[0122] The semiconductor device (30) may include a plurality of active regions (ACTs) arranged to have a long axis in the first horizontal direction (X direction).

[0123] A plurality of word lines (WL) may be extended parallel to each other along a second horizontal direction (Y direction) that is orthogonal to a first horizontal direction (X direction) across a plurality of active regions (ACT). A plurality of bit lines (BL) may be extended parallel to each other along the first horizontal direction (X direction) above (or below) the plurality of word lines (WL).

[0124] Multiple bit lines (BL) can be connected to multiple active regions (ACT) through direct contacts (DC).

[0125] In the semiconductor device (30) of the present embodiment, a shield line (SL) extending in a second horizontal direction (Y direction) may be formed between two adjacent active regions (ACTs) among a plurality of active regions (ACTs). Specifically, in the process of forming a second buried film (102, see FIG. 3L), a plurality of shield structures (301) may be formed. A plurality of shield structures (301) may be buried in a part of the second buried film (102, see FIG. 3L) and may extend parallel to each other along the second horizontal direction (Y direction).

[0126] In the semiconductor device (30) of the present embodiment, the upper surface of a plurality of shield structures (301) may be located at substantially the same level as the upper surface of the substrate (100). Each of the plurality of shield structures (301) may be composed of a conductive material surrounded by an insulating material. Specifically, an insulating liner may be disposed in the portion of the plurality of shield structures (301) that contacts the substrate (100), and a conductive material may be disposed to fill the interior of the insulating liner.

[0127] FIG. 8 is a layout showing a semiconductor device according to an embodiment of the technical concept of the present invention, and FIG. 9 is a cross-sectional view showing the cross-sectional configuration of the XX' line and the YY' line of FIG. 8 together.

[0128] Referring to FIGS. 8 and FIGS. 9 together, the semiconductor device (40) may include a substrate (410), a plurality of first conductive lines (420), a channel layer (430), a gate electrode (440), a gate insulating layer (450), and a capacitor structure (480).

[0129] The semiconductor device (40) may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer (430) extends along a vertical direction from the substrate (410).

[0130] A lower insulating layer (412) may be disposed on a substrate (410), and a plurality of first conductive lines (420) may be spaced apart from each other in a first horizontal direction (X direction) and extended in a second horizontal direction (Y direction) on the lower insulating layer (412). A plurality of first insulating patterns (422) may be disposed on the lower insulating layer (412) to fill the space between the plurality of first conductive lines (420). The plurality of first insulating patterns (422) may be extended in a second horizontal direction (Y direction), and the upper surface of the plurality of first insulating patterns (422) may be disposed at the same level as the upper surface of the plurality of first conductive lines (420). The plurality of first conductive lines (420) may function as bit lines of a semiconductor device (40).

[0131] In some embodiments, a plurality of first conductive lines (420) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (420) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of, or a combination thereof, but is not limited thereto. A plurality of first conductive lines (420) may comprise a single layer or a multilayer of the aforementioned materials. In some embodiments, a plurality of first conductive lines (420) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or a combination thereof.

[0132] The channel layer (430) may be arranged in a matrix form spaced apart in a first horizontal direction (X direction) and a second horizontal direction (Y direction) on a plurality of first conductive lines (420). The channel layer (430) may have a first width in the first horizontal direction (X direction) and a first height in the vertical direction (Z direction), and the first height may be greater than the first width. The bottom portion of the channel layer (430) functions as a first source / drain area (not shown), the top portion of the channel layer (430) functions as a second source / drain area (not shown), and a portion of the channel layer (430) between the first and second source / drain areas may function as a channel area (not shown).

[0133] In some embodiments, the channel layer (430) may include an oxide semiconductor, for example, the oxide semiconductor is In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yO, or a combination thereof may be included. The channel layer (430) may include a single layer or a multilayer of the oxide semiconductor. In some examples, the channel layer (430) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel layer (430) may have a bandgap energy of about 1.5 eV to about 5.6 eV. For example, the channel layer (430) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to about 4.0 eV. For example, the channel layer (430) may be polycrystalline or amorphous, but is not limited thereto. In some embodiments, the channel layer (430) may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0134] The gate electrode (440) may extend in a first horizontal direction (X direction) on both side walls of the channel layer (430). The gate electrode (440) may include a first sub-gate electrode (440P1) facing the first side wall of the channel layer (430) and a second sub-gate electrode (440P2) facing the second side wall opposite the first side wall of the channel layer (430). As one channel layer (430) is disposed between the first sub-gate electrode (440P1) and the second sub-gate electrode (440P2), the semiconductor device (40) may have a dual-gate transistor structure. However, the technical concept of the present invention is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (440P2) and forming only the first sub-gate electrode (440P1) facing the first side wall of the channel layer (430).

[0135] In the semiconductor device (40) of the present embodiment, the gate electrode (440) can be formed using the semiconductor device manufacturing method (S10 or S20) described above. That is, the gate electrode (440) can be formed with a uniform distribution by using a trench formation process and a filling process thereof.

[0136] The gate electrode (440) may be made of a metal, a metal nitride, a metal carbide, or a combination thereof. In some embodiments, the gate electrode (440) may be made of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof.

[0137] The gate insulating layer (450) surrounds the sidewalls of the channel layer (430) and may be interposed between the channel layer (430) and the gate electrode (440). For example, the entire sidewall of the channel layer (430) may be surrounded by the gate insulating layer (450), and a portion of the sidewall of the gate electrode (440) may be in contact with the gate insulating layer (450). In other embodiments, the gate insulating layer (450) may extend in the extension direction of the gate electrode (440) (i.e., the first horizontal direction), and only two sidewalls of the channel layer (430) facing the gate electrode (440) may be in contact with the gate insulating layer (450).

[0138] In some embodiments, the gate insulating layer (450) may be made of silicon oxide, silicon oxynitride, a high dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high dielectric material may be made of a metal oxide or a metal oxynitride. For example, a high dielectric material that can be used as the gate insulating layer (450) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0139] A plurality of second insulation patterns (432) may be extended along a second horizontal direction (Y direction) on a plurality of first insulation patterns (422), and a channel layer (430) may be disposed between two adjacent second insulation patterns (432) among the plurality of second insulation patterns (432). Additionally, between two adjacent second insulation patterns (432), a first filling layer (434) and a second filling layer (436) may be disposed in the space between two adjacent channel layers (430). The first filling layer (434) may be disposed at the bottom of the space between two adjacent channel layers (430), and the second filling layer (436) may be formed to fill the remainder of the space between two adjacent channel layers (430) on the first filling layer (434). The upper surface of the second buried layer (436) is positioned at the same level as the upper surface of the channel layer (430), and the second buried layer (436) can cover the upper surface of the gate electrode (440). Alternatively, a plurality of second insulating patterns (432) may be formed as a material layer continuous with a plurality of first insulating patterns (422), or the second buried layer (436) may be formed as a material layer continuous with the first buried layer (434).

[0140] A capacitor contact (460) may be disposed on the channel layer (430). The capacitor contact (460) may be arranged in a matrix form that is vertically overlapped with the channel layer (430) and spaced apart in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The capacitor contact (460) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x, or a combination thereof, but is not limited thereto. The upper insulating layer (462) may surround the sidewall of the capacitor contact (460) on a plurality of second insulating patterns (432) and a second embedded layer (436).

[0141] An etch stop layer (470) may be disposed on the upper insulating layer (462), and a capacitor structure (480) may be disposed on the etch stop layer (470). The capacitor structure (480) may include a lower electrode (482), a capacitor dielectric layer (484), and an upper electrode (486).

[0142] The lower electrode (482) can be electrically connected to the upper surface of the capacitor contact (460) by penetrating the etch stop layer (470). The lower electrode (482) may be formed as a pillar type extending in the vertical direction (Z direction), but is not limited thereto. In some embodiments, the lower electrode (482) may be arranged in a matrix form that is positioned to overlap vertically with the capacitor contact (460) and spaced apart in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Alternatively, a landing pad (not shown) may be further positioned between the capacitor contact (460) and the lower electrode (482), so that the lower electrode (482) may be arranged in a hexagonal shape.

[0143] Although embodiments of the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0144] S10, S20: Method for manufacturing a semiconductor device 10, 20, 30: Semiconductor devices 100: Substrate 102: Second landfill 103: Third landfill 110T: 1st Trench 113: 1st landfill 115: Spacer 120T: 2nd Trench 123: Gate structure

Claims

Claim 1 A step of forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; a step of forming a plurality of first buried films that fill the plurality of first trenches and have protrusions that extend to protrude onto the substrate; a step of forming spacers on the side walls of the protrusions of each of the plurality of first buried films so that a portion of the substrate is exposed between the plurality of first buried films; a step of etching the substrate exposed through the spacers to form a plurality of second trenches around the plurality of first trenches; a step of forming a plurality of second buried films that fill the plurality of second trenches and have upper surfaces at the same level as the upper surface of the substrate; a step of removing all of the plurality of first buried films and the spacers; a step of forming a gate material layer that extends to conformally cover the inner walls of the plurality of first trenches; a step of separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; A method for manufacturing a semiconductor device comprising the step of forming a third filling film between the pair of gate structures in each of the plurality of first trenches, wherein the width of each of the pair of gate structures along the first horizontal direction is substantially the same as the thickness of the gate material layer. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the plurality of first filling films comprises: a step of filling the plurality of first trenches with a first filling film material; and a step of removing the upper portion of the substrate by a predetermined thickness so that the side wall of the protrusion is exposed. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the spacer comprises: forming a spacer material that extends and conformally covers the substrate and the protrusion; and partially etching the spacer material so that a portion of the substrate is exposed between the plurality of first buried films. Claim 4 A step of forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; a step of forming a plurality of first buried films that fill the plurality of first trenches and have protrusions that extend to protrude onto the substrate; a step of forming spacers on the side walls of the protrusions of each of the plurality of first buried films so that a portion of the substrate is exposed between the plurality of first buried films; a step of etching the substrate exposed through the spacers to form a plurality of second trenches around the plurality of first trenches; a step of forming a plurality of second buried films that fill the plurality of second trenches and have upper surfaces at the same level as the upper surface of the substrate; a step of removing all of the plurality of first buried films and the spacers; a step of forming a gate material layer that extends to conformally cover the inner walls of the plurality of first trenches; a step of separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; A method for manufacturing a semiconductor device comprising the step of forming a third filling film between the pair of gate structures in each of the plurality of first trenches; wherein the first filling film is a sacrificial film, the second filling film is a device isolation film made of an insulating material, and the third filling film is an epitaxial growth film. Claim 5 A step of forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; a step of forming a plurality of first buried films that fill the plurality of first trenches and have protrusions that extend to protrude onto the substrate; a step of forming spacers on the side walls of the protrusions of each of the plurality of first buried films so that a portion of the substrate is exposed between the plurality of first buried films; a step of etching the substrate exposed through the spacers to form a plurality of second trenches around the plurality of first trenches; a step of forming a plurality of second buried films that fill the plurality of second trenches and have upper surfaces at the same level as the upper surface of the substrate; a step of removing all of the plurality of first buried films and the spacers; a step of forming a gate material layer that extends to conformally cover the inner walls of the plurality of first trenches; a step of separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; A method for manufacturing a semiconductor device comprising the step of forming a third filling film between the pair of gate structures in each of the plurality of first trenches; wherein the first filling film is a sacrificial film, and at least one of the second filling film and the third filling film comprises a conductive material. Claim 6 A method for manufacturing a semiconductor device according to claim 5, wherein a portion of the second buried membrane extends in the second horizontal direction and is a shield structure made of a conductive material. Claim 7 A method for manufacturing a semiconductor device according to claim 1, wherein, along the first horizontal direction, the width of each of the plurality of first trenches is greater than the width of each of the plurality of second trenches, and the vertical level of the bottom surface of each of the plurality of first trenches is positioned higher than the vertical level of the bottom surface of each of the plurality of second trenches. Claim 8 delete Claim 9 A step of forming a plurality of first trenches that are spaced apart from each other in a first horizontal direction on a substrate and extend in a second horizontal direction orthogonal to the first horizontal direction; a step of forming a plurality of first buried films that fill the plurality of first trenches and have protrusions that extend to protrude onto the substrate; a step of forming spacers on the side walls of the protrusions of each of the plurality of first buried films so that a portion of the substrate is exposed between the plurality of first buried films; a step of etching the substrate exposed through the spacers to form a plurality of second trenches around the plurality of first trenches; a step of forming a plurality of second buried films that fill the plurality of second trenches and have upper surfaces at the same level as the upper surface of the substrate; a step of removing all of the plurality of first buried films and the spacers; a step of forming a gate material layer that extends to conformally cover the inner walls of the plurality of first trenches; a step of separating the gate material layer to form a pair of gate structures in each of the plurality of first trenches; A method for manufacturing a semiconductor device comprising the step of forming a third filling film between the pair of gate structures in each of the plurality of first trenches; wherein, in the substrate, a plurality of active regions defined by being surrounded by the plurality of second filling films have a long axis along the first horizontal direction, and the long axis direction of the plurality of active regions is orthogonal to the extension direction of the pair of gate structures. Claim 10 A method for manufacturing a semiconductor device according to claim 1, wherein each of the pair of gate structures operates as a word line constituting a vertical channel transistor.

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