Semiconductor devices and manufacturing methods for the same

Abstract

A semiconductor device comprises: a substrate having a plurality of active regions defined therein; a plurality of word lines disposed within a plurality of word line trenches formed on the substrate and extending in a first direction parallel to the upper surface of the substrate; a plurality of bit line structures formed on the substrate and extending in a second direction parallel to the upper surface of the substrate; and a plurality of cell pad structures disposed on the active regions with each of the plurality of bit line structures in between, wherein each cell pad structure has a pair of first sidewalls extending in the first direction and a pair of second sidewalls extending in a diagonal direction inclined with respect to the first direction and the second direction.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a bit line and a method for manufacturing the same. Background Technology

[0002] With the downscaling of semiconductor devices, the size of individual fine circuit patterns required to implement these devices is further decreasing. Furthermore, as integrated circuits become more highly integrated, the line width of bit lines is shrinking, and the difficulty of the process for forming contacts between bit lines is increasing. [Prior Art Literature] [Patent Literature] (Patent Document 1) U.S. Registered Patent Publication No. 9,379,114 (Published October 3, 2013) The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a semiconductor device capable of reducing the difficulty of the process of forming contacts between bit lines.

[0004] The technical problem that the technical concept of the present invention aims to solve is to provide a method for manufacturing a semiconductor device that can reduce the difficulty of the process of forming contacts between bit lines. means of solving the problem

[0005] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a substrate having a plurality of active regions defined therein; a plurality of word lines disposed within a plurality of word line trenches formed on the substrate and extending in a first direction parallel to the upper surface of the substrate; a plurality of bit line structures formed on the substrate and extending in a second direction parallel to the upper surface of the substrate; and a plurality of cell pad structures disposed on the active region between each of the plurality of bit line structures, each having a pair of first sidewalls extending in the first direction and a pair of second sidewalls extending in a diagonal direction inclined with respect to the first direction and the second direction.

[0006] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a substrate having a plurality of active regions defined therein; a plurality of word lines disposed within a plurality of word line trenches formed on the substrate and extending in a first direction parallel to the upper surface of the substrate; a plurality of bit line structures formed on the substrate and extending in a second direction parallel to the upper surface of the substrate; and a plurality of cell pad structures disposed on the active region between each of the plurality of bit line structures, each of which extends in a second diagonal direction inclined with respect to the first direction and the second direction.

[0007] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a substrate having a plurality of active regions defined therein; a plurality of word lines disposed within a plurality of word line trenches formed on the substrate and extending in a first direction parallel to the upper surface of the substrate; a plurality of bit line structures formed on the substrate and extending in a second direction parallel to the upper surface of the substrate; a plurality of first cell pad separation patterns extending in the first direction on the substrate; a plurality of second cell pad separation patterns extending in a diagonal direction on the substrate; and a plurality of cell pad structures disposed on the plurality of active regions, each comprising a first sidewall in contact with one of the plurality of first cell pad separation patterns and a second sidewall in contact with one of the plurality of second cell pad separation patterns. Effects of the invention

[0008] According to the technical concept of the present invention, cell pad structures between the active region of a substrate and a landing pad may have a pair of first sidewalls extending in a first direction and a pair of second sidewalls extending in a diagonal direction. The cell pad structures may be patterned in a self-aligned manner using a reference pattern extending in a diagonal direction and a pair of spacers, thereby preventing variations in the area of ​​the cell pad structures caused by misalignment of the patterning mask. The semiconductor device may have excellent reliability. Brief explanation of the drawing

[0009] FIG. 1 is a layout diagram showing a semiconductor device according to exemplary embodiments. Figure 2 is an enlarged layout of part II of Figure 1. Figure 3 is a cross-sectional view along the AA', BB', and CC' lines of Figure 2. FIG. 4 is a layout diagram showing a semiconductor device according to exemplary embodiments. Figure 5 is a cross-sectional view along the AA', BB', and CC' lines of Figure 4. FIGS. 6a to 13b are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 6a, 7a, 8a, 9a, 10a, 11a, 12a, and 13a are plan views shown in the order of processes, and FIGS. 6b, 7b, 8b, 9b, 10b, 11b, 12b, and 13b are cross-sectional views corresponding to the AA' line, BB' line, and CC' line of FIGS. 6a, 7a, 8a, 9a, 10a, 11a, 12a, and 13a. Specific details for implementing the invention

[0010] Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a layout diagram showing a semiconductor device (100) according to exemplary embodiments. FIG. 2 is an enlarged layout diagram of part II of FIG. 1. FIG. 3 is a cross-sectional view along lines AA', BB', and CC' of FIG. 2.

[0012] Referring to FIGS. 1 through 3, a semiconductor device (100) may include a substrate (110) comprising a cell array region (MCA) and a peripheral circuit region (PCA). The cell array region (MCA) may be a memory cell region of a DRAM device, and the peripheral circuit region (PCA) may be a core region or a peripheral circuit region of a DRAM device. For example, the cell array region (MCA) may include a cell transistor (CTR) and a capacitor structure (180) connected thereto, and the peripheral circuit region (PCA) may include a peripheral circuit transistor (not shown) for transmitting a signal and / or power to the cell transistor (CTR) included in the cell array region (MCA). In exemplary embodiments, the peripheral circuit transistor may comprise various circuits such as a command decoder, control logic, address buffer, row decoder, column decoder, sense amplifier, and data input / output circuit.

[0013] A device isolation trench (112T) is formed in the substrate (110), and a device isolation film (112) may be formed within the device isolation trench (112T). A plurality of active regions (AC) may be defined in the substrate (110) by the device isolation film (112).

[0014] A plurality of active regions (ACs) may each be arranged to have a major axis in a first diagonal direction (D1) inclined with respect to a first horizontal direction (X) and a second horizontal direction (Y). A plurality of word lines (WLs) may extend mutually parallel along the first horizontal direction (X) across the plurality of active regions (ACs). A plurality of bit lines (BLs) may extend mutually parallel along the second horizontal direction (Y) over the plurality of word lines (WLs). The plurality of bit lines (BLs) may be connected to the plurality of active regions (ACs) through direct contacts (DCs).

[0015] Among a plurality of bit lines (BL), a plurality of cell pad structures (130) may be formed between two mutually adjacent bit lines (BL). The plurality of cell pad structures (130) may be arranged to extend along a second diagonal direction (D2) inclined with respect to a first horizontal direction (X) and a second horizontal direction (Y). The plurality of cell pad structures (130) may include a first cell pad (130L) and a second cell pad (130R) spaced apart from each other with a direct contact (DC) in between. A direct contact (DC) may be arranged between the first cell pad (130L) and the second cell pad (130R) spaced apart along the first horizontal direction (X), and a second cell pad separation pattern (134) may be arranged between the second cell pad (130R) and the first cell pad (130L) spaced apart along the first horizontal direction (X).

[0016] The first cell pad (130L) and the second cell pad (130R) may have the same shape as each other, and the first cell pad (130L) and the second cell pad (130R) may have the same horizontal cross-sectional area as each other. Each of the plurality of cell pad structures (130) may have a horizontal cross-section in the shape of a parallelogram and may include a pair of first side walls (130S1) extending along the first horizontal direction (X) and a pair of second side walls (130S2) extending along the second diagonal direction (D1).

[0017] A plurality of landing pads (LP) may be formed on a plurality of cell pad structures (130). The plurality of cell pad structures (130) and the plurality of landing pads (LP) may serve to connect the lower electrode (not shown) of a capacitor structure (not shown) formed on the upper part of a plurality of bit lines (BL) to an active region (AC). Each of the plurality of landing pads (LP) may be positioned to partially overlap with the cell pad structures (130) and the bit lines (BL).

[0018] The substrate (110) may comprise silicon, for example, single-crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate (110) may comprise at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate (110) may comprise a conductive region, for example, an impurity-doped well, or an impurity-doped structure. The device isolation film (112) may comprise an oxide film, a nitride film, or a combination thereof.

[0019] A plurality of word line trenches (120T) extending in a first direction (X direction) are disposed on a substrate (110), and a buried gate structure (120) may be disposed within the plurality of word line trenches (120T). The buried gate structure (120) may include a gate dielectric film (122), a gate electrode (124), and a capping insulating film (126) disposed within each of the plurality of word line trenches (120T). The plurality of gate electrodes (124) may correspond to the plurality of word lines (WL) illustrated in FIG. 2.

[0020] A plurality of gate dielectric films (122) may include silicon oxide, silicon nitride, silicon oxynitride, ONO (oxide / nitride / oxide) film, or a high-k dielectric film having a dielectric constant higher than that of silicon oxide. A plurality of gate electrodes (124) may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. A plurality of capping insulating films (126) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0021] A plurality of direct contacts (DC) may be formed within a plurality of direct contact trenches (DCT) on a substrate (110). A plurality of direct contacts (DC) may be connected to a plurality of active regions (AC). A plurality of direct contacts (DC) may include TiN, TiSiN, W, tungsten silicide, doped polysilicon, or a combination thereof. A direct contact trench (DCT) may extend in a second diagonal direction (D2), and the bottom portion of a direct contact trench (DCT) may have a flat bottom surface. A direct contact spacer (DCS) may cover the lower side of a direct contact (DC) inside a direct contact trench (DCT).

[0022] A direct contact trench (DCT) is extended along the second diagonal direction (D2), and a tail portion (DCTL) may be formed at the bottom of the side wall of the direct contact (DC) spaced apart in the second diagonal direction (D2). The tail portion (DCTL) may be formed in a patterning process of the conductive layer (152L) to form a conductive layer (152L) that fills the direct contact trench (DCT) and subsequently define the width along the first horizontal direction (X) of the direct contact (DC).

[0023] In the plan view, the direct contact (DC) may have a rectangular horizontal cross-section. For example, the direct contact (DC) may include a pair of first side walls (DCS1) extending in a first horizontal direction (X) and a pair of second side walls (DCS2) extending in a second horizontal direction (Y).

[0024] A plurality of bit line structures (150) may be extended along a second horizontal direction (Y) on a substrate (110) and a plurality of direct contacts (DC). Each of the plurality of bit line structures (150) may be connected to an active region (AC) through a direct contact (DC). Each of the plurality of bit line structures (150) may include a conductive layer (152), an intermediate conductive layer (154), a bit line conductive layer (156), and a bit line capping layer (158), and the bit line conductive layer (156) may correspond to a bit line (BL) illustrated in FIG. 2.

[0025] In exemplary embodiments, the conductive layer (152) may comprise polysilicon, and the intermediate conductive layer (154) may comprise at least one of TiN, TiSiN, cobalt silicide, nickel silicide, and tungsten silicide. The bit line conductive layer (156) may comprise at least one of ruthenium (Ru), tungsten (W), cobalt (Co), titanium (Ti), and titanium nitride (TiN). The bit line capping layer (158) may comprise at least one of silicon nitride, silicon oxide, and silicon oxynitride. Bit line spacers (160) may be disposed on both side walls of each bit line structure (150).

[0026] A plurality of cell pad structures (130) may be disposed between each of the plurality of bit line structures (150). For example, one cell pad structure (130) may be disposed between two adjacent bit line structures (150) at a vertical level lower than the bit line structure (150), and the bottom surface of the cell pad structure (130) may be in contact with the active area (AC).

[0027] In exemplary embodiments, a plurality of cell pad structures (130) may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0028] A first cell pad separation pattern (132) may be disposed between two cell pad structures (130) arranged in a second horizontal direction (Y), and a second cell pad separation pattern (134) may be disposed between two cell pad structures (130) arranged in a first horizontal direction (X). The first cell pad separation pattern (132) may be disposed within a first cell pad separation trench (132T) and may extend in the first horizontal direction (X), and may be disposed at a position that vertically overlaps with a landfill gate structure (120). The second cell pad separation pattern (134) may be disposed within a second cell pad separation trench (134T) and may extend in a second diagonal direction (D2). The first cell pad separation pattern (132) and the second cell pad separation pattern (134) may include silicon nitride.

[0029] In exemplary embodiments, the bottom surface of the first cell pad separation pattern (132) may be positioned at a lower level than the bottom surface of the direct contact (DC), and the bottom surface of the second cell pad separation pattern (134) may be positioned at a lower level than the bottom surface of the direct contact (DC). For example, the first cell pad separation trench (132T) and the second cell pad separation trench (134T) may have bottom surfaces positioned at a lower level than the bottom surface of the direct contact trench (DCT). That is, the vertical distance between the direct contact trench (DCT) and the upper surface of the gate electrode (124) may be greater than the vertical distance between the first cell pad separation trench (132T) and the upper surface of the gate electrode (124) and / or the vertical distance between the second cell pad separation trench (134T) and the upper surface of the gate electrode (124).

[0030] A first insulating layer (140A) and a second insulating layer (140B) may be sequentially disposed between a plurality of cell pad structures (130) and bit line structures (150). The first insulating layer (140A) may include silicon oxide, and the second insulating layer (140B) may include silicon nitride.

[0031] A plurality of insulating fences (162) may be positioned along the second horizontal direction (Y) between two adjacent bit line structures (150). The plurality of insulating fences (162) may be positioned in a location that vertically overlaps with a plurality of word line trenches (120T).

[0032] A plurality of landing pads (LP) may be disposed on a plurality of cell pad structures (130). Each of the plurality of landing pads (LP) may include a conductive barrier film (164) and a landing pad conductive layer (166). The conductive barrier film (164) may include Ti, TiN, or a combination thereof. The landing pad conductive layer (166) may include a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the landing pad conductive layer (166) may include W. The plurality of landing pads (LP) may have a plurality of island-shaped pattern shapes when viewed in a planar view.

[0033] A plurality of landing pads (LP) may be electrically insulated from one another by an insulating pattern (168) surrounding the plurality of landing pads (LP). The insulating pattern (168) may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0034] Generally, a portion of the cell pad structure (130) is removed to form an island-type direct contact hole, and a direct contact is formed by filling the direct contact hole with a conductive material. However, if misalignment occurs during the patterning process for forming the direct contact hole, a cell pad structure having a locally small area may be formed, and in such cases, the contact resistance between the active region and the landing pad may increase, thereby degrading the electrical characteristics of the semiconductor device.

[0035] However, according to exemplary embodiments, a cell pad preliminary pattern (130P2) is formed by forming a first cell pad separation pattern (132) and a second cell pad separation pattern (134) to intersect at an acute angle, and then a direct contact trench (DCT) is formed in a double patterning manner using a reference pattern (142) and a spacer (144) extending in a second diagonal direction (D2), thereby forming a first cell pad (132L) and a second cell pad (132R). Thus, the first cell pad (132L) and the second cell pad (132R) can be formed to have the same area, and the semiconductor device (100) can have excellent electrical characteristics.

[0036] FIG. 4 is a layout diagram showing a semiconductor device (100A) according to exemplary embodiments. FIG. 5 is a cross-sectional view along the lines AA', BB', and CC' of FIG. 4.

[0037] Referring to FIGS. 4 and 5, a plurality of cell pad structures (130) may be arranged to extend along a second diagonal direction (D1) inclined with respect to a first horizontal direction (X) and a second horizontal direction (Y). The plurality of cell pad structures (130) may include a first cell pad (130L) and a second cell pad (130R) spaced apart from each other with a direct contact (DCA) in between. A direct contact (DCA) may be arranged between the first cell pad (130L) and the second cell pad (130R) spaced apart along the first horizontal direction (X), and a second cell pad separation pattern (134) may be arranged between the second cell pad (130R) and the first cell pad (130L) spaced apart along the first horizontal direction (X).

[0038] Each of the plurality of cell pad structures (130) may have a horizontal cross-section in the shape of a parallelogram and may include a pair of first side walls (130S1) extending along a first horizontal direction (X) and a pair of second side walls (130S2) extending along a second diagonal direction (D1).

[0039] A direct contact (DCA) may be positioned between the first cell pad (130L) and the second cell pad (130R), adjacent to both the first cell pad (130L) and the second cell pad (130R). In exemplary embodiments, the direct contact (DCA) may have a horizontal cross-section in the shape of a parallelogram, or a parallelogram with some corners cut off (e.g., a hexagon). For example, the direct contact (DCA) may include a pair of first side walls (DCS1) extending in a second diagonal direction (D2) and a pair of second side walls (DCS2) extending in a second horizontal direction (Y). The pair of first side walls (DCS1) extending in the second diagonal direction (D2) may each face a pair of second side walls (130S2) of the cell pad structure (130).

[0040] An insulating liner (172) may be disposed between the direct contact (DCA) and the cell pad structure (130). The insulating liner (172) may be disposed on the sidewall of the direct contact trench (DCT), and the direct contact (DCA) and the cell pad structure (130) may be electrically insulated from each other by the insulating liner (172). The insulating liner (172) may comprise silicon nitride or silicon oxide.

[0041] FIGS. 6a to 13b are cross-sectional views illustrating a method of manufacturing a semiconductor device (100) according to exemplary embodiments. Specifically, FIGS. 6a, 7a, 8a, 9a, 10a, 11a, 12a, and 13a are plan views shown in the order of process, and FIGS. 6b, 7b, 8b, 9b, 10b, 11b, 12b, and 13b are cross-sectional views corresponding to the AA' line, BB' line, and CC' line of FIGS. 6a, 7a, 8a, 9a, 10a, 11a, 12a, and 13a. In FIGS. 6a to 13b, the same reference numerals as in FIGS. 1 to 5 indicate the same components.

[0042] Referring to FIGS. 6a and 6b, a plurality of device isolation trenches (112T) can be formed in the cell array region (MCA) of the substrate (110).

[0043] Subsequently, a device isolation film (112) can be formed to fill a plurality of device isolation trenches (112T). By forming the device isolation film (112), a plurality of first active regions (AC) are defined on the substrate (110). The plurality of first active regions (AC) may extend along a first diagonal direction (D1) inclined at a predetermined angle with respect to the first horizontal direction (X1) and the second horizontal direction (Y).

[0044] In exemplary embodiments, the device isolation layer (112) may be formed using silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some examples, the device isolation layer (112) may be formed as a double-layer structure of a silicon oxide layer and a silicon nitride layer, but is not limited thereto.

[0045] A mask pattern (not shown) can be formed on a substrate (110), and a word line trench (120T) can be formed by removing a portion of the substrate (110) using the mask pattern as an etching mask. For example, the mask pattern for forming the word line trench (120T) can be formed using double patterning technology (DPT) or quadruple patterning technology (QPT), but is not limited thereto.

[0046] Afterwards, a gate dielectric film (122), a gate electrode (124), and a capping insulating film (126) can be sequentially formed within the word line trench (120T).

[0047] For example, a gate dielectric film (122) may be conformally disposed on the inner wall of a word line trench (120T). A gate electrode (124) may be formed by filling the word line trench (120T) with a conductive layer (not shown) and then etching back the top of the conductive layer to expose a portion of the upper side of the word line trench (120T). A capping insulating film (126) may be formed by filling the remaining portion of the word line trench (120T) with an insulating material and flattening the insulating material until the upper surface of the buried insulating layer (114A) is exposed.

[0048] Referring to FIGS. 7a and 7b, a conductive layer (not shown) is formed on an active region (AC) and a device isolation layer (112), a mask pattern (M10) having a line-shaped opening (M10H) extending in a first horizontal direction (X) is formed on the conductive layer, and a plurality of cell pad line patterns (130P1) can be formed by patterning the conductive layer using the mask pattern (M10) as an etching mask.

[0049] In exemplary embodiments, the cell pad line pattern (130P1) may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. For example, the cell pad line pattern (130P1) may include polysilicon.

[0050] Afterwards, an insulating layer (not shown) is formed in the space between the plurality of cell pad line patterns (130P1), and the upper surface of the insulating layer is flattened until the upper surface of the plurality of cell pad line patterns (130P1) is exposed to form the plurality of first cell pad separation patterns (132).

[0051] In exemplary embodiments, a plurality of cell pad line patterns (130P1) may have a line shape extending in a first horizontal direction (X). Additionally, a plurality of first cell pad separation patterns (132) may have a line shape extending in a first horizontal direction (X). For example, a plurality of cell pad line patterns (130P1) and a plurality of first cell pad separation patterns (132) may be arranged alternately along a second horizontal direction (Y), and each first cell pad separation pattern (132) may be arranged between two adjacent cell pad line patterns (130P1).

[0052] In exemplary embodiments, a plurality of first cell pad separation patterns (132) may be arranged to overlap vertically with the word line trench (120T), and a plurality of first cell pad separation patterns (132) may be arranged on the capping insulating film (126).

[0053] Referring to FIGS. 8a and 8b, a buffer insulating layer (140) can be formed on a plurality of cell pad line patterns (130P1) and a plurality of first cell pad separation patterns (132). In exemplary embodiments, the buffer insulating layer (140) may have a stacked structure of a first insulating layer (140A), a second insulating layer (140B), and a third insulating layer (140C).

[0054] Subsequently, a reference pattern (142) can be formed on the buffer insulating layer (140) having an opening (not shown) extending in a second diagonal direction (D2) inclined at a predetermined angle with respect to the first horizontal direction (X1) and the second horizontal direction (Y). The second diagonal direction (D2) may be inclined at an acute angle with respect to the first diagonal direction (D1). For example, the second diagonal direction (D2) may be inclined at an angle of 10 to 30 degrees with respect to the first diagonal direction (D1).

[0055] In exemplary embodiments, the reference pattern (142) may include a plurality of line patterns defined by a plurality of openings having a line shape, and the plurality of line patterns of the reference pattern (142) may be arranged having a first pitch. For example, the plurality of line patterns may be arranged at a first interval with a first width along a second diagonal direction (D2). The first width may correspond to the width of a direct contact trench (DCT) (see FIG. 10b).

[0056] Subsequently, a spacer layer (not shown) is formed on the buffer insulating layer (140) to conformally cover the upper surface and side wall of the reference pattern (142), and an anisotropic etching process is performed on the spacer layer to remove a portion of the spacer layer placed on the upper surface of the reference pattern (142) and the bottom portion of the opening (142H), and leave a portion of the spacer layer placed on the side wall of the reference pattern (142) to form a pair of spacers (144).

[0057] In exemplary embodiments, a pair of spacers (144) may be placed on both side walls of the reference pattern (142), and each spacer (144) may have a second width substantially equal to the first width along the second diagonal direction (D2). Additionally, by forming a pair of spacers (144) on the side walls of the opening, the width of the upper surface of the buffer insulation layer (140) exposed at the bottom of the opening may be narrowed.

[0058] Referring to FIGS. 9a and 9b, a portion of the buffer insulating layer (140), cell pad line pattern (130P1), and substrate (110) can be removed using a reference pattern (142) and a pair of spacers (144) as an etching mask, thereby forming a second cell pad separation trench (134T) extending in a second diagonal direction (D2).

[0059] An insulating layer (not shown) can be formed inside the second cell pad separation trench (134T), and a plurality of second cell pad separation patterns (134) can be formed by etching back the upper part of the insulating layer.

[0060] In exemplary embodiments, a plurality of second cell pad separation patterns (134) may extend in a second diagonal direction (D2). Additionally, the upper surface of the plurality of second cell pad separation patterns (134) may be positioned at a lower level than the upper surface of the reference pattern (142) and a pair of spacers (144). Furthermore, a plurality of cell pad preliminary patterns (130P2) may be formed from the cell pad line pattern (130P1) by a plurality of first cell pad separation patterns (132) extending in a first horizontal direction (X) and a plurality of second cell pad separation patterns (134) extending in a second diagonal direction (D2). Each of the plurality of cell pad preliminary patterns (130P2) may be formed to have a horizontal cross-section in the shape of a parallelogram. That is, one cell pad preliminary pattern (130P2) may be disposed between two adjacent first cell pad separation patterns (132) and two adjacent second cell pad separation patterns (134), and the one cell pad preliminary pattern (130P2) may include two first side walls in contact with the two first cell pad separation patterns (132) and two second side walls of the two second cell pad separation patterns (134).

[0061] Referring to FIGS. 10a and 10b, the reference pattern (142) and the spacer (144) can be removed. Subsequently, the buffer insulating layer (140), the cell pad preliminary pattern (130P2), and the substrate (110) portions in the area where the reference pattern (142) and the spacer (144) have been removed can be further removed to form a direct contact trench (DCT).

[0062] In exemplary embodiments, the direct contact trench (DCT) may extend in a second diagonal direction (D2), and, for example, the bottom surface of the direct contact trench (DCT) along the second diagonal direction (D2) may have a flat profile.

[0063] A direct contact trench (DCT) can be positioned to extend parallel to two adjacent second cell pad separation patterns (134), thereby removing a portion of the cell pad preliminary pattern (130P2) to form a pair of cell pad structures (130). In a plan view, a direct contact trench (DCT) can be positioned between a pair of cell pad structures (130), and each cell pad structure (130) can have a horizontal cross-section in the shape of a parallelogram. A cell pad structure (130) may include a pair of first side walls (130S1) extending in a first horizontal direction (X) and a pair of second side walls (130S2) extending in a second diagonal direction (D2).

[0064] In exemplary embodiments, the direct contact trench (DCT) may have a bottom portion positioned at a higher level than the bottom surface of a plurality of first cell pad separation patterns (132) and the bottom surface of a plurality of second cell pad separation patterns (134).

[0065] Referring to FIG. 11a and FIG. 11b, the third insulating layer (140C) of the buffer insulating layer (140) can be removed and the upper surface of the second insulating layer (140B) exposed.

[0066] Subsequently, a conductive layer (152) filling the interior of a direct contact trench (DCT) may be formed on a plurality of cell pad structures (130), a plurality of first cell pad separation patterns (132), and a plurality of second cell pad separation patterns (134). A portion of the conductive layer (152) extends in a second diagonal direction (D2), and, for example, a portion of the conductive layer (152) may extend at a predetermined angle with respect to the plurality of first cell pad separation patterns (132) and the plurality of second cell pad separation patterns (134). In exemplary embodiments, the conductive layer (152) may comprise polysilicon.

[0067] Subsequently, an intermediate conductive layer (154), a bit line conductive layer (156), and a bit line capping layer (158) can be formed on the conductive layer (152).

[0068] In exemplary embodiments, the intermediate conductive layer (154) may comprise at least one of TiN, TiSiN, cobalt silicide, nickel silicide, and tungsten silicide. The bit line conductive layer (156) may comprise at least one of ruthenium (Ru), tungsten (W), cobalt (Co), titanium (Ti), and titanium nitride (TiN).

[0069] Referring to FIG. 12a and FIG. 12b, a mask pattern (not shown) is formed on a bit line capping layer (158), and a bit line structure (150) can be formed by patterning the bit line capping layer (158), the bit line conductive layer (156), the intermediate conductive layer (154), and the conductive layer (152) using the mask pattern.

[0070] The bit line structure (150) may be extended along the second horizontal direction (Y), and a conductive layer (152) may be formed to a relatively large depth at the intersection of the direct contact trench (DCT) and the bit line structure (150). At the intersection of the direct contact trench (DCT) and the bit line structure (150), the portion of the conductive layer (152) positioned between the bit line structure (150) and the active region (AC) may be referred to as the direct contact (DC).

[0071] In the process for forming a direct contact (DC), a tail portion (DCTL) may be formed on both side walls of the direct contact (DC) at the bottom portion of the direct contact trench (DCT), but the technical concept of the present invention is not limited thereto.

[0072] Subsequently, a bit line spacer (160) can be formed on the side wall of the bit line structure (150). A portion of the bit line spacer (160) may be placed on the side wall of the direct contact (DC), and a portion of the bit line spacer (160) surrounding the side wall of the direct contact (DC) may be referred to as a direct contact spacer (DCS).

[0073] Subsequently, a plurality of insulating fences (162) can be formed between each of the plurality of bit line structures (150). The plurality of insulating fences (162) can be formed at the same height as the upper surface of the plurality of bit lines (BL) and fill the bottom portion of the direct contact trench (DCT).

[0074] Referring to FIGS. 13a and 13b, the second insulating layer (140B) and the first insulating layer (140A) exposed between the bit line structures (150) are removed to expose the upper surface of the cell pad structure (130).

[0075] Subsequently, a conductive barrier film (164) and a landing pad conductive layer (166) are formed to cover the exposed surface on the cell pad structure (130). By patterning the conductive barrier film (164) and the landing pad conductive layer (166), a plurality of landing pads (LP) composed of the conductive barrier film (164) and the landing pad conductive layer (166) can be formed.

[0076] Afterwards, an insulating pattern (168) covering multiple landing pads (LP) can be formed.

[0077] Subsequently, a plurality of lower electrodes (not shown) connected to a landing pad (LP) can be formed, and a capacitor dielectric layer (not shown) and an upper electrode (not shown) can be sequentially formed on the side walls of the plurality of lower electrodes.

[0078] A semiconductor device (100) can be completed by performing the above-described method.

[0079] Generally, an island-type direct contact hole is formed by removing a portion of the cell pad structure, and a direct contact is formed by filling the direct contact hole with a conductive material. However, if misalignment occurs during the patterning process for forming the direct contact hole, a cell pad structure with a locally small area may be formed. In such cases, the contact resistance between the active region and the landing pad increases, which may degrade the electrical characteristics of the semiconductor device.

[0080] However, according to exemplary embodiments, a cell pad preliminary pattern (130P2) is formed by forming a first cell pad separation pattern (132) and a second cell pad separation pattern (134) to intersect at an acute angle, and then a direct contact trench (DCT) is formed in a double patterning manner using a reference pattern (142) and a spacer (144) extending in a second diagonal direction (D2), thereby forming a first cell pad (132L) and a second cell pad (132R). Thus, the first cell pad (132L) and the second cell pad (132R) can be formed to have the same area, and the semiconductor device (100) can have excellent electrical characteristics.

[0081] Additionally, according to exemplary embodiments, a direct contact trench (DCT) can be formed in the process of patterning the cell pad structure (130) without performing a separate patterning process for forming the direct contact hole. Thus, the process of forming the cell pad structure (130) and the direct contact (DC) can be simplified. Furthermore, by patterning the cell pad structure (130) in a self-aligning manner using a reference pattern (142) and a spacer (144), a cell pad structure (130) having a relatively small width can be formed within the resolution limit of the photolithography process.

[0082] Meanwhile, FIGS. 6a to 13b exemplarily describe a method of forming a direct contact (DC) by directly filling a conductive layer (152) on the inner wall of a direct contact trench (DCT) and patterning the conductive layer (152). In other embodiments, before forming the conductive layer (152) on the inner wall of a direct contact trench (DCT), an insulating liner (172) may be conformally formed on the inner wall of a direct contact trench (DCT), a portion of the insulating liner (172) covering the bottom of an active region (AC) may be removed, and a conductive layer (152) filling the interior of the direct contact trench (DCT) may be formed on the insulating liner (172). In this case, the semiconductor device (100A) described with reference to FIGS. 4 and 5 may be formed. According to the above-described embodiment, even if the gap between the direct contact (DCA) and the cell pad structure (130) is relatively small, a process defect in which the cell pad structure (130) and the direct contact (DCA) are electrically connected can be prevented.

[0083] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0084] 100: Semiconductor device 130: Cell pad structure 132: 1st cell pad separation pattern 134: 2nd cell pad separation pattern 142: Reference pattern 144: Spacer DCT: Direct Contact Trench

Claims

Claim 1 A semiconductor device comprising: a substrate having a plurality of active regions defined therein; a plurality of word lines disposed within a plurality of word line trenches formed on the substrate and extending in a first direction parallel to the upper surface of the substrate; a plurality of bit line structures formed on the substrate and extending in a second direction parallel to the upper surface of the substrate; and a plurality of cell pad structures disposed on the active region between each of the plurality of bit line structures, each having a pair of first sidewalls extending in the first direction within a plane defined by the first direction and the second direction, and a pair of second sidewalls extending in a diagonal direction inclined with respect to the first direction and the second direction within the plane. Claim 2 A semiconductor device according to claim 1, wherein the plurality of cell pad structures include a first cell pad and a second cell pad, and in a plan view, the first cell pad and the second cell pad have a parallelogram shape. Claim 3 A semiconductor device according to paragraph 2, characterized in that the horizontal cross-sectional area of ​​the first cell pad is the same as the horizontal cross-sectional area of ​​the second cell pad. Claim 4 A semiconductor device according to claim 2, further comprising: a plurality of first cell pad separation patterns extending in the first direction on the substrate and contacting the pair of first sidewalls of the plurality of cell pad structures; and a plurality of second cell pad separation patterns extending in the diagonal direction on the substrate and contacting the pair of second sidewalls of the plurality of cell pad structures. Claim 5 A semiconductor device according to claim 4, characterized in that the first cell pad, the bit line, and the second cell pad are spaced apart from each other between two adjacent first cell pad separation patterns among the plurality of first cell pad separation patterns and between two adjacent second cell pad separation patterns among the plurality of second cell pad separation patterns. Claim 6 A semiconductor device according to claim 4, further comprising a direct contact disposed between the plurality of bit line structures and the plurality of active regions within a direct contact trench extending in the diagonal direction, wherein the direct contact has a pair of first sidewalls extending in the first direction and a pair of second sidewalls extending in the second direction. Claim 7 A semiconductor device according to claim 6, further comprising an insulating fence disposed within the direct contact trench and covering the sidewall of the direct contact and the sidewall of the bit line structure, wherein the bottom surface of the insulating fence is disposed at the same level as the bottom surface of the direct contact. Claim 8 A semiconductor device according to claim 6, characterized in that the bottom surface of the direct contact is positioned at a higher level than the bottom surface of the first cell pad separation pattern, and the bottom surface of the direct contact is positioned at a higher level than the bottom surface of the second cell pad separation pattern. Claim 9 A semiconductor device according to claim 4, further comprising a direct contact disposed between the plurality of bit line structures and the plurality of active regions within a direct contact trench extending in the diagonal direction, wherein the direct contact has a pair of first sidewalls extending in the diagonal direction and a pair of second sidewalls extending in the second direction. Claim 10 A semiconductor device according to claim 9, further comprising an insulating liner disposed on the inner wall of the direct contact trench, wherein the insulating liner is interposed between the pair of first sidewalls of the direct contact and the pair of second sidewalls of the cell pad structure.

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