Printed circuit board and semiconductor package using the same

Abstract

A printed circuit board according to one embodiment comprises: a substrate structure having a first surface including a chip mounting area on which a semiconductor chip is mounted and a second surface opposite to the first surface, wherein the second surface has a rectangular shape having first to fourth corners and first to fourth corners defined by the first to fourth corners; and pad patterns disposed on the second surface of the substrate structure, wherein the second surface includes a first area that includes an area corresponding to the chip mounting area and contacts each corner of the second surface, and second areas that are adjacent to each corner of the second surface and spaced apart from each other by the first area, and the pad patterns may include first pad patterns disposed on the first area and surface-treated with a nickel / gold (Ni / Au) layer, and second pad patterns disposed on the second areas and surface-treated with an organic solderability preservative (OSP).

Description

Technology Field

[0001] The present invention relates to a printed circuit board and a semiconductor package using the same. Background Technology

[0003] Semiconductor packages are mounted on a substrate (e.g., a main board) via connection bumps, such as solder balls. The reliability of a semiconductor package is affected by the connection status between the connection bumps and the package. To ensure the reliability of the semiconductor package, technology capable of preventing cracks occurring in pad patterns and connection bumps is required. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a printed circuit board with improved electrical characteristics and reliability, and a semiconductor package using the same. means of solving the problem

[0007] A printed circuit board according to one embodiment comprises: a substrate structure having a first surface including a chip mounting area on which a semiconductor chip is mounted and a second surface opposite to the first surface, wherein the second surface has a rectangular shape having first to fourth corners and first to fourth corners defined by the first to fourth corners; and pad patterns disposed on the second surface of the substrate structure, wherein the second surface includes a first area that includes an area corresponding to the chip mounting area and contacts each corner of the second surface, and second areas that are adjacent to each corner of the second surface and spaced apart from each other by the first area, and the pad patterns may include first pad patterns disposed on the first area and surface-treated with a nickel / gold (Ni / Au) layer, and second pad patterns disposed on the second areas and surface-treated with an organic solderability preservative (OSP).

[0009] A semiconductor package according to one embodiment comprises: a semiconductor chip; a substrate structure having a first surface including a chip mounting area on which the semiconductor chip is mounted and a second surface opposite to the first surface, wherein the second surface has a rectangular shape having first to fourth corners and first to fourth corners defined by the first to fourth corners; pad patterns disposed on the second surface of the substrate structure; and connecting bumps each connected to the pad patterns, wherein the pad patterns may include first pad patterns disposed in a first area adjacent to each of the first to fourth corners and including an area corresponding to at least the chip mounting area, and directly contacting the connecting bumps and made of a first metal material, and second pad patterns disposed in second areas adjacent to each of the first to fourth corners and being areas other than the first area, made of a first metal material, and having a metal layer made of a second metal material disposed at an interface contacting the connecting bumps. Effects of the invention

[0011] By varying the surface treatment of the pad pattern according to the position of the pad pattern, a printed circuit board and a semiconductor package with improved electrical characteristics and reliability can be provided.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1 is a cross-sectional view showing a printed circuit board according to one embodiment. Figure 2 is a plan view taken from direction I of Figure 1. FIGS. 3a and FIGS. 3b are drawings for explaining how solder balls are attached to a pad pattern of a printed circuit board according to one embodiment. FIGS. 4a to 4d are variations of the pad pattern of FIG. 2. FIG. 5 is a cross-sectional view showing a semiconductor package employing the printed circuit board of FIG. 1. Specific details for implementing the invention

[0016] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0018] With reference to FIGS. 1 and FIGS. 2, a printed circuit board according to one embodiment will be described. FIGS. 1 is a cross-sectional view showing a printed circuit board according to one embodiment, and FIGS. 2 is a plan view seen in direction I of FIGS. 1.

[0020] Referring to FIGS. 1 and 2, a printed circuit board (100) may include a substrate structure (120) on which pad patterns (133P) are disposed. The substrate structure (120) may include insulating layers (121, 122, 123), passivation layers (124, 125), and a wiring structure (130). One embodiment is described as an example in which the substrate structure (120) is formed as a multilayer structure including insulating layers (121, 122, 123). However, it is not limited thereto, and the substrate structure (120) may be formed as a single layer structure. The wiring structure (130) may include wiring patterns (133), connection vias (135), and pad patterns (133P). The printed circuit board (100) may be a support substrate for manufacturing a semiconductor package by mounting a semiconductor chip. A substrate structure (120) may have a first surface (S1) and a second surface (S2) located on opposite sides. In one embodiment, the first surface (S1) and the second surface (S2) may have a rectangular shape. A chip mounting area (AC) on which a semiconductor chip is mounted may be provided on the first surface (S1). Pad patterns (133P) may be disposed on the second surface (S2).

[0022] The insulating layers (121, 122, 123) may include a plurality of insulating layers (121, 122, 123) stacked in the vertical direction (Z), for example, a first insulating layer (121), a second insulating layer (122), and a third insulating layer (123). The insulating layers (121, 122, 123) may cover wiring patterns (133) and connection vias (135). The insulating layers (121, 122, 123) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler or / and glass fiber (glass fiber, glass cloth, glass fabric) is impregnated into these resins, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine). The insulating layers (121, 122, 123) may include a photosensitive resin such as PID (Photoimageable Dielectric) resin. In this case, the insulating layers (121, 122, 123) may be formed thinner, and fine wiring patterns (133) and connecting vias (135) may be formed. Depending on the process, the boundary between different levels of insulating layers (121, 122, 123) may be indistinct.

[0023] Passivation layers (124, 125) may be provided as layers to protect the semiconductor package from external physical or chemical damage, etc. Passivation layers (124, 125) may protect the substrate structure (120). The first passivation layer (124) may be disposed in the lower region of the substrate structure (120), for example, to cover the lower surface of the first insulating layer (121). The second passivation layer (125) may be disposed in the upper region of the substrate structure (120), for example, to cover the upper surface of the third insulating layer (123). The passivation layers (124, 125) may include an insulating resin and an inorganic filler, but may not include glass fibers. For example, the passivation layers (124, 125) may include ABF, but are not limited thereto, a photosensitive insulating material (PID) or an insulating polymer, for example, PSPI (Photosensitive Polyimide). The passivation layers (124, 125) may each have openings (OP) that open the lower and upper surfaces of the substrate structure (120). The openings (OP) of the first passivation layer (124) may open the second surface (S2) of the substrate structure (120), and one region of the pad patterns (133P) may be exposed through the openings (OP). Connecting bumps, such as solder balls, may be connected to the one region of the pad patterns (133P) exposed through the openings (OP). A printed circuit board (100) of one embodiment may be provided with connection bumps not connected to the pad patterns (133P).

[0025] Pad patterns (133P) may be disposed adjacent to a second surface (S2) of a substrate structure (120). The pad patterns (133P) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. One embodiment is described as an example where the pad patterns (133P) include copper.

[0027] Referring to FIGS. 1 and 2, the pad patterns (133P) may include first pad patterns (133P-1) and second pad patterns (133P-2). The first pad patterns (133P-1) may be placed in a first region (A1) of the second surface (S2), and the second pad patterns (133P-2) may be placed in second regions (A2) of the second surface (S2). The pad patterns (133P) may be arranged in a matrix form forming rows and columns on the second surface (S2) of the substrate structure (120). The width and spacing of the pad patterns (133P) may be arranged uniformly, but are not limited thereto, and depending on the embodiment, the width and spacing of the pad patterns (133P) may not be uniform. Additionally, one embodiment is described as an example where the pad patterns (133P) are arranged in a 7×7 configuration, but is not limited thereto, and the number and arrangement of the pad patterns (133P) can be varied in many ways.

[0029] Referring to FIG. 2, the first region (A1) and the second regions (A2) can be arranged on the second surface (S2) of the substrate structure (120) so as not to overlap each other.

[0030] The first region (A1) is positioned adjacent to at least one of the first to fourth corners (E1 to E4) of the second surface (S2) and may include all areas corresponding to the chip mounting area (AC) of the first surface (S1). That is, the first region (A1) may be positioned to include the chip mounting area (AC) while being adjacent to all of the first to fourth corners (E1 to E4). The first pad patterns (133P-1) described above may be positioned in the first region (A1).

[0032] The second regions (A2) are regions other than the first region (A1) and may be disposed adjacent to the first to fourth corners (C1 to C4) of the substrate structure (120), respectively. The second regions (A2) may be spaced apart from each other by the first region (A1). The second regions (A2) may include regions extending along the first to fourth corners (E1 to E4) to the extent of being spaced apart. The second regions (A2) may have shapes that are mirror-symmetric to each other and may have the same area. Accordingly, the same number of second pad patterns may be disposed in each of the second regions (A2). According to an embodiment, the second regions (A2) may have shapes that are mirror-symmetric to each other. The second regions (A2) may be arranged rotationally symmetrically every 90° with respect to the center (CA) of the second surface (S2). The shape of the second regions (A2) may be a square, a triangle, an L-shape, an I-shape, or a combination thereof. One embodiment is described by giving an example where the second regions (A2) are L-shaped.

[0033] In the second regions (A2), a second pad pattern (133P-2A) may be disposed adjacent to each of the first to fourth corners (C1 to C4) of the pad patterns (133P). Additionally, in the second regions (A2), at least one second pad pattern (133P-2B) may be further included in addition to the second pad pattern (133P-2A) closest to each of the first to fourth corners (C1 to C4).

[0034] The arrangement of the second regions (A2) can be varied in many ways. FIGS. 4a to 4d are examples of variations of the pad pattern of FIG. 2.

[0036] FIG. 4a shows a case where the first regions (A1) are minimally arranged on the second surface (S2) of the substrate structure (120) included in the printed circuit board (100A). The second regions (A2) may be arranged to include only one second pad pattern (133P-2A) adjacent to the first to fourth corners (C1 to C4) of the second surface (S2) of the substrate structure (120). Thus, the area of ​​the first region (A1) can be maximized. The second pad patterns (133P-2) may be arranged in a shape and column on the first regions (A1).

[0038] FIG. 4b shows a case where the first regions (A1) are arranged in an I-shape on the second surface (S2) of the substrate structure (120) included in the printed circuit board (100B). The second regions (A2) may be arranged extending along the third corner (E3) and the fourth corner (E4), while adjacending the first to fourth corners (C1 to C4) of the second surface (S2) of the substrate structure (120). Additionally, the chip mounting region (AC) may be arranged adjacent to the first corner (E1) and the second corner (E2) of the second surface (S2). The second pad patterns (133P-2) may be arranged in a shape and row on the first regions (A1).

[0040] FIG. 4c is a case where the first regions (A1) are arranged in a triangle on the second surface (S2) of the substrate structure (120) included in the printed circuit board (100C). The second regions (A2) may be arranged in a triangle extending along the first to fourth corners (E1 to E4), each adjacent to the first to fourth corners (C1 to C4) of the second surface (S2) of the substrate structure (120). The second pad patterns (133P-2) may be arranged in a shape and row on the first regions (A1).

[0042] FIG. 4d is a case where the first regions (A1) have an overall triangular shape on the second surface (S2) of the substrate structure (120) included in the printed circuit board (100D), and have a cut portion so as not to overlap with the first and second chip mounting regions (AC1, AC2). The second pad patterns (133P-2) can be arranged in a shape and row on the first regions (A1).

[0044] Referring again to FIG. 1, the surface of each of the first pad patterns (133P-1) can be surface-treated with a metal layer (137N). The metal layer (137N) can improve thermal cycle (TC) reliability among board level reliability (BLR). As the pad pattern (133P) becomes finer, its thickness decreases, making it vulnerable to pattern cracking. For example, the occurrence of pattern cracking can cause a significant decrease in thermal cycle (TC) reliability among board level reliability (BLR). Here, TC reliability is a test that checks whether reliability is maintained up to a predetermined number of times by repeatedly raising and lowering the temperature periodically at the board level. In one embodiment, a metal layer (137N) is formed by additionally performing a surface treatment process on the first pad patterns (133P-1), thereby preventing cracks from occurring in the first pad patterns (133P-1). Accordingly, TC reliability is improved, the lifespan is enhanced, and the electrical characteristics and reliability of the semiconductor package can be improved.

[0045] In one embodiment, the metal layer (137N) may be a nickel / gold (Ni / Au) layer. The metal layer (137N) may be formed to cover the first pad patterns (133P-1) while in contact with the side of the openings (OP). The metal layer (137N) may be a multilayer structure in which a nickel layer (137N-1) and a gold layer (137N-2) are sequentially stacked. The nickel layer (137N-1) may be positioned in direct contact with the first pad patterns (133P-1), and the gold layer (137N-2) may be positioned to cover the nickel layer (137N-1). Thus, the gold layer (137N-2) may be exposed on the bottom surface of the openings (OP). The gold layer (137N-2) is consumed during the process of attaching connecting bumps to the first pad patterns (133P-1), but the nickel layer (137N-1) remains between the first pad patterns (133P-1) and the connecting bumps. Therefore, compared to the case where the metal layer (137N) is not formed on the first pad patterns (133P-1), it can be made thicker by the thickness (t1) of the nickel layer (137N-1).

[0046] Referring to FIG. 3a, before connecting the connecting bumps (180) to the first pad patterns (133P-1), solder (138) is applied on the metal layer (137N) and connecting bumps (180), such as solder balls, are attached. The gold layer (137N-2) of the nickel / gold layer (137N) diffuses into the interior of the connecting bumps (180) when the connecting bumps (180) are attached, thereby facilitating the fusion between the first pad patterns (133P-1) and the connecting bumps (180). Thus, a metal bonding layer (L1) made of a nickel-tin alloy can be formed at the interface between the first pad patterns (133P-1) and the connecting bumps. The metal bonding layer (L1) made of an alloy of nickel and tin has high TC reliability, but has a relatively low BLR drop reliability, which is a test against external impact or bending.

[0048] The surfaces of the second pad patterns (133P-2) can each be surface-treated with an organic solderability preservative (OSP) (137o). OSP is an organic solvent that has the characteristic of high adhesion to copper surfaces, and when surface-treated, it can prevent the surfaces of the second pad patterns (133P-2) from oxidizing.

[0049] Referring to FIG. 3b, before connecting the connection bumps (180) to the second pad patterns (133P-1), flux (FL) can be applied to the OSP (137o) to clean the OSP (137o). Thus, a metal bonding layer (L2) made of an alloy of copper and tin can be formed at the interface between the second pad patterns (133P-2) and the connection bumps (180). The metal bonding layer made of an alloy of copper and tin has high drop reliability because it is strong against external impact and bending, but it has a weakness of relatively low TC reliability compared to the case where the surface is treated with a metal layer.

[0050] When a printed circuit board (100) is mounted on a board such as a module board via connection bumps (180), the pad patterns of the board connected to the connection bumps (180) mostly contain copper and are surface-treated with OSP. Therefore, if the second pad patterns (133P-1) are surface-treated with OSP (137o), the surface treatment is identical to that of the pad patterns of the board, so drop reliability can be further improved.

[0052] In one embodiment, the printed circuit board (100) can simultaneously improve the TC reliability and Drop reliability of the semiconductor package in which the printed circuit board (100) is employed by surface treating the second pad patterns (133P-2) placed in the corner area of ​​the printed circuit board (100) where relatively high stress due to impact is applied with OSP (137o), and surface treating the first pad patterns (133P-1) placed in the other area with a metal layer (137N).

[0054] Referring to FIG. 1, wiring patterns (133) may be placed on or within insulating layers (121, 122, 123). Wiring patterns (133) may be electrically connected to each other. Wiring patterns (133) may include a barrier layer (131) and a wiring conductive layer (132). The barrier layer (131) may include at least one of titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride (TiN), and tantalum nitride (TaN). The wiring conductive layer (132) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0056] Connecting vias (135) can interconnect a plurality of wiring patterns (133) by penetrating insulating layers (121, 122, 123). Connecting vias (135) can interconnect a plurality of wiring patterns (133) and pad patterns (133P). Connecting vias (135) may include a barrier layer (131) and a wiring via layer (134). The barrier layer (131) may extend along the bottom surface of the wiring patterns (133) and along the bottom surface and sides of the connecting vias (135). The wiring via layer (134) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The connecting vias (135) may have the form of a filled via in which a metallic material is filled inside the via hole, or a conformal via in which a metallic material is formed along the inner wall of the via hole.

[0058] Referring to FIG. 5, a semiconductor package according to one embodiment will be described. FIG. 5 is a cross-sectional view showing a semiconductor package employing the printed circuit board (100) of FIG. 1. Since the printed circuit board employed in the semiconductor package of one embodiment has the same configuration as the printed circuit board (100) described above in FIG. 1, a detailed description is omitted.

[0060] A semiconductor chip (200) is disposed on the upper surface of a printed circuit board (100) and may include a connection pad (P) that is electrically connected to wiring patterns (133) of the printed circuit board (100). For example, the semiconductor chip (200) may be disposed such that the side on which the connection pad (P) is not disposed faces the printed circuit board (100). The connection pad (P) may include a metallic material, for example, aluminum (Al). In an exemplary embodiment, the semiconductor chip (200) may be stacked in one or more numbers. Each semiconductor chip (140) may include an adhesive layer (210) disposed on the lower surface, and the adhesive layer (210) may be bonded to the printed circuit board (100). The connection pad (P) may be disposed on the side opposite to the side on which the adhesive layer (210) is disposed on the semiconductor chip (200). In an exemplary embodiment, the semiconductor chip (200) may be mounted on the printed circuit board (100) by wire bonding. For example, the bonding wire (220) may be connected to the connection pad (P) and the wiring patterns (133) to provide an electrical connection path between them. Alternatively, the semiconductor chip (200) may be mounted on the printed circuit board (100) by flip-chip bonding.

[0061] The semiconductor chip (200) may be a logic chip or a memory chip. The logic chip may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc. The memory chip may include, for example, a volatile memory device such as a dynamic RAM (DRAM) or a static RAM (SRAM), or a non-volatile memory device such as a phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or flash memory.

[0063] A capping layer (300) is placed on a printed circuit board (100) and can cover a semiconductor chip (200) and the printed circuit board (100). The capping layer (300) may include an insulating material, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg including an inorganic filler or / and glass fiber, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), EMC (Epoxy Molding Compound), etc.

[0065] The connection bumps (180) may have the form of lands, balls, or pins. The connection bumps (180) may include, for example, tin (Sn) or an alloy containing tin (Sn) (e.g., Sn-Ag-Cu). The connection bumps (180) are placed below the printed circuit board (100), for example, on the second side (S2) of the printed circuit board (100), and may be electrically connected to the pad patterns (133P). The connection bumps (180) may be electrically connected to a nickel layer (137N-1) placed below the pad patterns (133P). The connection bumps (180) may physically and / or electrically connect the semiconductor package (10) to a separate board. The connection bumps (180) may include, for example, lead-free solder balls.

[0067] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0069] 10: Semiconductor package 100: Printed circuit board 121, 122, 123: Insulation layer 124, 125: Passivation layer 130: Wiring structure 131: Barrier layer 132: Wiring conductive layer 133: Wiring pattern 134: Wiring via layer 135: Connection via 137, 138, 139: Metal layer 140: Semiconductor chip 145: Bonding wire 150: Capping layer 160, 180: Connecting bumps 170: Underfill resin 190: Vertical connection structure 200: Semiconductor chip 300: Capping layer

Claims

Claim 1 A substrate structure having a first surface including a chip mounting area on which a semiconductor chip is mounted, and a second surface opposite to the first surface—the second surface is in the shape of a rectangle having first to fourth corners and first to fourth corners defined by the first to fourth corners—; A printed circuit board comprising pad patterns disposed on a second surface of the substrate structure, wherein the second surface comprises a first region that contacts each corner of the second surface and includes a region corresponding to the chip mounting area, and second regions that are adjacent to each corner of the second surface and spaced apart from each other by the first region, wherein the pad patterns comprise first pad patterns disposed in the first region and surface-treated with a nickel / gold (Ni / Au) layer, and second pad patterns disposed in the second regions and surface-treated with an organic solderability preservative (OSP), wherein the level of at least one lower surface of the surface-treated first pad patterns is lower than the level of at least one lower surface of the surface-treated second pad patterns. Claim 2 A printed circuit board according to claim 1, wherein the substrate structure further comprises a passivation layer having openings that cover some of the pad patterns and open a portion of the second surface to define the pad patterns. Claim 3 In paragraph 2, the organic solder preservative and the nickel / gold layer are each a printed circuit board in contact with the openings. Claim 4 In paragraph 3, the nickel / gold layer comprises: a nickel layer in direct contact with the first pad patterns along a direction perpendicular to the second plane; and a gold layer laminated on the nickel layer, comprising a printed circuit board. Claim 5 In paragraph 2, the pad patterns are printed circuit boards containing copper (Cu). Claim 6 A printed circuit board according to claim 1, wherein the second pad patterns include first to fourth corner adjacent pad patterns adjacent to each of the first to fourth corners. Claim 7 In claim 6, the second regions each comprise a printed circuit board including a region extended along the first to fourth corners. Claim 8 In claim 1, the pad patterns are arranged in a matrix form having multiple rows and columns on a printed circuit board. Claim 9 A substrate structure having a first surface including a chip mounting area on which a semiconductor chip is mounted and a second surface opposite to the first surface; and pad patterns disposed on the second surface of the substrate structure, wherein the second surface includes a first area that contacts each corner of the second surface and includes an area corresponding to the chip mounting area, and second areas that are adjacent to each corner of the second surface and spaced apart from each other, wherein the pad patterns include first pad patterns surface-treated with a metal layer and second pad patterns surface-treated with an anti-oxidation layer, wherein the first pad patterns are disposed within the first area and the second pad patterns are disposed within the second areas, and the level of at least one lower surface of the surface-treated first pad patterns is lower than the level of at least one lower surface of the surface-treated second pad patterns. Claim 10 In claim 9, the metal layer comprises a nickel / gold (Ni / Au) layer, and the oxidation prevention layer comprises an organic solderability preservative (OSP) printed circuit board. Claim 11 In claim 9, the second regions are each printed circuit boards that do not overlap with the chip mounting region. Claim 12 In claim 9, the second regions are printed circuit boards arranged rotationally symmetrically every 90° with respect to the center of the second surface. Claim 13 In claim 9, the second regions each have substantially the same area and are printed circuit boards. Claim 14 In claim 9, the second regions each include a second pad pattern adjacent to the corner among the second pad patterns, on a printed circuit board. Claim 15 A semiconductor chip; a substrate structure having a first surface including a chip mounting area on which the semiconductor chip is mounted and a second surface opposite to the first surface, wherein the second surface has a rectangular shape having first to fourth corners and first to fourth corners defined by the first to fourth corners; pad patterns disposed on the second surface of the substrate structure; and connection bumps each connected to the pad patterns, wherein the pad patterns include first pad patterns disposed in a first area adjacent to each of the first to fourth corners and including an area corresponding to at least the chip mounting area, and having a first metal material in direct contact with the connection bumps, and having a metal layer made of a second metal material disposed at an interface in contact with the connection bumps, and second pad patterns disposed in second areas adjacent to each of the first to fourth corners and being areas other than the first area, and having a first metal material, wherein the level of at least one lower surface of the first pad patterns is lower than the level of at least one lower surface of the second pad patterns. Claim 16 In claim 15, the first metal material comprises copper (Cu), the second metal material comprises nickel (Ni), and the connecting bumps comprise tin (Sn) in a semiconductor package. Claim 17 In claim 15, in a vertical direction perpendicular to the second surface, the first pad pattern has a first thickness between the upper surface and the lower surface, in the vertical direction, the second pad pattern has a second thickness between the upper surface and the lower surface, the metal layer has a third thickness between the upper surface and the lower surface, and the sum of the second thickness and the third thickness is greater than the first thickness, for a semiconductor package. Claim 18 In claim 15, the substrate structure further comprises a passivation layer having openings that cover some of the pad patterns and open a portion of the second surface to define the pad patterns, and the connecting bumps each contact the sides of the openings and are connected to the pad patterns. Claim 19 A semiconductor package according to claim 18, further comprising a capping layer covering a first surface of the semiconductor chip and the substrate structure. Claim 20 In paragraph 18, the above-mentioned connecting bumps are lead-free solder balls in a semiconductor package.

Images