Semiconductor devices

Abstract

A semiconductor device comprises a substrate having a plurality of active patterns, a bit line extending in a first direction across the plurality of active patterns on the substrate, and bit line contacts arranged in the first direction below the bit line and electrically connected to each of the plurality of active patterns. The bit line includes an upper conductive pattern extending in the first direction over the bit line contacts, a bit line capping pattern extending in the first direction over the upper conductive pattern, and a diffusion barrier pattern extending in the first direction between the upper conductive pattern and the bit line capping pattern. The upper conductive pattern comprises ruthenium (Ru), and the diffusion barrier pattern comprises a graphene pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and / or low operating voltages. To meet these requirements, semiconductor devices are becoming more highly integrated. As the integration of semiconductor devices intensifies, their reliability may decrease. However, as the electronics industry develops to a high degree, the demand for high reliability in semiconductor devices is increasing. Consequently, much research is being conducted to improve the reliability of semiconductor devices. Prior art literature

[65535] U.S. Patent Application Publication US 2018 / 0158828 A1 The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and a method for manufacturing the same.

[0005] Another technical objective of the present invention is to provide a semiconductor device having excellent reliability and a method for manufacturing the same. means of solving the problem

[0006] A semiconductor device according to the present invention may include a substrate (100) comprising a plurality of active patterns (ACT); a bit line (BL) extending in a first direction across the plurality of active patterns on the substrate; and bit line contacts (DC) arranged in the first direction below the bit line and electrically connected to each of the plurality of active patterns. The bit line may include an upper conductive pattern (134) extending in the first direction over the bit line contacts; a bit line capping pattern (BCP) extending in the first direction over the upper conductive pattern; and a diffusion barrier pattern (136) extending in the first direction between the upper conductive pattern and the bit line capping pattern. The upper conductive pattern (134) may include ruthenium (Ru), and the diffusion barrier pattern (136) may include a graphene pattern.

[0007] A semiconductor device according to the present invention may include: a substrate (100) comprising a plurality of active patterns (ACT); bit lines (BL) crossing the plurality of active patterns on the substrate, wherein the bit lines extend in a first direction and are spaced apart from each other in a second direction, wherein the first direction and the second direction are parallel to the lower surface of the substrate and intersect each other; bit line contacts arranged in the first direction below each of the bit lines and electrically connected to corresponding active patterns among the plurality of active patterns; storage node contacts spaced apart from each other in the first direction between the bit lines and electrically connected to the ends of corresponding active patterns among the plurality of active patterns; and a capacitor structure connected to the storage node contacts. Each of the bit lines may include an upper conductive pattern extending in the first direction on the bit line contacts and comprising ruthenium (Ru); and a bit line capping pattern extending in the first direction on the upper conductive pattern and comprising a silicon compound. and may include a diffusion barrier pattern extending in the first direction between the upper conductive pattern and the bit line capping pattern. The diffusion barrier pattern may include a graphene pattern. Effects of the invention

[0008] According to the concept of the present invention, a bit line may include a diffusion barrier pattern interposed between an upper conductive pattern containing ruthenium (Ru) and a bit line capping pattern, and the diffusion barrier pattern may include a graphene pattern. As the upper conductive pattern contains ruthenium (Ru), the bit line may have low resistance. Additionally, the graphene pattern may prevent silicon within the bit line capping pattern from diffusing into the upper conductive pattern, and as a result, an increase in the resistance of the bit line may be prevented. Accordingly, a semiconductor device with improved electrical characteristics and excellent reliability may be provided. Brief explanation of the drawing

[0009] FIG. 1 is a plan view of a semiconductor device according to embodiments of the present invention. Figure 2 is a cross-sectional view along A-A' of Figure 1. Figure 3 is a cross-sectional view along B-B' of Figure 1. Figures 4a to 4d are enlarged views of part P1 of Figure 2. FIGS. 5, FIGS. 8, FIGS. 10, FIGS. 12 and FIGS. 14 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views corresponding to A-A' of FIG. 1. FIGS. 6, FIGS. 9, FIGS. 11, FIGS. 13, and FIGS. 15 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views corresponding to B-B' of FIG. 1. Figures 7a to 7d are enlarged views of part P2 of Figure 5. Figure 16 is an XPS graph of a graphene pattern within a diffusion barrier pattern of Figure 1. Figure 17 is a graph showing the Raman peaks of the graphene pattern within the diffusion barrier pattern of Figure 1. Specific details for implementing the invention

[0010] The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings.

[0011] FIG. 1 is a plan view of a semiconductor device according to embodiments of the present invention. FIG. 2 is a cross-sectional view along A-A' of FIG. 1, and FIG. 3 is a cross-sectional view along B-B' of FIG. 1. FIG. 4a to 4d are enlarged views of portion P1 of FIG. 2.

[0012] Referring to FIGS. 1, 2 and 3, a substrate (100) may be provided. The substrate (100) may be a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of active patterns (ACTs) may be disposed on the substrate (100). The active patterns (ACTs) may be spaced apart from each other along a first direction (D1) and a second direction (D2) parallel to the lower surface (100L) of the substrate (100). The first direction (D1) and the second direction (D2) may intersect each other. Each of the active patterns (ACTs) may have a bar shape extending in a third direction (D3) parallel to the lower surface (100L) of the substrate (100) and intersecting both the first direction (D1) and the second direction (D2). Each of the above active patterns (ACT) may be a part of the substrate (100) protruding from the substrate (100) along a fourth direction (D4) perpendicular to the lower surface (100L) of the substrate (100).

[0013] A device isolation layer (102) may be disposed on the substrate (100) to define the active patterns (ACT). The device isolation layer (102) may be interposed between the active patterns (ACT). The device isolation layer (102) may, for example, comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

[0014] A plurality of word lines (WL) may be disposed on the substrate (100) and may cross the active patterns (ACT) and the device isolation film (102). The word lines (WL) may be spaced apart from each other in the first direction (D1) and may extend along the second direction (D2). The word lines (WL) may be embedded word lines embedded within the substrate (100) and may be embedded within the active patterns (ACT) and the device isolation film (102).

[0015] Each of the above word lines (WL) may include a gate electrode (GE) penetrating the upper portions of the active patterns (ACT) and the device isolation layer (102), a gate dielectric pattern (GI) interposed between the gate electrode (GE) and the active patterns (ACT) and between the gate electrode (GE) and the device isolation layer (102), and a gate capping pattern (GC) on the upper surface of the gate electrode (GE). The upper surface of the gate capping pattern (GC) may be co-plane with the upper surfaces of the active patterns (ACT). For example, the upper surface of the gate capping pattern (GC) may be located at the same height as the upper surfaces of the active patterns (ACT).

[0016] The gate electrode (GE) may include a conductive material. For example, the conductive material may be any one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). The gate dielectric pattern (GI) may include, for example, a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film. The gate capping pattern (GC) may include, for example, a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film.

[0017] A first impurity injection region (110a) and second impurity injection regions (110b) may be provided within each of the active patterns (ACT). The second impurity injection regions (110b) may be spaced apart from each other with the first impurity injection region (110a) in between. The first impurity injection region (110a) may be provided between a pair of word lines (WL) crossing each of the active patterns (ACT). The second impurity injection regions (110b) may be spaced apart from each other with the pair of word lines (WL) in between. The first impurity injection region (110a) may contain impurities of the same conductivity type as the second impurity injection regions (110b).

[0018] An insulating film (120) may be disposed on the substrate (100) and may cover the active patterns (ACT), the device isolation film (102), and the word lines (WL). The insulating film (120) may include, for example, a single film or multiple films comprising at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0019] A plurality of bit lines (BL) may be disposed on the substrate (100) and on the insulating film (120). The bit lines (BL) may cross the word lines (WL). The bit lines (BL) may extend in the first direction (D1) and may be spaced apart from each other in the second direction (D2). Each of the bit lines (BL) may include lower conductive patterns (130) arranged in the first direction (D1) on the insulating film (120), a lower barrier pattern (132) extending in the first direction (D1) on the lower conductive patterns (130), and an upper conductive pattern (134), a diffusion barrier pattern (136), and a bit line capping pattern (BCP) stacked in sequence on the lower barrier pattern (132). Each of the upper conductive pattern (134), the diffusion barrier pattern (136), and the bit line capping pattern (BCP) may extend in the first direction (D1). The bit line capping pattern (BCP) may include a lower capping pattern (140) and an upper capping pattern (142) stacked sequentially on the diffusion barrier pattern (136), and each of the lower capping pattern (140) and the upper capping pattern (142) may extend in the first direction (D1).

[0020] The lower conductive patterns (130) may comprise polysilicon that is doped with or undoped with impurities, and the lower barrier pattern (132) may comprise at least one of a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride) and a metal silicide. The upper conductive pattern (134) may comprise at least one of a metal (e.g., ruthenium, tungsten, titanium, tantalum, etc.) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride). For example, the upper conductive pattern (134) may comprise ruthenium (Ru). The bit line capping pattern (BCP) may comprise a silicon compound. Each of the lower capping pattern (140) and the upper capping pattern (142) may include a silicon compound, and the silicon compound may include, for example, at least one of single-crystal silicon, polysilicon doped with or undoped with impurities, SiOx, SiC, SiN, SiOC, and SiOCN.

[0021] Referring to FIG. 2 and FIG. 4a, the diffusion barrier pattern (136) may include a graphene pattern (136a). The graphene pattern (136a) may be a single graphene layer interposed between the upper conductive pattern (134) and the bit line capping pattern (BCP, i.e., the lower capping pattern (140)), or it may include a plurality of graphene layers stacked in the fourth direction (D4) between the upper conductive pattern (134) and the bit line capping pattern (BCP, i.e., the lower capping pattern (140)). The number of the plurality of graphene layers may be, for example, 2 to 20. The graphene pattern (136a) may have a thickness (136a_T) along the fourth direction (D4), and the thickness (136_T) of the graphene pattern (136a) may be, for example, less than or equal to 100 Å. The graphene pattern (136a) may have a first surface (136a_S1) and a second surface (136a_S2) facing each other in the fourth direction (D4). According to some embodiments, the first surface (136a_S1) of the graphene pattern (136a) may be in contact with the upper conductive pattern (134), and the second surface (136a_S2) of the graphene pattern (136a) may be in contact with the bit line capping pattern (BCP, i.e., the lower capping pattern (140)).

[0022] Referring to FIG. 2, FIG. 4b and FIG. 4c, according to some embodiments, the diffusion barrier pattern (136) may further include an upper barrier pattern (136b) interposed between the graphene pattern (136a) and the bit line capping pattern (BCP, i.e., the lower capping pattern (140)), or between the graphene pattern (136a) and the upper conductive pattern (134). The upper barrier pattern (136b) may include a metal element. The upper barrier pattern (136b) may include at least one of a conductive metal nitride and a metal silicide. The upper barrier pattern (136b) may include, for example, at least one of TiSiN, TiN, TaN, WN, and WSi.

[0023] For example, referring to FIG. 4b, the upper barrier pattern (136b) may be interposed between the graphene pattern (136a) and the bit line capping pattern (BCP, i.e., the lower capping pattern (140)). In this case, the first surface (136a_S1) of the graphene pattern (136a) may be in contact with the upper conductive pattern (134), and the second surface (136a_S2) of the graphene pattern (136a) may be in contact with the upper barrier pattern (136b). The upper barrier pattern (136b) may be interposed between the second surface (136a_S2) of the graphene pattern (136a) and the bit line capping pattern (BCP, i.e., the lower capping pattern (140)).

[0024] As another example, referring to FIG. 4c, the upper barrier pattern (136b) may be interposed between the graphene pattern (136a) and the upper conductive pattern (134). In this case, the first surface (136a_S1) of the graphene pattern (136a) may be in contact with the upper barrier pattern (136b), and the second surface (136a_S2) of the graphene pattern (136a) may be in contact with the bit line capping pattern (BCP, i.e., the lower capping pattern (140)). The upper barrier pattern (136b) may be interposed between the first surface (136a_S1) of the graphene pattern (136a) and the upper conductive pattern (134).

[0025] Referring to FIG. 2 and FIG. 4d, according to some embodiments, the lower capping pattern (140) of the bit line capping pattern (BCP) may include a first lower capping pattern (140a) adjacent to the diffusion barrier pattern (136), and a second lower capping pattern (140b) on the first lower capping pattern (140a). The first lower capping pattern (140a) may be interposed between the diffusion barrier pattern (136) and the second lower capping pattern (140b). The first lower capping pattern (140a) may include a material deposited at a lower temperature than the second lower capping pattern (140b). For example, the first lower capping pattern (140a) may include silicon nitride (SiN) deposited at a relatively low temperature (for example, about 300°C), and the second lower capping pattern (140b) may include silicon nitride (SiN) deposited at a relatively high temperature (for example, about 630°C to 740°C). The thickness (140a_T) of the first lower capping pattern (140a) along the fourth direction (D4) may be smaller than the thickness of the second lower capping pattern (140b) along the fourth direction (D4). The diffusion barrier pattern (136) may include the graphene pattern (136a). According to some embodiments, the first surface (136a_S1) of the graphene pattern (136a) may be in contact with the upper conductive pattern (134), and the second surface (136a_S2) of the graphene pattern (136a) may be in contact with the first lower capping pattern (140a).

[0026] Referring again to FIGS. 1, 2 and 3, bit line contacts (DC) may be positioned below each of the bit lines (BL) and arranged in the first direction (D1). The bit line contacts (DC) may be spaced apart from each other in the first direction (D1) and may be positioned between the lower conductive patterns (130). The lower conductive patterns (130) and the bit line contacts (DC) may be arranged alternately along the first direction (D1). The bit line contacts (DC) may penetrate the insulating film (120) and may be electrically connected to each of the corresponding active patterns (ACT). Each of the bit line contacts (DC) may be electrically connected to the first impurity injection region (110a) of each of the corresponding active patterns (ACT). The upper conductive pattern (134) may extend in the first direction (D1) over the lower conductive patterns (130) and the bit line contacts (DC). The lower barrier pattern (132) may extend in the first direction (D1) between the lower conductive patterns (130) and the upper conductive pattern (134), and between the bit line contacts (DC) and the upper conductive pattern (134).

[0027] A bitline spacer (150) may be placed on each of the two sides of the bit lines (BL). The bitline spacer (150) may extend in the first direction (D1) along each of the sides of the bit lines (BL). The bitline spacer (150) may include a first spacer (151), a second spacer (155), and a third spacer (157) stacked in sequence on each of the sides of the bit lines (BL). The first spacer (151) and the second spacer (155) may be placed on the insulating film (120). The first spacer (151) may extend from each of the respective sides of the bit lines (BL) between the second spacer (155) and the insulating film (120), and the lowest surface of the first spacer (151) may contact the upper surface of the insulating film (120). The lowest surface of the second spacer (155) may contact the first spacer (151). The third spacer (157) may cover the side of the insulating film (120), and the lowest surface of the third spacer (157) may contact the upper surface of the substrate (100).

[0028] The first spacer (151) and the third spacer (157) may each comprise the same insulating material (e.g., silicon nitride), and the second spacer (155) may comprise a material different from the first spacer (151) and the third spacer (157). According to some embodiments, the second spacer (155) may comprise an insulating material (e.g., silicon oxide) having an etch selectivity ratio with respect to the first and third spacers (151, 157). According to other embodiments, the second spacer (155) may be an air gap region.

[0029] A buried insulating pattern (153) may be disposed on each side of the bit line contacts (DC). The buried insulating pattern (153) may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first spacer (151) may extend between each side of the bit line contacts (DC) and the buried insulating pattern (153), and may extend further between the device isolation film (102) and the buried insulating pattern (153). An insulating liner (152) may be interposed between the first spacer (151) and the buried insulating pattern (153). The buried insulating pattern (153) may be spaced apart from the first spacer (151) with the insulating liner (152) in between. At least a portion of the insulating liner (152) may extend between the first spacer (151) and the third spacer (157) and may come into contact with the lowest surface of the second spacer (155). The embedded insulating pattern (153) may come into contact with the lowest surface of the third spacer (157). The insulating liner (152) may, for example, comprise silicon oxide.

[0030] Storage node contacts (BC) may be positioned between adjacent pairs of bit lines (BL). The storage node contacts (BC) may be spaced apart in the first direction (D1) between the pairs of bit lines (BL) and may be electrically connected to the ends of corresponding active patterns (ACT) among the active patterns (ACT). Each of the storage node contacts (BC) may be electrically connected to the second impurity injection region (SD2) of each of the corresponding active patterns (ACT). The storage node contacts (BC) may comprise polysilicon that is impurity-doped or undoped. Insulating fences may be positioned between the storage node contacts (BC). The insulating fences and the storage node contacts (BC) may be alternately positioned in the first direction (D1) between the pairs of bit lines (BL). The insulating fences may comprise silicon nitride, for example.

[0031] The bitline spacer (150) may be interposed between each of the bitlines (BL) and the storage node contacts (BC). The first spacer (151) may be interposed between each of the bitlines (BL) and the second spacer (155), and the third spacer (157) may be interposed between the second spacer (155) and the storage node contacts (BC).

[0032] Landing pads (LP) may be disposed on each of the storage node contacts (BC). The landing pads (LP) may contain a metal-containing material such as tungsten. Each upper portion of the landing pads (LP) may cover the upper surface of the bit line capping pattern (BCP, i.e., the upper capping pattern (142)) and may have a greater width than each of the storage node contacts (BC). Each upper portion of the landing pads (LP) may be shifted sideways from each of the storage node contacts (BC) (for example, in the second direction (D2) or in the opposite direction of the second direction (D2)). Each upper portion of the landing pads (LP) may overlap vertically with the corresponding bit line (BL) among the bit lines (BL). Although not illustrated, a storage node ohmic layer and a diffusion prevention pattern may be interposed between each of the storage node contacts (BC) and each of the landing pads (LP). The above storage node ohmic layer may include a metal silicide. The above diffusion prevention pattern may include a metal nitride, such as a titanium nitride film or a tantalum nitride film.

[0033] A first upper insulating film (160) may fill the space between the landing pads (LP). The first upper insulating film (160) may penetrate a portion of the bit line capping pattern (BCP) (for example, portions of the upper capping pattern (142) and the lower capping pattern (140)) and may come into contact with the upper surfaces of the first to third spacers (151, 155, 157). The first upper insulating film (160) may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0034] A capacitor structure (CAP) may be disposed on the landing pads (LP). The capacitor structure (CAP) may include lower electrodes (BE) disposed on each of the landing pads (LP), an upper electrode (TE) covering the lower electrodes (BE), and a dielectric film (175) between each of the lower electrodes (BE) and the upper electrode (TE). Each of the lower electrodes (BE) may have a cylindrical shape, a hollow cylinder, or a cup shape. The lower electrodes (BE) may include at least one of impurity-doped polysilicon, a metal nitride film such as titanium nitride, and a metal film such as tungsten, aluminum, and copper.

[0035] An upper support pattern (182) may support the upper sidewalls of the lower electrodes (BE), and a lower support pattern (180) may support the lower sidewalls of the lower electrodes (BE). The upper and lower support patterns (182, 180) may include insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. An etch stop layer (170) may cover the first upper insulating layer (160) between the lower electrodes (BE). The etch stop layer (170) may include insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride, for example.

[0036] The dielectric film (175) may cover the surface of the lower electrodes (BE) and the surface of the upper and lower support patterns (182, 180). The dielectric film (175) may include, for example, at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film (for example, a hafnium oxide film). The upper electrode (TE) may be placed on the dielectric film (175) and may fill the space between the lower electrodes (BE) and between the upper support pattern (182) and the lower support pattern (180). The upper electrode (TE) may include at least one of an impurity-doped polysilicon film, an impurity-doped silicon germanium film, a metal nitride film such as a titanium nitride film, and a metal film such as tungsten, aluminum, and copper.

[0037] In each of the bit lines (BL), when the upper conductive pattern (134) containing ruthenium (Ru) and the bit line capping pattern (CP) containing a silicon compound come into direct contact, ruthenium silicide may be formed at the interface between the upper conductive pattern (134) and the bit line capping pattern (BCP), and as a result, there may be a problem of increased resistance of the bit lines (BL).

[0038] According to the concept of the present invention, each of the upper conductive patterns (134) of the bit lines (BL) may contain ruthenium (Ru), and accordingly, the bit lines (BL) may have low resistance. Additionally, the diffusion barrier pattern (136) may be interposed between the upper conductive pattern (134) containing ruthenium (Ru) and the bit line capping pattern (CP) containing a silicon compound, and the diffusion barrier pattern (136) may include the graphene pattern (136a). The graphene pattern (136a) may include at least one graphene layer. Graphene is a two-dimensional carbon material in which carbon atoms are bonded in a honeycomb structure, and the distance between adjacent carbon atoms may be smaller than the size of a silicon atom. Accordingly, the graphene pattern (136a) may prevent silicon within the bit line capping pattern (BCP) from diffusing into the upper conductive pattern (134). As a result, the formation of ruthenium silicide between the upper conductive pattern (134) and the bit line capping pattern (BCP) can be prevented, and the resistance of the bit lines (BL) can be prevented from increasing.

[0039] Therefore, a semiconductor device with improved electrical characteristics and excellent reliability can be provided.

[0040] FIGS. 5, 8, 10, 12, and 14 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views corresponding to A-A' in FIG. 1. FIGS. 6, 9, 11, 13, and 15 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views corresponding to B-B' in FIG. 1. FIGS. 7a to 7d are enlarged views of portion P2 in FIG. 5. For the sake of simplicity, descriptions that overlap with the semiconductor device described with reference to FIGS. 1, FIGS. 2, FIGS. 3, and FIGS. 4a to 4d are omitted.

[0041] Referring to FIGS. 1, 5 and 6, active patterns (ACTs) may be formed on the substrate (100). Forming the active patterns (ACTs) may, for example, include forming first mask patterns on the substrate (100) and etching the upper surface of the substrate (100) using the first mask patterns as an etching mask. As the upper surface of the substrate (100) is etched, a trench (T) exposing the sides of the active patterns (ACTs) may be formed within the substrate (100). A device isolation film (102) may be formed to fill the trench (T). Forming the device isolation film (102) may, for example, include forming a device isolation insulating film that fills the trench (T) on the substrate (100) and flattening the device isolation insulating film until it is exposed on the upper surface of the substrate (100).

[0042] Word lines (WL) may be formed within the substrate (100) and may cross the active patterns (ACT) and the device isolation film (102). The word lines (WL) may be spaced apart from each other in the first direction (D1) and may extend along the second direction (D2). Each of the word lines (WL) may include a gate electrode (GE) penetrating the upper portions of the active patterns (ACT) and the device isolation film (102), a gate dielectric pattern (GI) interposed between the gate electrode (GE) and the active patterns (ACT) and between the gate electrode (GE) and the device isolation film (102), and a gate capping pattern (GC) on the upper surface of the gate electrode (GE). Forming the gate electrode (GE) and the gate dielectric pattern (GI) may, for example, include forming grooves that penetrate the upper portions of the active patterns (ACT) and the device isolation film (102) within the substrate (100), forming a gate dielectric film covering the inner surface of each of the grooves, forming a gate electrode film that fills each of the grooves, and flattening the gate dielectric film and the gate electrode film until they are exposed on the upper surface of the substrate (100). Forming the gate capping pattern (GC) may, for example, include recessing the upper portion of the gate electrode (GE) to form an empty region within each of the grooves, forming a gate capping film that fills the empty region, and flattening the gate capping film until it is exposed on the upper surface of the substrate (100).

[0043] A first impurity injection region (110a) and second impurity injection regions (110b) may be formed within each of the above active patterns (ACT). Forming the first and second impurity injection regions (110a, 110b) may, for example, involve injecting impurities of the same conductivity type into the active patterns (ACT) using the gate capping pattern (GC) and the device isolation film (102) as masks.

[0044] An insulating film (120) may be formed on the substrate (100) and may cover the active patterns (ACT), the device isolation film (102), and the word lines (WL). A lower conductive film (130L) may be laminated on the insulating film (120). Recessed regions (R1) may be formed to penetrate the insulating film (120) and the lower conductive film (130L), and to extend into the active patterns (ACT) and the device isolation film (102). Forming the recessed regions (R1) may, for example, include forming a second mask pattern on the lower conductive film (130L) that defines the area where the recessed regions (R1) are to be formed, and etching the lower conductive film (130L), the insulating film (120), the active patterns (ACT), and the device isolation film (102) using the second mask pattern as an etching mask. After the above recess regions (R1) are formed, the second mask patterns can be removed.

[0045] A bitline contact film (DCL) may be formed to fill the recess regions (R1). Forming the bitline contact film (DCL) may, for example, include forming the bitline contact film (DCL) that fills the recess regions (R1) on the lower conductive film (130L), and flattening the bitline contact film (DCL) until the upper surface of the lower conductive film (130L) is exposed. Accordingly, the bitline contact film (DCL) may be formed locally within the recess regions (R1).

[0046] A lower barrier film (132L), an upper conductive film (134L), a diffusion barrier film (136L), a lower capping film (140L), and an upper capping film (142L) may be sequentially stacked on the lower conductive film (130L) and may extend onto the bitline contact film (DCL). The lower barrier film (132L) may cover the upper surfaces of the lower conductive film (130L) and the bitline contact film (DCL). Each of the lower barrier film (132L), the upper conductive film (134L), the diffusion barrier film (136L), the lower capping film (140L), and the upper capping film (142L) may be formed using a physical vapor deposition, chemical vapor deposition, or atomic layer deposition method.

[0047] Referring to FIG. 5 and FIG. 7a, the diffusion barrier film (136L) may include a graphene thin film (136La). The graphene thin film (136La) may be a single graphene layer interposed between the upper conductive film (134L) and the lower capping film (140L), or may include a plurality of graphene layers stacked in the fourth direction (D4) between the upper conductive film (134L) and the lower capping film (140L). The graphene thin film (136La) may be formed, for example, using a chemical vapor deposition (CVD) method using microwave plasma, inductively coupled plasma (ICP), capacitively coupled plasma (CCP), or pulsed plasma, a thermal chemical vapor deposition (CVD) method, or an atomic layer deposition (ALD) method.

[0048] Referring to FIG. 5, FIG. 7b and FIG. 7c, according to some embodiments, the diffusion barrier film (136L) may further include an upper barrier film (136Lb) interposed between the graphene thin film (136La) and the lower capping film (140L), or between the graphene thin film (136La) and the upper conductive film (134L). The upper barrier film (136Lb) may be formed using a physical vapor deposition, chemical vapor deposition, or atomic layer deposition method. For example, referring to FIG. 7b, the upper barrier film (136Lb) may be formed between the graphene thin film (136La) and the lower capping film (140L). For another example, referring to FIG. 7c, the upper barrier film (136Lb) may be formed between the graphene thin film (136La) and the upper conductive film (134L).

[0049] Referring to FIGS. 5 and FIGS. 7d, according to some embodiments, the lower capping film (140L) may include a first lower capping film (140La) adjacent to the diffusion barrier film (136L), and a second lower capping film (140Lb) on the first lower capping film (140La). The first lower capping film (140La) may be formed between the diffusion barrier film (136L) and the second lower capping film (140Lb). The deposition process of the first lower capping film (140La) may be performed at a lower temperature than the deposition process of the second lower capping film (140Lb). For example, the first lower capping film (140La) may include silicon nitride (SiN) deposited at a relatively low temperature (for example, about 300°C), and the second lower capping film (140Lb) may include silicon nitride (SiN) deposited at a relatively high temperature (for example, about 630°C to 740°C).

[0050] Each of the lower capping film (140L) and the upper capping film (142L) may contain a silicon compound. When the first lower capping film (140La) is formed by a low-temperature deposition process, the diffusion of silicon within the lower capping film (140L) into the upper conductive film (134L) may be suppressed.

[0051] Referring to FIGS. 1, 8 and 9, the upper capping film (142L), the lower capping film (140L), the diffusion barrier film (136L), the upper conductive film (134L), the lower barrier film (132L), and the lower conductive film (130L) can be etched sequentially, and accordingly, bit lines (BL) can be formed. The bit lines (BL) can be formed on the insulating film (120) and can cross the word lines (WL). The bit lines (BL) can be extended in the first direction (D1) and can be spaced apart from each other in the second direction (D2). Each of the bit lines (BL) may include an upper capping pattern (142), a lower capping pattern (140), a diffusion barrier pattern (136), an upper conductive pattern (134), a lower barrier pattern (132), and lower conductive patterns (130), which are respectively formed by etching the upper capping film (142L), the lower capping film (140L), the diffusion barrier film (136L), the upper conductive film (134L), the lower barrier film (132L), and the lower conductive film (130L). The upper capping pattern (142) and the lower capping pattern (140) may be referred to as bit line capping patterns (BCP). Each of the lower conductive patterns (130) of the bit lines (BL) may be arranged in the first direction (D1) on the insulating film (120).

[0052] Bitline contacts (DC) may be formed below each of the bitlines (BL) and may be spaced apart from each other in the first direction (D1). The lower conductive patterns (130) and the bitline contacts (DC) may be arranged alternately along the first direction (D1). The bitline contacts (DC) may be formed by etching the bitline contact film (DCL). The inner surface of each of the recess regions (R1) may be exposed on each side of the bitline contacts (DC).

[0053] A first spacer (151) may be formed on each side of the bit lines (BL) and may extend onto the insulating film (120). The first spacer (151) may extend onto each side of the bit line contacts (DC) and may cover each of the exposed inner surfaces of the recessed regions (R1). An insulating liner (152) and a buried insulating pattern (153) may be formed on each side of the bit line contacts (DC) and may be formed to fill each of the remainder of the recessed regions (R1). The insulating liner (152) may be interposed between the first spacer (151) and the buried insulating pattern (153).

[0054] Forming the first spacer (151), the insulating liner (152), and the embedded insulating pattern (153) may, for example, include forming a first spacer film covering each of the bit lines (BL), each of the bit line contacts (DC), and each of the exposed inner surfaces of the recessed regions (R1); forming an insulating liner film extending along the first spacer film on the first spacer film; forming an embedded insulating film filling each remainder of the recessed regions (R1); and anisotropically etching the embedded insulating film, the insulating liner film, and the first spacer film.

[0055] Referring to FIGS. 1, 10 and 11, a second spacer (155) may be formed on each of the bit lines (BL). The first spacer (151) may be interposed between each of the bit lines (BL) and the second spacer (155) and may extend between the upper surface of the insulating film (120) and the second spacer (155). Forming the second spacer (155) may, for example, include forming a second spacer film covering each of the bit lines (BL) and anisotropically etching the second spacer film. A portion of the insulating film (120) exposed by the second spacer (155) may be etched together during the anisotropic etching of the second spacer film.

[0056] A third spacer (157) may be formed on each of the aforementioned sides of the bit lines (BL). The first and second spacers (151, 155) may be interposed between each of the aforementioned sides of the bit lines (BL) and the third spacer (157). The third spacer (157) may cover the side of the insulating film (120) and may come into contact with the upper surface of the substrate (100) and the upper surface of the embedded insulating pattern (153). The third spacer (157) may be formed in substantially the same manner as the second spacer (155).

[0057] The first to third spacers (151, 155, 157) may form a bitline spacer (150). The bitline spacer (150) may extend in the first direction (D1) along each of the sides of the bit lines (BL).

[0058] Referring to FIGS. 1, 12 and 13, a preliminary contact film (PBC) may be formed on the substrate (100) and between the bit lines (BL). The bit line spacer (150) may be interposed between each of the bit lines (BL) and the preliminary contact film (PBC). Forming the preliminary contact film (PBC) may, for example, include forming a contact conductive film that fills the space between the bit lines (BL) on the substrate (100), and flattening the contact conductive film until the upper surface of the upper capping pattern (142) is exposed. The preliminary contact film (PBC) may extend in the first direction (D1) between a pair of adjacent bit lines (BL).

[0059] Referring to FIGS. 1, 14, and 15, the upper portion of the preliminary contact film (PBC) may be recessed. Subsequently, storage node contacts (BC) may be formed by patterning the preliminary contact film (PBC). The storage node contacts (BC) may be spaced apart from each other in the first direction (D1) between a pair of adjacent bit lines (BL). Insulating fences may be formed between the storage node contacts (BC). The insulating fences and the storage node contacts (BC) may be alternately arranged in the first direction (D1) between the pair of bit lines (BL). A conductive film (CL) may be formed on the substrate (100) to cover the upper surfaces of the bit lines (BL), the storage node contacts (BC), and the insulating fences.

[0060] Referring again to FIGS. 1, 2 and 3, landing pads (LP) can be formed by patterning the conductive film (CL). A first upper insulating film (160) can be formed to fill the space between the landing pads (LP).

[0061] An etch stop layer (170) may be formed on the landing pads (LP) and the first upper insulating layer (160). Lower electrodes (BE) may each be formed on the landing pads (LP). Each of the lower electrodes (BE) may penetrate the etch stop layer (170) and be connected to a corresponding landing pad (LP) among the landing pads (LP).

[0062] An upper support pattern (182) may be formed on the upper sidewalls of the lower electrodes (BE) and may support the upper sidewalls of the lower electrodes (BE). A lower support pattern (180) may be formed on the lower sidewalls of the lower electrodes (BE) and may support the lower sidewalls of the lower electrodes (BE). A dielectric film (175) may be formed to cover the surface of the lower electrodes (BE) and the surface of the upper and lower support patterns (182, 180). An upper electrode (TE) may be formed on the active cell region (ACR) and may fill the space between the lower electrodes (BE). The lower electrodes (BE), the dielectric film (175), and the upper electrode (TE) may constitute a capacitor structure (CAP).

[0063] Figure 16 is an XPS graph of a graphene pattern within a diffusion barrier pattern of Figure 1, and Figure 17 is a graph showing the Raman peak of a graphene pattern within a diffusion barrier pattern of Figure 1.

[0064] Referring to FIG. 16, sp2 bonds may account for more than about 50% of the total fitting within the graphene pattern (136a). For example, sp2 bonds within the graphene pattern (136a) may be greater than or equal to 50% and less than 100% of the total fitting within the graphene pattern (136a).

[0065] Referring to FIG. 17, the intensity of the G peak may increase as the thickness of the graphene pattern (136a) increases. The G peak is a peak that commonly appears in graphite-based materials and corresponds to a mode in which carbon atoms in a hexagonal structure vibrate in opposite directions to adjacent atoms. The D peak and the 2D peak are peaks caused by defects within the graphene pattern (136a). According to embodiments of the present invention, the graphene pattern (136a) may satisfy the conditions that i) (D peak intensity) / (G peak intensity) is less than or equal to 2.0 and ii) (2D peak intensity) / (G peak intensity) is greater than or equal to 0.1.

[0066] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art.

Claims

Claim 1 A semiconductor device comprising: a substrate including a plurality of active patterns; a bit line extending in a first direction across the plurality of active patterns on the substrate; and bit line contacts arranged in the first direction below the bit line and electrically connected to each of the plurality of active patterns, wherein the bit line comprises: an upper conductive pattern extending in the first direction on the bit line contacts; a bit line capping pattern extending in the first direction on the upper conductive pattern; and a diffusion barrier pattern extending in the first direction between the upper conductive pattern and the bit line capping pattern, wherein the upper conductive pattern comprises ruthenium (Ru), the diffusion barrier pattern comprises a graphene pattern, and the diffusion barrier pattern further comprises an upper barrier pattern interposed between the upper conductive pattern and the graphene pattern, or between the bit line capping pattern and the graphene pattern. Claim 2 A semiconductor device according to claim 1, wherein the bit line comprises: lower conductive patterns interposed between the bit line contacts below the upper conductive pattern; and a lower barrier pattern extending in the first direction between the lower conductive patterns and the upper conductive pattern, and between the bit line contacts and the upper conductive pattern, wherein the lower conductive patterns and the bit line contacts are alternately arranged along the first direction. Claim 3 In claim 1, the bit line capping pattern is a semiconductor device comprising a silicon compound. Claim 4 delete Claim 5 A semiconductor device according to claim 1, wherein the upper barrier pattern comprises at least one of a conductive metal nitride and a metal silicide. Claim 6 A semiconductor device according to claim 1, wherein the bit line capping pattern comprises a first lower capping pattern adjacent to the diffusion barrier pattern and a second lower capping pattern on the first lower capping pattern, wherein each of the first lower capping pattern and the second lower capping pattern has a thickness along a direction perpendicular to the lower surface of the substrate, and the thickness of the first lower capping pattern is smaller than the thickness of the second lower capping pattern. Claim 7 A semiconductor device according to claim 1, wherein the graphene pattern comprises a plurality of graphene layers stacked in a direction perpendicular to the lower surface of the substrate. Claim 8 A semiconductor device according to claim 1, wherein the bit lines are provided in a plurality, the plurality of bit lines extend in the first direction and are spaced apart from each other in a second direction intersecting the first direction, and the first direction and the second direction are parallel to the lower surface of the substrate. Claim 9 A semiconductor device comprising: a substrate including a plurality of active patterns; a bit line extending in a first direction across the plurality of active patterns on the substrate; and bit line contacts arranged in the first direction below the bit line and electrically connected to each of the plurality of active patterns, wherein the bit line comprises: an upper conductive pattern extending in the first direction on the bit line contacts; a bit line capping pattern extending in the first direction on the upper conductive pattern; and a diffusion barrier pattern extending in the first direction between the upper conductive pattern and the bit line capping pattern, wherein the diffusion barrier pattern comprises a graphene pattern, and the bit line capping pattern comprises a first lower capping pattern adjacent to the diffusion barrier pattern and a second lower capping pattern on the first lower capping pattern, wherein each of the first lower capping pattern and the second lower capping pattern has a thickness along a direction perpendicular to the lower surface of the substrate, and the thickness of the first lower capping pattern is smaller than the thickness of the second lower capping pattern. Claim 10 A semiconductor device according to claim 9, wherein the bit line comprises: lower conductive patterns interposed between the bit line contacts below the upper conductive pattern; and a lower barrier pattern extending in the first direction between the lower conductive patterns and the upper conductive pattern, and between the bit line contacts and the upper conductive pattern.

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