Nonvolatile memory device and operation method thereof

Abstract

A non-volatile memory device according to the present invention includes a plurality of bit lines connected to a plurality of cell strings, a common source line connected to a plurality of cell strings, at least one dummy bit line provided between the common source line and the plurality of bit lines, a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver configured to selectively provide a first voltage to at least one dummy bit line in response to the dummy bit line driving signal.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory, and more specifically, to a non-volatile memory device and a method of operating the same. Background Technology

[0002] Semiconductor memory is classified into volatile memory devices, such as SRAM and DRAM, in which stored data is lost when the power supply is cut off, and non-volatile memory devices, such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when the power supply is cut off.

[0003] A flash memory device reads data stored in memory cells by detecting voltage changes in the bit lines connected to the memory cells during a read operation. At this time, current flows through the common source line connected to the memory cells, and noise caused by the current in the common source line may be introduced into the bit line. In this case, the voltage of the bit line may be affected by the noise caused by the current in the common source line, and the reliability of the flash memory device may be degraded. The problem to be solved

[0004] The objective of the present invention is to provide a non-volatile memory device having improved performance and improved reliability by minimizing the influence of noise caused by a common source line, and a method of operating the same. means of solving the problem

[0005] According to the present invention, a non-volatile memory device comprises: a plurality of bit lines connected to a plurality of cell strings; a common source line connected to the plurality of cell strings; at least one dummy bit line provided between the common source line and the plurality of bit lines; a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device; and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

[0006] According to the present invention, a non-volatile memory device comprises: a peripheral circuit formed on a semiconductor substrate; a memory cell array formed on the peripheral circuit and comprising a plurality of cell strings; and a metal layer formed on the memory cell array, wherein the metal layer comprises: a plurality of bit lines connected to the plurality of cell strings; a common source line connected to the plurality of cell strings; and at least one dummy bit line provided between the plurality of bit lines and the common source line, and wherein the peripheral circuit comprises: a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device; and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal.

[0007] According to the present invention, a method of operating a non-volatile memory device comprises: receiving a read command from an external device; applying a first voltage to at least one dummy bit line located between a plurality of bit lines and a common source line in response to the read command; performing a read operation in response to the read command; receiving an erase command from the external device; floating the at least one dummy bit line, electrically connecting the at least one dummy bit line to the common source line, or applying an erase voltage to the at least one dummy bit line in response to the erase command; and performing an erase operation in response to the erase command. Effects of the invention

[0008] According to the present invention, a non-volatile memory device can prevent noise caused by the current of a common source line from entering the bit lines by controlling the voltage of the common source line and adjacent dummy bit lines, and can shorten the time for the common source line or the bit line to reach the erase voltage during an erase operation. Accordingly, a non-volatile memory device having improved performance and improved reliability and a method of operating the same are provided. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a non-volatile memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of one memory block (BLK) among a plurality of memory blocks included in the memory cell array of FIG. 1. FIG. 3 is a perspective view schematically showing the non-volatile memory device of FIG. 1. Figure 4 shows a cross-sectional view of a non-volatile memory device along line A of Figure 3. Figure 5 shows a cross-sectional view of a non-volatile memory device along line B of Figure 3. Figure 6 is a plan view showing the cell core region in the metal layer of Figure 3. Figure 7 is a plan view showing the third contact area in the metal layer of Figure 5. Figure 8 is a circuit diagram showing the dummy bitline driver of Figure 1. FIG. 9 is a timing diagram for explaining the first dummy bitline driving signal provided by the dummy bitline driver of FIG. 8. FIGS. 10a to 10c are drawings for explaining the levels of the bit line, dummy bit line, and common source line (CSL) according to the timing diagram of FIG. 9. FIGS. 11a and FIGS. 11b are drawings showing a dummy bitline driver of FIG. 1. FIG. 12 is a timing diagram for explaining the first and second dummy bitline driving signals of FIG. 11a or FIG. 11b. FIGS. 13a to 13c are drawings for explaining the levels of the bit line, dummy bit line, and common source line according to the timing diagram of FIG. 12. FIG. 14 is a timing diagram for explaining the first and second dummy bitline driving signals of FIG. 11a or FIG. 11b. FIGS. 15a and FIGS. 15b are drawings for explaining a control method for dummy bit lines. FIG. 16 is a diagram showing an embodiment in which a non-volatile memory device includes a plurality of dummy bitline drivers. FIG. 17 is a flowchart showing the operation of the non-volatile memory device of FIG. 1. FIGS. 18a and FIGS. 18b are timing diagrams for explaining the operation of a non-volatile memory device according to an embodiment of the present invention. FIG. 19 is a drawing illustrating an exemplary memory device (1400) according to the present invention. FIGS. 20 to 22 are drawings for explaining various stacked structures of a non-volatile memory device according to the present invention. FIG. 23 is a block diagram showing a memory system according to one embodiment of the present invention. Specific details for implementing the invention

[0010] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0011] FIG. 1 is a block diagram showing a non-volatile memory device according to an embodiment of the present invention. Referring to FIG. 1, the non-volatile memory device (100) may include a memory cell array (110), an address decoder (120), a page buffer circuit (130), an input / output circuit (140), a control logic and voltage generation circuit (150), and a dummy bitline driver (160). In one embodiment, components other than the memory cell array (110), for example, the address decoder (120), the page buffer circuit (130), the input / output circuit (140), the control logic and voltage generation circuit (150), and the dummy bitline driver (160) may be included in the peripheral circuit (PERI). In one embodiment, the non-volatile memory device (100) may have a COP (Cell on Peripheral) or CUA (CMOS under Array) structure in which a memory cell array (110), a memory cell structure, or a memory cell region is stacked on top of a peripheral circuit (PERI) (or peripheral circuit region).

[0012] A memory cell array (110) may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings, and each of the plurality of cell strings may be connected to a plurality of bit lines (BL). Each of the plurality of cell strings may include a plurality of cell transistors connected in series. The plurality of cell transistors may be connected to string select lines (SSL), word lines (WL), and ground select lines (GSL).

[0013] The address decoder (120) can be connected to the memory cell array (110) via string select lines (SSL), word lines (WL), and ground select lines (GSL). The address decoder (120) can receive an address (ADDR) from an external device (e.g., a memory controller) and can decode the received address (ADDR). The address decoder (120) can control or drive the string select lines (SSL), word lines (WL), and ground select lines (GSL) based on the decoded address (ADDR).

[0014] The page buffer circuit (130) can be connected to the memory cell array (110) via bit lines (BL). The page buffer circuit (130) can detect voltage changes in the bit lines (BL) and read data stored in the memory cells of the memory cell array (110). The page buffer circuit (130) can provide the read data to the input / output circuit (140). The page buffer circuit (130) can be configured to temporarily store data (DATA) received through the input / output circuit (140). The page buffer circuit (130) can control or drive the bit lines (BL) based on the temporarily stored data (DATA).

[0015] The input / output circuit (140) can exchange data (DATA) with an external device (e.g., a memory controller). The input / output circuit (140) can transfer data (DATA) received from the external device to the page buffer circuit (130) or transfer data (DATA) received from the page buffer circuit (130) to the external device.

[0016] The control logic and voltage generation circuit (150) (hereinafter referred to as the control logic circuit) can be configured to generate various voltages required for the operation of the non-volatile memory device (100), such as a plurality of program voltages, a plurality of program verification voltages, a plurality of pass voltages, a plurality of read voltages, a plurality of erase voltages, etc.

[0017] The control logic circuit (150) can control the operation of the non-volatile memory device (100) in response to a command (CMD) and a control signal (CTRL) from an external device. For example, the control logic circuit (150) can control an address decoder (120), a page buffer circuit (130), an input / output circuit (140), and a dummy bitline driver (160) in response to a command (CMD) so that an operation corresponding to the command (CMD) (e.g., a program operation, a read operation, an erase operation, etc.) is performed.

[0018] A dummy bitline driver (160) may be connected to dummy bitlines (DBL) of a memory cell array (110). The dummy bitline driver (160) may be configured to control the voltage of the dummy bitlines (DBL) or provide a bias under the control of a control logic circuit (150). For example, the memory cell array (110) may include dummy bitlines (DBL). The dummy bitlines (DBL) may refer to bitlines that are formed in a similar pattern on the same layer (e.g., a metal layer on top of the memory cell array (110)) as the bitlines (BL) of the memory cell array (110), but are not electrically connected to the cell transistors or to the page buffer circuit (130). Alternatively, dummy bitlines (DBL) may be formed in the same shape or structure as bitlines (BL) but may indicate bitlines that are not used in the operation (e.g., read operation, program operation, or erase operation) of the non-volatile memory device (100).

[0019] The dummy bitline driver (160) can control the voltage of the dummy bitlines (DBL) according to the control of the control logic circuit (150). As the dummy bitlines (DBL) are controlled by the dummy bitline driver (160), noise generated by the common source line (CSL) of the memory cell array (110) is not introduced into the bitlines (BL), so the operational reliability of the non-volatile memory device (100) can be improved. The operation and structure of the dummy bitline driver (160) will be described in more detail with reference to the drawings below.

[0020] FIG. 2 is a circuit diagram showing an example of a single memory block (BLK) among a plurality of memory blocks included in the memory cell array of FIG. 1. A single memory block (BLK) is described with reference to FIG. 2, but the scope of the present invention is not limited thereto. A plurality of memory blocks included in the memory cell array (110) may have a structure identical or similar to the memory block (BLK) of FIG. 2. Referring to FIG. 1 and FIG. 2, the memory block (BLK) may include a plurality of cell strings (CS11, CS12, CS21, CS22). Each of the plurality of cell strings (CS11, CS12, CS21, CS22) may be arranged in the row direction and the column direction.

[0021] Cell strings located in the same column among a plurality of cell strings (CS11, CS12, CS21, CS22) may be connected to the same bit line. For example, cell strings (CS11, CS21) may be connected to a first bit line (BL1), and cell strings (CS12, CS22) may be connected to a second bit line (BL2). Each of the plurality of cell strings (CS11, CS12, CS21, CS22) may include a plurality of cell transistors. Each of the plurality of cell transistors may be a charge trap flash (CTF) memory cell, but the scope of the present invention is not limited thereto. The plurality of cell transistors may be stacked in the height direction, which is perpendicular to the plane formed by the row direction and the column direction (e.g., a semiconductor substrate (not shown) or peripheral circuit (PERI)).

[0022] Multiple cell transistors may be serially connected between a corresponding bit line (e.g., BL1 or BL2) and a common source line (CSL). For example, the multiple cell transistors may include string select transistors (SSTb, SSTa), dummy memory cells (DMC1, DMC2), memory cells (MC1 to MC8), and ground select transistors (GSTa, GSTb). Serially connected string select transistors (SSTb, SSTa) may be provided or connected between serially connected memory cells (MC1 to MC8) and a corresponding bit line (e.g., BL1 or BL2). Serially connected ground select transistors (GSTa, GSTb) may be provided or connected between serially connected memory cells (MC1 to MC8) and a common source line (CSL). In one embodiment, a second dummy memory cell (DMC2) may be provided between serially connected string select transistors (SSTb, SSTa) and serially connected memory cells (MC1~MC8), and a first dummy memory cell (DMC1) may be provided between serially connected memory cells (MC1~MC8) and serially connected ground select transistors (GSTb, GSTa).

[0023] Among the memory cells (MC1~MC8) of each of the multiple cell strings (CS11, CS12, CS21, CS22), memory cells located at the same height may share the same word line. For example, the first memory cells (MC1) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may be located at the same height from the substrate (not shown) and may share the first word line (WL1). The second memory cells (MC2) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may be located at the same height from the substrate (not shown) and may share the second word line (WL2). Likewise, each of the third to eighth memory cells (MC3~MC8) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) may be located at the same height from the substrate (not shown) and may share the third to eighth word lines (WL3~WL8) respectively.

[0024] Among the dummy memory cells (DMC1, DMC2) of each of the multiple cell strings (CS11, CS12, CS21, CS22), dummy memory cells located at the same height may share the same dummy wordline. For example, the first dummy memory cells (DMC1) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may share the first dummy wordline (DWL1), and the second dummy memory cells (DMC2) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may share the second dummy wordline (DWL2). In one embodiment, dummy wordlines may be added for a multi-stacked structure. For example, dummy wordlines may be added between wordlines (e.g., WL4, WL5), and dummy wordlines may be connected to dummy memory cells added between memory cells (e.g., MC4, MC5). However, the scope of the invention is not limited thereto.

[0025] Among the string select transistors (SSTa, SSTb) of each of the multiple cell strings (CS11, CS12, CS21, CS22), string select transistors located in the same row and at the same height can be connected to the same string select line. For example, the string select transistors (SSTb) of the cell strings (CS11, CS12) can be connected to the string select line (SSL1b), and the string select transistors (SSTa) of the cell strings (CS11, CS12) can be connected to the string select line (SSL1a). The string select transistors (SSTb) of the cell strings (CS21, CS22) can be connected to the string select line (SSL2b), and the string select transistors (SSTa) of the cell strings (CS21, CS22) can be connected to the string select line (SSL2a).

[0026] Although not illustrated in the drawing, string select transistors (SSTb, SSTa) of each of the multiple cell strings (CS11, CS12, CS21, CS22) located in the same row may share the same string select line. For example, the string select transistors (SSTb, SSTa) of the cell strings (CS11, CS12) may share a first string select line, and the string select transistors (SSTb, SSTa) of the cell strings (CS21, CS22) may share a second string select line different from the first string select line.

[0027] Among the ground select transistors (GSTb, GSTa) of each of the multiple cell strings (CS11, CS12, CS21, CS22), ground select transistors located in the same row and at the same height can be connected to the same ground select line. For example, the ground select transistors (GSTb) of the cell strings (CS11, CS12) can be connected to the ground select line (GSL1b), and the ground select transistors (GSLa) of the cell strings (CS11, CS12) can be connected to the ground select line (GST1a). The ground select transistors (GSTb) of the cell strings (CS21, CS22) can be connected to the ground select line (GSL2b), and the ground select transistors (GSLa) of the cell strings (CS21, CS22) can be connected to the ground select line (GST2a).

[0028] Although not shown in the drawing, the ground select transistors (GST1b, GST1a) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may share the same ground select line. Alternatively, the ground select transistors of the same height among the ground select transistors (GSTb, GSTa) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may share the same ground select line. Alternatively, the ground select transistors located in the same row among the ground select transistors (GSTb, GSTa) of each of the multiple cell strings (CS11, CS12, CS21, CS22) may share the same ground select line.

[0029] In one embodiment, although not illustrated in the drawings, each of the plurality of cell strings (CS11, CS12, CS21, CS22) of the memory block (BLK) may further include an erase control transistor (ECT). The erase control transistor (ECT) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) may be located at the same height from the substrate and may be connected to the same erase control line (ECL). For example, the erase control transistor (ECT) may be located between the common source line (CSL) and the ground select transistor (GSTa) in each of the plurality of cell strings (CS11, CS12, CS21, CS22). Alternatively, the erase control transistor (ECT) may be located between the bit lines (BL1, BL2) and the string select transistors (SSTb). However, the scope of the present invention is not limited thereto.

[0030] In one embodiment, the memory block (BLK) illustrated in FIG. 2 is exemplary, and the number of cell strings may be increased or decreased, and the number of rows and columns constituting the cell strings may be increased or decreased depending on the number of cell strings. Additionally, the number of cell transistors (GST, MC, DMC, SST, etc.) of the memory block (BLK) may be increased or decreased, and the height of the memory block (BLK) may be increased or decreased depending on the number of cell transistors. Additionally, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased depending on the number of cell transistors.

[0031] FIG. 3 is a perspective view schematically showing the non-volatile memory device of FIG. 1. For convenience of explanation, the schematic structure of the non-volatile memory device (100) is described below based on one memory block (BLK), but the scope of the present invention is not limited thereto. Also, for the sake of brevity of the drawings and convenience of explanation, only configurations related to the technical concept of the present invention are described, but the scope of the present invention is not limited thereto.

[0032] Referring to FIGS. 1 to 3, the peripheral circuit (PERI) of the non-volatile memory device (100) may be formed on a plane (e.g., a semiconductor substrate) defined by row and column directions. A memory block (BLK) of a three-dimensional structure may be formed on top of the peripheral circuit (PERI) or in a direction perpendicular to the peripheral circuit (PERI), i.e., in the height direction. That is, the non-volatile memory device (100) may have a COP structure.

[0033] Various signal lines of the memory block (BLK) (e.g., bit line (BL), word line (WL), string select line (SSL), ground select line (GSL), common source line (CSL), etc.) can be connected to the peripheral circuit (PERI) through conductive lines included in the metal layer (ML). In one embodiment, the bit lines (BL) of the memory block (BLK) can be connected to the peripheral circuit (PERI) in the contact area (CT). For example, the bit lines (BL) of the memory block (BLK) can be electrically connected to the conductive lines of the metal layer (ML). A dummy memory block (dBLK) having a structure similar to that of the memory block (BLK) can be formed in the contact area (CT), and the conductive lines of the metal layer (ML) and the peripheral circuit (PERI) (in particular, the page buffer circuit (130)) can be electrically connected through a through plug that penetrates the dummy memory block (dBLK) in the height direction. In one embodiment, the page buffer circuit (130) may be formed in the contact area (CT) of the peripheral circuit (PERI).

[0034] FIG. 4 shows a cross-sectional view of a non-volatile memory device along line A of FIG. 3. FIG. 5 shows a cross-sectional view of a non-volatile memory device along line B of FIG. 3. For the sake of brevity of the drawings and convenience of explanation, components unnecessary for describing embodiments of the present invention and detailed descriptions thereof are omitted. For example, some string selection lines, some word lines, dummy word lines, some ground selection lines, etc. of a memory block (BLK) are omitted in the following drawings, but the scope of the present invention is not limited thereto.

[0035] Referring to FIGS. 1, FIGS. 3, FIGS. 4, and FIGS. 5, a peripheral circuit (PERI) may be formed on a semiconductor substrate (SUB). A cell region (CELL) may be formed on top of the peripheral circuit (PERI) or along the height direction from the peripheral circuit (PERI). The cell region (CELL) may refer to an area where a memory block (BLK) is formed. In the cell region (CELL), a common source line (CSL), a ground select line (GSL), word lines (WL1–WL6), and a string select line (SSL) may be vertically stacked in the height direction from the peripheral circuit (PERI).

[0036] In the first contact area (CNR1), the common source line (CSL), ground select line (GSL), word lines (WL1–WL6), and string select line (SSL) may be formed in a stepped shape. For example, in the first contact area (CNR1), the length along the row direction of each of the common source line (CSL), ground select line (GSL), word lines (WL1–WL6), and string select line (SSL) may become shorter as they move further away from the peripheral circuit (PERI).

[0037] In the first contact area (CNR1), the ground select line (GSL), word lines (WL1–WL6), and string select line (SSL) can be connected to the first contact plugs (CT1) through the first through plugs (TP1). The first contact plugs (CT1) can be connected to the first conductive lines (CL1) of the metal layer (ML). The first through plugs (TP1) can be formed along the height direction (i.e., the direction perpendicular to the peripheral circuit (PERI)) in the cell area (CELL). In one embodiment, the first through plug (TP1) or the through plugs described below may refer to a vertical through structure such as a Through Silicon Via (TSV) or a Through Hole Via (THV). In one embodiment, the metal layer (ML) may include a plurality of layers to provide various wiring or patterns of the conductive lines (CL1).

[0038] The first conductive lines (CL1) of the metal layer (ML) can be connected to the second contact plug (CT2) in the second contact region (CNR2). The second contact plug (CT2) can be electrically connected to the peripheral circuit (PERI) through the second through plug (TP2). In one embodiment, as shown in FIG. 4, the first word line (WL1) can be electrically connected to the peripheral circuit (PERI), in particular, the address decoder (120), through the first through plug (TP1), the first contact plug (CT1), the first conductive line (CL1), the second contact plug (CT2), and the second through plug (TP2). The connection structure of the word lines (WL1–WL6) of the memory block (BLK) described above is merely an example, and the scope of the invention is not limited thereto.

[0039] Channels (CH) can be provided in the cell core region (CAR). Channels (CH) can be provided to pass through the vertically stacked common source line (CSL), ground select line (GSL), word lines (WL1–WL6), and string select line (SSL). Channels (CH) can be connected to bit lines (BL) through a third contact (CT3).

[0040] In one embodiment, the metal layer (ML) may include a conductive line corresponding to a common source line (CSL). The conductive line corresponding to the common source line (CSL) may be connected to the common source line (CSL) of the cell region (CELL) through a fourth contact plug (CT4) and a fourth through plug (TP4). In one embodiment, the common source line (CSL) in the metal layer (ML) may be commonly connected to the entire or part of the memory cell array through a mesh structure or a ring structure. In one embodiment, in the cell region (CELL), the common source line (CSL) may be commonly connected to the entire or part of the memory cell array through a mesh structure or a ring structure.

[0041] Next, as illustrated in FIG. 5, a bit line (BL) electrically connected to a channel (CH) and a third contact plug (CT3) can be extended in a thermal direction. The bit line (BL) extended in a thermal direction in a metal layer (ML) can be electrically connected to a page buffer circuit (130) of a peripheral circuit (PERI) through a fifth contact plug (CT5) and a fifth through plug (TP5) in a third contact area (CNR3). In one embodiment, the third contact area (CNR3) may be an area corresponding to the contact area (CT) or dummy block (dBLK) described with reference to FIG. 3. That is, the third contact area (CNR3) may refer to an area (e.g., a bit line contact area) where through plugs are formed to electrically connect the bit lines (BL) and the page buffer circuit (130). In the third contact area (CNR3), the area corresponding to the ground select line (GSL), word lines (WL1–WL6), and string select line (SSL) can be provided as a mold pattern (MP).

[0042] In one embodiment, the dummy bitline (DBL) may be extended along the row direction in the cell core region (CAR) and may be electrically connected to the dummy bitline driver (160) of the peripheral circuit (PERI) through the sixth contact plug (CT6) and the sixth through plug (TP6) in the third contact region (CNR3). In one embodiment, the dummy bitline (DBL) may refer to a bitline that is formed in the same pattern as the bitline (BL) in the metal layer but is not electrically connected to the channel (CH). Alternatively, the dummy bitline (DBL) may be electrically connected to the bitline (BL) and the channel, but the channel connected to the dummy bitline (DBL) may have a different structure from the channel (CH) connected to the bitline (BL).

[0043] In one embodiment, the page buffer circuit (130) may be provided in the third contact area (CNR3) of the peripheral circuit (PERI), and the dummy bitline driver (160) may be provided at a location different from the third contact area (CNR3) of the peripheral circuit (PERI). That is, the dummy bitline (DBL) is connected to the peripheral circuit (PERI) through a sixth through plug (TP6) formed in the area (i.e., the third contact area (CNR3)) where fifth through plugs are provided to electrically connect the bitline (BL) and the page buffer circuit (130) of the peripheral circuit (PERI), but the dummy bitline driver (160) electrically connected to the dummy bitline (DBL) may be provided at a location different from the third contact area (CNR3) or at a location different from the page buffer circuit (130).

[0044] FIG. 6 is a plan view showing the cell core region in the metal layer of FIG. 3. Referring to FIG. 3 and FIG. 6, in the cell core region of the metal layer (ML) of the non-volatile memory device (100), the common source line (CSL), dummy bit lines (DBLa, DBLb), and bit lines (BLa, BLb) can be extended along the column direction. The common source line (CSL), dummy bit lines (DBLa, DBLb), and bit lines (BLa, BLb) can be arranged along the row direction.

[0045] Bitlines (BLa, BLb) may be electrically connected to channels or memory cells of multiple memory blocks. Dummy bitlines (DBLa, DBLb) may be located in the metal layer (ML) between the common source line (CSL) and the bitlines (BLa, BLb). For example, dummy bitlines (DBLa) may be placed between the common source line (CSL) and the bitlines (BLa), and dummy bitlines (DBLb) may be placed between the common source line (CSL) and the bitlines (BLb).

[0046] In one embodiment, when the level of the common source line (CSL) changes, noise from the common source line (CSL) may be introduced into the bit lines (BLa, BLb). For example, when the non-volatile memory device (100) performs a read operation or a program verification operation, a large current may flow through the common source line (CSL). Due to the large current flowing through the common source line (CSL), noise may be generated in the bit lines (BLa, BLb), and this noise degrades the reliability of the read data.

[0047] In one embodiment, the dummy bitline driver (160) according to the present invention may be configured to control the levels of dummy bitlines (DBLa, DBLb) according to the operation of the non-volatile memory device (100). In this case, noise generated from the common source line (CSL) may be blocked or prevented from entering the bitlines (BLa, BLb).

[0048] FIG. 7 is a plan view showing a third contact area in the metal layer of FIG. 5. Referring to FIG. 5 and FIG. 7, a plurality of bit lines (BL) and dummy bit lines (DBL) may be provided in the third contact area (CNR3) of the metal layer (ML). In one embodiment, the plurality of bit lines (BL) and dummy bit lines (DBL) provided in the third contact area (CNR3) of the metal layer (ML) may be electrically connected through various conductive lines of the metal layer (ML) with the bit lines (BLa, BLb) and dummy bit lines (DBLa, DBLb) described with reference to FIG. 6.

[0049] In the third contact area (CNR3) of the metal layer (ML), bit lines (BL) can be electrically connected to the page buffer circuit (130) of the peripheral circuit (PERI) through through plugs (TP) formed in the through plug area (TPA). At this time, the through plug areas (TPA) connected to the bit lines (BL) can be arranged based on a constant interval or pitch. For example, the distance between the first through plug area (TPA1) and the second through plug area (TPA2) adjacent to the first through plug area (TPA1) along the row direction can be a first length (L1), and the distance between the first through plug area (TPA1) and the third through plug area (TPA3) adjacent to the first through plug area (TPA1) along the column direction can be a second length (L2). That is, the through plug areas (TPA) configured to connect the bit lines (BL) can be formed in a regular or uniform pattern in the third contact area (CNR3).

[0050] A dummy bitline (DBL) can be electrically connected to a dummy bitline driver (160) of a peripheral circuit (PERI) through a dummy through-plug area (DTPA). The dummy through-plug area (DTPA) can be formed in an irregular pattern or at an irregular location compared to the through-plug areas (TPA) in the third contact area (CNR3). For example, the distance between the dummy through-plug area (DTPA) and the adjacent second through-plug area (TPA2) along the row direction may be a third distance (L3). In this case, the third distance (L3) may be shorter than the first distance (L1). That is, a dummy through-plug area (DTPA) electrically connected to the dummy bitline (DBL) can be formed between through-plug areas (TPA) formed to have a regular pattern. The dummy through-plug area (DTPA) may be irregular compared to the arrangement of the through-plug areas (TPA).

[0051] Although only one dummy through-plug region (DTPA) is shown in FIG. 7, the scope of the invention is not limited thereto, and the number of dummy through-plug regions (DTPA) can be varied. In an exemplary embodiment, the dummy through-plug regions (DTPA) may be commonly connected to a dummy bitline driver (160) through a ring structure or a mesh structure in a metal layer (not shown) of a peripheral circuit (PERI).

[0052] FIG. 8 is a circuit diagram showing the dummy bitline driver of FIG. 1. For convenience of explanation, it is assumed that the dummy bitline driven or controlled by the dummy bitline driver (160) is a dummy bitline adjacent to the common source line in the cell core region (CAR). That is, in FIG. 6, it is assumed that one dummy bitline closest to the common source line (CSL) among the dummy bitlines (DBLa) and one dummy bitline closest to the common source line (CSL) among the dummy bitlines (DBLb) are driven or controlled by the dummy bitline driver (160). However, the scope of the present invention is not limited thereto. For example, the dummy bitline driven or controlled by the dummy bitline driver (160) may be at least one dummy bitline closest to the common source line (CSL) among the dummy bitlines (DBLa), or one dummy bitline closest to the bitlines (BLa), or at least one dummy bitline among the dummy bitlines (DBLa). That is, the dummy bitline driven or controlled by the dummy bitline driver (160) can be varied.

[0053] Referring to FIGS. 1 and FIGS. 8, a dummy bitline driver (160) may include a first switch (SW1) connected between a dummy bitline (DBL) and a zero voltage (V0). The first switch (SW1) may operate in response to a first dummy bitline driving signal (DBL_DRV1). In response to the first dummy bitline driving signal (DBL_DRV1), the first switch (SW1) may provide or block the zero voltage (V0) to the dummy bitline (DBL). In one embodiment, the first switch (SW1) may be implemented as an NMOS transistor, but the scope of the invention is not limited thereto.

[0054] In one embodiment, the zero voltage (V0) may be a ground voltage (GND or VSS), but the scope of the invention is not limited thereto, and the zero voltage (V0) may be a predetermined positive voltage or a predetermined negative voltage.

[0055] When a zero voltage (V0) is provided to a dummy bit line (DBL), the dummy bit line (DBL) can maintain the zero voltage (V0). In this case, noise generated by a high current in the common source line (CSL) can be blocked from flowing into other bit lines (BL).

[0056] FIG. 9 is a timing diagram for illustrating a first dummy bitline driving signal provided by the dummy bitline driver of FIG. 8. Referring to FIG. 1, FIG. 8, and FIG. 9, the control logic circuit (150) can control the first dummy bitline driving signal (DBL_DRV1) according to the operation of the non-volatile memory device (100). For example, the non-volatile memory device (100) can perform a read operation (RD), a program operation (PGM), and an erase operation (ERS).

[0057] The control logic circuit (150) can generate a first dummy bitline driving signal (DBL_DRV1) such that the first switch (SW1) of the dummy bitline driver (160) is turned on while the non-volatile memory device (100) performs a read operation (RD) or a program operation (PGM), and the first switch (SW1) of the dummy bitline driver (160) is turned off while the non-volatile memory device (100) performs an erase operation (ERS).

[0058] For example, while the non-volatile memory device (100) performs a read operation (RD), current flows through the common source line (CSL), and noise may be introduced into adjacent bit lines (BL) due to the current in the common source line (CSL). In this case, by the operation of the dummy bit line driver (160), a zero voltage (V0) may be applied to the dummy bit lines (DBL) located between the common source line (CSL) and the bit lines (BL), thereby blocking the introduction of noise caused by the current in the common source line (CSL) into the bit lines (BL). In one embodiment, the program verification step of the program operation (PGM) of the non-volatile memory device (100) may be performed by a mechanism similar to the read operation, and noise caused by the current in the common source line (CSL) may be blocked by an operation similar to that described above.

[0059] In one embodiment, the non-volatile memory device (100) can perform an erase operation (ERS) through an erase operation using a Gate Induced Drain Leakage (GIDL) method. That is, an erase voltage can be applied through the common source line (CSL) of the non-volatile memory device (100). At this time, if the voltage of the dummy bit lines (DBL) adjacent to the common source line (CSL) is maintained or biased at a zero voltage (V0), the time for the common source line (CSL) to rise to the erase voltage may be delayed.

[0060] The dummy bitline driver (160) can turn off the first switch (SW1) in response to the first dummy bitline driving signal (DBL_DRV1) from the control logic circuit (150). In this case, during the erase operation (ERS) of the non-volatile memory device (100), the dummy bitline (DBL) can be in a floating state, and accordingly, the time for the common source line (CSL) to rise to the erase voltage can be shortened.

[0061] FIGS. 10a to 10c are drawings illustrating the levels of bitlines, dummy bitlines, and common source lines (CSL) according to the timing diagram of FIG. 9. For convenience of explanation, in FIGS. 10a to 10c, only some of the various lines included in the cell core region (CAR) of the metal layer (ML) are shown, and it is assumed that the dummy bitlines controlled by the dummy bitline driver (160) are the first and second dummy bitlines (DBL1, DBL2) adjacent to the common source line (CSL). However, the scope of the present invention is not limited thereto, and the number and location of the dummy bitlines or the number and location of the dummy bitlines controlled by the dummy bitline driver (160) may be varied in many ways.

[0062] First, referring to FIG. 9 and FIG. 10a, when a non-volatile memory device (100) performs a read operation (RD) or a program operation (PGM) (in particular, a program verification operation), the first to fourth bit lines (BL1, BL2, BL3, BL4) may have first to fourth bit line voltages (VBL1, VBL2, VBL3, VBL4) depending on the state of the corresponding memory cells.

[0063] When a non-volatile memory device (100) performs a read operation (RD) or a program operation (PGM) (particularly, a program verification operation), a ground voltage (GND) may be applied to the common source line (CSL), and a current may flow depending on the state of the memory cells that are the target of the read operation (RD) or program operation (PGM) (particularly, a program verification operation). Noise caused by the current flowing through the common source line (CSL) may affect adjacent bit lines (e.g., BL2, BL3). At this time, the dummy bit line driver (160) according to the present invention may apply a zero voltage (V0) to the first and second dummy bit lines (DBL1, DBL2). That is, the first and second dummy bit lines (DBL1, DBL2) may maintain the zero voltage (V0) by the dummy bit line driver (160). In one embodiment, the zero voltage (V0) may be provided from a power source or voltage terminal physically separated from the common source line (CSL). The zero voltage (V0) may be a ground voltage (GND or VSS). Alternatively, the zero voltage (V0) may be a predetermined positive voltage or a predetermined negative voltage.

[0064] As the first and second dummy bit lines (DBL1, DBL2) are biased to a zero voltage (V0), noise generated by the current of the common source line (CSL) can be blocked from flowing into adjacent bit lines (e.g., BL2, BL3). That is, since the adjacent bit lines (e.g., BL2, BL3) are not affected by noise caused by the current of the common source line (CSL), the state of the memory cells connected to the adjacent bit lines (e.g., BL2, BL3) or the data stored in the memory cells can be accurately detected.

[0065] Next, referring to FIG. 9 and FIG. 10b, while the non-volatile memory device (100) performs an erase operation (ERS), an erase voltage (VERS) may be applied to the common source line (CSL). The erase voltage (VERS) may be a positive high voltage. If, while the erase voltage (VERS) is applied to the common source line (CSL), the first and second dummy bit lines (DBL1, DBL2) maintain a zero voltage (V0) or other bias voltage, the time required for the common source line (CSL) to rise to the erase voltage (VERS) will increase.

[0066] A dummy bitline driver (160) according to an embodiment of the present invention can float first and second dummy bitlines (DBL1, DBL2) adjacent to a common source line (CSL) while the non-volatile memory device (100) performs an erase operation (ERS). In this case, as the common source line (CSL) and the adjacent first and second dummy bitlines (DBL1, DBL2) are coupled while the level of the common source line (CSL) rises to the erase voltage (VERS), the time for the common source line (CSL) to reach the erase voltage (VERS) can be shortened.

[0067] Next, referring to FIG. 9 and FIG. 10c, the dummy bitline driver (160) can float the first and second dummy bitlines (DBL1, DBL2) adjacent to the common source line (CSL) and bitlines (BL2, BL3) while the non-volatile memory device (100) performs an erase operation (ERS). For example, the non-volatile memory device (100) can apply an erase voltage (VERS) to the common source line (CSL) and bitlines (BL1~BL4) during the erase operation (ERS). That is, unlike the embodiment of FIG. 10b, the non-volatile memory device (100) can further apply an erase voltage (VERS) to the bitlines (BL1~BL4). In this case, the dummy bitline driver (160) can shorten the time it takes for the common source line (CSL) and bitlines (BL2, BL3) to reach the erase voltage (VERS) by floating the first and second dummy bitlines (DBL1, DBL2) adjacent to the common source line (CSL) and bitlines (BL2, BL3).

[0068] Although the embodiment of FIG. 10c is illustrated as having one dummy bitline (DBL1) between the common source line (CSL) and the bitline (BL2), the scope of the invention is not limited thereto. For example, as described with reference to FIG. 6, there may be a plurality of dummy bitlines (DBLa) between the common source line (CSL) and the bitlines (BLa). In this case, the dummy bitline driver (160) may be configured to float at least one dummy bitline adjacent to the common source line (CSL) and at least one dummy bitline adjacent to the bitlines (BLa) among the plurality of dummy bitlines (DBLa).

[0069] As described above, according to embodiments of the present invention, a dummy bitline driver (160) may be configured to apply a zero voltage (V0) to at least one dummy bitline adjacent to a common source line (CSL), and may be configured to float at least one dummy bitline adjacent to the common source line (CSL) while the non-volatile memory device (100) performs an erase operation (ERS). Accordingly, the reliability of the sensing operation is improved because noise caused by the current of the common source line (CSL) is not introduced into the bitlines during the sensing operation (e.g., a read operation or a program verification operation) of the non-volatile memory device (100). Additionally, during the erase operation (ERS) of the non-volatile memory device (100), the time for the common source line (CSL) or bitlines (BL) to rise to the erase voltage (VERS) may be shortened. Thus, a non-volatile memory device having improved reliability and improved performance is provided.

[0070] FIGS. 11a and FIGS. 11b are drawings showing a dummy bitline driver of FIG. 1. The dummy bitline driver (160) of FIG. 1 can be replaced with the dummy bitline drivers (160a, 160b) of FIGS. 11a and FIG. 11b.

[0071] First, referring to FIG. 1 and FIG. 11a, the dummy bitline driver (160a) may include first and second switches (SW1, SW2). The first switch (SW1) is connected between the dummy bitline (DBL) and the zero voltage (V0) and may operate in response to the first dummy bitline driving signal (DBL_DRV1). Since the first switch (SW1) and the first dummy bitline driving signal (DBL_DRV1) are similar to those previously described, a detailed description thereof is omitted.

[0072] The second switch (SW2) is connected between the common source line (CSL) and the dummy bit line (DBL) and can operate in response to the second dummy bit line driving signal (DBL_DRV2). For example, during an erase operation (ERS) of the non-volatile memory device (100), the common source line (CSL) may receive an erase voltage (VERS) from the erase voltage generator (10). In one embodiment, the erase voltage generator (10) may be included in the control logic and voltage generation circuit (150) of FIG. 1 or may be replaced by the control logic and voltage generation circuit (150) of FIG. 1.

[0073] During the erase operation (ERS) of the non-volatile memory device (100), the second switch (SW2) of the dummy bitline driver (160a) can electrically connect the common source line (CSL) and the dummy bitline (DBL) in response to the second dummy bitline driving signal (DBL_DRV2). That is, during the erase operation (ERS) of the non-volatile memory device (100), the erase voltage (VERS) can be applied together to the dummy bitline (DBL) and the common source line (CSL) by the second switch (SW2) of the dummy bitline driver (160a). In this case, since the dummy bitline (DBL) rises to the erase voltage (VERS) together with the common source line (CSL), the time it takes for the common source line (CSL) to reach the erase voltage (VERS) can be shortened.

[0074] Next, referring to FIG. 1 and FIG. 11b, the dummy bitline driver (160b) may include first and second switches (SW1, SW2). The first switch (SW1) is connected between the dummy bitline (DBL) and the zero voltage (V0) and may operate in response to the first dummy bitline driving signal (DBL_DRV1). Since the first switch (SW1) and the first dummy bitline driving signal (DBL_DRV1) are similar to those previously described, a detailed description thereof is omitted.

[0075] The second switch (SW2) of FIG. 11b is connected between the dummy bit line (DBL) and the erase voltage generator (11) and can operate in response to the second dummy bit line driving signal (DBL_DRV2). For example, the erase voltage generator (11) may be configured to provide an erase voltage (VERS) to the common source line (CSL), bit lines (BL), or common source line and bit lines (CSL / BL) during the erase operation (ERS) of the non-volatile memory device (100). That is, during the erase operation of the non-volatile memory device (100), the time for the common source line (CSL), bit lines (BL), or common source line and bit lines (CSL / BL) to reach the erase voltage (VERS) may be shortened.

[0076] FIG. 12 is a timing diagram for explaining the first and second dummy bitline driving signals of FIG. 11a or FIG. 11b. For convenience of explanation, a detailed description of the previously described components is omitted. Referring to FIG. 1, FIG. 11a, FIG. 11b, and FIG. 12, the control logic circuit (150) can generate first and second dummy bitline driving signals (DBL_DRV1, DBL_DVR2) according to the operation of the non-volatile memory device (100).

[0077] For example, the control logic circuit (150) can generate a first dummy bitline driving signal (DBL_DRV1) such that the first switch (SW1) of the dummy bitline driver (160a or 160b) is turned on during the read operation (RD) and program operation (PGM) of the non-volatile memory device (100), and the first switch (SW1) of the dummy bitline driver (160a or 160b) is turned off during the erase operation (ERS) of the non-volatile memory device (100). The control logic circuit (150) can generate a second dummy bitline driving signal (DBL_DRV2) such that when the non-volatile memory device (100) performs a read operation (RD) and a program operation (PGM), the second switch (SW2) of the dummy bitline driver (160a or 160b) is turned off, and when the non-volatile memory device (100) performs an erase operation (ERS), the second switch (SW2) of the dummy bitline driver (160a or 160b) is turned on.

[0078] The operation of the dummy bitline driver (160a or 160b) according to the first and second dummy bitline driving signals (DBL_DRV1, DBL_DRV2) of the timing diagram of FIG. 12 has been described previously, so a detailed description thereof is omitted.

[0079] FIGS. 13a to 13c are drawings for explaining the levels of bitlines, dummy bitlines, and common source lines according to the timing diagram of FIG. 12. For convenience of explanation, detailed descriptions of the previously described components are omitted. In one embodiment, the levels of bitlines, dummy bitlines, and common source lines in a read operation or program operation of a non-volatile memory device (100) are similar to those described with reference to FIG. 10a, so detailed descriptions thereof are omitted.

[0080] Referring to FIG. 1 and FIG. 13a, during the erase operation (ERS) of a non-volatile memory device (100), an erase voltage (VERS) may be applied together to the common source line (CSL) and dummy bit lines (DBL1, DBL2). In this case, since the common source line (CSL) and adjacent dummy bit lines (DBL1, DBL2) rise together to the erase voltage (VERS), the time it takes for the common source line (CSL) to reach the erase voltage (VERS) may be shortened. In one embodiment, the method of applying an erase voltage (VERS) to dummy bit lines (DBL1, DBL2) of a non-volatile memory device (100) can be achieved by electrically connecting the dummy bit line (DBL) to the common source line (CSL) through the second switch (SW2) as shown in FIG. 11a, or by providing an erase voltage (VERS) from the erase voltage generator (11) to the dummy bit line (DBL) through the second switch (SW2) as shown in FIG. 11b.

[0081] Referring to FIG. 1 and FIG. 13b, during the erase operation (ERS) of the non-volatile memory device (100), an erase voltage (VERS) may be applied together to bit lines (BL1 to BL4) and dummy bit lines (DBL1, DBL2). In this case, since the dummy bit lines (DBL1, DBL2) adjacent to the bit lines (BL2, BL3) rise together to the erase voltage (VERS), the time for the bit lines (BL2, BL3) to rise to the erase voltage (VERS) may be shortened. In one embodiment, the method of applying the erase voltage (VERS) to the dummy bit lines (DBL1, DBL2) of the non-volatile memory device (100) can be achieved by providing the erase voltage (VERS) from the erase voltage generator (11) to the dummy bit line (DBL) through the second switch (SW2), as shown in FIG. 11b.

[0082] Referring to FIG. 1 and FIG. 13c, during the erase operation (ERS) of a non-volatile memory device (100), an erase voltage (VERS) may be applied together to the common source line (CSL), bit lines (BL1 to BL4), and dummy bit lines (DBL1, DBL2). In this case, since the common source line (CSL) and bit lines (BL3, BL4) and adjacent dummy bit lines (DBL1, DBL2) rise together to the erase voltage (VERS), the time it takes for the common source line (CSL) and bit lines (BL3, BL4) to reach the erase voltage (VERS) may be shortened. In one embodiment, the method of applying an erase voltage (VERS) to dummy bit lines (DBL1, DBL2) of a non-volatile memory device (100) can be achieved by electrically connecting the dummy bit line (DBL) to the common source line (CSL) through the second switch (SW2) as shown in FIG. 11a, or by providing an erase voltage (VERS) from the erase voltage generator (11) to the dummy bit line (DBL) through the second switch (SW2) as shown in FIG. 11b.

[0083] FIG. 14 is a timing diagram for explaining the first and second dummy bitline driving signals of FIG. 11a or FIG. 11b. For convenience of explanation, detailed descriptions of the previously described components are omitted. Referring to FIG. 1, FIG. 11a, FIG. 11b, and FIG. 13, the control logic circuit (150) can generate first and second dummy bitline driving signals (DBL_DRV1, DBL_DVR2) according to the operation of the non-volatile memory device (100).

[0084] For example, the control logic circuit (150) can generate a first dummy bitline drive signal (DBL_DRV1) as described with reference to FIG. 12 during a read operation (RD) and a program operation (PGM) of the non-volatile memory device (100). The control logic circuit (150) can generate a second dummy bitline drive signal (DBL_DRV2) so that the second switch (SW2) of the dummy bitline driver (160a or 160b) is turned off (OFF). According to the timing diagram of FIG. 14, the dummy bitline driver (160a or 160b) can operate as described with reference to FIG. 8 through FIG. 10b, and a detailed description thereof is omitted.

[0085] In one embodiment, a dummy bitline driver is implemented as shown in FIG. 11a, but when the non-volatile memory device (100) performs an erase operation by applying an erase voltage (VERS) to the bitlines (BL), the control logic circuit (150) can float the dummy bitlines (DBL) during the erase operation by generating first and second dummy bitline driving signals (DBL_DRV1, DBL_DRV2) as shown in the timing diagram of FIG. 14. Accordingly, the time for the bitlines (BL) to rise to the erase voltage (VERS) can be shortened.

[0086] FIGS. 15a and FIGS. 15b are drawings illustrating a method for controlling dummy bitlines. Although a configuration for controlling a single dummy bitline (DBL) between a common source line (CSL) and bitlines (BL) has been described through the embodiments described above, the scope of the present invention is not limited thereto.

[0087] For example, as illustrated in FIG. 15a, there may be a plurality of dummy bitlines (DBL1a, DBL2a, DBL3a, DBL1b, DBL2b, DBL3b) between the bitline (BL) and the common source line (CSL). In this case, the dummy bitline driver (160c) can control the dummy bitlines (DBL1a, DBL1b) adjacent to the common source line (CSL) among the plurality of dummy bitlines (DBL1a, DBL2a, DBL3a, DBL1b, DBL2b, DBL3b) based on the driving method described above. Some of the dummy bit lines (DBL2a, DBL2b) among the plurality of dummy bit lines (DBL1a, DBL2a, DBL3a, DBL1b, DBL2b, DBL3b) may be biased to a zero voltage (V0) or a predetermined voltage, and some of the other dummy bit lines (DBL3a, DBL3b) may be floating. At this time, some of the dummy bit lines (DBL2a, DBL2b) and some of the other dummy bit lines (DBL3a, DBL3b) may maintain a biased state or a floating state regardless of the operation of the non-volatile memory device (100).

[0088] In one embodiment, the positions of the dummy bit lines biased to a zero voltage (V0) or a floating state can be varied. For example, as shown in FIG. 15b, some dummy bit lines (DBL2a, DBL2b) may be floating, and some other dummy bit lines (DBL3a, DBL3b) may have the zero voltage (V0) or a predetermined voltage applied to them.

[0089] The embodiments of FIGS. 15a and FIGS. 15b are simple examples and the scope of the invention is not limited thereto. For example, the positions of dummy bitlines controlled by the dummy bitline driver (160) according to the operation of the non-volatile memory device (100), or the positions of dummy bitlines biased to a predetermined state, may be varied in various ways.

[0090] FIG. 16 is a diagram showing an embodiment in which a non-volatile memory device includes a plurality of dummy bitline drivers. For the sake of brevity of the drawing and convenience of explanation, unnecessary components are omitted. For brevity of the drawing, in FIG. 16, dummy bitlines are indicated by dotted lines.

[0091] Referring to FIGS. 1 and FIGS. 16, each of the first to third bitline groups (BL_G1 to BL_G3) may include a plurality of bitlines and may be connected to each of the first to third page buffer circuits (130-1 to 130-3). The number of plurality of bitlines included in each of the first to third bitline groups (BL_G1 to BL_G3) may be the same, but the scope of the present invention is not limited thereto.

[0092] The first to third bitline groups (BL_G1~BL_G3) may be separated by a common source line (CSL). For example, the first bitline group (BL_G1) may be located between the first and second common source lines (CSL1, CSL2), the second bitline group (BL_G2) may be located between the second and third common source lines (CSL2, CSL3), and the third bitline group (BL_G3) may be located between the third and fourth common source lines (CSL3, CSL4). In the embodiment of FIG. 16, the first to fourth common source lines (CSL1~CSL4) are shown as being separated from each other, but the scope of the present invention is not limited thereto. For example, the first to fourth common source lines (CSL1~CSL4) may be connected to a single common source line (CSL) through a mesh structure or a ring structure.

[0093] Each of the plurality of dummy bitline drivers (160-1 to 160-4) may be connected to or control dummy bitlines adjacent to the common source lines (CSL1 to CSL4). For example, the first dummy bitline driver (160-1) may be configured to control dummy bitlines adjacent to the first common source line (CSL1), the second dummy bitline driver (160-2) may be configured to control dummy bitlines adjacent to the second common source line (CSL2), the third dummy bitline driver (160-3) may be configured to control dummy bitlines adjacent to the third common source line (CSL3), and the fourth dummy bitline driver (160-4) may be configured to control dummy bitlines adjacent to the fourth common source line (CSL4).

[0094] Each of the plurality of dummy bitline drivers (160-1 to 160-4) may operate independently depending on the operating state of the non-volatile memory device (100) and the operating state of the bitline groups (BL_G1). For example, when a read operation is performed on the second bitline group (BL_G2), the second and third dummy bitline drivers (160-2, 160-3) corresponding to the second and third common source lines (CSL2, CSL3) adjacent to the second bitline group (BL_G2) may operate based on the previously described operation method. In one embodiment, the remaining dummy bitline drivers (160-1, 160-4) may be disabled, or the corresponding dummy bitlines may be maintained at a specific voltage or floated.

[0095] FIG. 17 is a flowchart showing the operation of the non-volatile memory device of FIG. 1. Referring to FIG. 1 and FIG. 17, in step S110, the non-volatile memory device (100) can receive a command (CMD). For example, the non-volatile memory device (100) can receive a command (CMD) from an external device (e.g., a memory controller).

[0096] In step S120, the non-volatile memory device (100) can determine whether the received command (CMD) is an erase command (ERS CMD). If it is not an erase command (ERS CMD), in step S130, the non-volatile memory device (100) can provide a zero voltage (V0) to a dummy bit line (DBL). For example, the control logic circuit (100) of the non-volatile memory device (100) can generate a first dummy bit line driving signal (DBL_DRV1) or a second dummy bit line driving signal (DBL_DRV2) in response to the command (CMD) so that the zero voltage (V0) is provided to the dummy bit line (DBL). In one embodiment, the control logic circuit (100) may maintain a first dummy bitline driving signal (DBL_DRV1) or a second dummy bitline driving signal (DBL_DRV2) so that a zero voltage (V0) is provided to a dummy bitline (DBL).

[0097] A dummy bitline driver (at least one of 160, 160a, 160b, or 160-1 to 160-4) can provide a zero voltage (V0) to a dummy bitline (DBL) in response to a first dummy bitline driving signal (DBL_DRV1) or a second dummy bitline driving signal (DBL_DRV2).

[0098] In the case of an erase command (ERS CMD), at step S140, the non-volatile memory device (100) may apply an erase voltage (VERS) to a dummy bit line (DBL) or float the dummy bit line (DBL). For example, the control logic circuit (100) may generate a first dummy bit line driving signal (DBL_DRV1) or a second dummy bit line driving signal (DBL_DRV2) in response to the erase command (ERS CMD) so that an erase voltage (VERS) is applied to the dummy bit line (DBL) or the dummy bit line (DBL) is floated. A dummy bitline driver (160, 160a, 160b, or at least one of 160-1 to 160-4) may provide or float an erase voltage (VERS) to a dummy bitline (DBL) in response to a first dummy bitline drive signal (DBL_DRV1) or a second dummy bitline drive signal (DBL_DRV2). In one embodiment, the dummy bitline driver (160a, or at least one of 160-1 to 160-4) may electrically connect the dummy bitline (DBL) to a common source line (CSL) in response to the first dummy bitline drive signal (DBL_DRV1) or the second dummy bitline drive signal (DBL_DRV2).

[0099] In step S150, the non-volatile memory device (100) can perform an operation corresponding to a command (CMD). For example, if the command (CMD) is a read command, the non-volatile memory device (100) can perform a read operation. In this case, since the dummy bit line (DBL) is biased to the zero voltage (V0) through step S130, noise caused by the current of the common source line (CSL) is not introduced into the bit lines. If the command (CMD) is an erase command, the non-volatile memory device (100) can perform an erase operation. In this case, since the erase voltage (VERS) is applied to the dummy bit line (DBL) through step S140 or the dummy bit line (DBL) is in a floating state, the speed at which the common source line (CSL) or bit lines (BL) reach the erase voltage (VERS) can be shortened.

[0100] FIGS. 18a and FIGS. 18b are timing diagrams for explaining the operation of a non-volatile memory device according to an embodiment of the present invention. For the brevity of the drawings and convenience of explanation, the read operation and program operation of the non-volatile memory device (100) are schematically illustrated. However, the scope of the present invention is not limited thereto. The horizontal axes of the timing diagrams in FIGS. 18a and FIGS. 18b indicate time.

[0101] In the embodiments described above, when the non-volatile memory device (100) does not perform an erase operation (i.e., when performing a read operation or a program operation), the dummy bit lines (DBL) maintain a zero voltage (V0). However, the scope of the invention is not limited thereto, and while the non-volatile memory device (100) performs a read operation or a program operation, the voltage of the dummy bit lines (DBL) can be controlled in various ways.

[0102] For example, referring to FIG. 1 and FIG. 18a, a non-volatile memory device (100) can perform a read operation. The read operation may include a bitline precharge operation (BL_PRECH), a wordline setup operation (WL_SETUP), a select read voltage application operation (VRD), and a sensing operation (SENSING).

[0103] As illustrated in FIG. 18a, a first voltage (V1) may be applied to dummy bitlines (DBL) during a bitline precharge operation (BL_PRECH) during a read operation of a non-volatile memory device (100), and a zero voltage (V0) may be applied to dummy bitlines (DBL) during the remaining operations (WL_SETUP, VRD, SENSING). As the first voltage (V1) is applied to the dummy bitlines (DBL) during the bitline precharge operation (BL_PRECH), the precharge speed of the bitlines (BL) may be improved.

[0104] For example, the precharge operation (BL_PRECH) of bitlines (BL) is an operation of charging bitlines (BL) to a precharge voltage. At this time, if the dummy bitline (DBL) maintains a zero voltage (V0), the precharge speed of the bitline (BL) adjacent to the dummy bitline (DBL) may decrease. On the other hand, if a first voltage (V1) is applied to the dummy bitlines (DBL) during the precharge operation (BL_PRECH) of bitlines (BL), the precharge speed of the bitline (BL) adjacent to the dummy bitline (DBL) will be improved. In one embodiment, the first voltage (V1) may be provided to the dummy bitline (DBL) at the same level as the bitline precharge voltage or in the same form.

[0105] In one embodiment, during the sensing operation of the read operation, the voltage of the dummy bit lines (DBL) can be maintained at a zero voltage (V0). In this case, as previously described, noise caused by the current flowing through the common source line (CSL) can be prevented from entering the bit lines (BL).

[0106] Next, referring to FIG. 1 and FIG. 18b, the non-volatile memory device (100) can perform a program operation. The program operation may include a bitline disable operation (BL_INH), a wordline setup operation (WL_SETUP), a program voltage application operation (VPGM), and a verification operation (VERI). In one embodiment, the verification operation (VERI) may be similar to the read operation described above. That is, the verification operation (VERI) may include a plurality of sub-operations as described with reference to FIG. 18a, and during any one of the plurality of sub-operations (e.g., a bitline precharge operation), a first voltage (V1) may be provided to dummy bitlines (DBL).

[0107] As illustrated in FIG. 18b, during the bitline disable operation (BL_INH) of the program operation of the non-volatile memory device (100), a second voltage (V2) may be provided to the dummy bitlines (DBL), and during the remaining operations (WL_SETUP, VPGM, VERI), a zero voltage (V0) may be applied to the dummy bitlines (DBL). As the first voltage (V1) is applied to the dummy bitlines (DBL) during the bitline disable operation (BL_INH), the precharge speed of the bitlines (BL) may be improved. For example, the bitline disable operation (BL_INH) may refer to an operation of charging the memory cells to be disabled and the corresponding bitlines to the power supply voltage (VCC). At this time, as described above, as the second voltage (V2) is provided to the dummy bitlines (DBL), the bitlines adjacent to the dummy bitlines (DBL) may be rapidly charged to the power supply voltage (VCC).

[0108] In one embodiment, the timing diagrams shown in FIGS. 18a and 18b are exemplary and the scope of the invention is not limited thereto. A non-volatile memory device (100) according to an embodiment of the invention may control dummy bitlines (DBL) through various other methods other than the method of controlling dummy bitlines (DBL) shown in FIGS. 18a and 18b.

[0109] For example, a read operation may include a plurality of read sub-operations. In at least one first read sub-operation among the plurality of read sub-operations, the non-volatile memory device (100) may provide a first voltage (V1) to dummy bit lines (DBL). At this time, at least one first read sub-operation may include a bit line precharge operation (i.e., an operation that directly controls the voltage of the bit line). In at least one second read sub-operation among the plurality of read sub-operations, the non-volatile memory device (100) may provide a zero voltage (V0) to dummy bit lines (DBL). At least one second read sub-operation may include a sensing operation (i.e., an operation in which noise may be generated by the current of the common source line).

[0110] Likewise, the program operation includes a plurality of program sub-operations, and in at least one first program sub-operation among the plurality of program sub-operations, the non-volatile memory device (100) may provide a second voltage (V2) to dummy bitlines (DBL). At this time, at least one first program sub-operation may include a bitline disable operation (i.e., an operation that directly controls the voltage of the bitline). In at least one second program sub-operation among the plurality of program sub-operations, the non-volatile memory device (100) may provide a zero voltage (V0) to dummy bitlines (DBL). At this time, at least one second program sub-operation may include a verification operation or a bitline precharge operation included in the verification operation.

[0111] As described above, the non-volatile memory device (100) according to an embodiment of the present invention can block noise caused by current flowing through a common source line (CSL) from entering the bit lines (BL) by maintaining the voltage of the dummy bit lines (DBL) at a zero voltage (V0) during a program operation or a read operation. In one embodiment, the non-volatile memory device (100) can control the voltage of the dummy bit lines (DBL) to a predetermined voltage (e.g., V1, V2, etc.) during a sub-operation that directly controls the voltage of the bit line (BL) during a program operation or a read operation, or during an operation that charges the voltage of the bit lines (BL) to a specific voltage (e.g., precharge voltage, power supply voltage, etc.). In this case, the performance of the non-volatile memory device (100) can be improved because the time for charging the bit lines to a specific voltage is shortened.

[0112] FIG. 19 is a drawing illustrating an exemplary memory device (1400) according to the present invention. Referring to FIG. 19, the memory device (1400) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip including a cell region (CELL) on a first wafer, fabricating a lower chip including a peripheral circuit region (PERI) on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip together by a bonding method. Here, the bonding process may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For example, the bonding metal may include copper (Cu) using Cu-to-Cu bonding. However, exemplary embodiments are not limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0113] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (1400) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0114] The peripheral circuit region (PERI) may include a first substrate (1210), an interlayer insulating layer (1215), a plurality of circuit elements (1220a, 1220b, 1220c) formed on the first substrate (1210), a first metal layer (1230a, 1230b, 1230c) connected to each of the plurality of circuit elements (1220a, 1220b, 1220c), and a second metal layer (1240a, 1240b, 1240c) formed on the first metal layer (1230a, 1230b, 1230c). In one embodiment, the first metal layer (1230a, 1230b, 1230c) may be formed of tungsten, which has relatively high electrical resistance, and the second metal layer (1240a, 1240b, 1240c) may be formed of copper, which has relatively low electrical resistance.

[0115] In this specification, only the first metal layer (1230a, 1230b, 1230c) and the second metal layer (1240a, 1240b, 1240c) are illustrated and described, but are not limited thereto, and in exemplary embodiments, at least one additional metal layer may be further formed on the second metal layer (1240a, 1240b, 1240c). At least some of the one or more additional metal layers formed on the upper part of the second metal layer (1240a, 1240b, 1240c) may be formed of aluminum or the like, having a lower electrical resistance than the copper forming the second metal layer (1240a, 1240b, 1240c).

[0116] The interlayer insulating layer (1215) is disposed on a first substrate (210) to cover a plurality of circuit elements (1220a, 1220b, 1220c), a first metal layer (1230a, 1230b, 1230c), and a second metal layer (1240a, 1240b, 1240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0117] A lower bonding metal (1271b, 1272b) may be formed on the second metal layer (1240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (1271b, 1272b) of the peripheral circuit region (PERI) may be electrically coupled to the upper bonding metal (1371b, 1372b) of the cell region (CELL) by a bonding method. The lower bonding metal (1271b, 1272b) and the upper bonding metal (1371b, 1372b) may be formed of aluminum, copper, or tungsten, etc.

[0118] Additionally, the upper bonding metal (1371b, 1372b) within the cell region (CELL) may be referred to as the first metal pad, and the lower bonding metal (1271b, 1272b) within the peripheral circuit region (PERI) may be referred to as the second metal pad.

[0119] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (1310), an interlayer insulating film (1315), and a common source line (1320). On the second substrate (1310), a plurality of word lines (1331–1338; 1330) may be stacked along a direction perpendicular to the upper surface of the second substrate (1310) (Z-axis direction). String selection lines and ground selection lines may be disposed on the upper and lower sides of each of the word lines (1330), and a plurality of word lines (330) may be disposed between the string selection lines and the ground selection lines.

[0120] The widths of the word lines (1330) along the X-direction may vary. As the distance from the first substrate (1210) of the peripheral circuit region (PERI) to a corresponding one of the multiple word lines (1330) increases, the width of the corresponding one of the multiple word lines (1330) decreases. Likewise, as the distance from the second substrate (1310) of the cell region (CELL) to a corresponding one of the multiple word lines (1330) increases, the width of the corresponding one of the multiple word lines (1330) increases.

[0121] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction perpendicular to the upper surface of the second substrate (1310) (Z-direction) and penetrate wordlines (1330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (1350c) and a second metal layer (1360c). For example, the first metal layer (1350c) may be a bitline contact, and the second metal layer (1360c) may be a bitline. In one embodiment, the bitline (1360c) may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (1310).

[0122] The interlayer insulating layer (1315) is disposed on a second substrate (310) to cover a common source line (1320), a plurality of word lines (1330), a plurality of cell contact plugs (1340), a first metal layer (1350a, 1350b, 1350c), and a second metal layer (1360a, 1360b, 1360c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0123] In one embodiment illustrated in FIG. 19, the area where the channel structure (CH) and the bit line (1360c) are placed may be defined as a bit line bonding area (BLBA). The bit line (1360c) may be electrically connected to circuit elements (1220c) that provide a page buffer (1393) in the peripheral circuit area (PERI) in the bit line bonding area (BLBA). The bit line (1360c) is connected to an upper bonding metal (1371c, 1372c) in the peripheral circuit area (PERI), and the upper bonding metal (1371c, 1372c) may be connected to a lower bonding metal (1271c, 1272c) that is connected to the circuit elements (1220c) of the page buffer (1393).

[0124] In the wordline bonding area (WLBA), wordlines (1330) may be extended along a second direction (X-axis direction) perpendicular to the first direction and parallel to the upper surface of the second substrate (1310), and may be connected to a plurality of cell contact plugs (1341–1347; 1340). The wordlines (1330) and the cell contact plugs (1340) may be connected to each other at pads provided by extending at least some of the wordlines (1330) along the second direction at different lengths. A first metal layer (1350b) and a second metal layer (1360b) may be connected in sequence to the upper portion of the cell contact plugs (1340) connected to the wordlines (330). The cell contact plugs (1340) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (1371b, 1372b) of the cell area (CELL) and the lower bonding metal (1271b, 1272b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0125] Cell contact plugs (1340) may be electrically connected to circuit elements (1220b) forming a row decoder (394) in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (1220b) of the row decoder (1394) may be different from the operating voltage of the circuit elements (1220c) forming the page buffer (1393). For example, the operating voltage of the circuit elements (1220c) forming the page buffer (1393) may be greater than the operating voltage of the circuit elements (1220b) forming the row decoder (1394).

[0126] A common source line contact plug (380) may be disposed in the external pad bonding area (PA). The common source line contact plug (1380) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to the common source line (320). A first metal layer (1350a) and a second metal layer (1360a) may be stacked sequentially on top of the common source line contact plug (1380). For example, the area where the common source line contact plug (1380), the first metal layer (1350a), and the second metal layer (1360a) are disposed may be defined as the external pad bonding area (PA).

[0127] Meanwhile, input / output pads (1205, 1305) may be disposed in the external pad bonding area (PA). Referring to FIG. 19, a lower insulating film (1201) covering the lower surface of the first substrate (1210) may be formed on the lower surface of the first substrate (1210), and a first input / output pad (1205) may be formed on the lower insulating film (1201). The first input / output pad (1205) is connected to at least one of a plurality of circuit elements (1220a, 1220b, 1220c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (1203), and may be separated from the first substrate (1210) by the lower insulating film (1201). Additionally, a side insulating film is disposed between the first input / output contact plug (1203) and the first substrate (1210) to electrically separate the first input / output contact plug (1203) and the first substrate (1210).

[0128] Referring to FIG. 19, an upper insulating film (1301) covering the upper surface of the second substrate (1310) may be formed on the upper surface of the second substrate (1310), and a second input / output pad (1305) may be disposed on the upper insulating film (1301). The second input / output pad (1305) may be connected to at least one of a plurality of circuit elements (1220a, 1220b, 1220c) disposed in the peripheral circuit area (PERI) through the second input / output contact plug (1303) and the lower bonding metal (1271a, 1272a) of the peripheral circuit area (PERI). In an exemplary embodiment, the second input / output pad (1305) may be electrically connected to the circuit element (1220a).

[0129] According to the embodiments, the second substrate (1310) and common source line (1320), etc., may not be placed in the area where the second input / output contact plug (1303) is placed. Additionally, the second input / output pad (1305) may not overlap with the word lines (1330) in the third direction (Z-axis direction). Referring to FIG. 19, the second input / output contact plug (1303) is separated from the second substrate (1310) in a direction parallel to the upper surface of the second substrate (1310) and may be connected to the second input / output pad (1305) by penetrating the interlayer insulating layer (1315) of the cell area (CELL).

[0130] According to embodiments, the first input / output pad (1205) and the second input / output pad (1305) may be formed optionally. For example, the memory device (1400) may include only the first input / output pad (1205) disposed on the upper part of the first substrate (1210), or only the second input / output pad (1305) disposed on the upper part of the second substrate (1310). Alternatively, the memory device (1400) may include both the first input / output pad (1205) and the second input / output pad (1305).

[0131] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern provided on the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0132] The memory device (1400) may form a lower metal pattern (1273a) having the same cross-sectional shape as the upper metal pattern (1372a) of the interconnected cell region (CELL) in the upper metal layer of the peripheral circuit region (PERI), corresponding to the upper metal pattern (1372a) formed in the upper metal layer of the cell region (CELL) in the external pad bonding region (PA). The lower metal pattern (273a) formed in the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, in the external pad bonding region (PA), an upper metal pattern (1372a) having the same shape as the lower metal pattern (1273a) of the peripheral circuit region (PERI) may be formed in the upper metal layer of the cell region (CELL) in correspondence to the lower metal pattern (1273a) formed in the upper metal layer of the peripheral circuit region (PERI).

[0133] A lower bonding metal (1271b, 1272b) may be formed on the second metal layer (1240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (1271b, 1272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (1371b, 1372b) of the cell region (CELL) by a Cu-to-Cu bonding method.

[0134] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (1392) having the same cross-sectional shape as the lower metal pattern (1252) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (1252) formed on the upper metal layer of the peripheral circuit area (PERI). A contact may not be formed on the upper metal pattern (1392) formed on the upper metal layer of the cell area (CELL).

[0135] In an exemplary embodiment, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern, corresponding to the metal pattern formed on the top metal layer in one of the cell region (CELL) and the peripheral circuit region (PERI), may be formed on the top metal layer in the other of the cell region (CELL) and the peripheral circuit region (PERI). A contact pattern may not be formed in the reinforcement metal pattern.

[0136] In one embodiment, the memory device (1400) of FIG. 19 may include the non-volatile memory device (100) described with reference to FIG. 1 through 17. The cell region (CELL) and peripheral circuit (PERI) of the non-volatile memory device (100) described with reference to FIG. 1 through 17 may correspond to the cell region (CELL) and peripheral circuit region (PERI) of the memory device (1400) of FIG. 19. The bitline bonding region (BLBA) of FIG. 19 may further include bonding pads for dummy bitlines, and the dummy bitlines may be electrically connected to a dummy bitline driver of the peripheral circuit region (PERI) through the added bonding pads. The dummy bitline driver of the peripheral circuit region (PERI) may control the dummy bitlines based on the method described with reference to FIG. 1 through 19. In one embodiment, a dummy bitline driver may be formed in a peripheral circuit area (PERI) so as to be physically separated or physically spaced apart from the page buffer (1393).

[0137] FIGS. 20 to 22 are drawings illustrating various stacked structures of a non-volatile memory device according to the present invention. In one embodiment, the various memory structures described with reference to FIGS. 20 to 22 may be the non-volatile memory device described with reference to FIGS. 1 to 19 or may operate based on the method described with reference to FIGS. 1 to 19. The number of memory structures described with reference to FIGS. 20 to 22 is exemplary, and the number of memory structures may be varied.

[0138] Referring to FIG. 20, the memory device (2000) may include a plurality of memory structures (2100 to 2400). The plurality of memory structures (2100 to 2400) may be stacked in a direction perpendicular to the substrate. For example, a first memory structure (2100) may be formed on a lower substrate (not shown), and a second memory structure (2200) may be formed on top of the first memory structure (2100). A third memory structure (2300) may be formed on top of the second memory structure (2200), and a fourth memory structure (2400) may be formed on top of the third memory structure (2300).

[0139] Each of the plurality of memory structures (2100 to 2400) may have a COP structure. For example, the first memory structure (2100) may include a first peripheral circuit (2110) and a first cell array (2120) formed on top of the first peripheral circuit (2110). Similarly, each of the second to fourth memory structures (2200 to 2400) may include second to fourth peripheral circuits (2210 to 2410) and second to fourth cell arrays (2220 to 2420) formed on top of each of the second to fourth peripheral circuits (2210 to 2410).

[0140] In one embodiment, each of the first to fourth cell arrays (2120 to 2420) may include dummy bitlines, and each dummy bitline may be connected to a dummy bitline driver of a corresponding peripheral circuit. For example, the dummy bitlines of the first cell array (2120) may be connected to a dummy bitline driver of the first peripheral circuit (2110), the dummy bitlines of the second cell array (2220) may be connected to a dummy bitline driver of the second peripheral circuit (2210), the dummy bitlines of the third cell array (2320) may be connected to a dummy bitline driver of the third peripheral circuit (2310), and the dummy bitlines of the fourth cell array (2420) may be connected to a dummy bitline driver of the fourth peripheral circuit (2410). The dummy bitline drivers may control the dummy bitlines based on the method described with reference to FIGS. 1 through 19.

[0141] Referring to FIG. 21, the memory device (3000) may include a peripheral circuit (3001) and a plurality of cell arrays (3120 to 3420). Compared to the memory device (2000) of FIG. 10, the memory device (3000) of FIG. 21 may not have a peripheral circuit between the plurality of cell arrays (3120 to 3420). For example, a peripheral circuit (3001) may be formed on a lower substrate (not shown), a first cell array (3120) may be formed on the peripheral circuit (3001), a second cell array (3220) may be formed on the first cell array (3120), a third cell array (3320) may be formed on the second cell array (3220), and a fourth cell array (3420) may be formed.

[0142] Each of the plurality of cell arrays (3120–3420) may include a metal layer for a word line, a bit line, or a dummy bit line. Each of the dummy bit lines of the plurality of cell arrays (3120–3420) may be connected to a dummy bit line driver of the peripheral circuit (3001).

[0143] In one embodiment, the channels of a plurality of cell arrays (3120 to 3420) may be shared as one channel, and in this case, cell strings sharing the same channel among the plurality of cell arrays (3120 to 3420) may form one memory block.

[0144] Referring to FIG. 22, the memory device (4000) may include a plurality of memory structures (4100 to 4400). The plurality of memory structures (4100 to 4400) may be stacked in a direction perpendicular to the substrate. Each of the plurality of memory structures (4100 to 4400) may include a peripheral circuit and a cell array joined by a bonding method, as described with reference to FIG. 19. For example, the first memory structure (4100) may include a first peripheral circuit (4110) and a first cell array (4120) formed on top of the first peripheral circuit (4110). At this time, the first peripheral circuit (4110) and the first cell array (4120) may be electrically connected to each other through a bonding method, as described with reference to FIG. 19. Likewise, each of the second to fourth memory structures (4200 to 4400) may include second to fourth peripheral circuits (4210 to 4410) and second to fourth cell arrays (4220 to 4420) joined by a bonding method on top of each of the second to fourth peripheral circuits (4210 to 4410).

[0145] As described above, a non-volatile memory device according to an embodiment of the present invention may have various stacked structures. The non-volatile memory device may control dummy bit lines according to the operating state. Accordingly, a non-volatile memory device having improved reliability and improved performance is provided.

[0146] FIG. 23 is a block diagram illustrating a memory system (5000) according to one embodiment of the present invention. Referring to FIG. 23, the memory system (5000) may include a memory controller (5100) and a memory device (5200). The memory device (5200) may include first to eighth pins (P11 to P18), a memory interface circuit (5210), a control logic circuit (5220), and a memory cell array (5230). The memory device (5200) may be a non-volatile memory device as described with reference to FIG. 1 to FIG. 22.

[0147] The memory interface circuit (5210) can receive a chip enable signal (nCE) from the memory controller (5100) through the first pin (P11). The memory interface circuit (5210) can transmit and receive signals with the memory controller (5100) through the second to eighth pins (P12 to P18) according to the chip enable signal (nCE). For example, when the chip enable signal (nCE) is in an enable state (e.g., low level), the memory interface circuit (5210) can transmit and receive signals with the memory controller (5100) through the second to eighth pins (P12 to P18).

[0148] The memory interface circuit (5210) can receive a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) from the memory controller (5100) through the second to fourth pins (P12 to P14). The memory interface circuit (5210) can receive a data signal (DQ) from the memory controller (5100) or transmit a data signal (DQ) to the memory controller (5100) through the seventh pin (P17). A command (CMD), an address (ADDR), and data (DATA) can be transmitted through the data signal (DQ). For example, the data signal (DQ) can be transmitted through a plurality of data signal lines. In this case, the seventh pin (P17) may include a plurality of pins corresponding to the plurality of data signals (DQ).

[0149] The memory interface circuit (5210) can obtain a command (CMD) from a data signal (DQ) received during the enable period (e.g., high level state) of a command latch enable signal (CLE) based on the toggle timings of a write enable signal (nWE). The memory interface circuit (5210) can obtain an address (ADDR) from a data signal (DQ) received during the enable period (e.g., high level state) of an address latch enable signal (ALE) based on the toggle timings of a write enable signal (nWE).

[0150] In an exemplary embodiment, the write enable signal (nWE) may maintain a static state (e.g., high level or low level) and then toggle between the high level and the low level. For example, the write enable signal (nWE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory interface circuit (5210) may obtain a command (CMD) or an address (ADDR) based on the toggle timings of the write enable signal (nWE).

[0151] The memory interface circuit (5210) can receive a read enable signal (nRE) from the memory controller (5100) through the fifth pin (P15). The memory interface circuit (5210) can receive a data strobe signal (DQS) from the memory controller (5100) through the sixth pin (P16) or transmit a data strobe signal (DQS) to the memory controller (5100).

[0152] In the data (DATA) output operation of the memory device (5200), the memory interface circuit (5210) may receive a read enable signal (nRE) that toggles through the fifth pin (P15) before outputting the data (DATA). The memory interface circuit (5210) may generate a data strobe signal (DQS) that toggles based on the toggling of the read enable signal (nRE). For example, the memory interface circuit (5210) may generate a data strobe signal (DQS) that begins to toggle after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read enable signal (nRE). The memory interface circuit (5210) may transmit a data signal (DQ) containing data (DATA) based on the toggling timing of the data strobe signal (DQS). Accordingly, the data (DATA) can be aligned with the toggle timing of the data strobe signal (DQS) and transmitted to the memory controller (5100).

[0153] In the data (DATA) input operation of the memory device (5200), when a data signal (DQ) containing data (DATA) is received from the memory controller (5100), the memory interface circuit (5210) may receive a data strobe signal (DQS) that toggles along with the data (DATA) from the memory controller (5100). The memory interface circuit (5210) may acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS). For example, the memory interface circuit (5210) may acquire data (DATA) by sampling the data signal (DQ) at the rising edge and falling edge of the data strobe signal (DQS).

[0154] The memory interface circuit (5210) can transmit a ready / busy output signal (nR / B) to the memory controller (5100) through the eighth pin (P18). The memory interface circuit (5210) can transmit status information of the memory device (5200) to the memory controller (5100) through the ready / busy output signal (nR / B). When the memory device (5200) is in a busy state (i.e., when internal operations of the memory device (5200) are being performed), the memory interface circuit (5210) can transmit a ready / busy output signal (nR / B) indicating the busy state to the memory controller (5100). When the memory device (5200) is in a ready state (i.e., when internal operations of the memory device (5200) are not performed or are completed), the memory interface circuit (5210) may transmit a ready / busy output signal (nR / B) indicating the ready state to the memory controller (5100). For example, while the memory device (5200) reads data (DATA) from the memory cell array (5230) in response to a page read command, the memory interface circuit (5210) may transmit a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the memory controller (5100). For example, while the memory device (5200) programs data (DATA) into the memory cell array (5230) in response to a program command, the memory interface circuit (5210) may transmit a ready / busy output signal (nR / B) indicating a busy state to the memory controller (5100).

[0155] The control logic circuit (5220) can control various operations of the memory device (5200) overall. The control logic circuit (5220) can receive a command / address (CMD / ADDR) obtained from the memory interface circuit (5210). The control logic circuit (5220) can generate control signals to control other components of the memory device (5200) according to the received command / address (CMD / ADDR). For example, the control logic circuit (5220) can generate various control signals to program data (DATA) into the memory cell array (5230) or to read data (DATA) from the memory cell array (5230).

[0156] The memory cell array (5230) can store data (DATA) obtained from the memory interface circuit (5210) under the control of the control logic circuit (5220). The memory cell array (5230) can output the stored data (DATA) to the memory interface circuit (5210) under the control of the control logic circuit (5220).

[0157] The memory cell array (5230) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, or MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments of the present invention will be described with a focus on embodiments in which the memory cells are NAND flash memory cells.

[0158] The memory controller (5100) may include first to eighth pins (P21 to P28) and a controller interface circuit (5110). The first to eighth pins (P21 to P28) may correspond to the first to eighth pins (P11 to P18) of the memory device (5200).

[0159] The controller interface circuit (5110) can transmit a chip enable signal (nCE) to the memory device (5200) through the first pin (P21). The controller interface circuit (5110) can transmit and receive signals to and from the selected memory device (5200) through the second to eighth pins (P22~P28) via the chip enable signal (nCE).

[0160] The controller interface circuit (5110) can transmit a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) to the memory device (5200) through the second to fourth pins (P22 to P24). The controller interface circuit (5110) can transmit a data signal (DQ) to the memory device (5200) or receive a data signal (DQ) from the memory device (5200) through the seventh pin (P27).

[0161] The controller interface circuit (5110) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the memory device (5200) along with a toggling write enable signal (nWE). The controller interface circuit (5110) can transmit a data signal (DQ) containing a command (CMD) to the memory device (5200) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the memory device (5200) by transmitting an address latch enable signal (ALE) having an enable state.

[0162] The controller interface circuit (5110) can transmit a read enable signal (nRE) to the memory device (5200) through the fifth pin (P25). The controller interface circuit (5110) can receive a data strobe signal (DQS) from the memory device (5200) or transmit a data strobe signal (DQS) to the memory device (5200) through the sixth pin (P26).

[0163] In the data (DATA) output operation of the memory device (5200), the controller interface circuit (5110) can generate a toggling read enable signal (nRE) and transmit the read enable signal (nRE) to the memory device (5200). For example, the controller interface circuit (5110) can generate a read enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggling state before the data (DATA) is output. Accordingly, a toggling data strobe signal (DQS) can be generated in the memory device (5200) based on the read enable signal (nRE). The controller interface circuit (5110) can receive a data signal (DQ) containing data (DATA) along with the toggling data strobe signal (DQS) from the memory device (5200). The controller interface circuit (5110) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0164] In the data (DATA) input operation of the memory device (5200), the controller interface circuit (5110) can generate a toggling data strobe signal (DQS). For example, the controller interface circuit (5110) can generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the controller interface circuit (5110) can transmit a data signal (DQ) containing the data (DATA) to the memory device (5200).

[0165] The controller interface circuit (5110) can receive a ready / busy output signal (nR / B) from the memory device (5200) through the eighth pin (P28). The controller interface circuit (5110) can determine the status information of the memory device (5200) based on the ready / busy output signal (nR / B).

[0166] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention.

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Claims

Claim 1 A non-volatile memory device comprising: a plurality of bit lines connected to a plurality of cell strings; a common source line connected to the plurality of cell strings; at least one dummy bit line provided between the common source line and the plurality of bit lines; a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device; and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal, wherein the dummy bit line driver comprises: a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage and configured to operate in response to a first dummy bit line driving signal among the at least one dummy bit line driving signals; and a second switch connected between the at least one dummy bit line and the common source line and configured to operate in response to a second dummy bit line driving signal among the at least one dummy bit line driving signals. Claim 2 A non-volatile memory device according to claim 1, wherein the dummy bitline driver comprises: a first switch connected between the at least one dummy bitline and a first terminal receiving the first voltage, and configured to operate in response to the first dummy bitline driving signal among the at least one dummy bitline driving signals. Claim 3 A non-volatile memory device according to claim 2, wherein the control logic circuit is configured to generate the first dummy bitline driving signal so that the first switch is turned on in response to the command not being an erase command, and to generate the first dummy bitline driving signal so that the first switch is turned off in response to the command being an erase command. Claim 4 delete Claim 5 A non-volatile memory device according to claim 1, wherein the control logic circuit is configured to generate the first and second dummy bitline driving signals such that the first switch is turned on and the second switch is turned off in response to the command not being an erase command, and to generate the first and second dummy bitline driving signals such that the first switch is turned off and the second switch is turned on in response to the command being an erase command. Claim 6 A non-volatile memory device according to claim 1, further comprising an erase voltage generator configured to generate an erase voltage during an erase operation and provide the erase voltage to the common source line, the bit line, or the common source line and the bit line. Claim 7 In claim 6, the dummy bitline driver is: a non-volatile memory device further configured to be connected between the at least one dummy bitline and the erase voltage generator, and to selectively provide the erase voltage from the erase voltage generator to the dummy bitline in response to the second dummy bitline driving signal among the at least one dummy bitline driving signals. Claim 8 A non-volatile memory device according to claim 1, wherein the first voltage is a ground voltage. Claim 9 In claim 8, when the command is a read command, the dummy bitline driver is configured to apply a second voltage to the dummy bitline while a precharge operation for the plurality of bitlines is performed, and to provide the first voltage to the dummy bitline while a sensing operation for the plurality of bitlines is performed, and the second voltage is a precharge voltage for the plurality of bitlines, a non-volatile memory device. Claim 10 A non-volatile memory device according to claim 1, further comprising a page buffer circuit electrically connected to the plurality of bit lines, wherein the page buffer circuit and the dummy bit line driver are formed in a peripheral circuit region on a semiconductor substrate, and the plurality of cell strings, the plurality of bit lines, the common source line, and at least one dummy bit line are formed in a memory cell region above the peripheral circuit region. Claim 11 A non-volatile memory device according to claim 10, wherein each of the plurality of bit lines is electrically connected to the page buffer circuit through first through-plugs penetrating the memory cell region, and at least one dummy bit line is connected to the dummy bit line driver through at least one second through-plug penetrating the memory cell region. Claim 12 A non-volatile memory device according to claim 11, wherein the first through plugs and the at least one second through plug are formed on a plane on which the page buffer circuit is formed, each of the first through plugs is formed at a first interval along a first direction, and the interval between the at least one second through plug among the first through plugs and one adjacent along the first direction and the at least one second through plug is a second interval narrower than the first interval. Claim 13 A non-volatile memory device comprises: a peripheral circuit formed on a semiconductor substrate; a memory cell array formed on the peripheral circuit and comprising a plurality of cell strings; and a metal layer formed on the memory cell array, wherein the metal layer comprises: a plurality of bit lines connected to the plurality of cell strings; a common source line connected to the plurality of cell strings; and at least one dummy bit line provided between the plurality of bit lines and the common source line, wherein the peripheral circuit comprises: a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device; and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal, wherein the dummy bit line driver comprises: a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage, and configured to operate in response to a first dummy bit line driving signal among the at least one dummy bit line driving signals. A non-volatile memory device comprising a second switch connected between the at least one dummy bitline and the common source line and configured to operate in response to a second dummy bitline driving signal among the at least one dummy bitline driving signals. Claim 14 In claim 13, the peripheral circuit further comprises a page buffer circuit electrically connected to the plurality of bit lines in a non-volatile memory device. Claim 15 In claim 14, the memory cell array comprises: a plurality of first through-plugs formed in a direction perpendicular to the semiconductor substrate and configured to electrically connect the plurality of bit lines and the page buffer circuit; and at least one second through-plug formed in a direction perpendicular to the semiconductor substrate and configured to electrically connect the at least one dummy bit line and the dummy bit line driver. Claim 16 In claim 15, the plurality of first through plugs and the at least one second through plug are non-volatile memory devices formed in a bitline contact area. Claim 17 A non-volatile memory device according to claim 13, wherein the control logic circuit is configured to: generate the at least one dummy bitline driving signal such that the first voltage is provided to the at least one dummy bitline in response to the command not being an erase command, and generate the at least one dummy bitline driving signal such that the at least one dummy bitline is floated, or the at least one dummy bitline is connected to the common source line, or an erase voltage is applied to the at least one dummy bitline in response to the command being an erase command. Claim 18 A method of operation of a non-volatile memory device comprising: receiving a read command from an external device; in response to the read command, applying a precharge voltage to at least one dummy bit line located between a plurality of bit lines and a common source line, and while a sensing operation for the plurality of bit lines is performed, applying a first voltage different from the precharge voltage to the at least one dummy bit line to perform a read operation; receiving an erase command from the external device; in response to the erase command, floating the at least one dummy bit line, electrically connecting the at least one dummy bit line to the common source line, or applying an erase voltage to the at least one dummy bit line; and performing an erase operation in response to the erase command. Claim 19 A method of operation according to claim 18, wherein the plurality of bit lines are connected to a page buffer circuit, and the at least one dummy bit line is connected to a dummy bit line driver. Claim 20 In claim 18, the erasure operation comprises an operation of applying the erasure voltage to the common source line, the plurality of bit lines, or the common source line and the plurality of bit lines.

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