Semiconductor wafer splitting method

Abstract

A method for splitting a semiconductor wafer comprises: forming one or more epitaxial layers on a semiconductor wafer; forming a plurality of device structures on one or more epitaxial layers; forming a metallization layer and / or passivation layer on the plurality of device structures; attaching a carrier to the semiconductor wafer having one or more epitaxial layers — the carrier protects the plurality of device structures and mechanically stabilizes the semiconductor wafer —; forming a separation region within the semiconductor wafer — the separation region has at least one altered physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor wafer —; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer is split into two separate pieces — one of the pieces holds the plurality of device structures —.

Description

Background Technology

[0001] Wafer costs account for a significant portion of the total production cost of silicon carbide (SiC) semiconductor devices. Reducing these costs can secure a competitive advantage. One method to reduce wafer costs is to reuse standard wafers at least twice; that is, after creating device structures, the SiC wafer is split, and a thinner, recycled wafer portion that does not contain device structures is reused to form additional device structures. Integrating SiC wafer splitting into the standard SiC production process is complex and requires changes or adjustments to the production process for efficient manufacturing.

[0002] Therefore, it is necessary to integrate the SiC wafer splitting process and the SiC production process in an efficient and cost-sensitive manner.

[0003] Of course, the present invention is not limited to the features and advantages described above. In fact, those skilled in the art will recognize additional features and advantages by reading the following detailed description and looking at the accompanying drawings.

[0004] According to one embodiment of a method for dividing a semiconductor wafer, the method comprises: forming one or more epitaxial layers on a semiconductor wafer; forming a plurality of device structures on one or more epitaxial layers; forming a metallization layer and / or passivation layer on the plurality of device structures; attaching a carrier to the semiconductor wafer having one or more epitaxial layers — the carrier protects the plurality of device structures and mechanically stabilizes the semiconductor wafer —; forming a separation region within the semiconductor wafer — the separation region has at least one altered physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor wafer —; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer is divided into two separate pieces — one of the pieces holds the plurality of device structures —.

[0005] According to another embodiment of a method for dividing a semiconductor wafer, the method comprises: forming one or more epitaxial layers on a semiconductor wafer; forming a plurality of device structures on one or more epitaxial layers; forming a metallization layer and / or passivation layer on the plurality of device structures; attaching a carrier to the semiconductor wafer having one or more epitaxial layers — the carrier protects the plurality of device structures and mechanically stabilizes the semiconductor wafer —; applying laser radiation to a separation region within the semiconductor wafer such that the separation region has increased thermomechanical stress compared to the rest of the semiconductor wafer and at least one crack propagates along the separation region; and dividing the semiconductor wafer into two separate pieces along the at least one crack — one of the pieces retains the plurality of device structures —.

[0006] According to one embodiment of a method for splitting off a semiconductor wafer from a semiconductor boule, the method comprises the steps of: forming a separation region within the semiconductor boule—the separation region having at least one altered physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor boule—; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and the wafer is split off from the semiconductor boule.

[0007] Those skilled in the art will recognize additional features and benefits when reading the following detailed description and viewing the attached drawings. Brief explanation of the drawing

[0008] The components of the drawings are not necessarily scaled relative to one another. Similar reference numerals indicate corresponding similar parts. Features of the various embodiments illustrated may be combined unless they are mutually exclusive. Embodiments are illustrated in the drawings and described in detail in the following description. FIGS. 1a to 1e illustrate cross-sectional views of a semiconductor wafer during different stages of a wafer splitting process according to an embodiment. FIG. 2 shows a cross-sectional view of another embodiment of a carrier used during the wafer splitting process. FIG. 3 illustrates a portion of a separation region formed within a semiconductor substrate, comprising microcracks that are at least partially separated from each other within the separation region. Figure 4a shows a graph of temperature versus storage modulus for a polymer that is used during the wafer splitting process and does not contain filler. Figure 4b shows a graph of temperature versus storage modulus for the polymer of Figure 4a (this polymer contains one or more fillers). FIGS. 5a to 5d illustrate cross-sectional views of inclined edges of a semiconductor wafer according to different embodiments. Specific details for implementing the invention

[0009] In particular, those skilled in the art who benefit from the teachings presented in the foregoing description and the related drawings will be able to devise variations and other embodiments of the disclosed invention(s). Accordingly, it should be kept in mind that the invention(s) are not limited to the specific embodiments disclosed, and that variations and other embodiments are intended to be included within the scope of this disclosure. Specific terms may be used herein, but such terms are used only in a general and descriptive sense and are not intended to be limiting.

[0010] The embodiments described herein relate to a semiconductor wafer splitting process that reduces manufacturing costs associated with the production of semiconductor devices. While the focus is on SiC wafers and SiC devices produced using SiC wafers, the embodiments described herein are not limited to SiC wafers and may be used with other semiconductor wafer technologies such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), sapphire, etc. Device structures are created on a base (thick) semiconductor wafer, and the base wafer is subsequently split into a thinner device wafer containing the device structures and a thinner regeneration wafer. The regeneration wafer can be processed, and additional devices can be created within the regeneration wafer.

[0011] The wafer splitting technology described herein comprises at least two main steps, namely, (i) forming a separation region within a semiconductor wafer—the separation region having at least one altered physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor wafer—and (ii) applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer is split into two separate pieces.

[0012] In some embodiments, the step of forming a separation region includes the step of forming microcracks that are at least partially disconnected from each other within the separation region. The microcracks connect to each other in response to an external force applied to the semiconductor wafer, forming at least one crack that propagates along the separation region and divides the semiconductor wafer into two separate pieces. Instead of creating connected cracks in a single step / process, material waste / loss can be reduced by first creating microcracks and then subsequently connecting the microcracks.

[0013] External forces applied to the semiconductor wafer may include, for example, ultrasonic vibration or the application of a polymer layer. If the semiconductor wafer is split using only ultrasonic vibration or a polymer layer without first creating a separation region having at least one altered physical property that increases thermomechanical stress within the separation region, uncontrolled splitting and / or unwanted surface structures such as Wallner lines, river lines, etc. may occur due to the influence of acoustic reflection during splitting that occurs as at least one crack propagates.

[0014] Next, various embodiments of the semiconductor wafer splitting process are described.

[0015] FIGS. 1a through 1e illustrate cross-sectional views of a semiconductor wafer (100) during different stages of a splitting process according to an embodiment. As previously described, the semiconductor wafer (100) may be any type of wafer used to manufacture semiconductor devices. For example, the semiconductor wafer may be a SiC wafer such as 4H-SiC and may have a thickness (T_wafer) that may vary depending on the wafer diameter. Generally, 4-inch and 6-inch SiC wafers have a thickness of 350 µm (microns), for example, with an accuracy of up to ±40 µm or up to ±25 µm. For larger SiC wafer diameters, the thickness may be greater. The wafer splitting process described herein may also be used with other SiC polytypes and / or other semiconductor materials (e.g., Si, GaAs, GaN, sapphire, etc.) as previously described, with corresponding adjustments of process parameters.

[0016] FIG. 1a illustrates a semiconductor wafer (100) after one or more epitaxial layers (102) are formed on the semiconductor wafer (100), a device structure (104) is formed on one or more epitaxial layers (102), a metallization layer and / or passivation layer (106) (e.g., at least one passivation layer) is formed on the device structure (104), and a carrier (108) is attached to the semiconductor wafer (100) having one or more epitaxial layers (102). The layer (106) is shown as a continuous layer in cross-section, but may instead be discontinuous. For example, in the case of a passivation layer, the layer (106) may exist only on the device structure (104). In the case of a metallization layer, the layer (106) may be patterned. The carrier (108) protects the device structure (104) from damage during and / or after the splitting process and mechanically stabilizes the semiconductor wafer (100).

[0017] The doping regions (110, 112, 114) of the device structure (104) are created by injection and subsequent annealing steps or by doping during the epitaxy process. For example, the first deposited epitaxial layer (114) may be an n-doped drain or emitter layer having a thickness ranging from, for example, 10 μm to 50 μm in the case of a power MOSFET (metal-oxide-semiconductor field effect transistor) or power diode device, or a p-doped emitter layer in the case of an IGBT (insulated gate bipolar transistor) device. A second epitaxially deposited layer (not shown) may be deposited as a buffer layer to prevent punch-through of the space charge layer toward the emitter / drain layer (114). The thickness of the buffer layer is generally 1 µm to 40 µm or 2 µm to 30 µm. Then, an n-type drift zone layer (112) can be deposited by epitaxy technology. The thickness of the drift zone layer (112) depends on the target breakdown voltage (typically, in the range of 8 µm to 12 µm for 1200 V devices, and in the range of 25 µm to 35 µm for 3.3 kV devices). The doping level of the drift zone layer (112) can also be adjusted according to the desired breakdown voltage (typically, about 1016 cm⁻³ for 1200 V devices, and several times 1015 cm⁻³ for 3.3 kV devices). Front device structures (110), such as the p-body and source region for a power MOSFET or IGBT, or the p-emitter for a power diode, can be formed by masked ion implantation and a subsequent annealing step. For switchable devices, the gate structure is also implemented in the form of a planar or trench-based gate.

[0018] After forming the device, the semiconductor wafer (100) has a front surface having a device structure (104) and a front metallization layer and / or passivation layer (106). The device structure (104) may be a semiconductor device such as a MEMS (microelectromechanical systems) and / or MOEMS (micro-opto-electro-mechanical system) device; a diode such as an MPS (merged-pin-Schottky) diode, a Schottky diode, a MOS-gated diode, etc.; or a transistor device such as a MOSFET, JFET (junction FET), IGBT, fin-FET, thyristor, etc.; or a structure of a combination thereof. If the device structure (104) includes a Schottky contact, the front metallization layer (108) may include a Schottky contact metal. Additionally, or as an alternative to cases where there is no Schottky contact, the front metallization layer (108) may include an ohmic contact metal.

[0019] FIG. 1b illustrates a semiconductor wafer (100) after forming a separation region (116) within the semiconductor wafer (100). The separation region (116) has at least one altered physical property that increases the thermomechanical stress within the separation region (166) compared to the rest of the semiconductor wafer (100). A carrier (108) that protects the device structure (104) from damage and mechanically stabilizes the semiconductor wafer (100) during and / or after the separation process may be attached to the semiconductor wafer (100) having one or more epitaxial layers (102) before or after forming the separation region. The carrier (108) may be a single piece of material or a carrier system comprising a multi-layer and / or composite structure.

[0020] The shape of the carrier (108) may be similar to or even identical to the shape of the semiconductor wafer (100). While the semiconductor wafer (100) may have flattened cuts on one or more sides to indicate the crystallographic plane of the wafer (100), the carrier (108) may not have such planes. The carrier (108) may have a larger diameter than the semiconductor wafer (100), for example, a diameter that is at least 0.1% larger. The diameter of the carrier (108) may be, for example, up to 3 times, up to 2 times, or up to 1.5 times the diameter of the semiconductor wafer (100). The mechanically stabilized portion of the carrier (108) and / or an optional immobilization layer of the carrier (108) may completely cover the front surface of the semiconductor wafer (100), for example, as shown in FIGS. 1a through 1e. Alternatively, the mechanically stabilized portion of the carrier (108) and / or the optional immobilization layer divides the front (active surface) of the semiconductor wafer (100) into sections along the surface of the wafer (100) as illustrated in FIG. 2. According to this embodiment, the mechanically stabilized portion of the carrier (108) and / or the optional immobilization layer may have the form of a ring or a grid, and / or may exist only in the edge region of the semiconductor wafer (100) (e.g., a ring intersecting the outer / edge portion of the wafer (100)). In each case, the topography of the device structure (104) may be embedded in the carrier (108) by a potting material and / or an adhesive layer and / or a non-adhesive layer (118) between the semiconductor wafer (100) and the carrier (108), for example, having one or more epitaxial layers (102) and a front metallization (106).

[0021] A carrier (108) may be temporarily (reversibly) or permanently attached to a semiconductor wafer (100) having one or more epitaxial layers (102). In the case of temporary attachment, the carrier (108) may include an adhesive tape having heat or UV emission; an adhesive layer (organic or inorganic composition) combined with a rigid support such as a transparent substrate, an opaque substrate, a polymer film, etc.; a fixed or movable electrostatic chuck; a fixed or movable vacuum chuck; a movable vacuum carrier, etc. In the case of permanent attachment, the carrier (108) may include high-temperature embossed glass (e.g., in the form of a grid, a ring, etc.); a glass grid and / or ring attached via solder glass; a glass grid and / or ring attached via a laser welding process, etc.; or bonded to a semiconductor wafer (100) having one or more epitaxial layers (102) via one or more diffusion soldering layers. It may include a substrate such as a semiconductor metal insulator (e.g., glass) substrate, a substrate bonded to a semiconductor wafer (100) having one or more epitaxial layers (102) through an aerobic and / or anaerobic adhesive or other bonding components.

[0022] The separation region (116) allows for the splitting of the semiconductor wafer (100) at a defined location. Otherwise, splitting may occur at any location that may be affected by crystal damage, etc. Additionally, without the defined separation region (116), it would be more difficult to perform reproducible manufacturing because only a portion of the device wafer and / or regenerated wafer could be used. A well-defined separation region (116) significantly reduces material loss (also called kerf loss) during wafer splitting. The thickness (t_sep) of the separation region (116) can define the kerf loss. For example, the loss may result from the vertical extent of microcracks and additional loss due to chemical, mechanical, electrochemical, and / or plasma material removal.

[0023] The location of the separation region (116) can be selected such that, after defining the device structure (104), the distance 'd1' to the front of the semiconductor wafer (100) having one or more epitaxial layers (102) is sufficiently high to allow mechanical processing of the thinner device wafer produced as a result of the splitting process, while the distance (d1) to the front is sufficiently low and thus the distance 'd2' to the back is sufficiently high so that the recycled wafer produced as a result of the splitting process can be processed. In one embodiment, the separation region (116) is close to the interface between the wafer (100) and the first deposited epitaxial layer (114) (substrate / drain layer in the case of a power MOSFET or substrate / emitter layer in the case of a diode). Generally, the distance between the interface between the wafer (100) and the first deposited epitaxial layer (114) and the separation region (116) is less than 10 μm, less than 4 μm, or less than 2 μm.

[0024] Generally, thermomechanical stress may be increased within the separation region (116) relative to the rest of the semiconductor wafer (100), which simplifies, for example, applying mechanical force and / or thermal stress to the wafer (100) to split the semiconductor wafer (100) into device wafers and regeneration wafers. The thermomechanical stress generated within the separation region (116) may be sufficient to cause wafer splitting without necessarily requiring the application of external force. For example, laser radiation may be applied to the separation region (116) such that the separation region (116) has increased thermomechanical stress relative to the rest of the semiconductor wafer (100) and at least one crack propagates along the separation region (116), thereby enabling wafer splitting without external force. However, external force may still be applied to lift one of the split wafer pieces and / or to assist in wafer splitting.

[0025] In one embodiment, the separation region (116) is formed by damaging the material of the semiconductor wafer (100) at a target location. For example, if SiC is used as the wafer material, the SiC material may be damaged. In some cases, the SiC may be at least partially decomposed, for example, into Si and C. This may be accomplished, for example, by generating a plasma in the SiC material at a target location within the semiconductor wafer (100). At least some of the atoms of the plasma may be modified into carbon clusters and silicon material, for example, in the form of amorphous carbon and / or amorphous silicon. Additionally, or alternatively, at least some of the atoms may be recrystallized, semicrystallized, and / or reconfigured into at least one polytype of SiC (e.g., 4H-SiC, 6H-SiC, or 3C-SiC) or amorphous SiC (where both the Si and C phases are amorphous). In some examples, the separation region (106) may include at least one polytype crystalline portion of SiC or silicon or carbon (e.g., microcrystalline form), an amorphous portion of SiC or silicon or carbon, and / or cavities.

[0026] In one embodiment, plasma is generated in the material at the target location within the semiconductor wafer (100) by focusing laser radiation at the target location within the semiconductor wafer (100). The semiconductor wafer (100) may be irradiated through the rear side opposite the device structure (104) or through the front side where the device structure (104) is located, and focused into a well-defined area within the wafer (100) to ignite the plasma within the wafer (100), which decomposes the laser-irradiated semiconductor material into components. For example, in the case of SiC, the laser-irradiated SiC decomposes into SiC → Si + C. Interaction with the laser radiation may result in other material phases and / or microcracks within the semiconductor wafer (100), for example, as described above. Irradiating the semiconductor wafer (100) with laser radiation through the front surface is preferably performed before creating the device structure (104) or at least before creating the front metallization (106), because the laser radiation can damage the device structure (104) and the metallization (106) is not transparent to the laser radiation.

[0027] If the separation region (116) is already predefined by an injection, for example as briefly described above and described in more detail below, the laser radiation applied to the separation region (116) may be in a resonant regime in which a single-photon process (e.g., single-photon absorption) is dominant, that is, the probability of a multiphoton process is small (e.g., more than 10 times smaller than the probability of a single-photon process). In the resonant regime, the band gap of the material within the separation region (116) may be in the photon energy range of the laser radiation, for example (e.g., having a detuning of the band gap of up to ±5% or up to ±1% or up to ±0.1% or up to ±0.01% depending on the laser energy). Since laser radiation can be absorbed in the separation region (116) and may cause further damage to the separation region (116) (e.g., decomposition of SiC in the case of a SiC wafer (100)), mechanical force and / or thermal stress may not be required at all or may be required little to no time to split the semiconductor wafer (100) in the separation region (116).

[0028] The separation region (116) within the semiconductor wafer (100) may be defined by focusing laser radiation on a well-defined region, such as a region having a thickness less than the target thickness (e.g., 50% or less of the target thickness), or by additionally defining a predefined layer formed in advance, for example, by ion implantation. In this case, the laser radiation may be in an off-resonant regime, so that the probability of a single-photon process in the separation region (116) is low and most multiphoton processes (in particular, multiphoton absorption) may need to be accounted for. For example, an off-resonant regime may be achieved if the band gap of the separation region (116) is greater than the photon energy of the laser radiation (e.g., at least 2 times or at least 10 times the photon energy of the laser radiation). In the case of a multiphoton process, damage generation may be further supported by a predefined layer (e.g., formed by ion implantation) that increases absorption within the region where the focus of the laser radiation is located.

[0029] Laser radiation may be pulsed laser radiation. Parameters of laser radiation, such as pulse duration, repetition rate, pulse energy, intensity, wavelength, pulse waveform, polarization, etc., are interrelated and can be optimized according to specific applications or requirements. For example, laser radiation may have a pulse duration of 100 fs to 100 ns (e.g., 50 ps to 10 ns), a repetition rate of 10 kHz to 10 MHz, a pulse energy of 100 nJ to 50 μJ, and a peak wavelength of 400 nm to 2100 nm (e.g., 900 nm to 1200 nm).

[0030] Laser radiation can be applied along laser lines that are essentially parallel to each other (also referred to as scribe lines). For each laser line, a laser beam is scanned along that line. The laser scanning speed is very fast so that adjacent single laser shots can be distinguished (e.g., without overlapping). Here, a single laser shot can correspond to damage generated by a single pulse of laser radiation, as shown in FIG. 3.

[0031] In FIG. 3, which shows a small section of the separation region (116), the dashed ellipse labeled 'A' corresponds to the location of individual / single laser shots. At each single laser shot location 'A', the material of the separation region (116) is decomposed, and microcracks extending along the crystal plane of the wafer material appear, as indicated by additional microcracks labeled 'B' and 'C'. The microcracks 'A', 'B', and 'C' formed within the separation region (116) are at least partially disconnected from each other. The microcrack labeled 'C' is created by tension between other microcracks 'A' and is not formed directly by the laser shot. In the case of 4H-SiC, the growth direction of the semiconductor wafer (100), which corresponds to the vertical direction in which the wafer (100) has a thickness (T_wafer), can generally be tilted slightly with respect to the main crystal axis by 4° (also called the off-axis angle). Thus, the crystal plane is tilted.

[0032] If the separation region (116) has only one large crack that is flat but tilted, the separation region (116) will be tilted 4° with respect to the lateral direction (i.e., the direction perpendicular to the vertical direction). This will result in a massive loss along the entire diameter of the semiconductor wafer (100). Therefore, in the case of SiC, if the separation surface is not flat but zigzag / serrated, the splitting process may be useful for 4H-SiC. Microcracks 'A', 'B', and 'C' are subsequently connected to enable the splitting of the semiconductor wafer (100), as will be described in more detail later.

[0033] In addition to damaging the semiconductor wafer (100) with laser radiation to form a separation region (116), or alternatively, the material of the semiconductor wafer (100) may be damaged at the target location by implanting ions into the semiconductor wafer (100) at a depth corresponding to the target location within the wafer (100) to create and / or predefine the separation region (116). The ions may directly cause higher absorption, for example, due to a higher absorption rate in the separation region (116) where most of the implanted ions are present. If SiC is used as the material of the semiconductor wafer (100), the ions may cause a conversion of the crystal structure of the SiC wafer to a different material, for example, to a different polytype (e.g., 4H-SiC to 3C-SiC) and / or a different degree of crystallinity and / or amorphous SiC and / or silicon and carbon (amorphous or crystalline), thereby causing the absorption coefficient at the wavelength of the laser radiation to increase in the separation region (116). Ions can also cause the material of the semiconductor wafer (100) to decompose in the separation area (116).

[0034] In one embodiment, the ions may be selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions, and helium ions. For example, atoms such as nitrogen and / or phosphorus atoms may be injected into the separation region (116) in an injection amount that results in the formation of an amorphous layer and / or cavity. Additionally or alternatively, helium ions or protons may be injected to create a localized damaged layer within the separation region (116). Light ions such as helium and hydrogen penetrate deeper into the semiconductor wafer (100) compared to heavier ions for the same energy, thereby increasing the depth of the separation region (116) if desired. Light ions such as helium and hydrogen may preferentially create vacancy clusters and a damaged layer at the end-of-range of the injection, thereby facilitating the separation process in this region. Phosphorus and / or nitrogen are suitable for creating a severely damaged layer in SiC. In the case of phosphorus and / or nitrogen, the injection amount may be selected so that an amorphous layer and / or cavity is created in the separation region (116). Optionally, channeling during injection may be utilized, which results in lower surface damage to the surface where the injection is performed. Ions may be injected before one or more epitaxial layers (102) are formed. For example, ions may be injected through the surface of the semiconductor wafer (100) where one or more epitaxial layers (102) are to be formed.

[0035] After ion implantation, a device structure (104) may be created. After or before creating the device structure (104), laser radiation as described above may be irradiated through the semiconductor wafer (100), whereby the focus is approximately located in the implantation layer. The ions and / or the semiconductor material converted by the ions have increased absorption compared to the rest of the wafer (100), thereby improving the decomposition of, for example, SiC into Si and C by enhanced local heating of the wafer. For example, to increase the thermomechanical stress within the separation region (116) compared to the rest of the semiconductor wafer (100), a combination of multiphoton and single-photon processes may occur within the predefined ion implantation layer.

[0036] The separation region (116) may be formed before or after the device structure (104) is formed. In some embodiments, part of the separation region (116) may be formed before the device structure (104) is formed, for example, before epitaxial growth, and other part of the separation region (116) may be formed after the device structure (104) is formed.

[0037] In one embodiment, the separation region (116) is formed by laser irradiation and ion implantation of the semiconductor wafer (100). In particular, by implanting ions into the semiconductor wafer (100) at a depth corresponding to a target location within the wafer (100), the material of the semiconductor wafer (100) can be damaged at the target location within the semiconductor wafer (100). After the ions are implanted, laser radiation is focused at the target location within the semiconductor wafer (100). According to this embodiment, the implanted ions increase the absorption coefficient within the separation region (116) at the wavelength of the laser radiation, which further increases the thermomechanical stress within the separation region (116) compared to the rest of the semiconductor wafer (100).

[0038] After the formation of the separation region (116), an external force is applied to the semiconductor wafer (100) so that at least one large crack propagates along the separation region (116) and the semiconductor wafer (100) is divided into two separate pieces. The force equilibrium of surface energy, bonding force, and (optional) external pressure shifts in favor of the external force, so that the internal bonding force still present within the semiconductor wafer (100) is overcome in the separation region (116), causing crack propagation. Alternatively, laser radiation propagates a sufficient crack along the separation region (116), so that an external force does not necessarily need to be applied to divide the semiconductor wafer (100). However, an external force may still be applied to assist in the lift-off process of the divided wafer pieces and / or wafer splitting.

[0039] The separation region (116) has at least one altered physical property that increases the thermomechanical stress within the separation region (116) compared to the rest of the semiconductor wafer (100) as described above. For example, laser radiation and / or ion implantation may be used to alter at least one physical property of the separation region (116). Laser radiation may form microcracks 'A', 'B', 'C' in the separation region (116), while implanted ions may increase the absorption coefficient of the separation region (116) at the wavelength of the laser radiation. The local increase in thermomechanical stress limits crack propagation to the separation region (116) in a controlled and reproducible manner. The local increase in thermomechanical stress may be sufficient to propagate a sufficient crack along the separation region (116), so that an external force may not necessarily need to be applied to split the semiconductor wafer (100). However, in other embodiments, a force may be used to assist in splitting the semiconductor wafer (100).

[0040] In one embodiment, the external force applied to the semiconductor wafer (100) to divide the wafer (100) along the separation region (116) includes applying ultrasonic vibrations (sound waves) to the semiconductor wafer (100). The ultrasonic vibrations may have frequencies in the kHz range, for example, at least 20 kHz and at most 60 kHz (e.g., 30 kHz to 50 kHz, 35 kHz to 45 kHz). When applying ultrasonic vibrations, the semiconductor wafer (100) may be placed in a container filled with a fluid such as pure water, deionized water, a general solvent, dimethylformamide, isopropyl alcohol, methanol and / or ethanol. For example, ultrasonics may be applied to the semiconductor wafer (100) using a device similar to an ultrasonic cleaning device.

[0041] FIGS. 1c through 1e illustrate other embodiments of applying an external force to a semiconductor wafer (100) to divide the wafer (100) along a separation region (116). According to this embodiment, a polymer (120) is applied to the semiconductor wafer (100) and / or carrier (108) as shown in FIG. 1c. The polymer (120) has a CTE (Coefficient of Thermal Expansion) different from that of the semiconductor wafer (100). The polymer (120) and the semiconductor wafer (100) then undergo a temperature process in which the polymer (120) applies mechanical stress to the semiconductor wafer (100), as indicated by the dashed arrow in FIG. 1d. The mechanical stress causes at least one large crack (122) to propagate along the separation region (116), thereby causing the semiconductor wafer (100) to be divided into two separate pieces (124, 126) as shown in FIG. 1e. One piece (124) holds the device structure (104). Another piece (126) can be used for subsequent device processing.

[0042] In the case of a separation region (116) containing microcracks 'A', 'B', and 'C' as described above in relation to FIG. 3, the microcracks 'A', 'B', and 'C' are connected to each other by mechanical stress applied to the semiconductor wafer (100) to form a large crack (122), thereby splitting the wafer (100). That is, the individual microcracks 'A', 'B', and 'C' move relative to each other in response to an external force. Therefore, the separation region (116) can be considered as a combination of several microcracks 'A', 'B', and 'C' that are joined only during splitting, rather than being considered as a single layer within the semiconductor wafer (100). When SiC is used as the material for the semiconductor wafer (100), combining the microcracks A', 'B', and 'C' creates two individual pieces (124, 126) having a sawtooth pattern separation surface (128, 130). Therefore, in the case of SiC, the generated device piece (124) and regeneration piece (126) do not have a smooth flat surface. In one embodiment, after the semiconductor wafer (100) is divided into two separate pieces (124, 126), each separation surface (128, 130) created by a large crack (122) propagating along the separation region (116) is smoothed. Residual decomposition material may be present on the separation surface (128, 130) of each piece (124, 126) divided from the wafer (100), and this can be removed by a cleaning process.

[0043] A polymer (120) may be attached to a semiconductor wafer (100) while a carrier (108) is already attached to the wafer (100). The polymer (120) may be attached to the front surface of the semiconductor wafer (100) and to the back surface (132) of the semiconductor wafer (100) facing away from the carrier (108). Alternatively, the polymer (108) may be attached to the outer surface (134) of the carrier (108) facing away from the semiconductor wafer (100). In this case, the carrier (108) is positioned between the polymer (120) and the semiconductor wafer (100). According to another embodiment, the polymer (120) may be attached to both the back surface (132) of the semiconductor wafer (100) and the outer surface (134) of the carrier (108). For example, when a glass grid or glass ring is used as the carrier (108), the polymer (120) may be applied to the back surface (132) of a semiconductor wafer (100) having one or more epitaxial layers (102) and additionally to the outer surface (134) of the carrier (108). Generally, an additional layer (e.g., an adhesive layer such as an adhesive, and / or a layer that facilitates the subsequent removal of the polymer (120)) may be applied between the surface to which the polymer (120) is applied and the polymer (120).

[0044] The polymer (120) may be selected based on CTE as well as considering a number of parameters. The CTE of the polymer (120) must be different from the CTE of the semiconductor wafer (100). For example, it is desirable that the CTE of the polymer (120) be greater than the CTE of the semiconductor wafer (100). In addition to the difference in CTE, a linear course of the CTE of the polymer (120) over a wide temperature range may be advantageous for successful separation.

[0045] Additionally, the polymer (120) must have sufficiently high thermal conductivity. In one embodiment, one or more fillers, such as ZnO and / or carbon black, are added to the polymer (120) prior to the temperature process. The filler(s) increase the thermal conductivity of the polymer (120) and reduce the slope of the storage modulus of the polymer (120), thereby extending the linear course of the polymer (120)'s CTE over a smaller temperature range. By adding ZnO and / or carbon black to the polymer (120), the percolation chains formed can significantly increase the thermal conductivity of the polymer (120). When filler materials are used, the polymer material may be selected so that the filler material is easily and homogeneously distributed throughout the polymer (120).

[0046] For a sufficiently large heat transfer coefficient for the semiconductor wafer (100), adding one or more fillers, such as ZnO and / or carbon black, to the polymer reduces the time required to achieve a temperature difference that generates sufficient mechanical stress for splitting the semiconductor wafer (100) along the separation region (116) by more than half. At the same time, the increase in elastic modulus is distributed over a larger temperature range because it is already evident at higher temperatures compared to the unfilled polymer. As a result, less wafer breakage and higher splitting efficiency are achieved during the manufacturing process. An example of the polymer (120) is polydimethylsiloxane (PDMS), which generally contains at least one filler. PDMS can generate high adhesion to the surface. Therefore, to allow for damage-free polymer removal, the adhesion may require some pretreatment or pre-adjustment. For example, a foil may be placed between the surface to which the polymer is to be attached and the polymer.

[0047] The attachment of the polymer (120) is generally performed at a higher temperature (e.g., higher than room temperature but less than 300°C). A binding process may be applied to allow for a solid adhesion throughout the entire temperature process. For example, before applying the polymer (120), the application surface of the polymer (120) and / or the semiconductor wafer (100) and / or the carrier (108) may undergo chemical and / or physical surface treatment (e.g., plasma) to allow for a solid bond. An indirect, temporary low-temperature plasma activation process may be used for the easy subsequent removal of the polymer (120). This has the advantage that the ambivalent nature of the structure-property relationship can be achieved here and that a significant thermal diffusion process is not expected at the low temperatures occurring. Diffusion can be a problem in the case of metal impurities, such as impurities originating from the metal layer of the device structure (104), for example. The polymer bond is sufficient to perform a splitting operation but weak enough to allow for the complete removal of the polymer (120) in a subsequent step.

[0048] Another additional or alternative approach is to apply a bonding (sacrificial) layer between a semiconductor wafer (100) having one or more epitaxial layers (102) (and / or a carrier (108) if applicable) and a polymer (120). The bonding layer may be selected such that its adhesion to the polymer (120) is reduced, for example, through chemical or heat treatment.

[0049] The polymer (120) may not be formed directly on the semiconductor wafer (100) and / or carrier (108) having one or more epitaxial layers (102). Rather, the polymer (120) may be formed beforehand and subsequently attached to the semiconductor wafer (100) and / or carrier (108) having one or more epitaxial layers (102). In another embodiment, the polymer (120) is formed directly on the semiconductor wafer (100) and / or carrier (108) having one or more epitaxial layers (102), for example, by spraying or coating.

[0050] After attaching the polymer (120) to a semiconductor wafer (100) and / or a carrier (108) having one or more epitaxial layers (102), a temperature process is performed. In one embodiment, the temperature process is selected such that the polymer (120) undergoes partial glass transition and partial crystallization during the temperature process. This may include a first step in which the polymer (120) and the semiconductor wafer (100) undergo a temperature gradient from a starting temperature (300°C or lower but higher than room temperature) to room temperature, and a second step in which the polymer (120) and the semiconductor wafer (100) are further cooled to a lower temperature. For example, the lower temperature may correspond to ±40°C of the boiling temperature of the cooling liquid (e.g., liquid nitrogen) used for cooling. The lower temperature may be, for example, -170°C, particularly for the entire wafer (100). In some examples, the lower temperature may be below the glass transition temperature (Tg) of the polymer (120) depending on the cooling conditions (e.g., cooling liquid).

[0051] FIGS. 4a and 4b illustrate the storage modulus (in MPa) as a function of temperature (°C) for the same polymer (120) with no filler (FIG. 4a) and with one or more fillers (FIG. 4b). During the second stage of the temperature process, the polymer (120) may undergo partial glass transition and partial crystallization processes as illustrated in FIGS. 4a and 4b. The definition of glass transition (Tg) is not standardized. There are several methods for determining Tg that depend on the method used to define Tg and the parameters used in that method, rather than being a constant material property. For example, when using a dynamic mechanical analyzing (DMA) method to measure viscoelastic modulus, the dynamic glass transition temperature and the parameters used for measurement (e.g., frequency of external load, ramping speed, ramping direction, measurement accuracy, etc.) must be explicitly specified.

[0052] In Fig. 4a, the glass transition temperature (Tg) is found at the turning point (at least for some methods defining Tg). In Fig. 4b, crystallization begins at a temperature higher than the glass transition (a steeper slope between T1 and T2), where T3 is less than T2 and T2 is less than T1 (a higher slope than T2). The turning point and, therefore, Tg, can no longer be clearly determined compared to the same but filler-free polymer in Fig. 4a.

[0053] By adding one or more fillers to the polymer (120), the degrees of freedom of the polymer used crystallize faster than the degrees of freedom of the polymer without fillers. At temperatures higher than the glass transition, polymer molecules are flexible and can adopt different forms, for example, through bond rotation around flexible Si-O-Si siloxane single bonds ([R3Si-O-SiR3]n). As the temperature decreases, the activation energy required for bond rotation is achieved statistically less frequently, so there is a limit to the existing degrees of freedom and thus the mobility of the elastomer molecules decreases. The frequency of positional changes of polymer molecules decreases as the temperature decreases. Due to additional intermolecular interactions occurring between filler particles and polymer molecules, the rearrangement dynamics of the polymer molecules decrease as the group vibration or cooperative motion of surrounding chains and molecules decreases due to the lower free volume. Particle-particle interactions must be accounted for at very high filler content (e.g., > 20 w%).

[0054] The storage modulus of the polymer (120) increases at higher temperatures for the polymer (120) of Fig. 4b having one or more fillers compared to the polymer of Fig. 4a without fillers. Consequently, the slope of the increase in storage modulus is lower. The increase in force during the splitting process is proportional to the storage modulus. Therefore, the lower the slope, the lower the increase in force and the smoother the increase in force, resulting in smoother crack propagation. By adding one or more fillers to the polymer (120), tension within the semiconductor wafer (100) can be relieved while reducing wafer breakage outside the separation region (116). In contrast, for higher increases in force, non-uniformity has a greater impact on the splitting process. Polymer crystallization may lead to lower overall force, but this can be compensated for, for example, by increasing the thickness of the polymer (120). The temperature gradient and temperature process are preferably selected so that local temperature differences within the semiconductor wafer (100) are reduced. Excessive local temperature differences can cause excessive stress increase and unwanted cracks within the semiconductor wafer (100).

[0055] A semiconductor wafer (100) may have a beveled edge (136), for example, as shown in FIG. 5a. The beveled edge (136) has a chamfered outer surface as shown in FIG. 5a. The shape of the beveled edge (136) may cause problems when preparing the separation region (116), the location of which is indicated by a dashed line in FIG. 5a. For example, a change in the thickness of the beveled edge (136) may cause a change in the propagation length of the laser beam. Thus, the focus of the laser beam changes at the wafer bevel. Consequently, the separation region (116) may not continue to the outer rim / edge surface (138) of the semiconductor wafer (100). A change in thickness and / or location at the outer rim / edge surface (138) of the semiconductor wafer (100) may also interfere with ion implantation for defining or pre-defining the separation region (116).

[0056] To allow access to the separation region (116) from the outer rim / edge face (138) and thus facilitate or at least simplify the splitting process, the shape of the slanted face may be changed as illustrated in FIGS. 5b and 5c. According to these embodiments, the slanted edge (136) of the semiconductor wafer (100) is thinned to a depth (T_thin) below the separation region (116), the location of which is indicated by a dotted line in FIGS. 5b and 5c. Depending on the type of thinning used, the thinned region may have square (Fig. 5b) or rounded (Fig. 5c) edges. The slanted edge (136) of the semiconductor wafer (100) may be thinned by mechanical removal such as grinding, cutting, laser pulverization, electro(chemical) discharge machining, etching, etc.

[0057] FIG. 5d illustrates another embodiment, according to which a slot (500) is formed on the slanted edge (136) of a semiconductor wafer (100) and the slot extends laterally to a separation region (116) whose location is indicated by a dashed line in FIG. 5d. The slot (500) may be formed in addition to or alternatively to the thinning shown in FIG. 5b and 5c. In each case, the slanted edge (136) of the semiconductor wafer (100) may be processed before or after creating the separation region (116).

[0058] During the wafer splitting process, pressure may be applied to the semiconductor wafer (100). For example, a piston may apply pressure to the semiconductor wafer (100) having one or more epitaxial layers (102). The piston may be pressed toward the wafer (100) with pressurized air, or only the load force of the piston may be applied to the wafer (100). This process is better controlled than immersing the wafer (100) containing the polymer (120) (e.g., completely or gradually) in a cryogenic fluid (e.g., nitrogen), particularly for the spatial resolution of the cooling process.

[0059] After the division of the semiconductor wafer (100), the piece (124) holding the device structure (104) may be thinner than the other piece (126). For example, the piece (124) holding the device structure (104) may have a thickness of up to 100 μm (e.g., up to 70 μm or up to 50 μm) and at least the required thickness of the drift region as described above (or at least a thickness 10 μm greater than the required thickness), and the other piece (126) may have a thickness of at least 150 μm (e.g., at least 190 μm).

[0060] Polymer removal may be used to allow the reuse of the polymer (120) and to avoid breakage of the divided wafer pieces (124, 126). For example, the polymer (120) may be removed by mechanical means from both the device-side separation surface (128) (if applicable) and the regeneration-side separation surface (130) without chemical etching (generally, without chemicals), plasma etching, or other gas-phase sputtering processes. Thus, the polymer (120) can be rapidly removed in an environmentally friendly and residue-free manner due to the attachment process described herein.

[0061] After wafer splitting, the separation surfaces (128, 130) of the split wafer pieces (124, 126) are processed. For the back surface of the piece (124) having the device structure (104), damage removal may be performed, for example, by mechanical grinding and / or chemical mechanical polishing and / or etching. After damage removal, the final roughness of the separation surface (128) may have a root-mean-square (rms) value of less than 5 μm or less than 2 μm. Then, additional processing may be performed. For the piece (126) without the device structure (104), the separation surface (130) may require processing for preparation for subsequent epitaxial growth. In this case, the rms value of the separation surface (130) may be less than 500 nm or less than 300 nm. Since the thickness of the piece (126) without the device structure (104) can be adjusted to the original thickness of the wafer (100) by a deposition technique such as CVD-epithelial technology, the same procedure described above can be repeated several times for the thickened piece (126).

[0062] The embodiments described herein include splitting a new wafer from a base semiconductor wafer. Alternatively, the splitting technique described herein may be applied to split a semiconductor wafer from a semiconductor boule. A semiconductor boule is a single-crystal ingot produced by synthesis means such as the Bridgman technique or the Czochralski process. The splitting technique described herein may be applied to split a semiconductor wafer from a semiconductor boule by forming a separation region within the semiconductor boule, wherein the separation region has at least one modified physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor boule. For example, the thermomechanical stress within the separation region may be increased by focusing laser radiation at a target location within the semiconductor boule. Then, an external force is applied to the semiconductor boule so that at least one crack propagates along the separation region and the wafer is split from the semiconductor boule. In one embodiment, an external force is applied to the semiconductor boule by applying a polymer having a CTE different from the CTE of the semiconductor boule to the semiconductor boule. The polymer and the semiconductor bowl undergo a temperature process in which the polymer imparts mechanical stress to the semiconductor bowl. Additionally, as described herein, the thermomechanical stress generated within the separation region of the semiconductor bowl may be sufficient to cause wafer splitting without necessarily requiring the application of external force. In either case, the process may be applied multiple times to yield multiple wafers from a single semiconductor bowl.

[0063] The numbered embodiments below illustrate one or more aspects of the present disclosure, but the present disclosure is not limited thereto.

[0064] Example 1: A method for splitting a semiconductor wafer, wherein the method comprises the step of forming one or more epitaxial layers on the semiconductor wafer;

[0065] A method for dividing a semiconductor wafer, comprising: forming a plurality of device structures on one or more epitaxial layers; forming a metallization layer and / or passivation layer on the plurality of device structures; attaching a carrier to the semiconductor wafer having the one or more epitaxial layers — the carrier protects the plurality of device structures and mechanically stabilizes the semiconductor wafer —; forming a separation region within the semiconductor wafer — the separation region has at least one altered physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor wafer —; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer is divided into two separate pieces — one of the pieces retains the plurality of device structures.

[0066] Example 2: A method for dividing a semiconductor wafer, wherein, in Example 1, the step of forming the separation region within the semiconductor wafer includes the step of damaging the material of the semiconductor wafer at a target location within the semiconductor wafer.

[0067] Example 3: A method for splitting a semiconductor wafer, wherein, in Example 2, the step of damaging the material of the semiconductor wafer at the target location within the semiconductor wafer includes the step of generating plasma in the material at the target location within the semiconductor wafer.

[0068] Example 4: A method for dividing a semiconductor wafer, wherein, in Example 3, the step of generating the plasma in the material at the target location within the semiconductor wafer includes the step of focusing laser radiation at the target location within the semiconductor wafer.

[0069] Example 5: A method for splitting a semiconductor wafer, wherein, in Example 2, the step of damaging the material of the semiconductor wafer at the target location within the semiconductor wafer comprises the step of implanting ions into the semiconductor wafer at a depth corresponding to the target location within the semiconductor wafer.

[0070] Example 6: A method for dividing a semiconductor wafer in Example 5, wherein the ions are selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions, and helium ions.

[0071] Example 7: A method for splitting a semiconductor wafer in Example 5 or Example 6, wherein the amount of ion implantation is selected such that the material of the semiconductor wafer damaged by the implanted ions becomes amorphous or cavities are created.

[0072] Example 8: A method for splitting a semiconductor wafer, wherein, in Example 2, the step of damaging the material of the semiconductor wafer at the target location within the semiconductor wafer comprises the step of implanting ions into the semiconductor wafer at a depth corresponding to the target location within the semiconductor wafer, and the step of focusing laser radiation at the target location within the semiconductor wafer after the ions are implanted, wherein the implanted ions increase the absorption coefficient of the separation region at the wavelength of the laser radiation.

[0073] Example 9: A method for dividing a semiconductor wafer, wherein, in any one of Examples 1 to 8, the inclined edge of the semiconductor wafer is further thinned to a depth of the separation region or below.

[0074] Example 10: A method for dividing a semiconductor wafer, further comprising the step of forming a slot extending laterally into the separation region at an inclined edge of the semiconductor wafer in any one of Examples 1 to 9.

[0075] Example 11: A method for dividing a semiconductor wafer, wherein in any one of Examples 1 to 10, the step of applying the external force to the semiconductor wafer includes the step of applying ultrasonic vibration to the semiconductor wafer.

[0076] Example 12: A method for dividing a semiconductor wafer, wherein in any one of Examples 1 to 11, the step of applying the external force to the semiconductor wafer comprises the step of applying a polymer to the semiconductor wafer and / or the carrier — the polymer having a CTE (coefficient of thermal expansion) different from the CTE of the semiconductor wafer — and the step of causing the polymer and the semiconductor wafer to undergo a temperature process in which the polymer imparts mechanical stress to the semiconductor wafer.

[0077] Example 13: A method for dividing a semiconductor wafer in which, in Example 12, the temperature process is selected such that the polymer undergoes partial glass transition and partial crystallization during the temperature process.

[0078] Example 14: A method for splitting a semiconductor wafer, wherein, in Example 12 or Example 13, the temperature process comprises a first step in which the polymer and the semiconductor wafer undergo a temperature gradient from a starting temperature to room temperature—wherein the starting temperature is 300°C or lower but higher than room temperature—and a second step in which the polymer and the semiconductor wafer are further cooled to a temperature below the glass transition temperature of the polymer.

[0079] Example 15: A method for splitting a semiconductor wafer, comprising, in any one of Examples 12 to 14, further adding one or more fillers to the polymer before the temperature process to increase the thermal conductivity of the polymer and decrease the gradient of the storage modulus of the polymer.

[0080] Example 16: A method for splitting a semiconductor wafer in Example 15, wherein one or more fillers comprise ZnO and / or carbon black.

[0081] Example 17: A method for dividing a semiconductor wafer, wherein, in any one of Examples 12 to 16, the method further comprises the step of chemically and / or physically treating the surface of the polymer and / or the surface of the semiconductor wafer and / or the surface of the carrier before applying the polymer.

[0082] Example 18: A method for splitting a semiconductor wafer in any one of Examples 12 to 17, wherein at least one crack propagates during partial crystallization of the polymer occurring during the temperature process.

[0083] Example 19: A method for dividing a semiconductor wafer, wherein in any one of Examples 1 to 18, the step of applying the external force to the semiconductor wafer comprises the step of applying pressure to the semiconductor wafer during the division of the semiconductor wafer into two separate pieces.

[0084] Example 20: A method for dividing a semiconductor wafer, wherein, in any one of Examples 1 to 19, after the semiconductor wafer is divided into two separate pieces, the method further comprises the step of reducing the surface roughness of the separation surfaces of the two pieces of the semiconductor wafer — each separation surface is a surface formed when the at least one crack propagates along the separation region —.

[0085] Example 21: A method for dividing a semiconductor wafer, wherein in any one of Examples 1 to 20, the at least one modified physical property of the separation region comprises a plurality of microcracks that are at least partially separated from each other within the separation region, and the plurality of microcracks are connected to each other in response to the external force to form the at least one crack that propagates along the separation region.

[0086] Example 22: A method for dividing a semiconductor wafer in Example 21, wherein the semiconductor wafer is a SiC wafer, and the at least one crack formed by the connection of the plurality of microcracks in response to the external force has a sawtooth pattern.

[0087] Example 23: A method for splitting a semiconductor wafer, the method comprising: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures on the one or more epitaxial layers; forming a metallization layer and / or passivation layer on the plurality of device structures; attaching a carrier to the semiconductor wafer having the one or more epitaxial layers — the carrier protects the plurality of device structures and mechanically stabilizes the semiconductor wafer —; applying laser radiation to a separation region within the semiconductor wafer such that the separation region has increased thermo-mechanical stress compared to the rest of the semiconductor wafer and at least one crack propagates along the separation region; and splitting the semiconductor wafer into two separate pieces along the at least one crack — one of the pieces retains the plurality of device structures —.

[0088] Example 24: A method for splitting off a semiconductor wafer from a semiconductor bowl, comprising the steps of: forming a separation region within the semiconductor bowl—the separation region having at least one altered physical property that increases the thermomechanical stress within the separation region compared to the rest of the semiconductor bowl—and applying an external force to the semiconductor bowl such that at least one crack propagates along the separation region and the wafer is separated from the semiconductor bowl.

[0089] Example 25: A method for splitting a semiconductor wafer from a semiconductor bowl, wherein, in Example 24, the step of applying the external force to the semiconductor bowl comprises: a step of applying a polymer to the semiconductor bowl — the polymer has a CTE (coefficient of thermal expansion) different from the CTE of the semiconductor bowl —; and a step of causing the polymer and the semiconductor bowl to undergo a temperature process in which the polymer imparts mechanical stress to the semiconductor bowl.

[0090] Terms such as "first," "second," etc., are used to describe various components, areas, sections, etc., and are not used with any restrictive intent. Throughout the specification, similar terms indicate similar components.

[0091] As used herein, terms such as “having,” “contain,” and “including” are open-ended terms indicating the presence of the mentioned components or features but not excluding additional components or features. The terms “one (a, an),” “the,” and “the” are intended to include both singular and plural forms unless the context clearly indicates otherwise.

[0092] Unless otherwise specifically stated, the features of the various embodiments described in this specification may be combined with one another.

[0093] Although specific embodiments have been illustrated and described herein, it will be recognized by those skilled in the art that, without departing from the scope of the invention, the specific embodiments illustrated and described may be replaced by various alternative and / or equivalent implementations. This application is intended to include any adaptation or variation of the specific embodiments discussed herein. Accordingly, the invention is intended to be limited only by the claims and their equivalents.

Claims

Claim 1 A method for splitting off a semiconductor wafer from a semiconductor bowl, the method comprising: forming a separation region within the semiconductor bowl — said separation region having at least one altered physical property that increases thermomechanical stress within said separation region compared to the rest of said semiconductor bowl —; forming a slot extending laterally into said separation region at an inclined edge of said semiconductor bowl; and applying an external force to said semiconductor bowl such that at least one crack propagates along said separation region and the wafer is split off from said semiconductor bowl. Claim 2 A method for dividing a semiconductor wafer according to claim 1, wherein the step of forming the separation region within the semiconductor bowl comprises the step of damaging the material of the semiconductor bowl at a target location within the semiconductor bowl. Claim 3 A method for splitting a semiconductor wafer according to claim 2, wherein the step of damaging the material of the semiconductor bowl at the target location within the semiconductor bowl comprises the step of generating plasma in the material at the target location within the semiconductor bowl. Claim 4 In paragraph 3, the step of generating the plasma in the material at the target location within the semiconductor bowl comprises the step of focusing laser radiation at the target location within the semiconductor bowl, in a method for dividing a semiconductor wafer. Claim 5 A method for splitting a semiconductor wafer according to claim 2, wherein the step of damaging the material of the semiconductor bowl at the target location within the semiconductor bowl comprises the step of implanting ions into the semiconductor bowl at a depth corresponding to the target location within the semiconductor bowl. Claim 6 A method for dividing a semiconductor wafer according to claim 5, wherein the ions are selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions, and helium ions. Claim 7 A method for dividing a semiconductor wafer according to claim 5, wherein the amount of ion implantation is selected such that the material of the semiconductor bowl damaged by the implanted ions becomes amorphous or cavities are created. Claim 8 In paragraph 2, the step of damaging the material of the semiconductor bowl at the target location within the semiconductor bowl comprises the step of implanting ions into the semiconductor bowl at a depth corresponding to the target location within the semiconductor bowl, and the step of focusing laser radiation at the target location within the semiconductor bowl after the ions are implanted, wherein the implanted ions increase the absorption coefficient of the separation region at the wavelength of the laser radiation, a method for splitting a semiconductor wafer. Claim 9 A method for dividing a semiconductor wafer according to claim 1, wherein the step of applying the external force to the semiconductor bowl includes the step of applying ultrasonic vibration to the semiconductor bowl. Claim 10 A method for dividing a semiconductor wafer according to claim 9, wherein the ultrasonic vibration has a frequency in the range of 20 kHz to 60 kHz. Claim 11 A method for dividing a semiconductor wafer according to claim 9, wherein when the ultrasonic vibration is applied, the semiconductor bowl is placed in a container filled with fluid so that the semiconductor bowl is immersed in the fluid. Claim 12 A method for dividing a semiconductor wafer according to claim 11, wherein the fluid is pure water, deionized water, or a solvent. Claim 13 A method for dividing a semiconductor wafer according to claim 1, wherein the step of applying the external force to the semiconductor bowl comprises the step of applying a polymer to the semiconductor bowl — the polymer having a CTE (coefficient of thermal expansion) different from the CTE of the semiconductor bowl — and the step of causing the polymer and the semiconductor bowl to undergo a temperature process in which the polymer imparts mechanical stress to the semiconductor bowl. Claim 14 In claim 13, the temperature process is selected such that the polymer undergoes partial glass transition and partial crystallization during the temperature process, a method for dividing a semiconductor wafer. Claim 15 A method for splitting a semiconductor wafer according to claim 13, wherein the temperature process comprises a first step in which the polymer and the semiconductor bowl undergo a temperature gradient from a starting temperature to room temperature—wherein the starting temperature is 300°C or lower but higher than room temperature—and a second step in which the polymer and the semiconductor bowl are further cooled to a temperature below the glass transition temperature of the polymer. Claim 16 A method for splitting a semiconductor wafer according to claim 13, further comprising the step of adding one or more fillers to the polymer before the temperature process, which increases the thermal conductivity of the polymer and decreases the gradient of the storage modulus of the polymer. Claim 17 A method for dividing a semiconductor wafer according to claim 16, wherein one or more of the fillers comprise ZnO and / or carbon black. Claim 18 A method for dividing a semiconductor wafer according to claim 13, further comprising the step of chemically and / or physically treating the surface of the polymer and / or the surface of the semiconductor bowl before applying the polymer. Claim 19 A method for splitting a semiconductor wafer according to claim 13, wherein at least one crack propagates during partial crystallization of the polymer occurring during the temperature process. Claim 20 A method for splitting a semiconductor wafer according to claim 1, comprising the steps of: forming a new separation region within the semiconductor bowl after the wafer is split from the semiconductor bowl — the new separation region having at least one altered physical property that increases the thermo-mechanical stress within the new separation region compared to the rest of the semiconductor bowl — and applying an external force to the semiconductor bowl such that at least one crack propagates along the new separation region and an additional wafer is separated from the semiconductor bowl. Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete

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