Memory system and a testing method

Abstract

A memory system includes an electronic device and a memory device. The memory device includes an input pad that receives an input signal and an output pad that outputs a first output signal in a first test mode and outputs a second output signal in a second test mode. The memory device further includes a memory interface having a transceiver and a mode selection circuit. The transceiver communicates with the electronic device, and the mode selection circuit selects a first test mode or a second test mode. The first test mode includes loading from the transceiver and the electronic device of the memory interface, and the second test mode excludes loading from the transceiver and the electronic device of the memory interface. The memory system can compare the first output signal and the second output signal to generate a test result.

Description

Technology Field

[0001] The present disclosure generally relates to testing of a memory system, and in particular to a memory system and a method for testing a memory system that can efficiently test the memory system without affecting normal user mode operations of the memory system. Background Technology

[0002] A memory system can consist of various chips, such as system-on-chip (SoC) devices and memory devices, interconnected via embedded pins. Intertransmission and reception between memory devices and SoC devices are becoming increasingly complex due to diverse product specifications and different customer requirements. Monitoring the interfaces of embedded pins under various conditions—such as high-speed operations, high / low voltage operations, different interface power levels, small pin cap requirements, numerous inputs / outputs (IOs), and strict DC or AC parameters—is challenging. To test the interfaces of embedded pins in a memory system, a design-for-testing (DfT) circuit can be directly connected to the memory interface of the memory device. However, DfT circuits can negatively impact the operation of the memory system, particularly its high-speed and / or low-power operations. The connection between the memory device interface and the DfT circuit can result in additional loading affecting the pin capacitance (Pin-Cap), negative impact on the memory device interface operation, potential leakage paths between the memory device and the SoC device, and an increase in chip size.

[0003] Alternatively, package ballouts or direct probing methods can be utilized to test pin interfaces in memory systems. However, package ballouts can impair the general user mode of a memory device due to additional loading, and test results may be distorted if the memory system is tested directly using probing methods. The designs of DfT circuits and package ballouts, or direct probing methods, can affect chip performance and cost during mass production of products.

[0004] A new technique for testing memory systems is needed that can effectively test the memory system and the interfaces of the pins embedded in the memory system. means of solving the problem

[0005] In some embodiments of the present disclosure, the memory system includes an electronic device, a memory device, and a test device. The memory device includes an input pad that receives an input signal and an output pad that outputs a first output signal in a first test mode and outputs a second output signal in a second test mode. The memory device further includes a memory interface having a transceiver and a mode selecting circuit. The transceiver communicates with the electronic device, and the mode selecting circuit selects a first test mode or a second test mode. Loading from the transceiver and the electronic device of the memory interface is included in the first test mode, and loading from the transceiver and the electronic device of the memory interface is excluded in the second test mode. The test device can generate a test result by comparing the first output signal and the second output signal.

[0006] In some embodiments of the present disclosure, the memory system includes an electronic device and a memory device. The memory device includes an input pad that receives an input signal and an output pad that outputs a first output signal in a first test mode and outputs a second output signal in a second test mode. The memory device further includes a memory interface having a transceiver and a mode selection circuit. The transceiver communicates with the electronic device, and the mode selection circuit selects a first test mode or a second test mode. Loading from the transceiver and the electronic device of the memory interface is included in the first test mode, and loading from the transceiver and the electronic device of the memory interface is excluded in the second test mode. The memory device may further include a signal comparator that compares the first output signal and the second output signal to generate a test result.

[0007] In some embodiments of the present disclosure, a method for testing a memory system including a memory device and an electronic device is introduced. The method comprises the steps of: supplying an input signal to an input pad of the memory device; controlling a mode selection circuit of the memory device to operate the memory device in a first test mode to generate a first output signal; controlling a mode selection circuit of the memory device to operate the memory device in a second test mode to generate a second output signal; and comparing the first output signal and the second output signal to generate a test result. Loading from a transceiver of the memory interface and an electronic device is included in the first test mode, and loading from a transceiver of the memory interface and an electronic device is excluded in the second test mode.

[0008] According to the above embodiments, a method for testing a memory system including an SoC device and a memory device connected via embedded pins is introduced. The test method is performed using a mode selection circuit and a transmitter and receiver built into the memory device. The memory system can be configured sequentially in a first test mode and a second test mode to generate a first output signal and a second output signal. The first output signal generated in the first test mode can be compared with the second output signal in the second test mode to generate a test result. In this way, the test method can determine if there is any degradation after passing through the transmitters, receivers, and pin interfaces between the SoC device and the memory device. Since the transmitter and receiver built into the memory interface of the memory device are essentially included in the memory device, no additional loading caused by DfT circuits, boolouts, or direct probing occurs during the testing of the memory system. Consequently, the test results become more accurate, and power consumption and test costs are reduced. Furthermore, because no additional loading occurs, testing the memory system does not affect the normal operating mode of the memory system. The test result output from the test technique can also be used to adjust the operations of other circuits and / or to set the parameters of other circuits in the memory system. Brief explanation of the drawing

[0009] FIG. 1 is a schematic diagram of a memory system including an external device, a memory device, and a test device according to some embodiments. FIG. 2a illustrates a test path of a memory system in a first test mode according to some embodiments. FIG. 2b illustrates a test path of a memory system in a second test mode according to some embodiments. FIG. 3 is a schematic diagram of a memory system including an external device and a memory device according to some embodiments. FIG. 4a illustrates a test path of a memory system in a first test mode according to some embodiments. FIG. 4b illustrates a test path of a memory system in a second test mode according to some embodiments. FIG. 5 is a flowchart of a method for testing a memory system according to some embodiments. Specific details for implementing the invention

[0010] With detailed reference to preferred embodiments of the present invention, examples are illustrated in the accompanying drawings. Where possible, the same reference numerals are used to refer to identical or similar parts in the drawings and description.

[0011] FIG. 1 illustrates a schematic diagram of a memory system (100) comprising a system-on-chip (SoC) device (110), a memory device (120), and a test device (130). The SoC device (110) may be referred to as an electronic device, and the test device (130) may be referred to as automated testing equipment (ATE). Each of the SoC device (110) and the memory device (120) may be packaged as a chip, and the SoC device (110) may be connected to the memory device (120) via microbumps (uBump) (140) or embedded pins. In some embodiments, the SoC device (110) and the memory device (120) may be stacked together via microbumps (140). In some embodiments, the memory device (120) may include a plurality of core dies stacked together using through-silicon via (TSV) technology.

[0012] The SoC device (110) may include a transmitter (111) and a receiver (113), and the SoC device (110) is connected to a memory device (120) via a microbump (140). The transmitter (111) of the SoC device (110) may transmit signals or data to the memory device (120), and the receiver (113) of the SoC device (110) may receive signals or data from the memory device (120). A test voltage (Vtest) may be supplied to each of the transmitter (111) and receiver (113) of the SoC device (110) during a test operation of the memory system (100). During normal operation of the SoC device (110), a voltage equal to or different from the test voltage (Vtest) may be supplied to the transmitter (111) and receiver (113) of the SoC device (110). It should be understood that the present disclosure is not intended to limit the circuit structures of the transmitter (111) and receiver (113) of the SoC device (110).

[0013] The memory device (120) may include an input pad (PAD1), an output pad (PAD2), a memory interface (121), and a memory test interface (123). The input pad (PAD1) is connected to the test device (130) to receive an input signal (IN) from the test device (130), and the output pad (PAD2) is connected to the test device (130) to output an output signal (OUT) to the test device (130). The input signal (IN) and the output signal (OUT) may be clock signals.

[0014] The memory interface (121) may include a transceiver and a mode selection circuit. The transceiver may include a transmitter (1211) and a receiver (1213), and the mode selection circuit may include a first switch (SW1) and a second switch (SW2). The transceiver is configured to transmit or receive data or signals to or from the SoC device (110) through a connection node (N3) and a microbump (140). For example, the transmitter (1211) may transmit data and signals to the SoC device (110) through the connection node (N3) and the microbump (140), and the receiver (1213) may receive data and signals from the SoC device (110) through the connection node (N3) and the microbump (140). The transmitter (1211) and the receiver (1213) may receive a test voltage (Vtest) during the test mode of the memory device (120). During the normal operation mode of the memory device (120), a supply voltage that may be the same as or different from the test voltage (Vtest) may be supplied to the transmitter (1211) and receiver (1213) of the memory interface (121).

[0015] The first switch (SW1) of the mode selection circuit is connected between the connection node (N1) and the transmitter (1211) of the memory interface (121), and is configured to control the electrical connection between the connection node (N1) and the transmitter (1211). The second switch (SW2) of the mode selection circuit is connected between the connection node (N1) and the second connection node (N2) of the memory interface (121), and is configured to control the electrical connection between the connection node (N1) and the connection node (N2). The connection node (N2) is connected to the receiver (1213) of the memory interface (121).

[0016] The first switch (SW1) and the second switch (SW2) are configured to set the test mode of the memory system (100). For example, when the first switch (SW1) is turned on and the second switch (SW2) is turned off, the memory system (100) operates in the first test mode, and when the first switch (SW1) is turned off and the second switch (SW2) is turned on, the memory system (100) operates in the second test mode. In some embodiments, the first switch (SW1) and the second switch (SW2) may be controlled by control signals (not shown) that may be provided from the memory device (120) or the test device (130).

[0017] The memory test interface (123) includes a receiving circuit (1231) and a transmitting circuit (1233) connected between the memory interface (121) and the test device (130). The receiving circuit (1231) of the memory test interface (123) can receive data or signals from the test device (130) through an input pad (PAD1) and output data or signals to a connection node (N1) of the memory interface (121). The transmitting circuit (1233) can receive data or signals from the memory interface (121) through a connection node (N2) and output data or signals to the test device (130) through an output pad (PAD2).

[0018] FIG. 2a illustrates a test path (PATH1) of a memory system (100) in a first test mode according to some embodiments. Identical elements of the memory system in FIG. 2a and FIG. 1 are illustrated with the same reference numbers. The memory system (100) operates in a first test mode when a first switch (SW1) is turned on and a second switch (SW2) is turned off. The first switch (SW1) is turned on to electrically connect a connection node (N1) to a transmitter (1211) of a memory interface (121), and the second switch (SW2) is turned off to electrically disconnect the connection node (N1) and the connection node (N2). In the first test mode, a test path (PATH1) is formed including an input pad (PAD1), a receiving circuit (1231), a connection node (N1), a first switch (SW1), a transmitter (1211), a connection node (N3), a receiver (1213), a connection node (N2), a transmitting circuit (1233), and an output pad (PAD2). The test path (PATH1) may represent loadings of the receiving circuit (1231) and the transmitting circuit (1233) of the test memory interface (123), loadings of the transmitter (1211) and the receiver (1213) of the memory interface (121), and loadings of the SoC device (110). When an input signal (IN) is supplied to the input pad (PAD1) of the memory device (120) by the test device (130), the input signal (IN) flows through the test path (PATH1) and generates a first output signal (OUT1) at the output pad (PAD2) of the memory device (120). The first output signal (OUT1) is provided to the test device (130).

[0019] FIG. 2b illustrates a test path (PATH2) of a memory system (100) in a second test mode according to some embodiments. Identical elements of the memory system in FIG. 2b and FIG. 1 are illustrated with the same reference numbers. The memory system (100) operates in a second test mode when a first switch (SW1) is turned off and a second switch (SW2) is turned on. The first switch (SW1) is turned off to electrically disconnect the connection node (N1) from the transmitter (1211) of the memory interface (121), and the second switch (SW2) is turned on to electrically connect the connection node (N1) to the connection node (N2). In the second test mode, a test path (PATH2) is formed including an input pad (PAD1), a receiving circuit (1231), a connection node (N1), a connection node (N2), a transmitting circuit (1233), and an output pad (PAD2). The test path (PATH2) may represent the loadings of the receiving circuit (1231) and the transmitting circuit (1233) of the test memory interface (123). The test path (PATH2) does not represent the loadings of the transmitter (1211) and receiver (1213) of the memory interface (121), or the loadings of the SoC device (110). When an input signal (IN) is supplied to the input pad (PAD1) of the memory device (120) by the test device (130), the input signal (IN) flows through the test path (PATH2) and generates a second output signal (OUT2) at the output pad (PAD2) of the memory device (120). The second output signal (OUT2) is provided to the test device (130).

[0020] In some embodiments, the memory system (100) is configured to operate sequentially in a first test mode and a second operation mode to generate a first output signal (OUT1) and a second output signal (OUT2). For example, a mode selection circuit turns on a first switch (SW1) and turns off a second switch (SW2) to operate the memory system (100) in the first test mode. Next, the mode selection circuit may turn off the first switch (SW1) and turn on the second switch (SW2) to operate the memory system (100) in the second test mode. In some embodiments, the input signal (IN), the first output signal (OUT1), and the second output signal (OUT2) are clock signals.

[0021] The test device (130) is configured to receive a first output signal (OUT1) and a second output signal (OUT2), and to generate a test result (RE_TEST) by comparing the first output signal (OUT1) and the second output signal (OUT2). In some embodiments, the test device (130) may generate a test result (RE_TEST) by comparing the data valid window (DVW) of the first output signal (OUT1) and the data valid window of the second output signal (OUT2). For example, the test device (130) may measure the data valid windows of the first output signal (OUT1) and the second output signal (OUT2), and generate a test result (RE_TEST) by comparing the data valid window of the first output signal (OUT1) and the data valid window of the second output signal (OUT2). Loadings of the SoC device, loadings of the transmitter and receiver of the memory interface, and loadings of the receiving circuit and transmitting circuit of the memory test interface may be included and appear in the first output signal (OUT1). On the other hand, the loadings of the SoC device and the loadings of the transmitter and receiver of the memory interface may be excluded from and not appear in the second output signal OUT2. The test device (130) can determine whether there is any performance degradation in the transmitters, receivers, and interfaces between the SoC circuit and the memory device by comparing the first output signal (OUT1) and the second output signal (OUT2). In this way, the performance of the memory system can be monitored using the built-in transmitter and receiver of the memory interface (i.e., memory interface (121)) of the memory device (i.e., memory device (120)). Additionally, testing of the memory system can be performed without additional loading by DfT circuit designs and / or ball-out packages and probing methods.

[0022] Additionally, the test results may also be used to set parameters or operating conditions of other circuits and / or devices of the memory system (100). For example, the test results may be used to adjust the driver strength of the transmitter (1211) and / or receiver (1213) of the memory device (120). The test results may also be used to adjust the internal falling and rising timing of the receiver (1213) of the memory device (120).

[0023] FIG. 3 is a schematic diagram of a memory system (300) including an SoC device (110) and a memory device (320) according to some embodiments. Identical elements of the memory system (300) shown in FIG. 3 and the memory system (100) shown in FIG. 1 are illustrated by the same reference numerals. The difference between the memory system (300) of FIG. 3 and the memory system (100) of FIG. 1 is that the memory system (300) includes a signal generator (325) and a signal comparator (327). Another difference between the memory system (300) of FIG. 3 and the memory system (100) of FIG. 1 is that the memory system (300) does not include a memory test interface (123), unlike the memory system (100).

[0024] In FIG. 3, the signal generator (325) is connected to the input pad (PAD1) and configured to generate an input signal (IN) and provide it to the input pad (PAD1). That is, the input signal (IN) is not provided from an external test device, but is generated by the internal signal generator (325) of the memory device (320). The signal generator (325) may be a clock generator configured to generate a clock signal that acts as an input signal. The signal comparator (327) is connected to the output pad (PAD2) and configured to receive output signals (OUT) from the output pad (PAD2) of the memory device (320). The signal comparator (327) can generate a test result (RE_TEST) by comparing the output signals (OUT) obtained in different test modes. The signal comparator (327) can output the test result (RE_TEST) to other circuits of the system (300). For example, the signal comparator (327) can provide results to the transmitter of the memory device (320) (i.e., transmitter (1211)) to adjust the operations or parameters of the transmitter.

[0025] FIG. 4a illustrates a test path (PATH3) of a memory system (300) in a first test mode according to some embodiments. Identical elements of the memory system in FIG. 4a and FIG. 3 are illustrated with identical reference numbers. The memory system (300) operates in a first test mode when the first switch (SW1) is turned on and the second switch (SW2) is turned off. In the first test mode, a test path (PATH3) is formed including an input pad (PAD1), a connection node (N1), a first switch (SW1), a transmitter (1211), a connection node (N3), a receiver (1213), a connection node (N2), and an output pad (PAD2). The test path (PATH3) may represent loadings of the transmitter (1211) and receiver (1213) of the memory interface (121) and loadings of the SoC device (110). When an input signal (IN) is supplied to the input pad (PAD1) of the memory device (320) by the signal generator (325), the input signal (IN) flows through the test path (PATH3) and generates a third output signal (OUT3) at the output pad (PAD2) of the memory device (320). The third output signal (OUT3) is provided to the signal comparator (327).

[0026] FIG. 4b illustrates a test path (PATH4) of a memory system (300) in a second test mode according to some embodiments. Identical elements of the memory system in FIG. 4b and FIG. 3 are illustrated with identical reference numbers. The memory system (300) operates in a second test mode when the first switch (SW1) is turned off and the second switch (SW2) is turned on. In the second test mode, a test path (PATH4) is formed including an input pad (PAD1), a connection node (N1), a connection node (N2), and an output pad (PAD2). The test path (PATH4) may represent loadings of an electrical path from the input pad (PAD1) to the output pad (PAD2). The test path (PATH4) may not represent loadings of the transmitter (1211) and receiver (1213) of the memory interface (121) and loadings of the SoC device (110). When an input signal (IN) is supplied to the input pad (PAD1) of the memory device (320) by the signal generator (325), the input signal (IN) flows through the test path (PATH4) and generates a fourth output signal (OUT4) at the output pad (PAD2) of the memory device (320). The fourth output signal (OUT4) is provided to the signal comparator (327).

[0027] In some embodiments, the memory system (300) is configured to operate sequentially in a first test mode and a second operation mode to generate a third output signal (OUT3) and a fourth output signal (OUT4). For example, the mode selection circuit turns on the first switch (SW1) and turns off the second switch (SW2) to operate the memory system (300) in the first test mode. Next, the mode selection circuit may turn off the first switch (SW1) and turn on the second switch (SW2) to operate the memory system (300) in the second test mode. In some embodiments, the input signal (IN), the third output signal (OUT3), and the fourth output signal (OUT4) are clock signals.

[0028] The signal comparator (327) is configured to receive the third output signal (OUT3) and the fourth output signal (OUT4), and to generate a test result (RE_TEST) by comparing the third output signal (OUT3) and the fourth output signal (OUT4). In some embodiments, the signal comparator (327) may generate a test result (RE_TEST) by comparing the data valid window of the third output signal (OUT3) and the data valid window of the fourth output signal (OUT4). For example, the signal comparator (327) may measure the data valid windows of the third output signal (OUT3) and the fourth output signal (OUT4), and generate a test result by comparing the data valid window of the third output signal (OUT3) and the data valid window of the fourth output signal (OUT4). Loads of the SoC device and loads of the transmitter and receiver of the memory interface may be included and appear in the third output signal (OUT3). On the other hand, loads of the SoC device and loads of the transmitter and receiver of the memory interface may be excluded and not appear in the fourth output signal OUT4. The signal comparator (327) can determine whether there is any performance degradation in the transmitters, receivers, and interfaces between the SoC circuit and the memory device by comparing the third output signal (OUT3) and the fourth output signal (OUT4). In this way, the performance of the memory system can be monitored using the built-in transmitters and receivers of the memory interface (i.e., memory interface (121)) of the memory device (i.e., memory device (320)). Additionally, testing of the memory system can be performed without additional loading by DfT circuit designs and / or ball-out packages and probing methods.

[0029] FIG. 5 is a flowchart of a method for testing a memory device according to some embodiments. In block (S501), an input signal is supplied to an input pad of the memory device. In block (S502), a mode selection circuit of the memory device is controlled to operate the memory device in a first test mode. In the first test mode, a first output signal is generated and output to an output pad of the memory device. In block (503), a mode selection circuit of the memory device is controlled to operate the memory device in a second test mode. In the second test mode, a second output signal is generated and output to an output pad of the memory device. In block (504), the first output signal is compared with the second output signal to generate a test result. The first test mode includes loading from the transceiver of the memory device and an external device (e.g., an SoC device), and the second test mode excludes loading from the transceiver of the memory device and an external device.

[0030] According to the above embodiments, a mode selection circuit and a transmitter and receiver embedded in the memory device may be utilized to test the memory system. The memory system may be sequentially set to a first test mode and a second test mode to generate a first output signal and a second output signal. The first output signal generated in the first test mode may be compared with the second output signal generated in the second test mode to generate a test result. Since the transmitter and receiver embedded in the memory interface of the memory device are essentially included in the memory device, no additional loading caused by DfT circuits, boolouts, or direct probing occurs during the testing of the memory system. Consequently, power consumption and cost for testing are reduced, and testing of the memory system does not affect the memory system's normal operating mode (e.g., general user mode operation). The test results may also be used to adjust the operation of other circuits and / or to set parameters of other circuits of the memory system.

[0031] Accordingly, the present disclosure provides an eco-friendly technology by reducing the power consumption of memory systems. Furthermore, according to the present disclosure, consumer demand for the miniaturization of memory systems can be more easily realized. Consequently, production costs and energy consumption for manufacturing a single IC are reduced, and energy consumption for subsequent packaging is also reduced, thereby reducing carbon emissions during the production of memory systems.

[0032] The memory device of the memory system may be DRAM, non-volatile memory, or a combination thereof. Furthermore, the present invention is particularly advantageous for 3D IC applications such as high bandwidth memory (HBM) and other types of stacked memory products. By integrating embedded transmitters and receivers for testing without the additional loading of DfT circuits or probing methods, the present invention significantly reduces power consumption and production costs. As a result, more efficient and compact memory systems can be realized, which is crucial for meeting the increasing demand for high-performance and energy-efficient 3D IC solutions.

[0033] It will be apparent to those skilled in the art that various modifications and changes may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. With the foregoing in mind, the present disclosure is intended to include modifications and variations that fall within the scope of the following claims and their equivalents.

Claims

Claim 1 A memory system comprising: an electronic device including a processor; a memory device; and a test device connected to the memory device, wherein the memory device comprises: an input pad for receiving an input signal; an output pad for outputting a first output signal in a first test mode and outputting a second output signal in a second test mode; and a memory interface connected to the electronic device, wherein the memory interface comprises: a transceiver communicating with the electronic device; and a mode selection circuit for selecting the first test mode or the second test mode, wherein loading from the transceiver of the memory interface and the electronic device is included in the first test mode, and the loading from the transceiver of the memory interface and the electronic device is excluded in the second test mode, and wherein the test device generates a test result by comparing the first output signal and the second output signal. Claim 2 In claim 1, the memory system comprises: a transmitter that transmits signals to the electronic device; and a receiver that receives signals from the electronic device. Claim 3 In paragraph 2, the mode selection circuit comprises: a first switch connected between a first connection node and the transmitter of the memory interface; and a second switch connected between the first connection node and a second connection node, wherein the second connection node is connected to the receiver of the memory interface, a memory system. Claim 4 A memory system according to paragraph 3, wherein in the first test mode, the first switch is turned on and the second switch is turned off, and in the second test mode, the first switch is turned off and the second switch is turned on. Claim 5 A memory system according to paragraph 3, further comprising a memory test interface connecting the memory interface and the test device, wherein the memory test interface comprises: a receiving circuit connected between the input pad of the memory device and the first connection node; and a transmitting circuit connected between the second connection node and the output pad of the memory device. Claim 6 In paragraph 5, the input signal, the first output signal, and the second output signal are clock signals, in a memory system. Claim 7 In claim 1, the test device is configured to generate the test result by comparing the data valid window of the first output signal with the data valid window of the second output signal, in a memory system. Claim 8 In claim 1, the electronic device is a system on chip (SoC) device, and the test device is an automated test equipment (ATE), in a memory system. Claim 9 A memory system comprising: an electronic device including a processor; and a memory device, wherein the memory device comprises: an input pad for receiving an input signal; an output pad for outputting a first output signal in a first test mode and outputting a second output signal in a second test mode; a memory interface connected to the electronic device; and a signal comparator, wherein the memory interface comprises: a transceiver communicating with the electronic device; and a mode selection circuit for selecting the first test mode or the second test mode, wherein loading from the transceiver and the electronic device of the memory interface is included in the first test mode, and loading from the transceiver and the electronic device of the memory interface is excluded in the second test mode, and the signal comparator generates a test result by comparing the first output signal and the second output signal. Claim 10 In claim 9, the memory system comprises: a transmitter that transmits signals to the electronic device; and a receiver that receives signals from the electronic device. Claim 11 In paragraph 10, the mode selection circuit comprises: a first switch connected between a first connection node and the transmitter of the memory interface; and a second switch connected between the first connection node and the second connection node, wherein the second connection node is connected to the receiver of the memory interface, a memory system. Claim 12 A memory system according to claim 11, wherein in the first test mode, the first switch is turned on and the second switch is turned off, and in the second test mode, the first switch is turned off and the second switch is turned on. Claim 13 In claim 11, the memory device further comprises a signal generator connected to the input pad of the memory device, generating the input signal, and supplying the input signal to the input pad of the memory device. Claim 14 In claim 9, the memory system is configured such that the signal comparator generates the test result by comparing the data valid window of the first output signal with the data valid window of the second output signal. Claim 15 In claim 9, the input signal, the first output signal and the second output signal are clock signals, and the electronic device is a system on chip (SoC) device, a memory system. Claim 16 A method for testing a memory system, wherein the memory system comprises: an electronic device including a processor; and a memory device connected to the electronic device through a memory interface; the method comprises the steps of: operating the memory device in a first test mode by means of a mode selection circuit of the memory device, such that an input signal passes through a transceiver of the memory interface to generate a first output signal; operating the memory device in a second test mode by means of a mode selection circuit of the memory device, such that the input signal bypasses the transceiver of the memory interface to generate a second output signal; and comparing the first output signal and the second output signal to generate a test result, wherein the first test mode includes loading from the electronic device and the transceiver of the memory interface, and the second test mode excludes the loading. Claim 17 In claim 16, the step of controlling the mode selection circuit comprises: turning on the first switch of the mode selection circuit and turning off the second switch in the first test mode; and turning off the first switch of the mode selection circuit and turning on the second switch in the second test mode. Claim 18 In claim 16, the memory system comprises a test device connected to the memory device, the memory device comprises an input pad receiving the input signal, and the method further comprises the step of supplying the input signal from the test device to the input pad of the memory device. Claim 19 In claim 16, the memory device comprises an input pad receiving the input signal and a signal generator connected to the input pad, and the method further comprises the step of the signal generator of the memory device generating the input signal; and the step of supplying the input signal generated by the signal generator to the input pad of the memory device. Claim 20 In claim 16, the step of generating a test result by comparing the first output signal and the second output signal comprises the step of generating the test result by comparing the data valid window of the first output signal with the data valid window of the second output signal.

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