Display apparatus

Abstract

A display device according to an embodiment of the present specification comprises a display panel having a plurality of subpixels to display an image, a data driver supplying image data to a plurality of subpixels, a gate driver supplying a gate signal to a plurality of subpixels, a controller converting the driving frequency of the data driver and the gate driver in a high-speed driving mode, and a gamma voltage generator generating a gamma voltage for each driving frequency, wherein the controller generates a horizontal synchronization signal based on the driving frequency in the high-speed driving mode. Accordingly, by applying the same operating period for each driving frequency, the image quality level for each driving frequency can be matched equally even if a driving frequency conversion occurs.

Description

Technology Field

[0001] This specification relates to a display device, and more specifically, to a display device that prevents distortion of brightness and color coordinates during driving frequency conversion. Background Technology

[0003] Video display devices, which display various information on a screen, are a core technology of the information and communication era and are evolving in a direction that is thinner, lighter, more portable, and higher in performance. Accordingly, display devices capable of being manufactured in a lightweight and thin form are gaining attention. As a self-emissive device, this display is being researched as a next-generation display because it is advantageous in terms of power consumption due to low-voltage operation, as well as offering high response speed, high luminous efficiency, excellent viewing angle, and contrast ratio. This display device implements images through multiple subpixels arranged in a matrix form. Each of the multiple subpixels includes a light-emitting element and multiple transistors that independently drive the light-emitting element.

[0004] Specific examples of such flat panel display devices include Liquid Crystal Display Apparatus (LCD), Quantum Dot Display Apparatus (QD), Field Emission Display Apparatus (FED), and Organic Light Emitting Diode (OLED). Among these, the Organic Light Emitting Diode, which does not require a separate light source and is gaining popularity as a means for compact devices and vivid color display, has the advantage of fast response speed, high contrast ratio, luminous efficiency, brightness, and viewing angle by using self-emitting Organic Light Emitting Diodes (OLEDs).

[0005] Depending on the image, such as a still image or a video, the driving frequency can be automatically switched from the Standard Frame Rate (SFR) to the High Frame Rate (HFR) for driving.

[0006] When driven at a general standard driving frequency, the periods of the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) may vary depending on the change in driving frequency. For example, the periods of the vertical synchronization signal and horizontal synchronization signal at a high driving frequency operating at 90Hz may be shorter than the periods of the vertical synchronization signal and horizontal synchronization signal at a standard driving frequency operating at 60Hz.

[0007] As such, as the vertical synchronization signal and the horizontal synchronization signal differ, a difference in time occurs in the horizontal period (1H; Horizontal time), and the operating period of the subpixel may also differ. Therefore, even if the same gamma is applied to the same RGB image data, the luminance and color coordinates may be distorted when the driving frequency is changed. In other words, to prevent defects caused by luminance differences during frequency driving, the standard driving frequency and the high-speed driving frequency must each perform separate optical compensation for luminance and color coordinates to compensate for the luminance difference; however, if optical compensation is performed for every driving frequency, there is a problem of the manufacturing process time becoming longer. The problem to be solved

[0009] The present specification relates to a display device that, in order to solve the aforementioned problem, generates a horizontal synchronization signal of the display device in accordance with the driving frequency of a high-speed driving mode, and generates an intermediate frequency and an interpolated gamma voltage when the driving frequency changes, thereby driving the device so that the luminance and color coordinates are not distorted.

[0010] The purposes of this specification are not limited to those mentioned above, and other purposes and advantages of this specification not mentioned may be understood from the following description and will be more clearly understood by the embodiments of this specification. Furthermore, it will be readily apparent that the purposes and advantages of this specification can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0012] A display device according to an embodiment of the present specification includes a display panel having a plurality of subpixels to display an image, a data driving unit that supplies image data to a plurality of subpixels, a gate driving unit that supplies a gate signal to a plurality of subpixels, a controller that converts the driving frequency of the data driving unit and the gate driving unit in a high-speed driving mode, and a gamma voltage generating unit that generates a gamma voltage for each driving frequency, wherein the controller can generate a horizontal synchronization signal based on the driving frequency in the high-speed driving mode.

[0013] Additionally, the display device according to the embodiment of the present specification includes a frequency converter that generates an intermediate frequency when converting the driving frequency from a first driving frequency to a second driving frequency, and a gamma voltage generator that stores gamma voltages for each driving frequency, wherein the gamma voltages of the first driving frequency and the second driving frequency are stored as pre-compensated values, and the gamma voltage of the intermediate frequency can be generated by interpolating the gamma voltages of the first driving frequency and the second driving frequency.

[0014] In addition to the technical problems of this specification mentioned above, other features and advantages of this specification are described below, or will be clearly understood by those skilled in the art to which this specification belongs from such description and explanation. Effects of the invention

[0016] According to the embodiments of this specification, by applying the same operating period for each driving frequency, the image quality level for each driving frequency can be matched equally even if driving frequency conversion occurs.

[0017] In addition, since optical compensation is performed only for certain driving frequencies, the time required for the manufacturing process can be reduced, thereby improving efficiency.

[0018] The effects according to the present invention are not limited to those exemplified above, and a wider variety of effects are included within the present invention. Brief explanation of the drawing

[0020] FIG. 1 is a system configuration diagram of a display device according to embodiments of the present specification. FIG. 2 is a drawing of a pixel circuit of a subpixel in a display device according to an embodiment of the present specification. FIG. 3 is a waveform diagram by driving frequency in a display device according to an embodiment of the present specification. FIG. 4 is a diagram of the driving frequency conversion operation in a display device according to an embodiment of the present specification. FIG. 5 is a block diagram of the operation of each function block in a display device according to an embodiment of the present specification. FIG. 6 is a diagram showing the operation of a gamma voltage interpolation unit in a display device according to an embodiment of the present specification. Specific details for implementing the invention

[0021] The advantages and features of this specification and the methods for achieving them will become clear by referring to the examples described below in detail together with the accompanying drawings. However, this specification is not limited to the examples disclosed below but may be implemented in various different forms. The examples of this specification are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention to which the invention of this specification belongs, and the invention of this specification is defined only by the scope of the claims.

[0022] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating examples of this specification are exemplary and are not limited to the matters depicted in this specification. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the examples of this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted.

[0023] Where terms such as "includes," "has," and "consists of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0024] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0025] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using terms such as "on," "on the upper," "on the lower," or "next to," one or more other parts may be located between the two parts unless "immediately" or "directly" is used.

[0026] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using "after," "followed by," "next," "before," etc., it may include cases where the sequence is not continuous unless "immediately" or "directly" is used.

[0027] The terms first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0028] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0029] The features of each of the various examples in this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each example may be implemented independently of one another or may be implemented together in an associated relationship.

[0030] Hereinafter, an example of a display device according to an embodiment of the present specification will be described in detail with reference to the attached drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, the scale of the components shown in the attached drawings is different from the actual scale for the convenience of explanation, and is therefore not limited to the scale shown in the drawings.

[0031] FIG. 1 is a system configuration diagram of a display device according to embodiments of the present specification.

[0032] Referring to FIG. 1, a display device (100) according to embodiments of the present specification includes a display panel (110) having a plurality of data lines (DL1~DLm) and a plurality of gate lines (GL1~GLn) arranged thereon and a plurality of subpixels (SP) arranged thereon, a data driving unit (120) connected to the top or bottom of the display panel (110) and driving a plurality of data lines (DL1~DLm), a gate driving unit (130) driving a plurality of gate lines (GL1~GLn), a controller (140) controlling the data driving unit (120) and the gate driving unit (130), a frequency converter (150) generating a driving frequency conversion signal (Sf) using a timing signal (TS) received by the controller (140), and a gamma voltage generating unit (160) supplying a gamma voltage to the data driving unit (120) according to the driving frequency conversion signal (Sf).

[0033] Referring to FIG. 1, a plurality of subpixels (SP) are arranged in a matrix type on the display panel (110).

[0034] Accordingly, there are multiple subpixel lines in the display panel (110), and the subpixel lines may be subpixel rows or subpixel columns. Below, subpixel rows are referred to as subpixel lines.

[0035] The data driving unit (120) drives a plurality of data lines (DL1 to DLm) by supplying data voltage to a plurality of data lines (DL1 to DLm). Here, the data driving unit (120) is also referred to as a source driving unit. The gate driving unit (130) drives a plurality of gate lines (GL1 to GLn) sequentially by supplying scan signals to a plurality of gate lines (GL1 to GLn). Here, the gate driving unit (130) is also referred to as a scan driving unit.

[0036] The controller (140) supplies various control signals to the data driving unit (120) and the gate driving unit (130) to control the data driving unit (120) and the gate driving unit (130).

[0037] The controller (140) starts scanning according to the timing implemented in each frame, converts externally input RGB image data (RGB Data) to match the data signal format used by the data driving unit (120), outputs the converted RGBG image data (RGBG Data), and controls data driving at an appropriate time in accordance with the scan.

[0038] The gate driving unit (130) sequentially drives the multiple gate lines (GL1~GLn) by supplying scan signals of an on voltage or off voltage to the multiple gate lines (GL1~GLn) according to the control of the controller (140).

[0039] Depending on the driving method or panel design method, the gate driver (130) may be located on only one side of the display panel (110) as in FIG. 1, or in some cases, on both sides. Additionally, the gate driver (130) may include one or more gate driver integrated circuits (GDIC).

[0040] The data driving unit (120) drives the multiple data lines (DL1~DLm) by converting the RGB image data (RGB Data) received from the controller (140) into an analog data voltage and supplying it to the multiple data lines (DL1~DLm) when a specific gate line is opened.

[0041] The data driver (120) can drive a plurality of data lines by including at least one source driver integrated circuit (SDIC).

[0042] Each of the aforementioned gate driver integrated circuits or source driver integrated circuits may be connected to a bonding pad of a display panel (110) by a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be placed directly on the display panel (110), or, in some cases, may be integrated and placed on the display panel (110).

[0043] Each source driver integrated circuit may include a logic unit including a shift register, a latch circuit, etc., a digital analog converter (DAC), an output buffer, etc., and, in some cases, may further include a sensing control unit for sensing the characteristics of a subpixel to compensate for the characteristics of the subpixel (e.g., threshold voltage (Vth) of a transistor, threshold voltage (Vth) of an organic light-emitting diode, brightness of the subpixel, etc.).

[0044] Additionally, each source driver integrated circuit can be implemented using a Chip On Film (COF) method. In this case, one end of each source driver integrated circuit is bonded to at least one source printed circuit board, and the other end is bonded to a display panel (110).

[0045] Meanwhile, the controller (140) receives various timing signals (TS) from an external source (e.g., a host system), including RGB video data (RGB Data), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, and a clock signal (CLK).

[0046] In addition to converting RGB image data (RGB Data) input from the outside to match the data signal format used by the data driver (120) and outputting the converted RGBG image data (RGBG Data), the controller (140) receives timing signals (TS), such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock (DCLK), to control the data driver (120) and the gate driver (130), and generates various control signals and outputs them to the data driver (120) and the gate driver (130).

[0047] For example, the controller (140) outputs various gate control signals (GCS: Gate Control Signal), including a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC: Gate Shift Clock), and a gate output enable signal (GOE: Gate Output Enable), in order to control the gate driver (130).

[0048] Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver (130). The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits and controls the shift timing of the scan signal (gate pulse). The gate output enable signal (GOE) specifies the timing information of one or more gate driver integrated circuits.

[0049] Additionally, the controller (140) outputs various data control signals (DCS), including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE), in order to control the data driving unit (120).

[0050] Here, the source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver (120). The source sampling clock (SSC) is a clock signal that controls the data sampling timing in each source driver integrated circuit. The source output enable signal (SOE) controls the output timing of the data driver (120).

[0051] The controller (140) may be placed on a control printed circuit board connected to a source printed circuit board, to which at least one source driving integrated circuit is bonded, via a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

[0052] Additionally, the controller (140) may be formed separately outside the substrate as described above, or may be formed integrated with the data driver (120). In this case, the data driver (120) may be implemented as a source driver integrated circuit using a Chip On Film (COF) method, or may be implemented on the substrate using a Chip On Glass (COG) method.

[0054] The frequency converter (150) can control the operation signals applied to the gate driver (130) according to the driving frequency conversion signal (Sf) received from the controller (140). The frequency converter (150) may be placed within the controller (140). However, it is not limited thereto and may be configured separately depending on the design.

[0055] The gamma voltage generation unit (160) can supply a gamma voltage corresponding to the driving frequency to the data driving unit (120) according to the driving frequency conversion signal (Sf). For convenience of explanation, the gamma voltage generation unit (160) is illustrated as being configured separately from the data driving unit (120), but is not limited thereto and may be configured inside the data driving unit (120) depending on the design.

[0057] The display device (100) according to the embodiments of the present specification is an organic light-emitting display device, wherein each subpixel (SP) is composed of an organic light-emitting diode (OLED) and circuit elements such as a transistor (TFT) for driving it. The type and number of circuit elements constituting each subpixel (SP) can be determined in various ways depending on the provided functions and design methods.

[0058] FIG. 2 is a drawing of a pixel circuit of a subpixel in a display device according to an embodiment of the present specification.

[0059] Referring to FIG. 2, each subpixel (SP) placed in the n-th (n is a natural number)th subpixel row may include a light-emitting element (EL), a driving transistor (D-TFT), a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor, and a capacitor (Cstg). The first to sixth transistors may be switching transistors.

[0060] A light-emitting device (EL) emits light by a driving current supplied from a driving transistor (D-TFT). A multilayer organic compound layer may be formed between the anode electrode and the cathode electrode of the light-emitting device (EL). The organic compound layer may include at least one hole transport layer and an electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into or transports holes to the emission layer, and may be, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). And, the electron transport layer is a layer that injects electrons into or transports electrons to the emission layer, and may be, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL). The anode electrode of the light-emitting element (EL) is connected to node 3 (N3), and the cathode electrode of the organic light-emitting element can be connected to the input terminal of the low potential driving voltage (EVSS).

[0061] The driving transistor (DT) can control the driving current applied to the light-emitting element (EL) according to its source-gate voltage (Vsg). The gate electrode of the driving transistor (D-TFT) can be connected to node 1 (N1), the source electrode can be connected to node 4 (N4), and the drain electrode can be connected to node 2 (N2).

[0062] The first transistor (T1) is connected between node 1 (N1) and node 2 (N2) and can be turned on / off according to the nth scan signal (SCAN(n)). The gate electrode of the first transistor (T1) is connected to the nth first scan line to which the nth scan signal (SCAN(n)) is applied, the source electrode of the first transistor (T1) is connected to node 1 (N1), and the drain electrode of the first transistor (T1) can be connected to node 2 (N2). Here, the first transistor (T1) may also be referred to as a sampling transistor.

[0063] The second transistor (T2) is connected between the data line (14) and the node 4 (N4) and can be turned on / off according to the nth scan signal (SCAN(n)). The gate electrode of the second transistor (T2) is connected to the nth first scan line to which the nth scan signal (SCAN(n)) is applied, the source electrode of the second transistor (T2) is connected to the data line (14), and the drain electrode of the second transistor (T2) can be connected to the node 4 (N4).

[0064] The third transistor (T3) is connected between the node 4 (N4) and the input terminal of the high potential driving voltage (EVDD) and can be turned on / off according to the nth light emission control signal (EM(n)). The gate electrode of the third transistor (T3) is connected to the nth first emission line to which the nth light emission control signal (EM(n)) is applied, the source electrode of the third transistor (T3) is connected to the input terminal of the high potential driving voltage (EVDD), and the drain electrode of the third transistor (T3) can be connected to the node 4 (N4).

[0065] The fourth transistor (T4) is connected between node 2 (N2) and node 3 (N3) and can be turned on / off according to the nth light emission control signal (EM(n)). The gate electrode of the fourth transistor (T4) is connected to the nth first emission line to which the nth light emission control signal (EM(n)) is applied, the source electrode of the fourth transistor (T4) is connected to node 2 (N2), and the drain electrode of the fourth transistor (T4) can be connected to node 3 (N3). Here, the fourth transistor (T4) may also be referred to as an emission transistor.

[0066] The fifth transistor (T5) is connected between Node 1 (N1) and the input terminal of the initialization voltage (Vini), and can be turned on / off according to the n-1st scan signal (SCAN(n-1)). The gate electrode of the fifth transistor (T5) is connected to the n-1st first scan line to which the n-1st scan signal (SCAN(n-1)) is applied, the source electrode of the fifth transistor (T5) is connected to Node 1 (N1), and the drain electrode of the fifth transistor (T5) can be connected to the input terminal of the initialization voltage (Vini). Here, the fifth transistor (T5) may also be referred to as the first initial transistor.

[0067] The sixth transistor (T6) is connected between the input terminal of the initialization voltage (Vini) and node 3 (N3) and can be turned on / off according to the nth scan signal (SCAN(n)). The gate electrode of the sixth transistor (T6) is connected to the nth first scan line to which the nth scan signal (SCAN(n)) is applied, the source electrode of the sixth transistor (T6) is connected to node 3 (N3), and the drain electrode of the sixth transistor (T6) can be connected to the input terminal of the initialization voltage (Vini). Here, the sixth transistor (T6) may also be referred to as the second initial transistor.

[0068] Also, the capacitor (Cstg) can be connected between Node 1 (N1) and the input terminal of the initialization voltage (Vini).

[0069] In a display device according to an embodiment of the present specification, each subpixel (SP) may be configured to include a light-emitting element (EL), a driving transistor (D-TFT), and the first to sixth transistors may include a switching transistor and a capacitor (Cstg). However, this is not limited thereto, and the configuration of the subpixel (SP) may be freely modified according to the design.

[0070] FIG. 3 is a waveform diagram by driving frequency in a display device according to an embodiment of the present specification.

[0071] FIG. 3(a) is a waveform diagram of the driving frequency vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync). FIG. 3(b) is a waveform diagram of the horizontal synchronization signal (Hsync) and light emission operation at the standard driving frequency (SFR). FIG. 3(c) is a waveform diagram of the horizontal synchronization signal (Hsync) and light emission operation at the high driving frequency (HFR).

[0072] Referring to Fig. 3(a), the horizontal synchronization signal (Hsync) is formed in accordance with the vertical synchronization signal (Vsync). Since a standard standard driving frequency (SFR) generates the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) according to the frequency, the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) may differ depending on the frequency. For example, when converting from a 60Hz driving frequency to a 90Hz driving frequency, the periods of the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) all change, and a difference occurs in the time of the horizontal period (1H), so the operation period of the code element (SP) may also change.

[0073] In contrast, when operating based on a high-speed driving frequency (HFR), a horizontal synchronization signal (Hsync) can be generated in accordance with a high-speed driving frequency (HFR) of 90Hz. Therefore, when driving at a driving frequency of 60Hz, the horizontal synchronization signal (Hsync) can be maintained identically even if the period of the vertical synchronization signal (Vsync) differs from the driving frequency of 90Hz. In this case, within one period of the vertical synchronization signal (vsync), the period after the horizontal synchronization signal (Hsync) generated in accordance with the high-speed driving frequency (HFR) ends can be a holding time that maintains the last frame or a blank time during which the image is not displayed.

[0074] Referring to FIGS. 3(b) to FIGS. 3(c), the subpixel (SP) includes an initialization period (I), a sampling period (S), and a light emission period (E), and each operation period operates according to the n-1st and nth scan signals (SCAN(n-1), SCAN(n)) and the nth light emission control signal (EM(n)) applied to the subpixel (SP). Since the transistor constituting the subpixel (SP) is a PMOS transistor, the low level is the on level and the high level is the off level. For ease of explanation, the low level will be described as the on level and the high level as the off level.

[0075] The initialization period (I) is included in the n-1st horizontal period (Hn-1) allocated for data writing of the n-1st pixel row. During the initialization period (I), the n-1st scan signal (SCAN(n-1)) is applied at the ON level, and the nth scan signal (SCAN(n)) and the nth light emission control signal (EM(n)) are applied at the OFF level. The sampling period (S) is included in the nth horizontal period (Hn) allocated for data writing of the nth pixel row. During the sampling period (S), the nth scan signal (SCAN(n)) is applied at the ON level, and the n-1st scan signal (SCAN(n-1)) and the nth light emission control signal (EM(n)) may be applied at the OFF level. The light emission period (E) may correspond to the remaining period excluding the initialization period (I) and the sampling period (S) within one frame period. During the light emission period (E), the nth light emission control signal (EM(n)) is applied at the ON level, and the n-1st scan signal (SCAN(n-1)) and the nth scan signal (SCAN(n)) can be applied at the OFF level.

[0076] Although the horizontal synchronization signal (Hsync) generated based on the standard driving frequency (SFR) and the horizontal synchronization signal (Hsync) generated based on the high driving frequency (HFR) have different periods, if the horizontal synchronization signal (Hsync) is generated based on the high driving frequency (HFR) and applied to each driving frequency, signal operation can be performed in accordance with the same horizontal synchronization signal (Hsync). Accordingly, the same operating period can be applied even if the driving frequency is varied. For example, if the horizontal synchronization signal (Hsync) is generated based on a driving frequency of 90Hz, it can operate in accordance with the same horizontal synchronization signal (Hsync) at 60Hz as well. In addition, if the horizontal synchronization signal (Hsync) is generated based on a frequency of 120Hz, it can operate in accordance with the same horizontal synchronization signal (Hsync) at both 90Hz and 60Hz.

[0077] In other words, by applying the same operating period for each driving frequency, the image quality level for each driving frequency can be matched equally even if the driving frequency is changed.

[0078] Meanwhile, a dummy period (D) may be additionally included between the initialization period (I) and the light emission period (E). During the dummy period (D), the nth scan signal (SCAN(n)) is applied at an off level, and the n-1st scan signal (SCAN(n-1)) and the nth light emission control signal (EM(n)) are applied at an off level. During the dummy period (D), while the nth scan signal (SCAN(n)) is applied at an off level, the nth light emission control signal (EM(n)) is not applied at an on level and is maintained at an off level for a certain period of time. Accordingly, noise caused by current changes or voltage changes that may occur when the nth scan signal (SCAN(n)) and the nth light emission control signal (EM(n)) are synchronized simultaneously can be prevented in advance.

[0079] FIG. 4 is a diagram of the driving frequency conversion operation in a display device according to an embodiment of the present specification.

[0080] Referring to FIG. 4, the display device (100) may have a transition section that generates and applies a plurality of intermediate frequencies for smooth image transition when converting the driving frequency.

[0081] In other words, when driving frequencies of 60Hz, 90Hz, and 120Hz are respectively referred to as the first driving frequency (f1), the second driving frequency (f2), and the third driving frequency (f3), the frame transition becomes rapidly faster when transitioning from the first driving frequency (f1) to the second driving frequency (f2), so the transition of the image displayed on the display panel (110) is not smooth, and noise may be perceived. Therefore, a first intermediate frequency (f12) that is greater than the first driving frequency (f1) and smaller than the second driving frequency (f2), or a second intermediate frequency (f23) that is greater than the second driving frequency (f2) and smaller than the third driving frequency (f3) may be generated.

[0082] For example, when converting from a first driving frequency (f1) of 60 Hz to a second driving frequency (f2) of 90 Hz, a first intermediate frequency (f12) of 75 Hz is generated and operated to prevent abrupt changes between driving frequencies. Additionally, when converting from a second driving frequency (f2) of 90 Hz to a third driving frequency (f3) of 120 Hz, a second intermediate frequency (f23) can be generated and operated. Conversely, when converting from a third driving frequency (f3) to a second driving frequency (f2) or a first driving frequency (f1), a first or second intermediate frequency (f12, f23) can likewise be generated and applied.

[0083] At this time, for the first to third driving frequencies (f1, f2, f3) of 60Hz, 90Hz, and 120Hz, optical compensation for the corresponding frequencies may be performed during the manufacturing process. Accordingly, the first to third driving frequencies (f1, f2, f3) can be operated using the gamma voltage stored in the gamma voltage generation unit (160 in FIG. 5) after optical compensation. However, for the gamma voltage of the first and second intermediate frequencies (f12, f23) newly generated between the first to third driving frequencies (f1, f2, f3), the gamma voltage generated by interpolating the gamma voltage of the first to third driving frequencies (f1, f2, f3) in the gamma voltage generation unit (160) may be applied. The generation of the interpolated gamma voltage of the intermediate frequencies will be described later.

[0084] FIG. 5 is a block diagram of the operation of each function block in a display device according to an embodiment of the present specification.

[0085] Referring to FIG. 5, the controller (140) receives various timing signals (TS), such as vertical synchronization signals (Vsync) and horizontal synchronization signals (Hsync), along with RGB image data (RGB Data) from an external host system.

[0086] The controller (140) converts RGB image data (RGB Data) to match the data signal format used by the data driver (120), outputs the converted RGBG image data (RGBG Data), and controls data driving at an appropriate time in accordance with the scan. At this time, the RGBG image data (RGBG Data) may be a data signal format for a pentile pixel structure. However, it is not limited to this and may have various data signal formats depending on the design. In addition, the controller (140) can vary the driving frequency according to the received RGB image data (RGB Data) and timing signal (TS).

[0087] The frequency converter (150) generates a driving frequency conversion signal (Sf) using a timing signal (TS) received by the controller (140), and thereby can control the operation signals applied to the gate driving unit (130). The frequency converter (150) may be placed within the controller (140). However, it is not limited thereto and may be configured separately depending on the design.

[0088] When generating a horizontal synchronization signal (Hsync) based on a standard driving frequency (SFR), all operation signals of the gate driving unit (130) can be converted according to the driving frequency conversion signal (Sf). Additionally, when generating a horizontal synchronization signal (Hsync) based on a high-speed driving frequency (HFR), the operation signals can be converted so that a portion of the period within one cycle of the vertical synchronization signal (vsync) becomes a holding time or a blank time.

[0089] The gamma voltage generation unit (160) may be configured to include a gamma voltage setting unit (161), an interpolation gamma voltage setting unit (162), and a gamma voltage selection unit (163). Although the gamma voltage generation unit (160) is illustrated as being configured separately from the data driving unit (120) for convenience of explanation, it is not limited thereto and may be configured inside the data driving unit (120) depending on the design.

[0090] The gamma voltage set unit (161) may include a first memory unit (1611) and a first selection unit (1612). The first memory unit (1611) may store gamma voltage sets (GMA Setn) for each driving frequency to which optical compensation is applied. The first selection unit (1612) may select one of the gamma voltage sets (GMA Setn) stored in the first memory unit (1611) according to a driving frequency conversion signal (Sf) and output it to the gamma voltage selection unit (163).

[0091] The interpolation gamma voltage set unit (162) may include a gamma voltage interpolation unit (1621), a second memory unit (1622), and a second selection unit (1623). The second memory unit (1622) may store an interpolation gamma voltage set (IP GMA Setn-1) for each driving frequency to which an interpolation method is applied. The second selection unit (1623) may select one of the interpolation gamma voltage sets (IP GMA Setn-1) stored in the second memory unit (1622) according to a driving frequency conversion signal (Sf) and output it to the gamma voltage selection unit (163).

[0092] The gamma voltage selection unit (163) can select a gamma voltage that matches the driving frequency from among the output gamma voltages of the gamma voltage set unit (161) or the interpolation gamma voltage set unit (162) according to the driving frequency conversion signal (Sf) and supply it to the data driving unit (120).

[0093] For example, the gamma voltage set unit (161) can perform optical compensation for first to third driving frequencies (f1, f2, f3), such as 60Hz, 90Hz, and 120Hz, during the manufacturing process of the display device (100) to store each gamma voltage set (GMA Setn) in advance, and select and output it according to the corresponding driving frequency when driving.

[0094] At this time, when the power of the display device (100) is turned on, the interpolation gamma voltage set unit (162) can generate and pre-store interpolation gamma voltage sets (IP GMA Set1, IP GMA Set2) corresponding to the first and second intermediate frequencies (f12, f23) between the first to third driving frequencies (f1, f2, f3) by referring to each gamma voltage set (GMA Set1, GMA Set2, GMA Set3) stored in the gamma voltage set unit (161). Therefore, even if the driving frequency changes during operation, the pre-stored interpolation gamma voltage sets (IP GMA Set1, IP GMA Set2) can be applied immediately, allowing for operation without delay.

[0095] The intermediate frequencies between the optically compensated driving frequencies and the driving frequencies are not limited, and n optically compensated driving frequencies and n-1 intermediate frequencies can be generated and applied as needed.

[0096] Therefore, since optical compensation is not required for every driving frequency at each stage during driving frequency conversion, process time can be reduced, enabling efficient manufacturing.

[0097] FIG. 6 is a diagram showing the operation of a gamma voltage interpolation unit in a display device according to an embodiment of the present specification.

[0098] Figure 6(a) shows a method of generating an interpolated gamma voltage set (IP GMA Setn-1) by calculating a compensation coefficient (K) through a proportional equation between driving frequencies. Figure 6(b) shows a method of calculating by directly inputting the compensation coefficient (K) from the outside.

[0099] Referring to FIG. 6(a), the gamma voltage compensation coefficient (K) of the intermediate frequency can be calculated based on the frequency band difference and ratio between the driving frequency and the intermediate frequency. For example, the gamma voltage set (GMA Setn) of each driving frequency at the first to third driving frequencies (f1, f2, f3) for which optical compensation has already been performed is denoted as α, β, and γ. At this time, the compensation coefficient (K) of the first intermediate frequency (f12) generated between the first driving frequency (f1) and the second driving frequency (f2) can be the value obtained by dividing the difference between the first driving frequency (f1) and the first intermediate frequency (f12) by the difference between the first driving frequency (f1) and the second driving frequency (f2). In other words, the compensation coefficient (K) of the first intermediate frequency (f12) can be (f12-f1) / (f2-f1). The compensation coefficient (K) of the second intermediate frequency (f23) generated between the second driving frequency (f2) and the third driving frequency (f3) can also be calculated in the same way.

[0100] The interpolated gamma voltage set (IP GMA Setn-1) of the first and second intermediate frequencies (f12, f23) can be derived by reflecting the calculated compensation coefficient (K) in the gamma voltage set (GMA Set) of the first to third driving frequencies (f1, f2, f3).

[0101] Referring to Fig. 6(b), the compensation coefficient (K) of the intermediate frequency can be directly set and entered by the user. The first and second intermediate frequencies (f12, f23) can be derived by receiving the compensation coefficient (K) as i and j, respectively, and reflecting this in the gamma voltage set (GMA Set) of the first to third driving frequencies (f1, f2, f3).

[0102] The display device according to the embodiment of the present specification can generate an intermediate frequency when converting the driving frequency, and can generate and apply a set of interpolated gamma voltages to be used at the intermediate frequency. Through this, smooth image transitions are possible by preventing abrupt frequency conversions. In addition, since optical compensation is performed only for some driving frequencies, efficiency can be improved by shortening the time in the manufacturing process.

[0103] A display device according to an embodiment of the present specification may be described as follows.

[0104] A display device according to an embodiment of the present specification includes a display panel having a plurality of subpixels to display an image, a data driving unit that supplies image data to a plurality of subpixels, a gate driving unit that supplies a gate signal to a plurality of subpixels, a controller that converts the driving frequency of the data driving unit and the gate driving unit in a high-speed driving mode, and a gamma voltage generating unit that generates a gamma voltage for each driving frequency, wherein the controller can generate a horizontal synchronization signal based on the driving frequency in the high-speed driving mode.

[0105] In a display device according to an embodiment of the present specification, the driving frequency is divided into a first driving frequency and a second driving frequency in a band higher than the first driving frequency, and the first driving frequency can be driven by a horizontal synchronization signal generated based on the second driving frequency.

[0106] In a display device according to an embodiment of the present specification, the controller includes a frequency converter internally, and the frequency converter can sequentially convert by generating an intermediate frequency between a first driving frequency and a second driving frequency during driving frequency conversion.

[0107] In a display device according to an embodiment of the present specification, the gamma voltage of the intermediate frequency may be a gamma voltage that is interpolated by calculating a compensation coefficient based on the frequency band difference and ratio of a first driving frequency and a second driving frequency, and applying the compensation coefficient to the gamma voltage of the second driving frequency.

[0108] In a display device according to an embodiment of the present specification, the gamma voltage generating unit may include a gamma voltage setting unit, an interpolation gamma voltage setting unit, and a gamma voltage selection unit.

[0109] In a display device according to an embodiment of the present specification, the gamma voltage set unit includes a first memory unit and a first selection unit, the first memory unit stores a plurality of optically compensated gamma voltage sets according to a driving frequency, and the first selection unit can select and output one of the plurality of gamma voltage sets according to a driving frequency selection signal.

[0110] In a display device according to an embodiment of the present specification, the interpolation gamma voltage set unit includes a gamma voltage interpolation unit, a second memory unit, and a second selection unit, and the gamma voltage interpolation unit can generate an interpolation gamma voltage set corresponding to an intermediate frequency using a plurality of gamma voltage sets stored in the gamma voltage set unit.

[0111] In the display device according to the embodiment of the present specification, the data driver and the gate driver can operate with the same horizontal synchronization signal even if the driving frequency is varied.

[0112] In a display device according to an embodiment of the present specification, the display panel may have the same operating period in accordance with the same horizontal synchronization signal.

[0113] In a display device according to an embodiment of the present specification, the controller can convert RGB image data received from an external host system into RGBG image data and output it.

[0114] A display device according to an embodiment of the present specification includes a frequency converter that generates an intermediate frequency when converting a driving frequency from a first driving frequency to a second driving frequency, and a gamma voltage generator that stores gamma voltages for each driving frequency, wherein the gamma voltages of the first driving frequency and the second driving frequency are stored as pre-compensated values, and the gamma voltage of the intermediate frequency can be generated by interpolating the gamma voltages of the first driving frequency and the second driving frequency.

[0115] In a display device according to an embodiment of the present specification, the second driving frequency is a higher band than the first driving frequency, and the first driving frequency can be driven by the horizontal synchronization signal generated based on the second driving frequency.

[0116] In a display device according to an embodiment of the present specification, the first driving frequency may have the same operating period as the second driving frequency and the subpixel.

[0117] In a display device according to an embodiment of the present specification, the compensation coefficient is not calculated through the driving frequency but can be pre-set.

[0118] In a display device according to an embodiment of the present specification, the gamma voltage selection unit can select and output a gamma voltage from the gamma voltage set unit and the interpolation gamma voltage set unit according to a driving frequency conversion signal.

[0119] The features, structures, effects, etc. described in the examples of this specification described above are included in at least one example of this specification and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of this specification may be combined or modified and implemented in other examples by a person skilled in the art to which this specification pertains. Accordingly, contents related to such combinations and modifications should be interpreted as being included within the scope of this specification.

[0120] It will be obvious to those skilled in the art that the specification described above is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical details of the specification. Therefore, the scope of the specification is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the specification. Explanation of the symbols

[0122] 110: Display panel 120: Data driver 130: Gate drive unit 140: Controller 150: Frequency converter 160: Gamma voltage generator

Claims

Claim 1 A display device comprising: a display panel including a plurality of pixels; a data driver for driving the display panel; and a gate driver for supplying at least one scan signal to the display panel, wherein the plurality of pixels include a light-emitting element comprising an anode electrode, a cathode electrode, and a multilayer-based organic compound stack between the anode electrode and the cathode electrode; a driving transistor for driving the light-emitting element; and a plurality of switching transistors electrically connected to the driving transistor, wherein the plurality of switching transistors include a sampling transistor connected to a first node of the driving transistor and a second node of the driving transistor; a second transistor connected to a data line and a fourth node of the driving transistor; a third transistor connected to the fourth node of the driving transistor and an input terminal of a high-potential driving voltage; an emission transistor connected to the second node of the driving transistor and a third node of the light-emitting element; a first initial transistor connected to the first node of the driving transistor and an input terminal of an initialization voltage; and a second initial transistor connected to the input terminal of the initialization voltage and a third node of the light-emitting element. A display device comprising a capacitor connected to the first node of the driving transistor and the input terminal of the high-potential driving voltage, wherein the duration of the at least one scan signal or at least one light emission control signal in a standard frame rate mode and the duration of the at least one scan signal or at least one light emission control signal in a high-speed frame rate mode are different. Claim 2 In claim 1, the display device is a display device driven by a standard frame rate mode or a high frame rate mode. Claim 3 In claim 1, a display device in which a horizontal synchronization signal used in standard frame rate mode is used in high-speed frame rate mode. Claim 4 delete Claim 5 In claim 1, the data driving unit is a display device driven by a first driving frequency, a second driving frequency, and at least one intermediate frequency. Claim 6 A display device according to claim 1, wherein the emission transistor is turned on / off based on at least one light emission control signal, the first initial transistor is turned on / off based on the at least one scan signal, and the second initial transistor is turned on / off based on the at least one scan signal. Claim 7 A display device according to claim 1, wherein at least one of the driving transistor and the plurality of switching transistors is a PMOS transistor. Claim 8 A display device according to claim 1, wherein the multilayer-based organic compound stack comprises a hole transport layer, an electron transport layer, and a light-emitting layer, the hole transport layer comprises a hole injection layer, a hole transport layer, and an electron blocking layer, and the electron transport layer comprises an electron transport layer, an electron injection layer, and a hole blocking layer. Claim 9 A display device according to claim 1, wherein the driving frequency of the data driving unit includes a first frequency and a second frequency, and when the first frequency is changed to the second frequency, the data driving unit operates at an intermediate frequency in at least some of the plurality of frames. Claim 10 A display device according to claim 9, further comprising a voltage generating unit that generates a voltage corresponding to the driving frequency and an intermediate voltage corresponding to the intermediate frequency. Claim 11 In claim 10, the voltage generating unit obtains a compensation coefficient by dividing the difference between the first frequency and the first intermediate driving frequency by the difference between the first frequency and the second frequency, and obtains an interpolated voltage by applying the compensation coefficient to a voltage corresponding to the second frequency, wherein the interpolated voltage is the intermediate voltage. Claim 12 In item 10, the intermediate voltage is selected from an intermediate voltage set, and the voltage generating unit generates the intermediate voltage set based on a pre-stored voltage set corresponding to a first driving frequency and a second driving frequency. Claim 13 In claim 10, the voltage generating unit is a display device that generates the intermediate voltage based on a value interpolated between a first voltage corresponding to a first frequency and a second voltage corresponding to a second frequency.

Images