Electronic device for performing repair and operating method thereof

Abstract

An electronic device according to embodiments of the present disclosure includes a first chiplet connected to a first local memory and a second chiplet connected to a second local memory, wherein the first chiplet is configured to identify a defective row among a plurality of rows included in the first local memory based on an error log for an error that occurred in the first local memory, and if it is determined that there is a shortage of redundant rows to replace the defective row in the first local memory, to perform repair on the defective row using a redundant row of the second local memory.

Description

Technology Field

[0001] The present disclosure relates to an electronic device for performing repair and a method of operating the same, specifically, to an electronic device for performing repair by sharing idle redundant rows among local memories of a plurality of chiplets and a method of operating the same. Background Technology

[0002] With the recent rapid advancement of artificial intelligence technology, the demand for Neural Processing Units (NPUs) to process large-scale computations at high speeds is surging. Consequently, chiplet architectures are being introduced to overcome the manufacturing limitations of single dies and maximize yield by integrating multiple functionally separated chiplets into a single package. In these chiplet-based systems, each chiplet is individually equipped with high-bandwidth local memory, such as High Bandwidth Memory (HBM), creating a structure that enhances computational efficiency and minimizes data transmission latency.

[0003] However, as semiconductor processes become more miniaturized and the integration density of memory devices increases, the frequency of defects occurring in specific word lines of local memory is increasing. Typically, memory devices secure yield by replacing defective rows using a limited number of internal redundant rows. However, if defects are concentrated in the local memory of a specific chiplet and its own redundant rows are exhausted, inefficiency occurs where the chiplet is judged as defective or the entire package must be discarded because spare redundant resources cannot be utilized in the local memory of adjacent chiplets, even though such resources exist. This is a major cause of increased NPU manufacturing costs and reduced overall production yield. The problem to be solved

[0004] The objective of the present disclosure is to provide an electronic device for performing repairs and a method of operating the same, which can integrate and operate physically separated local memory resources by repairing bad rows using idle redundant rows of local memory of another chiplet when the local memory of one chiplet is insufficient.

[0005] The objective of the present disclosure is to provide an electronic device and a method of operation thereof for performing repairs that can solve the problem of yield reduction caused by defects being concentrated in a specific local memory of a chiplet, increase the overall manufacturing yield of a high-performance neural processing device, and improve the durability and reliability of the system.

[0006] The technical problems to be solved in this disclosure are not limited to those mentioned above, and various unmentioned technical problems can be inferred by a person skilled in the art from this disclosure. means of solving the problem

[0007] An electronic device according to embodiments of the present disclosure includes a first chiplet connected to a first local memory and a second chiplet connected to the first chiplet and a second local memory, wherein the first chiplet is configured to identify a defective row among a plurality of rows included in the first local memory based on an error log for an error that occurred in the first local memory, and if it is determined that there is a shortage of redundant rows to replace the defective row in the first local memory, to perform repair on the defective row using a redundant row of the second local memory.

[0008] In one embodiment, the first chiplet may be configured to perform a repair by transmitting a repair request to the second chiplet to activate a redundant row of the second local memory, and by receiving the address of the redundant row activated according to the repair request from the second chiplet, to update address mapping information between the faulty row and the activated redundant row of the second local memory in a mapping table.

[0009] In one embodiment, when the first chiplet transmits a repair request to the second chiplet, the received from the second chiplet It can be configured to determine whether the redundant row available in the second local memory is sufficient to replace the defective row based on the redundant row information, and if it is determined that the redundant row available in the second local memory is sufficient, to transmit the repair request to the second chiplet.

[0010] In one embodiment, when the first chiplet transmits a repair request to the second chiplet, the received from the second chiplet It may be configured to determine whether the available redundant rows in the second local memory are sufficient to replace the defective rows based on the redundant row information, and to report a repair error to the host if it is determined that the available redundant rows in the second local memory are insufficient.

[0011] In one embodiment, the second local memory includes a plurality of normal rows included in a normal area and redundant rows included in a redundant area having an address range after the address range allocated to the normal area, and the mapping table may include an offset for obtaining an address corresponding to the normal area of ​​the second local memory by applying to the address of the bad row for which access was requested, and memory size information of the second local memory for obtaining an address of the redundant row of the redundant area by applying to the address corresponding to the normal area.

[0012] In one embodiment, the first chiplet may be configured to include a memory controller configured to control the first local memory, and a Redundant Row Connection Circuit (RRCC) connected to the memory controller and configured to control a repair operation using a redundant row of the second local memory.

[0013] In one embodiment, the RRCC may be further configured to receive the error log from the memory controller and determine the defective row based on the error log.

[0014] In one embodiment, the RRCC may be configured to determine the one row as the defective row when the number of single-bit errors occurring in one of the plurality of rows exceeds a preset value when determining the defective row.

[0015] In one embodiment, the first chiplet may be further configured to convert the address of the bad row to an address corresponding to a redundant row in the second local memory by referring to the mapping table when it receives an access request for the bad row.

[0016] In one embodiment, the first chiplet may be configured to transmit the access request and the converted address to the second chiplet.

[0017] In one embodiment, while a repair for the defective row is performed using a redundant row of the second local memory, the first chiplet and the second chiplet may be configured to stop all operations except for the operation to perform the repair.

[0018] A method of operating an electronic device including a first chiplet and a second chiplet according to embodiments of the present disclosure may include: a step of identifying a defective row among a plurality of rows included in a first local memory based on an error log for an error that occurred in a first local memory connected to the first chiplet by the first chiplet; and a step of performing a repair on the defective row using a redundant row of a second local memory connected to the second chiplet when it is determined by the first chiplet that there is a shortage of redundant rows to replace the defective row in the first local memory.

[0019] In one embodiment, the step of performing a repair for the defective row using the redundant row of the second local memory may include the step of transmitting a repair request to the second chiplet to activate the redundant row of the second local memory by the first chiplet, and the step of updating address mapping information between the defective row and the activated redundant row of the second local memory in a mapping table by the first chiplet upon receiving the address of the redundant row activated according to the repair request from the second chiplet.

[0020] In one embodiment, the step of transmitting the repair request to the second chiplet comprises receiving from the second chiplet by the first chiplet The method may include a step of determining whether the redundant row available in the second local memory is sufficient to replace the defective row based on redundant row information, and a step of transmitting a repair request to the second chiplet if it is determined by the first chiplet that the redundant row available in the second local memory is sufficient.

[0021] In one embodiment, the step of transmitting the repair request to the second chiplet comprises receiving from the second chiplet by the first chiplet The method may include a step of determining whether the available redundant row in the second local memory is sufficient to replace the defective row based on the redundant row information, and a step of reporting a repair error to the host if it is determined by the first chiplet that the available redundant row in the second local memory is insufficient.

[0022] In one embodiment, when the first chiplet receives an access request for the bad row, it may further include the step of converting the address of the bad row to an address corresponding to a redundant row in the second local memory by referring to the mapping table.

[0023] In one embodiment, the method may further include the step of transmitting the access request and the converted address to the second chiplet by the first chiplet. Effects of the invention

[0024] According to embodiments of the present disclosure, when the local memory of one chiplet lacks its own redundant resources, the bad row can be repaired using the idle redundant row of the local memory of another chiplet, thereby enabling the integrated operation of physically separated local memory resources.

[0025] According to the embodiments of the present disclosure, the problem of reduced yield caused by defects being concentrated in a specific local memory of a chiplet can be resolved, the overall manufacturing yield of a high-performance neural processing device can be increased, and the durability and reliability of the system can be improved.

[0026] The effects according to the technical concept of the present disclosure are not limited to the effects mentioned above, and various unmentioned effects can be clearly understood by a person skilled in the art from the present disclosure. Brief explanation of the drawing

[0027] FIG. 1 is a drawing for explaining a system including a neural processing device and a host device including a plurality of chiplets according to embodiments of the present disclosure. Figure 2 is a drawing for explaining an exemplary configuration of the chiplet of Figure 1. Figure 3 is a diagram for explaining the neural cluster of Figure 2 in detail. Figure 4 is a diagram for explaining the neural core of Figure 3 in detail. FIG. 5 is a flowchart illustrating the process of identifying defective rows according to embodiments of the present disclosure. FIG. 6 is a flowchart for explaining the process of determining whether to perform a repair using a redundant row of a second local memory according to embodiments of the present disclosure. Figure 7 is a flowchart illustrating the process of repairing using the redundant row of the second local memory of Figure 6. FIG. 8 is a diagram illustrating the process of converting the address of a defective row to the address of a redundant row of a second chiplet by referring to a mapping table according to embodiments of the present disclosure. FIG. 9 is a flowchart for explaining the process of writing data to a redundant row of a second chiplet using a converted address according to embodiments of the present disclosure. FIG. 10 is a flowchart for explaining the process of reading data from a redundant row of a second chiplet using a converted address according to embodiments of the present disclosure. Specific details for implementing the invention

[0028] Hereinafter, specific embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, specific descriptions of commonly known functions or configurations are omitted where there is a risk of unnecessarily complicating or obscuring the core of the invention.

[0029] The advantages, features, and methods for achieving the disclosed embodiments will be clearly understood by referring to the accompanying drawings and the embodiments described below. However, the present disclosure is not limited to these embodiments and may be implemented in various forms. These embodiments are provided merely as examples to aid in the overall understanding of the invention and do not limit the scope of the invention.

[0030] In the attached drawings, identical or similar components are assigned the same reference numbers. Additionally, when describing embodiments of the present disclosure, descriptions of identical or similar components may be omitted to avoid redundant descriptions. However, such omission of description is not intended to imply that the corresponding component is not included in a particular embodiment.

[0031] The terms used in this specification have been selected to fully reflect the function of the invention and are currently in general use; however, these may change depending on the perspectives of those skilled in the relevant field or new technological advancements. Additionally, in specific cases, terms may be selected at the applicant's discretion, and in such cases, their meanings will be described in detail in this specification. Accordingly, the terms in this specification should be interpreted based on their meanings and the overall content of this disclosure, rather than merely as names.

[0032] In this specification, when expressed in the singular, it may include a plural meaning unless explicitly limited to the singular. Conversely, when expressed in the plural, it may be interpreted as singular in context unless explicitly limited to the plural. Throughout the specification, when a specific part is described as including a certain component, this does not mean that other components are excluded, but rather that additional components may be included.

[0033] In this specification, the expressions “each of a plurality of A” or “each of a plurality of A” may refer to each of all elements included in a plurality of A, or may refer to each of some elements of a plurality of A.

[0034] In this specification, the expression “one or more A” may mean a set of one or more A's unless the context clearly indicates otherwise.

[0035] Expressions used herein such as "may include," "may be equipped," and "may have" imply the presence of the relevant feature (e.g., function, operation, or component, etc.) and do not exclude the presence of other additional features. In other words, these expressions should be understood as open-ended terms that leave open the possibility of including other embodiments.

[0036] As used herein, the expression "configured to..." may have meanings such as "set to...", "capable of...", "modified to...", "made to...", or "capable of..." depending on the context. This expression is not limited to "specifically designed in hardware"; for example, a processor configured to perform a specific operation may refer to a general-purpose processor capable of performing that operation through software execution, or a special-purpose computer structured through programming to perform the said specific operation.

[0037] Expressions such as "connection," "transmission," "sending," and "reception" used in this specification may mean directly connecting, transmitting, sending, or receiving between components, or they may mean indirectly connecting, transmitting, sending, or receiving through the interposition of other components.

[0038] FIG. 1 is a drawing for explaining a system including a neural processing device and a host device including a plurality of chiplets according to embodiments of the present disclosure.

[0039] Referring to FIG. 1, a system (1) according to embodiments of the present disclosure may include a neural processing device (10) and a host device (20).

[0040] The neural processing device (10) may be a device that communicates with the host device (20) and provides functions according to the commands of the host device (20). For example, the neural processing device (10) may be a device specialized in the computation of an artificial neural network model and may be an artificial neural network accelerator. The neural processing device (10) may perform parallel processing for at least some functions of the host device (20). In the present disclosure, the neural processing device (10) may be referred to as an electronic device.

[0041] The host device (20) is a general-purpose computing processor and may be, for example, a CPU (Central Processing Unit). The host device (20) may not be suitable for neural network operations in deep learning. Therefore, the host device (20) may request neural network operations from the neural processing device (10). That is, the host device (20) may be a host that sends commands to the neural processing device (10). The host device (20) may transmit a command stream to the neural processing device (10) to instruct neural network operations. The host device (20) may receive the results of the neural network operations from the neural processing device (10).

[0042] The neural processing device (10) may include a plurality of chiplets. The neural processing device (10) may distribute tasks according to the command to the plurality of chiplets according to the command of the host device (20) and process the tasks in parallel. A chiplet may be an individual integrated circuit and may be a semiconductor device in the form of a package formed by combining or connecting with external chiplets. That is, the neural processing device (10) may be packaged in a form including a plurality of chiplets. For example, the neural processing device (10) may include a first chiplet (100_1), a second chiplet (100_2), a third chiplet (100_3), and a fourth chiplet (100_4). However, this is exemplary, and the neural processing device (10) may include any number of chiplets.

[0043] The first chiplet (100_1) of the neural processing device (10) and the host device (20) may be connected by a host interface. The host interface may provide an external communication path for data transmission and reception and control signal exchange between one of the plurality of chiplets (100_1 to 100_3) (e.g., the first chiplet (100_1)) and the host device (20). The host interface may be implemented as one or more of various interfaces depending on the configuration of the system (1). The host interface may include various interfaces such as PCIe (Peripheral Component Interconnect Express), I2C (Inter-Integrated Circuit), or SMBus (System Management Bus).

[0044] Referring to FIG. 1, the first to fourth chiplets (100_1 to 100_4) may be arranged in a square array, and the first to fourth chiplets (100_1 to 100_4) may each be connected to adjacent chiplets to communicate. However, this is exemplary, and the chiplets including the first to fourth chiplets (100_1 to 100_4) within the neural processing device (10) may be arranged in various forms such as a straight line, a rectangle, or a grid and connected to each other.

[0045] The first to fourth chiplets (100_1 to 100_3) can be connected to each other via a silicon interposer using methods such as wire bonding or TSV (Through Silicon Via). Additionally, the first to fourth chiplets (100_1 to 100_3) can be connected to each other by an inter-chiplet interface. Specifically, the inter-chiplet interface is a die-to-die interface and can be implemented, for example, as a UCIe (Universal Chiplet Interconnect Express) interface. The UCIe interface can perform high-speed and bandwidth-extended communication between multiple chiplets. However, the scope of the present disclosure is not limited thereto, and the interface between chiplets may include various interfaces such as MIPI (Mobile Industry Processor Interface), I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), USART (Universal Synchronous Receiver / Transmitter), CAN (Controller Area Network), LIN (Local Interconnect Network), and SSI (Synchronous Serial Interface).

[0046] The first to fourth chiplets (100_1 to 100_4) may each be an artificial neural network accelerator that performs operations on an artificial neural network model. However, this is exemplary, and the first to fourth chiplets (100_1 to 100_4) may each include chiplets that perform various functions such as an artificial neural network accelerator, a CPU, an interface chip, or a memory chip, and the first to fourth chiplets (100_1 to 100_4) may be the same chiplet or different chiplets. If any one of the first to fourth chiplets (100_1 to 100_4) includes a CPU, the host device (20) may communicate with other chiplets within the neural processing device (10).

[0047] The neural processing device (10) may further include first to fourth local memories (110_1 to 110_4). The first to fourth chiplets (100_1 to 100_4) may be directly connected to each local memory and may directly manage each local memory. For example, the first chiplet (100_1) may be directly connected to the first local memory (110_1, LM1), the second chiplet (100_2) may be directly connected to the second local memory (110_2, LM2), the third chiplet (100_3) may be directly connected to the third local memory (110_3, LM3), and the fourth chiplet (100_4) may be directly connected to the fourth local memory (110_4, LM4).

[0048] The first to fourth local memories (110_1 to 110_4) may each include at least one of non-volatile memory and volatile memory. For example, non-volatile memory may include ROM (Read Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, MRAM (Magnetic RAM), spin-transfer torque MRAM, CBRAM (Conductive Bridging RAM), FeRAM (Ferroelectric RAM), PRAM (Phase Change RAM), etc., but the present disclosure is not limited thereto. For example, volatile memory may include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), etc., but the present disclosure is not limited thereto.

[0049] The first to fourth local memories (110_1 to 110_4) may each include a plurality of memory cells placed at points where a plurality of word lines (rows) and a plurality of bit lines (columns) intersect. As described below, each memory cell array of the first to fourth local memories (110_1 to 110_4) may include a normal area for storing data and a redundant area for performing repairs by replacing defective rows that may occur in the normal area.

[0050] The first to fourth chiplets (100_1 to 100_4) may each include a memory interface for communicating with a local memory. The memory interface may include various interfaces such as PCI, PCIe, etc.

[0051] Each of the first to fourth chiplets (100_1 to 100_4) may be configured as a single package (e.g., System in Package (SiP)) together with the connected first to fourth local memories (110_1 to 110_4), or may be packaged as physically separated separate chips. However, this is exemplary and the packaging forms of the present disclosure are not limited thereto.

[0052] Meanwhile, the number of redundant rows for repair provided in each of the first to fourth local memories (110_1 to 110_4) may be limited. As the semiconductor process becomes more miniaturized, the frequency of row-related defects may increase, and there may be cases where defects exceeding the number of self-redundant rows occur in the local memory of a specific chiplet (e.g., the first chiplet (100_1)). In this case, even though there are unused spare redundant rows in the local memory of another chiplet (e.g., the second chiplet (100_2)), the resources are not shared, so a problem may arise where the first chiplet (100_1) is treated as defective or the neural processing device (10) itself must be discarded. A row-related defect is a defect in which an error continuously occurs in a specific wordline due to reasons such as a physical defect in the wordline or degradation of the characteristics of the memory element.

[0053] According to embodiments of the present disclosure, if the first chiplet (100_1) determines that it lacks its own redundant row to repair a bad row in the first local memory (110_1), it can perform repair on the bad row using a redundant row of the second local memory (110_2) connected to another chiplet (e.g., the second chiplet (100_2)). Subsequently, the first chiplet (100_1) can remap access to the bad row to a redundant row of the second chiplet (100_2) to share redundant resources between chiplets.

[0054] Through this, when low-level defects are concentrated in a specific local memory and there is a shortage of its own redundant rows, the defective rows can be repaired by utilizing idle redundant resources from other local memories. As a result, the manufacturing yield and reliability of the expensive neural processing device (10) can be improved.

[0055] In the present disclosure, the first chiplet (100_1) and the second chiplet (100_2) are described under the assumption that they are each neural processing SoCs that perform neural network operations. An exemplary configuration of the chiplet composed of a neural processing SoC is described with reference to FIG. 2. The first chiplet (100_1) and the second chiplet (100_2) may each be configured as shown in FIG. 2.

[0056] Figure 2 is a drawing for explaining an exemplary configuration of the chiplet of Figure 1.

[0057] A chiplet (100) according to embodiments of the present disclosure may be a neural processing SoC. The chiplet (100) may include a neural cluster (1000), a Direct Memory Access (DMA, 2000), a memory (3000), a host interface (4000), a command processor (5000), a Root of Trust (RoT, 6000), a memory controller (7000), a Redundant Row Connection Circuit (RRCC, 8000), and a Network on Chip (NoC, 9000). The DMA (2000), the host interface (4000), the RoT (6000), the memory controller (7000), and the RRCC (8000) may each be implemented as a circuit or a circuitry.

[0058] A neural cluster (1000) may be a device that processes neural network operations. A neural cluster (1000) may be connected to a DMA (2000), memory (3000), host interface (4000), command processor (5000), RoT (6000), and RRCC (8000) via a system NoC (9000). Additionally, a neural cluster (1000) may be connected to another neural cluster (1000) via a system NoC (9000). Although two neural clusters (1000) are shown in FIG. 2, the present disclosure is not limited thereto. That is, a chiplet (100) may include three or more neural clusters (1000) or one neural cluster (1000). Additionally, each neural cluster (1000) may be the same or similar processor, or may be a heterogeneous processor.

[0059] The DMA (2000) can directly transfer data between memory and peripheral devices without the intervention of a host device (20) or neural cluster (1000) connected through the host interface (4000). The DMA (2000) can improve system performance by minimizing interrupts of processors such as the host device (20) and neural cluster (1000) and supporting parallel processing tasks. For example, the DMA (2000) can control data movement between memory (3000), data movement between chiplets, and data movement between local memory.

[0060] The memory (3000) can be shared by a plurality of neural clusters (1000). Additionally, the memory (3000) can be shared by other components of the chiplet (100) other than the neural cluster (1000). That is, the memory (3000) can operate as a global memory. The memory (3000) can store data received from a host device (20) or other chiplets, etc. The neural cluster (1000) can perform neural network operations based on the data stored in the memory (3000). The neural cluster (1000) can store the results of the neural network operations, etc., in the memory (3000). The data stored in the memory (3000) can be moved to the host device (20) or other chiplets, etc., by control of a DMA (2000), etc. For example, the memory (3000) can store input data, weights, task information, intermediate operation results, operation results, etc.

[0061] For example, the memory (3000) may be a memory with a relatively fast access speed, such as SRAM. However, this is exemplary, and the memory (3000) may include various types of memory such as DRAM, and the present disclosure is not limited thereto.

[0062] In an embodiment, the memory (3000) may be placed as an off-chip memory outside the chiplet (100) as a separate component. In this case, the memory (3000) may correspond to the local memory (110). In another embodiment, the memory (3000) may be placed inside the chiplet (100) as a memory separate from the local memory (110). In yet another embodiment, the memory (3000) may be configured as a memory inside the neural cluster (1000). In this case, the memory (3000) may correspond to an L1 cache memory. Here, the local memory (110) may correspond to a local memory connected to the chiplet (100) (e.g., one of the first to fourth local memories (110_1 to 110_4) of FIG. 1).

[0063] The host interface (4000) can perform communication between the chiplet (100) and the host device (20). Through the host interface (4000), the chiplet (100) can receive a command stream from the host device (20) and transmit the operation results and status information of the chiplet (100) to the host device (20). For example, the host interface (4000) can correspond to the host interface described in FIG. 1.

[0064] The command processor (5000) can receive a command stream from a host device (20) through a host interface (4000). The command processor (5000) can create one or more tasks based on the received command stream and transmit them to a neural cluster (1000) and a DMA (2000). The DMA (2000) can read data required for task execution (e.g., weights, input data, etc.) from memory (3000) or read from an external memory (e.g., local memory (110), etc.) in conjunction with a memory controller (7000) and transmit it to the neural cluster (1000). The neural cluster (1000) can perform neural network operations based on the received tasks and data and transmit a task progress status (e.g., completion signal, etc.) to the command processor (5000). The command processor (5000) can receive data transmission status, task progress status, etc. from the DMA (2000) and the neural cluster (1000).

[0065] The RoT (6000) is responsible for the security of the chiplet (100) and can perform tasks such as secure booting, checking firmware integrity, and maintaining system integrity during execution. The RoT (6000) can communicate with an external security device (40) to perform security procedures.

[0066] A memory controller (7000) may be connected to a local memory (110) corresponding to a chiplet (100) and configured to control the local memory (110). If the local memory (110) includes volatile memory, the memory controller (7000) may include a volatile memory controller for controlling operations of the volatile memory, such as data reading and writing and refreshing. If the local memory (110) includes non-volatile memory, the memory controller (7000) may include a non-volatile memory controller for controlling operations of the non-volatile memory, such as data reading and writing and wear leveling. The memory controller (7000) may perform control operations of the local memory (110) through commands of, for example, a neural cluster (1000), a DMA (2000), and a command processor (5000).

[0067] The memory controller (7000) may include an Error Correction Code (ECC) circuit. When the memory controller (7000) writes data to the local memory (110), it may generate an ECC parity code for the data and store it together in the local memory (110). Additionally, when the memory controller (7000) reads data from the local memory (110), it may use the ECC parity code that is read together to detect whether an error has occurred, correct the detected error, or generate an error log. The memory controller (7000) may generate an error log containing information about the error that occurred during the read operation (e.g., the address where the error occurred, the type of the error, etc.) and provide it to the RRCC (8000).

[0068] The RRCC (8000) is connected to the memory controller (7000) and may be configured to control a repair operation using redundant rows of local memory other than the local memory connected to the memory controller (7000). The RRCC (8000) receives an error log from the memory controller (7000) and can determine a defective row that occurred in the local memory (110) based on the received error log.

[0069] The RRCC (8000) may be configured to perform repair on a defective row using a redundant row in a local memory (e.g., a first local memory (110_1) if the chiplet (100) is a first chiplet (100_1)) connected to a chiplet (100) containing the RRCC (8000) when it is determined that there is a shortage of redundant rows to replace a defective row in the local memory (e.g., a second local memory (110_2)) connected to another chiplet (e.g., a second chiplet (100_2)). When the repair is completed, the RRCC (8000) may update and store address mapping information between the defective row and the redundant row in the local memory used for the repair in an internal mapping table.

[0070] Subsequently, when the RRCC (8000) receives an access request for a bad row, it may refer to a mapping table to convert the address of the bad row to an address corresponding to a redundant row in the local memory used for repair (e.g., the second local memory (110_2)). The RRCC (8000) may use the converted address to transmit the access request to the chiplet used for repair (e.g., the second chiplet (100_2)), thereby enabling normal memory operation to be performed using a redundant row in another local memory.

[0071] The system NoC (9000) can connect the neural cluster (1000), DMA (2000), memory (3000), host interface (4000), command processor (5000), RoT (6000), and RRCC (8000) to each other. Through the system NoC (9000), data or control signals can be exchanged between the neural cluster (1000), DMA (2000), memory (3000), host interface (4000), command processor (5000), RoT (6000), and RRCC (8000). Additionally, through the system NoC (9000), synchronization signals for controlling synchronization between the neural clusters (1000) can be exchanged between the neural clusters (1000).

[0072] For example, the system NoC (9000) may be configured in various forms such as a multi-layer architecture, a bus-based network structure, a ring structure, etc., but the present disclosure is not limited thereto.

[0073] Neural network operations of the chiplet (100) can be performed through the following process. First, the host device (20) can transmit a command stream for neural network operations to the chiplet (100). The command processor (5000) can generate one or more tasks based on the received command stream and transmit them to the neural cluster (1000) and the DMA (2000). Simultaneously or sequentially, computation-related data, such as weights and input data of the neural network for neural network operations, can be moved from off-chip memory (not shown) or local memory (110) to the memory (3000) of the chiplet (100). The movement of data can be performed by the memory controller of the host device (20) under the control of the host device (20), or by the memory controller (7000) of the chiplet (100) under the control of the DMA (2000) of the chiplet (100). The neural cluster (1000) of the chiplet (100) can perform neural network operations based on input data, weights, tasks, etc. The operation result can be stored in the memory (3000) of the chiplet (100), off-chip memory (not shown), or local memory (110). The host device (20) can read the operation result from the memory (3000), off-chip memory (not shown), or local memory (110).

[0074] In the following, for convenience of explanation, the components included in the first chiplet (100_1) may be referred to by adding the ordinal number 'first', and the components included in the second chiplet (100_2) may be referred to by adding the ordinal number 'second'. For example, the memory controller (7000) and RRCC (8000) of the first chiplet (100_1) may be referred to as 'first memory controller (7000_1)', 'first RRCC (8000_1)', and the memory controller (7000) and RRCC (8000) of the second chiplet (100_2) may be referred to as 'second memory controller (7000_2)', 'second RRCC (8000_2)', etc.

[0075] Figure 3 is a diagram for explaining the neural cluster of Figure 2 in detail.

[0076] A neural cluster (1000) according to embodiments of the present disclosure may include a neural core (10000), an L1 memory (20000), and an internal NoC (Internal NoC, 30000). The neural core (10000) may be implemented as a circuit or a network.

[0077] A neural cluster (1000) may include a plurality of neural cores (10000). The neural cores (10000) may be configured to process neural network operations. The neural cores (10000) may receive a task and perform operations according to the task. The neural cores (10000) may transmit a signal indicating the completion of the task to a command processor (5000) through an internal NoC (30000) and a system NoC (9000).

[0078] Although two neural cores (10000) are shown in FIG. 3, the neural cluster (1000) may include three or more neural cores (10000) or one neural core (10000), and the present disclosure is not limited thereto.

[0079] The L1 memory (20000) can be shared by multiple neural cores (10000). The L1 memory (20000) can also be shared by other components of the chiplet (100) other than the corresponding neural cluster (1000), such as multiple neural cores (10000) of other neural clusters (1000).

[0080] L1 memory (20000) can store data received from memory (3000), off-chip memory (not shown), or local memory (110). Neural cluster (1000) can perform neural network operations based on data stored in L1 memory (20000). Data stored in L1 memory (20000) can be moved to memory (3000), off-chip memory (not shown), or local memory (110) by control such as DMA (2000). For example, L1 memory (20000) can store input data, weights, task information, intermediate operation results, operation results, etc.

[0081] The internal NoC (30000) can connect multiple neural cores (10000) and L1 memory (20000) to each other. For example, the internal NoC (30000) can be configured in various forms such as a multi-layer structure, a bus-based network structure, a ring structure, or a mesh network, but the present disclosure is not limited thereto.

[0082] Figure 4 is a diagram for explaining the neural core of Figure 3 in detail.

[0083] The neural core (10000) may include a compute unit (11000), L0 memory (12000), neural DMA (13000), and task manager (14000). The compute unit (11000), neural DMA (13000), and task manager (14000) may each be implemented as a circuit or a network.

[0084] The compute unit (11000) can perform various computational tasks. The compute unit (11000) can combine SIMD (Single Instruction Multiple Data) computational elements and MIMD (Multiple Instruction Multiple Data) computational elements. SIMD is a method of processing multiple data elements simultaneously with a single instruction and is suitable for repeatedly applying the same operation to multiple data, while MIMD utilizes instruction parallelism by processing different data by executing different instructions simultaneously. By combining SIMD and MIMD computational elements, the compute unit (11000) can optimize parallel performance and instruction-level dependency control in various computational scenarios.

[0085] The compute unit (11000) can be connected to the L0 memory (12000). The compute unit (11000) uses the L0 memory (12000) as a cache memory and can write data, such as intermediate calculation results, to the L0 memory (12000) during the computation process, or read necessary data (e.g., input data, computation instructions, weights, etc.) from the L0 memory (12000). The input data may be computation target data read into the L0 memory (12000) from an external memory (e.g., L1 memory (20000), memory (3000), etc.). The intermediate calculation result may be data generated by the compute unit (11000) during computation and stored in the L0 memory (12000). Additionally, the compute unit (11000) can perform calculations based on calculation instructions stored in the L0 memory (12000), and can accelerate the calculation speed by caching data with high frequency in the calculation in the L0 memory (12000).

[0086] L0 memory (12000) can be connected to a compute unit (11000) and a neural DMA (13000). L0 memory (12000) can operate as a cache memory that stores data or instructions required for the operation of the compute unit (11000) and the neural DMA (13000). For example, L0 memory (12000) may be SRAM, but may be various types of memory other than SRAM, and the present disclosure is not limited thereto.

[0087] The neural DMA (13000) can be connected to the L0 memory (12000). The neural DMA (13000) can manage data transfer between the L0 memory (12000) and the L1 memory (20000).

[0088] The task manager (14000) can operate in conjunction with the command processor (5000) to maximize the utilization of the computational resources of each neural core (10000). The task manager (14000) can manage the task queue of the neural core (10000), the synchronization of the neural core (10000), and the priority of the tasks. The task manager (14000) can control the synchronization between the neural cores (10000). Through this, tasks distributed by the command processor (5000) can be executed simultaneously among the neural cores (10000).

[0089] Hereinafter, a method for repairing a defective row according to embodiments of the present disclosure will be described in detail. For convenience of explanation, the description focuses on an embodiment in which a defective row occurs in the first local memory (110_1) and is repaired by replacing it with a redundant row included in the second local memory (110_2). However, this is merely an example to aid in understanding the present disclosure, and the scope of the present disclosure is not limited thereto. The defective row may occur in any of the first to fourth local memories (110_1 to 110_4), and the same method of replacing it using a redundant row from any of the remaining local memories, excluding the memory where the defective row occurred, may also be applied.

[0090] FIG. 5 is a flowchart illustrating the process of identifying defective rows according to embodiments of the present disclosure.

[0091] Referring to FIG. 5, the first RRCC (8000_1) of the first chiplet (100_1) may interact with the first memory controller (7000_1) of the first chiplet (100_1) to perform a process of identifying a defective row that occurred in the first local memory (110_1). That is, the process of identifying a defective row in FIG. 5 may be performed in the first chiplet (100_1).

[0092] In step S110, the first memory controller (7000_1) may generate an error log for an error occurring during the runtime of the first local memory (110_1) and provide the generated error log to the first RRCC (8000_1). Specifically, the first memory controller (7000) may detect whether an error has occurred using an ECC parity code read along with data from the first local memory (110_1), generate an error log, and store it in a register. The error log may include the address of the detected error, the type of the error (single-bit error, multi-bit error, etc.). A single-bit error is an error in which a 1-bit error occurs within the read data and may be an error that can be corrected through the ECC circuit (not shown) of the first memory controller (7000_1). A multi-bit error is an error in which two or more bits occur within the read data and may be an error that can be detected through the ECC circuit (not shown) but cannot be corrected.

[0093] Generally, when a single-bit error occurs repeatedly in a specific row, it can be attributed to a physical defect in that row, making it relatively easy to identify the cause. In contrast, multi-bit errors can be caused by various factors, such as not only hardware defects but also software errors or temporary noise, making it difficult to conclude that they are defects in a specific row. Therefore, the first RRCC (8000_1) according to the embodiments of the present disclosure may be configured to identify defective rows based on the address and number of occurrences of a single-bit error for which the cause is clear.

[0094] In an embodiment, the first memory controller (7000_1) may transmit an interrupt signal to the first RRCC (8000_1) when a single-bit error log occurs. Upon receiving the interrupt signal, the first RRCC (8000_1) may load the single-bit error log from the register of the first memory controller (7000_1) and store it in a register inside the first RRCC (8000_1). In another embodiment, the first memory controller (7000_1) may transmit the generated error log directly to the first RRCC (8000_1) when a single-bit error log occurs, without a separate interrupt signal.

[0095] As an example, the first RRCC (8000_1) may include internal memory (not shown) for storing an error log and a mapping table to be described later.

[0096] In step S120, based on the received error log, the first RRCC (8000_1) can determine whether the number of single-bit errors occurring in a specific row among a plurality of rows exceeds a preset value. To determine row defects caused by physical defects rather than temporary errors in the first local memory (110_1), the first RRCC (8000_1) can count single-bit errors that occur repeatedly at the same row address.

[0097] Specifically, the first RRCC (8000_1) can increase the single-bit error count value of the address (row address) where the error occurred when a single-bit error occurs.

[0098] If the corresponding count value exceeds a preset value (yes direction), the first RRCC (8000_1) determines the corresponding row as a defective row with a defect and can perform a repair operation (S130). For example, the repair operation may include an operation based on Post Package Repair (PPR). For example, the preset value may be 10 times, 20 times, etc., to distinguish it from a temporary soft error, but this is an example and may be varied depending on the reliability policy of the memory device.

[0099] If the corresponding count value is less than or equal to a preset value (no direction), the first RRCC (8000_1) can perform step S120 again.

[0100] In an example, the first memory controller (7000_1) may provide an error log for all errors to the first RRCC (8000_1) without distinguishing between single-bit errors and multi-bit errors. In this case, the first RRCC (8000_1) may further perform a step of determining whether the provided error log corresponds to a single-bit error, and if it corresponds to a single-bit error, it may perform step S120 by counting the single-bit error at the corresponding address.

[0101] In step S130, the first RRCC (8000_1) can communicate with the second RRCC (8000_2) of the second chiplet (100_2) to perform a repair operation according to embodiments of the present disclosure.

[0102] For the repair operation of step S130, the first RRCC (8000_1) may first perform the process of FIG. 6. This is explained below.

[0103] FIG. 6 is a flowchart for explaining the process of determining whether to perform a repair using a redundant row of a second local memory according to embodiments of the present disclosure.

[0104] Referring to FIG. 6, a process is described in which, after the first RRCC (8000_1) of the first chiplet (100_1) identifies a defective row, it interacts with the second RRCC (8000_2) of the second chiplet (100_2) to determine whether to perform a repair using a redundant row of the second local memory (110_2).

[0105] In step S210, the first RRCC (8000_1) of the first chiplet (100_1) can determine whether there is a shortage of redundant rows to replace bad rows in the first local memory (110_1). For example, the first RRCC (8000_1) can determine that there is a shortage of redundant rows if there are no redundant rows remaining in the first local memory (110_1) or if the number of remaining redundant rows is less than the number of bad rows to replace.

[0106] If the number of available redundant rows in the first local memory (110_1) is sufficient to replace the defective rows (no direction), the first RRCC (8000_1) of the first chiplet (100_1) can perform repair of the defective rows itself using the redundant rows of the first local memory (110_1) (step S220).

[0107] If it is determined that there is a shortage of redundant rows to replace a bad row in the first local memory (110_1) (yes direction), the first RRCC (8000_1) of the first chiplet (100_1) may request redundant row information from the second RRCC (8000_2) of the second chiplet (100_2) (step S230). In an embodiment, as the second chiplet (100_2), the chiplet physically closest to the first chiplet (100_1) among a plurality of chiplets or the chiplet with the lowest communication latency (e.g., the second chiplet (100_2) or the fourth chiplet (100_4)) may be preferentially selected.

[0108] In an embodiment, the first local memory (110_1) and the second local memory (110_2) may each include a storage circuit (such as a register) for storing information about redundant rows. The information about redundant rows may include the total number of redundant rows, the number and address of used redundant rows, the number of available redundant rows, etc. As another example, the information about redundant rows may be stored in the storage circuits of the first memory controller (7000_1) and the second memory controller (7000_2), but the present disclosure is not limited thereto.

[0109] In step S240, the second RRCC (8000_2) of the second chiplet (100_2) can transfer redundant row information of the second local memory (110_2) to the first RRCC (8000_1).

[0110] In step S250, the first RRCC (8000_1) of the first chiplet (100_1) can determine whether the redundant row available in the second local memory (110_2) is sufficient to replace the bad row based on the redundant row information received from the second chiplet (100_2).

[0111] If there is a shortage of available redundant rows in the second local memory (110_2) (no direction), the first RRCC (8000_1) of the first chiplet (100_1) may perform steps S230 to S270 on other chiplets (e.g., the third chiplet (100_3) and the fourth chiplet (100_4)). Specifically, the first RRCC (8000_1) requests redundant row information from the fourth RRCC (8000_4) of the fourth chiplet (100_4) to check whether there are enough redundant rows in the fourth local memory (110_4), and if there are enough, performs repair using the redundant rows of the fourth local memory (110_4) connected to the fourth chiplet (100_4). If there is a shortage of redundant rows in the fourth local memory (110_4) as well, steps S230 to S270 can be performed for the third RRCC (8000_3) of the third chiplet (100_3). If there are no available redundant rows in all chiplets including the first to fourth chiplets (100_1 to 100_4), the first chiplet (100_1) can report a repair error to the host device (20).

[0112] When it is determined that there are enough available redundant rows in the second local memory (110_2) (yes direction), the first RRCC (8000_1) of the first chiplet (100_1) transmits a repair request to the second chiplet (100_2) so that repairs can be performed on defective rows that occurred in the first local memory (110_1) using the redundant rows of the second local memory (110_2) (step S270). The process of performing repairs on defective rows that occurred in the first local memory (110_1) using the redundant rows of the second local memory (110_2) (step S270) is explained in detail with reference to FIG. 7.

[0113] In an embodiment, while a repair for a defective row is being performed using a redundant row of the second local memory (110_2), the first chiplet (100_1) and the second chiplet (100_2) may be configured to stop all operations except for the operation to perform the repair. Specifically, if the first RRCC (8000_1) identifies a defective row in the first local memory (110_1), it may report this to the command processor (5000) of the first chiplet (100_1). The first command processor (5000_1) of the first chiplet (100_1) may report the occurrence of the defective row and the need for repair to the host device (20) through the first host interface (4000_1). In response to this, the host device (20) may send a stop operation command to the command processor (5000) of all chiplets, including the first chiplet (100_1) and the second chiplet (100_2). In accordance with the stop operation command, the command processor of each chiplet may temporarily suspend all operations, such as the operation of the neural cluster and the data transfer operation of the DMA, except for the exchange of control signals for the repair operation.

[0114] Figure 7 is a flowchart illustrating the process of repairing using the redundant row of the second local memory of Figure 6.

[0115] First, the first RRCC (8000_1) of the first chiplet (100_1) can disable a bad row in the first local memory (110_1) (Step ①). For example, the first RRCC (8000_1) (or the first memory controller (7000_1)) can transmit a command for entering PPR mode (e.g., an MRS command) to the first local memory (110_1). Then, the first RRCC (8000_1) (or the first memory controller (7000_1)) transmits address information of the bad row to the first local memory (110_1) and programs or marks the corresponding address in a bad address storage circuit (e.g., an anti-fuse array, a control register, etc.) inside the first local memory (110_1), thereby physically blocking or disabling the word line operation for the corresponding bad row. ① Step ① may be performed at any of the following steps, and the present disclosure is not limited thereto.

[0116] Next, the first RRCC (8000_1) may transmit a repair request to the second chiplet (100_2) (step ②). The repair request is a request to activate a redundant row of the second local memory (110_2) and may include a PPR command to activate a redundant row of the second local memory (110_2). Alternatively, the second RRCC (8000_2) or the second memory controller (7000_2) of the second chiplet (100_2) may generate a PPR command based on the repair request. In the present disclosure, the PPR command provided to the second chiplet (100_2) may be understood as a command to activate a specific redundant row of the local memory.

[0117] The second RRCC (8000_2) of the second chiplet (100_2) can activate a redundant row of the second local memory (110_2) through the second memory controller (7000_2) in response to a received repair request (step ③).

[0118] For example, the second RRCC (8000_2) (or the second memory controller (7000_2)) may transmit a command for entering PPR mode (e.g., an MRS command) and an address signal for selecting a redundant row to activate to the second local memory (110_2). Afterward, the second local memory (110_2) may maintain a self-refresh mode until the activation setting of the redundant row is completed and perform the operation to activate the redundant row.

[0119] Activation of redundant rows can be performed in a physical or software manner. For example, in the case of a physical hard PPR, redundant rows can be activated by permanently changing circuit connections by applying a high voltage to a non-volatile component, such as an anti-fuse, during the self-refresh mode period. On the other hand, in the case of a software soft PPR, redundant rows can be activated by logically establishing connections by storing activation information in an internal register or latch circuit during the self-refresh mode period. However, this is exemplary and the present disclosure is not limited thereto.

[0120] When a redundant row is activated, the second RRCC (8000_2) can receive address information of the activated redundant row from the second local memory (110_2) and the second memory controller (7000_2). Subsequently, the second RRCC (8000_2) can update and store redundant row information indicating that the corresponding redundant row in the second local memory (110_2) has been used in a storage circuit within the second RRCC (8000_2) or in a specific storage area of ​​the second local memory (110_2). Through this, the second chiplet (100_2) can identify available resources by excluding the redundant row that has already been used when there is another repair request later.

[0121] The second chiplet (100_2) can transmit the address of an activated redundant row to the first chiplet (100_1) (step ④). The first RRCC (8000_1) of the first chiplet (100_1) can receive the address of an activated redundant row from the second chiplet (100_2) in response to a repair request. The address of the redundant provided to the first chiplet (100_1) may be a logical address mapped to the actual physical address of the redundant address. This is illustrated in FIG. 8. As another example, it may be provided as the actual physical address of the redundant address. However, this is exemplary and the present disclosure is not limited thereto.

[0122] Upon receiving an activated redundant row address from the second chiplet (100_2) in response to a repair request, the first RRCC (8000_1) of the first chiplet (100_1) can update the mapping table by mapping the activated redundant row address of the second local memory (110_2) to the bad row address of the first local memory (110_1) (step ⑤).

[0123] For example, the first RRCC (8000_1) may set an information bit indicating that a repair using another chiplet has been performed in an entry corresponding to a bad row in the mapping table, and may store address mapping information between the bad row and an active redundant row of the second local memory (110_2). The mapping information may include an offset applied to the address of the bad row for which access was requested to obtain an address corresponding to the normal area of ​​the second local memory (110_2), and memory size information of the second local memory (110_2) applied to the address corresponding to the normal area to obtain a row address of the redundant area of ​​the second local memory (110_2). This is explained with reference to FIG. 8.

[0124] Subsequently, when the first chiplet (100_1) receives an access request for a bad row in the first local memory (110_1), the mapping table of the first RRCC (8000_1) may be accessed first and the mapping table may be referenced. If it is confirmed that the information bit of the corresponding bad row in the mapping table of the first RRCC (8000_1) is activated (e.g., logic 1), the first RRCC (8000_1) may refer to the mapping table and return the address of the redundant row in the second local memory (110_2) that replaced the bad row.

[0125] Through this address remapping process, redundant resources located in physically different local memories are logically connected, thereby enabling the completion of repairs between memories.

[0126] FIG. 8 is a diagram illustrating the process of converting the address of a defective row to the address of a redundant row of a second chiplet by referring to a mapping table according to embodiments of the present disclosure.

[0127] Referring to FIG. 8, a structure is shown in which the first to fourth local memories (110_1 to 110_4) within the neural processing unit (10) are mapped to a single unified logical address space.

[0128] Each of the first to fourth local memories (110_1 to 110_4) may include a normal area for storing data and a redundant area in which redundant rows are arranged to replace defective rows. The normal area is an area accessible by the host device (20) or chiplet (100) for general data input / output, and may have an address range corresponding to the capacity of each local memory. The redundant area is an area allocated after the address range of the normal area, and may be an area that exists physically but is not directly accessed by logical address under normal circumstances, and is mapped and accessible only when repair is performed.

[0129] The logical addresses of the first to fourth local memories (110_1 to 110_4) can be arranged sequentially. For example, the first local memory (110_1) can start from 0x0_0000_0000, the second local memory (110_2) can start from 0x1_0000_0000, and the third local memory (110_3) can start from 0x2_0000_0000, and a unique base address can be assigned to each local memory.

[0130] The RRCC (8000) of each chiplet may store a mapping table for accessing local memory connected to other chiplets. As previously described, the mapping table may store offset and memory size information. For example, with respect to the first chiplet (100_1), the offset for accessing the second local memory (110_2) may be the difference in base addresses between the first local memory (110_1) and the second local memory (110_2). In the example of FIG. 8, the offset for the target local memory (e.g., the second local memory (110_2)) may be set to 0x1_0000_0000. For example, the offset may include each offset for accessing the first to fourth local memories (110_1 to 110_4). Additionally, if the memory sizes of the first to fourth local memories (110_1 to 110_4) are different, the memory sizes may include the memory sizes of each local memory.

[0131] Below, a specific process is described for converting the logical address of a bad row into the physical address (PA, Physical Address) of a corresponding redundant row using offset and memory size information stored in the mapping table in the RRCC (8000) when an access request for the address of a bad row is received.

[0132] The following conversion process is described under the assumption that a bad row in the first local memory (110_1) has been repaired into a redundant row in the second local memory (110_2). In the example of FIG. 8, it is assumed that the address of the bad row in the first local memory (110_1) is 0x0_0000_1000, the offset of the second local memory (110_2) to replace it is 0x1_0000_0000, and the normal area size (Memory size) of each local memory is 0x0_1000_0000. However, this is exemplary, and the offset, normal area size, etc. may vary, and the present disclosure is not limited thereto.

[0133] First, the first RRCC (8000_1) can obtain an address corresponding to the normal area of ​​the second local memory (e.g., 0x1_0000_1000) by applying the offset (0x1_0000_0000) of the second local memory to the bad row address (0x0_0000_1000). Next, the first RRCC (8000_1) can obtain a row address of the redundant area by additionally applying the size (0x0_1000_0000) of the normal area of ​​the second local memory (110_2) to the first converted address. The redundant area can start immediately after the last address of the normal area. Therefore, by shifting the address by the size of the normal area (memory size), a logical address (0x1_1000_1000) referring to a specific redundant row within the redundant area of ​​the second local memory (110_2) can be obtained.

[0134] At this time, the acquired address (0x1_1000_1000) can be mapped to a physical redundant row inside the second local memory (110_2). Specifically, the second local memory (110_2) may store a separate RR mapping table in an internal storage circuit (such as a register) that defines the mapping relationship between the address of the redundant area and the physical address of the actual redundant row. When access is requested to an address recorded in the RR mapping table, the second local memory (110_2) may refer to the stored RR mapping table to convert the address into the final physical address of the redundant row where the actual data will be stored, thereby performing data access. For example, the RR mapping table may be stored in a storage circuit for storing information on the redundant row described in FIG. 6 or in a separate storage circuit, but the present disclosure is not limited thereto.

[0135] FIG. 9 is a flowchart for explaining the process of writing data to a redundant row of a second chiplet using a converted address according to embodiments of the present disclosure.

[0136] The data access process of FIGS. 9 and FIGS. 10 is described under the assumption that a bad row in the first local memory (110_1) has been repaired to a redundant row in the second local memory (110_2). Referring to FIG. 9, when a write request according to the command stream of the host device (20) targets the address of a bad row in the first chiplet (100_1), the process of converting the address to a converted address corresponding to a redundant row in the second local memory (110_2) and transmitting it to the second chiplet (100_2) is illustrated.

[0137] In step S310, the host device (20) can transmit a command stream to the first chiplet (100_1). The command stream can be received by the first command processor (5000_1) of the first chiplet (100_1).

[0138] In step S320, the command processor (5000_1) of the first chiplet (100_1) can generate a write request (e.g., a write command), data, and an address for the first local memory (110_1) based on the received command stream and transmit them to the first RRCC (8000_1).

[0139] In step S330, by referring to the mapping table, the first RRCC (8000_1) determines whether the received address corresponds to a bad row in the first local memory (110_1), and if it corresponds to a bad row, it can perform address conversion to the address of the bad row (of the second local memory (110_2)) to the address of the corresponding redundant row.

[0140] Specifically, the first RRCC (8000_1) can first refer to a mapping table to determine whether the address requested for access corresponds to a bad row. If the address requested for access does not correspond to a bad row, the first RRCC (8000_1) can write data to the address requested for access in the first local memory (110_1). On the other hand, if the address requested for access corresponds to a bad row, the first RRCC (8000_1) can refer to a mapping table to convert the address of the bad row to a converted address (remapped address) corresponding to a redundant row in the second local memory (110_2).

[0141] In step S340, the first RRCC (8000_1) can transmit a write request (e.g., a write command), data, and a converted address to the second RRCC (8000_2) of the second chiplet (100_2). That is, the first chiplet (100_1) can transmit an access request (write request) for a bad row of the first local memory (110_1) along with a converted address to the second chiplet (100_2).

[0142] In step S350, the second RRCC (8000_2) of the second chiplet (100_2) can transmit the received write command, data, and converted address to the second local memory (110_2) through the second memory controller (7000_2).

[0143] The second local memory (110_2) can write data to the redundant row of the second local memory (110_2) using the converted address.

[0144] In an example, after the write operation ends, the second local memory (110_2) may transmit a write completion signal to the second memory controller (7000_2). However, this is exemplary and the present disclosure is not limited thereto.

[0145] FIG. 10 is a flowchart for explaining the process of reading data from a redundant row of a second chiplet using a converted address according to embodiments of the present disclosure.

[0146] Referring to FIG. 10, when a read request according to the command stream of a host device (20) targets the address of a bad row of the first chiplet (100_1), the address is converted into a converted address corresponding to a redundant row of the second local memory (110_2) and transmitted to the second chiplet (100_2), and the data read from the second chiplet (100_2) is returned to the first chiplet (100_1).

[0147] In step S410, the host device (20) can transmit a command stream to the first chiplet (100_1). The command stream can be received by the first command processor (5000_1) of the first chiplet (100_1).

[0148] In step S420, the command processor (5000_1) of the first chiplet (100_1) can generate a read request (e.g., a read command) and an address for the first local memory (110_1) based on the received command stream and transmit them to the first RRCC (8000_1).

[0149] In step S430, the first RRCC (8000_1) determines whether the received address corresponds to a bad row in the first local memory (110_1), and if it corresponds to a bad row, it can perform address conversion from the bad row address to the address of a repaired redundant row.

[0150] Specifically, the first RRCC (8000_1) can check whether the address requested for access corresponds to a bad row by referring to a mapping table. If the address requested for access does not correspond to a bad row, the first RRCC (8000_1) can read data from the address requested for access in the first local memory (110_1). On the other hand, if the address requested for access corresponds to a bad row, the first RRCC (8000_1) can refer to a mapping table to convert the address of the bad row to a converted address (remapped address) corresponding to a redundant row in the second local memory (110_2).

[0151] In step S440, the first RRCC (8000_1) can transmit a read request (e.g., a read command) and a converted address to the second RRCC (8000_2) of the second chiplet (100_2). That is, the first chiplet (100_1) can transmit an access request (read request) for a bad row of the first local memory (110_1) along with a converted address to the second chiplet (100_2).

[0152] In step S450, the second RRCC (8000_2) of the second chiplet (100_2) can transmit the received read command and the converted address to the second local memory (110_2) through the second memory controller (7000_2).

[0153] In step S460, the second local memory (110_2) can read data from a redundant row of the second local memory (110_2) using the converted address. The second local memory (110_2) can transfer the read data to the second RRCC (8000_2) through the second memory controller (7000_2).

[0154] In step S470, the second RRCC (8000_2) can transmit the read data to the first RRCC (8000_1) of the first chiplet (100_1). Alternatively, the second RRCC (8000_2) can transmit the read data to another component of the first chiplet (neural cluster (1000), first memory (3000_1), first command processor (5000_1), etc.). Afterward, the component that received the data can complete the read operation by transmitting the received data to the requesting component (e.g., the neural cluster (1000), memory (3000), etc. of the first chiplet (100_1) or another chiplet) or to the host device (20).

[0155] As described above, according to the embodiments of the present disclosure, the first chiplet (100_1) can effectively replace defective rows by sharing idle redundant resources of another chiplet (e.g., the second chiplet (100_2)) even when there is a shortage of redundant rows in the first local memory (110_1) connected to the first chiplet (100_1). In particular, through address remapping via the RRCC (8000), memory resources (local memory) between physically separated chiplets can be logically connected to extend the scope of defect relief to the system (neural processing device (10)) level. Accordingly, physical limitations of local memory can be overcome and available resources of the entire system can be efficiently utilized, and as a result, the manufacturing yield of the high-performance neural processing device (10) can be maximized and operational reliability can be ensured.

[0156] In the flowchart according to the present disclosure, each step of the method or algorithm is described in a sequential order, but each step may be performed not only sequentially but also in any combination thereof. The description of the flowchart of the present disclosure does not exclude the addition, modification, or deletion of at least some steps of the method or algorithm. In the embodiments of the present disclosure, at least some steps may be performed in parallel or repeatedly.

[0157] In the embodiments of the present disclosure, components expressed as 'part', 'unit', 'block', 'module', 'component', etc., may be implemented as hardware that performs a specific function. Such hardware may include, for example, a circuit that performs operations or a circuitry which is a set of interconnected circuits to perform complex functions. Here, 'part', 'unit', 'block', 'module', 'component', etc., perform a specific role and are not limited to software or hardware, but may be used to encompass components of software or hardware, data, or combinations thereof. Furthermore, structures, methods, operations, processes, algorithms, etc., according to the embodiments of the present disclosure may be implemented through various means such as hardware, firmware, software, or combinations thereof.

[0158] Various embodiments of the present disclosure may be implemented as software recorded on a machine-readable recording medium. The software may be software for implementing the various embodiments of the present disclosure described above. The software may be inferred from the various embodiments of the present disclosure by programmers skilled in the art to which the present disclosure pertains. For example, the software may be a machine-readable instruction (e.g., code or code segment) or a program. The machine may be a device capable of operating according to instructions called from the recording medium, such as a computer. In one embodiment, the machine may be an electronic device according to the embodiments of the present disclosure. In one embodiment, the processor of the machine may execute the called instruction to cause the components of the machine to perform a function corresponding to the instruction. In one embodiment, the processor may be a processor of the electronic device according to the embodiments of the present disclosure. The recording medium may mean any type of recording medium in which data is stored that can be read by the machine. The recording medium may include, for example, ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc. In one embodiment, the recording medium may be a memory. In one embodiment, the recording medium may be implemented in a distributed form in a networked computer system, etc. Software may be stored and executed in a distributed manner in a computer system, etc. The recording medium may be a computer-readable non-transitory recording medium. A computer-readable non-transitory recording medium refers to a tangible medium that exists regardless of whether data is stored semi-permanently or temporarily, and does not include a signal that is transmitted transitory.

[0159] As explained above, those skilled in the art of the present disclosure will recognize that the present disclosure may be implemented in various forms without altering its technical principles or core features. Accordingly, it should be understood that the above embodiments are illustrative and do not limit the scope of the present disclosure. The scope of the present disclosure is defined by the claims below rather than the detailed description, and all variations or modifications based on the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present disclosure.

[0160] The features and advantages described herein are only partial, and further features and advantages will become apparent to those skilled in the art upon reference to the drawings, specification, and claims. Additionally, it should be noted that the language used herein is chosen for readability and illustrative purposes and is not necessarily chosen to limit or describe the subject matter of this disclosure.

[0161] The description of the above embodiments is provided for illustrative purposes only and is not intended to limit the scope of the disclosure in its exact form. Those skilled in the art will understand that various modifications and variations are possible from the content of the disclosure.

[0162] Therefore, the scope of the present disclosure is not limited by the detailed description but is defined by the claims of this specification. Accordingly, the embodiments of the present disclosure are exemplary and do not limit the scope of the present disclosure as set forth in the claims below.

Claims

Claim 1 An electronic device comprising: a first chiplet connected to a first local memory; and a second chiplet connected to the first chiplet and a second local memory, wherein the first chiplet is configured to: identify a defective row among a plurality of rows included in the first local memory based on an error log regarding an error that occurred in the first local memory, and, if it is determined that there is a shortage of redundant rows to replace the defective row within the first local memory, perform a repair on the defective row using a redundant row of the second local memory. Claim 2 An electronic device according to claim 1, wherein the first chiplet, in performing a repair, transmits a repair request to the second chiplet to activate a redundant row of the second local memory, and upon receiving the address of the redundant row activated according to the repair request from the second chiplet, updates address mapping information between the faulty row and the activated redundant row of the second local memory to a mapping table. Claim 3 In paragraph 2, when the first chiplet transmits a repair request to the second chiplet, the received from the second chiplet An electronic device configured to determine, based on redundant row information, whether the redundant row available in the second local memory is sufficient to replace the defective row, and, if it is determined that the redundant row available in the second local memory is sufficient, to transmit the repair request to the second chiplet. Claim 4 In paragraph 2, when the first chiplet transmits a repair request to the second chiplet, the received from the second chiplet An electronic device configured to determine, based on redundant row information, whether the redundant rows available in the second local memory are sufficient to replace the faulty rows, and to report a repair error to a host device outside the electronic device if it is determined that the redundant rows available in the second local memory are insufficient. Claim 5 An electronic device according to claim 2, wherein the second local memory comprises a plurality of normal rows included in a normal area and redundant rows included in a redundant area having an address range after the address range allocated to the normal area, and the mapping table comprises an offset for obtaining an address corresponding to the normal area of ​​the second local memory by applying to the address of the access requested bad row, and memory size information of the second local memory for obtaining an address of the redundant row of the redundant area by applying to the address corresponding to the normal area. Claim 6 An electronic device according to claim 1, wherein the first chiplet is configured to include a memory controller configured to control the first local memory; and a Redundant Row Connection Circuit (RRCC) connected to the memory controller and configured to control a repair operation using a redundant row of the second local memory. Claim 7 An electronic device according to claim 6, wherein the RRCC is further configured to receive the error log from the memory controller and determine the defective row based on the error log. Claim 8 An electronic device according to claim 7, wherein the RRCC is configured to determine the one row as the defective row when the number of single-bit errors occurring in one of the plurality of rows exceeds a preset value when determining the defective row. Claim 9 An electronic device according to paragraph 2, wherein the first chiplet is further configured to convert the address of the bad row to an address corresponding to a redundant row in the second local memory by referring to the mapping table when it receives an access request for the bad row. Claim 10 In claim 9, the electronic device wherein the first chiplet is configured to transmit the access request and the converted address to the second chiplet. Claim 11 An electronic device according to claim 1, wherein while a repair for the defective row is performed using a redundant row of the second local memory, the first chiplet and the second chiplet are configured to stop all operations except for the operation to perform the repair. Claim 12 A method of operating an electronic device comprising a first chiplet and a second chiplet, comprising: a step of identifying a defective row among a plurality of rows included in a first local memory based on an error log regarding an error that occurred in a first local memory connected to the first chiplet by the first chiplet; and a step of performing a repair on the defective row using a redundant row of a second local memory connected to the second chiplet when it is determined by the first chiplet that there is a shortage of redundant rows to replace the defective row in the first local memory. Claim 13 In claim 12, the step of performing a repair for the faulty row using the redundant row of the second local memory comprises: transmitting a repair request to the second chiplet to activate the redundant row of the second local memory by the first chiplet; and updating address mapping information between the faulty row and the activated redundant row of the second local memory in a mapping table by the first chiplet upon receiving the address of the redundant row activated according to the repair request from the second chiplet. Claim 14 In paragraph 13, the step of transmitting the repair request to the second chiplet is: received from the second chiplet by the first chiplet A method comprising: a step of determining whether the redundant row available in the second local memory is sufficient to replace the defective row based on redundant row information; and a step of transmitting a repair request to the second chiplet when it is determined by the first chiplet that the redundant row available in the second local memory is sufficient. Claim 15 In paragraph 13, the step of transmitting the repair request to the second chiplet is: received from the second chiplet by the first chiplet A method comprising: a step of determining whether the redundant rows available in the second local memory are sufficient to replace the defective rows based on redundant row information; and a step of reporting a repair error to a host device outside the electronic device if it is determined by the first chiplet that the redundant rows available in the second local memory are insufficient. Claim 16 A method according to claim 13, further comprising the step of, when the first chiplet receives an access request for the bad row, converting the address of the bad row to an address corresponding to a redundant row in the second local memory by referring to the mapping table. Claim 17 A method according to claim 16, further comprising the step of transmitting the access request and the converted address to the second chiplet by the first chiplet.

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