Semiconductor device and display device including the same

Abstract

In a transistor comprising an oxide semiconductor film, field-effect mobility and reliability are improved. A semiconductor device comprises a transistor comprising an oxide semiconductor film. The transistor includes a region in which the maximum value of the field-effect mobility of the transistor is 40 or greater and less than 150 at a gate voltage greater than 0V and less than or equal to 10V, a region in which the threshold voltage is minus 1V or greater and less than or equal to 1V, and a region in which the S value is less than 0.3V / decade.

Description

Technology Field

[0001] One embodiment of the present invention relates to a semiconductor device comprising an oxide semiconductor film and a display device comprising said semiconductor device.

[0002] Furthermore, one embodiment of the present invention is not limited to the technical field described above. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to articles, methods, or methods of production. The present invention relates to a process, machine, product, or composition of matter. One embodiment of the present invention is particularly related to an oxide semiconductor or a method of producing said oxide semiconductor. One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a capacitor device, a memory device, a method of driving the same, and a method of producing the same.

[0003] In the present specification and others, a semiconductor device generally refers to a device capable of functioning by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, computing devices, and memory devices are each a form of a semiconductor device. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells and organic thin-film solar cells, etc.), and electronic devices may each include a semiconductor device. Background Technology

[0004] Technology for forming transistors (also known as field-effect transistors (FETs) or thin film transistors (TFTs)) using semiconductor thin films formed on a substrate having an insulating surface is attracting attention. Such transistors are applied to a wide range of electronic devices, such as integrated circuits (ICs) or image display devices. Semiconductor materials, represented by silicon, are widely known as materials for semiconductor thin films that can be used in transistors. Oxide semiconductors are also attracting attention as another material. For example, a technology for fabricating transistors using In-Ga-Zn-based oxide semiconductors has been disclosed (see Patent Document 1).

[0005] In addition, a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer functioning as a channel in the plurality of oxide semiconductor layers comprises indium and gallium, and due to a structure in which the ratio of indium is higher than the ratio of gallium, a high electric field-effect mobility (simply mobility or μ) FE A semiconductor device that achieves (there are cases where it is said that) is disclosed (see Patent Document 1).

[0006] In Non-patent Literature 1, In 1- x Ga 1+ x O3(ZnO) m (-1≤ x ≤ and, m A homologous series represented by (is a natural number) is disclosed. Additionally, Non-patent Document 1 discloses a solid solution range of the homologous series. For example, m In the range of solid solutions of the same family in the case of this 1, x It is in the range from -0.33 to 0.08, and m In the range of solid solutions of the same family in this 2-person case, x It is in the range from -0.68 to 0.32. Prior art literature

[0007] Japanese Patent Publication No. JP 2007-96055 Japanese Patent Publication No. JP 2014-007399

[0008] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃," J. Solid State Chem., 1991, Vol. 93, pp. 298-315. The problem to be solved

[0009] For a transistor using an oxide semiconductor film as the channel region, it is desirable for the field-effect mobility to be as high as possible. However, as field-effect mobility increases, the transistor has a problem with its characteristics, namely, the problem that the transistor is prone to becoming "normally-on." Furthermore, "normally-on" refers to a state in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode.

[0010] Furthermore, in transistors using an oxide semiconductor film in the channel region, oxygen vacancies formed in the oxide semiconductor film adversely affect transistor characteristics. For example, oxygen vacancies formed in the oxide semiconductor film combine with hydrogen to function as carrier sources. These carrier sources in the oxide semiconductor film cause changes in the electrical characteristics of the transistor containing the oxide semiconductor film, typically resulting in fluctuations in the threshold voltage.

[0011] For example, if the amount of oxygen vacancies in the oxide semiconductor film is excessive, the threshold voltage of the transistor fluctuates in the negative direction, causing the transistor to exhibit normaly-on characteristics. Therefore, particularly in the channel region of the oxide semiconductor film, it is desirable to have a small amount of oxygen vacancies or an amount such that normaly-on characteristics do not appear.

[0012] In addition, Non-patent Literature 1 contains In x Zn y Ga z O w An example of is disclosed, x , y , and z so that a composition near ZnGa2O4 is obtained, i.e. x , y , and z When is set to be close to 0, 1, and 2, respectively, a spinel crystal structure is easily formed or mixed. As a compound having a spinel crystal structure, AB 2O4( A and B Compounds represented as metals are known.

[0013] However, when a spinel crystal structure is formed or mixed into an In-Ga-Zn oxide semiconductor, the electrical characteristics or reliability of a semiconductor device (e.g., a transistor) containing the In-Ga-Zn oxide semiconductor may be adversely affected by the spinel crystal structure.

[0014] Taking into account the aforementioned problems, an objective of one embodiment of the present invention is to improve the field-effect mobility and reliability of a transistor comprising an oxide semiconductor film. An objective of one embodiment of the present invention is to prevent changes in the electrical characteristics of a transistor comprising an oxide semiconductor film and to improve the reliability of the transistor. An objective of one embodiment of the present invention is to provide a semiconductor device with low power consumption. An objective of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. An objective of one embodiment of the present invention is to provide a novel oxide semiconductor. An objective of one embodiment of the present invention is to provide a novel semiconductor device. An objective of one embodiment of the present invention is to provide a novel display device.

[0015] Furthermore, the description of the aforementioned problem does not interfere with the existence of other problems. In one embodiment of the present invention, it is not necessary to achieve all of these problems. Problems other than the above problems will become apparent and can be derived from the description in the specification, etc. means of solving the problem

[0016] One embodiment of the present invention is a semiconductor device comprising a transistor comprising an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film. The first conductive film includes a region in contact with the oxide semiconductor film. The second conductive film includes a region in contact with the oxide semiconductor film. The third conductive film includes a region that overlaps with the oxide semiconductor film via an insulating film. The transistor has a maximum field-effect mobility of 40 cm², wherein the gate voltage is higher than 0 V and 10 V or less. 2 / Vs over 150cm 2 Region less than / Vs, region where the threshold voltage is between -1V and 1V, region where the S value is less than 0.3V / decade, and off-state current is 1×10 -12 A / cm 2 Includes a region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g In the case where =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 1 or more and less than 1.5.

[0017] One embodiment of the present invention is a semiconductor device comprising a transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. The transistor has a maximum field-effect mobility of 40 cm², wherein the gate voltage is higher than 0 V and 10 V or less. 2 / Vs over 150cm 2 Region less than / Vs, region where the threshold voltage is between -1V and 1V, region where the S value is less than 0.3V / decade, and off-state current is 1×10 -12 A / cm 2 Includes a region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g In the case where =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 1 or more and less than 1.5.

[0018] In the above-described configuration, the oxide semiconductor film has a density of shallow defect levels of 1.0 × 10⁻⁶ -12 cm -2 It is desirable to include an area less than [value].

[0019] One embodiment of the present invention is a semiconductor device comprising a transistor comprising an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film. The first conductive film includes a region in contact with the oxide semiconductor film. The second conductive film includes a region in contact with the oxide semiconductor film. The third conductive film includes a region that overlaps with the oxide semiconductor film via an insulating film. The transistor has a maximum value of field-effect mobility of 40 cm², wherein the gate voltage is higher than 0 V and 10 V or less. 2 / Vs over 150cm 2 Region less than / Vs, region where the threshold voltage is between -1V and 1V, region where the S value is less than 0.3V / decade, and off-state current is 1×10 -12 A / cm 2 Includes a region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g In the case where =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 1.5 or greater and less than 3.

[0020] One embodiment of the present invention is a semiconductor device comprising a transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. The transistor has a maximum field-effect mobility of 40 cm², wherein the gate voltage is higher than 0 V and 10 V or less. 2 / Vs over 150cm 2 Region less than / Vs, region where the threshold voltage is between -1V and 1V, region where the S value is less than 0.3V / decade, and off-state current is 1×10 -12 A / cm 2 Includes a region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g In the case where =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 1.5 or greater and less than 3.

[0021] In the above-described embodiment, the oxide semiconductor film has a density of shallow defect levels of 1.0 × 10⁻⁶ -12 cm -2 At most 2.0×10 -12 cm -2 It is desirable to include an area less than [value].

[0022] One embodiment of the present invention is a semiconductor device comprising a transistor comprising an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film. The first conductive film includes a region in contact with the oxide semiconductor film. The second conductive film includes a region in contact with the oxide semiconductor film. The third conductive film includes a region that overlaps with the oxide semiconductor film via an insulating film. The transistor has a maximum value of the field-effect mobility of the transistor, wherein the gate voltage is higher than 0V and 10V or less, and the maximum value is 10cm 2 / Vs over 100cm 2 Region less than / Vs, region where the threshold voltage is between -1V and 1V, region where the S value is less than 0.3V / decade, and off-state current is 1×10 -12 A / cm 2 Includes a region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g In the case where =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 3 or more and less than 10.

[0023] One embodiment of the present invention is a semiconductor device comprising a transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. The transistor has a maximum value of field-effect mobility of 10 cm², wherein the gate voltage is higher than 0 V and 10 V or less. 2 / Vs over 100cm 2 Region less than / Vs, region where the threshold voltage is between -1V and 1V, region where the S value is less than 0.3V / decade, and off-state current is 1×10 -12 A / cm 2 Includes a region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g In the case where =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 3 or more and less than 10.

[0024] In the above-described embodiment, the oxide semiconductor film has a density of shallow defect levels of 2.0 × 10⁻⁶ -12 cm -2 3.0×10 -12 cm -2 It is desirable to include an area less than [value].

[0025] In the above-described embodiment, the oxide semiconductor film comprises a composite oxide semiconductor in which a first region and a second region are mixed, wherein the first region comprises a plurality of first clusters comprising one or more selected from indium, zinc, and oxygen as main components, and the second region comprises indium, element M It comprises a plurality of second clusters comprising one or more selected from zinc and oxygen as main components, and said element M The material is Al, Ga, Y, or Sn, and the first region includes a portion where a plurality of first clusters are connected to each other, and the second region includes a portion where a plurality of second clusters are connected to each other.

[0026] In the form described above, indium, element M The atomic ratio of , and zinc is In: M :Zn=4:2:3 or a neighborhood of 4:2:3, and if In is 4, the element M It is preferable that [value] is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less. In the above-described form, indium, element M The atomic ratio of , and zinc is In: M If :Zn=5:1:6 or the vicinity of 5:1:6 and In is 5, M It is preferable that the value is 0.5 or more and 1.5 or less, and that Zn is 5 or more and 7 or less.

[0027] In the above-described form, it is preferable that the first cluster has electrical conductivity and the second cluster has electrical semiconductor properties.

[0028] In the above-described form, it is preferable that each first cluster includes a portion of 0.5 nm or more and 1.5 nm or less.

[0029] One embodiment of the present invention is a display device comprising a display element and a semiconductor device of any one of the above-described forms. One embodiment of the present invention is a display module comprising a display device and a touch sensor. One embodiment of the present invention is an electronic device comprising a semiconductor device of any one of the above-described forms, a display device, or a display module, and an operating key or a battery. One embodiment of the present invention is an electronic device comprising a semiconductor device of any one of the above-described forms and an inverter or a converter. Effects of the invention

[0030] One embodiment of the present invention can improve the field-effect mobility and reliability of a transistor comprising an oxide semiconductor film. One embodiment of the present invention can prevent changes in electrical characteristics in a transistor comprising an oxide semiconductor film and can improve the reliability of the transistor. One embodiment of the present invention can provide a semiconductor device with low power consumption. One embodiment of the present invention can provide a semiconductor device with good electrical characteristics. One embodiment of the present invention can provide a novel oxide semiconductor. One embodiment of the present invention can provide a novel semiconductor device. One embodiment of the present invention can provide a novel display device.

[0031] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment of the present invention is not required to achieve all of the effects described above. Other effects will become apparent and can be derived from the description in the specification, drawings, and claims, etc. Brief explanation of the drawing

[0032] Figure 1 shows a transistor's I d - V g It represents the characteristics. Figure 2 shows the transistor's I d - V g It represents the characteristics. Figure 3 shows the transistor'sI d - V g It represents the characteristics. Figures 4 (A) and (B) are a top view and a cross-sectional view illustrating a composite oxide semiconductor. Figures 5 (A) and (B) are a top view and a cross-sectional view illustrating a composite oxide semiconductor. Figures 6 (A) and (B) are a top view and a cross-sectional view illustrating a composite oxide semiconductor. Figures 7 (A) and (B) are a top view and a cross-sectional view illustrating a composite oxide semiconductor. Figure 8 shows the atomic ratio of oxide semiconductors. Figures 9 (A) and (B) illustrate a sputtering apparatus. Figure 10 is a process flow diagram showing a method for fabricating a composite oxide semiconductor. Figures 11 (A) and (B) show cross-sections near the target. Figures 12 (A) and (B) show cross-sections near the target. Figure 13 shows the HAADF-STEM observation. Figures 14 (A) and (B) of the transistor I d - V g Characteristics and I d - V d It represents the characteristics. Figure 15 is calculated based on GCA I d - V g This shows the characteristics and linear and saturated mobility curves. FIG. 16 is a FET including CAAC-OS. I d - V g This shows the curves of characteristics and electric field effect mobility. Figure 17 (A) is a top view of a transistor, and Figures 17 (B) and 17 (C) are cross-sectional views of a transistor. Figure 18 is a schematic diagram illustrating the concept of the effective channel length of a transistor. Figures (A) to (C) of Fig. 19 are schematic diagrams illustrating donor densities. Fig. 20 is I d - V g It represents the characteristics. Fig. 21 is I d - V g It represents the characteristics. Figure 22 shows the calculation results of the density of the interface level. Figures 23 (A) and (B) are I d - V g It represents the characteristics. Figure 24 shows the shape of the mobility curve. Fig. 25 is I d - V g This is a schematic diagram showing the contribution of drift current and diffusion current to the characteristics. FIG. 26 shows BGTC dual-gate FETs each including CAAC-OS when sDOS is not assumed. I d - V g This shows the characteristic and mobility curves. Figure 27 is a band diagram in the thickness direction. FIG. 28 shows BGTC dual-gate FETs each including CAAC-OS when sDOS is assumed. I d - V g This shows the characteristic and mobility curves. Figure 29 shows the dependence of the IGZO film thickness on the field-effect mobility (maximum value). Figures 30 (A) and (B) illustrate the shape of the sDOS distribution and mobility curve in an IGZO film. Figure 31 (A) is a circuit diagram showing a resistor and an FET, and Figure 31 (B) is a graph showing the relationship between the source and drain regions formed by reducing the resistance of the channel region and the field-effect mobility. Figure 32 is a graph showing the saturation mobility when mobility depends on temperature. Figure 33 shows the saturation mobility curve of the FET. Figure 34 is a graph illustrating the effect of a reduction in effective channel length on the shape of the mobility curve. Figures 35 (A) to (C) show mobility curves obtained by device simulation under different conditions. Figures 36 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 37 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 38 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 39 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 40 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 41 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 42 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 43 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 44 (A) to (C) show the band structure. Figures 45 (A) to (C) are top and cross-sectional views illustrating a semiconductor device. Figures 46 (A) to (C) are top and cross-sectional views illustrating a semiconductor device. Figures 47 (A) to (C) are top and cross-sectional views illustrating a semiconductor device. Figures 48 (A) to (C) are top and cross-sectional views illustrating a semiconductor device. Figures 49 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 50 (A) and (B) are cross-sectional views illustrating a semiconductor device. Figures 51 (A) to (C) are top and cross-sectional views illustrating a semiconductor device. FIG. 52 is a top view illustrating one form of a display device. FIG. 53 is a cross-sectional view illustrating one form of a display device. FIG. 54 is a cross-sectional view illustrating one form of a display device. FIG. 55 is a cross-sectional view illustrating one form of a display device. FIG. 56 is a cross-sectional view illustrating one form of a display device. FIG. 57 is a cross-sectional view illustrating one form of a display device. Figures 58 (A) to (D) are cross-sectional views illustrating a method for forming an EL layer. FIG. 59 is a conceptual diagram illustrating a droplet discharge device. Figures 60 (A) to (C) are block diagrams and circuit diagrams illustrating a display device. Figure 61 illustrates a display module. Figures 62 (A) to (E) illustrate electronic devices. Figures 63 (A) to (G) illustrate electronic devices. Figures 64 (A) to (E) illustrate electronic devices. Figures 65 (A) and (B) are perspective views illustrating a display device. Figures 66 (A) and (B) are perspective views illustrating a display device. Figures 67 (A) and (B) are circuit diagrams of a semiconductor device of one type, respectively. Figure 68 illustrates the cross-sectional structure of a semiconductor device of one type. Figure 69 illustrates the cross-sectional structure of a semiconductor device of one type. FIG. 70 is a circuit diagram illustrating a memory device of one form of the present invention. FIG. 71 is a circuit diagram illustrating a memory device of one form of the present invention. Figures 72 (A) to (C) are circuit diagrams and timing charts illustrating one embodiment of the present invention. Figures 73 (A) to (C) are graphs and circuit diagrams illustrating one embodiment of the present invention. Figures 74 (A) and (B) are a circuit diagram and a timing chart illustrating one embodiment of the present invention. Figures 75 (A) and (B) are a circuit diagram and a timing chart illustrating one embodiment of the present invention. FIGS. 76 (A) to (E) are block diagrams, circuit diagrams, and waveform diagrams illustrating one embodiment of the present invention. Figures 77 (A) and (B) are a circuit diagram and a timing chart illustrating one embodiment of the present invention. Figures 78 (A) and (B) are circuit diagrams illustrating one embodiment of the present invention. Figures 79 (A) to (C) are circuit diagrams illustrating one embodiment of the present invention. Figures 80 (A) and (B) are circuit diagrams illustrating one embodiment of the present invention. Figures 81 (A) to (C) are circuit diagrams illustrating one embodiment of the present invention. Figures 82 (A) and (B) are circuit diagrams illustrating one embodiment of the present invention. FIG. 83 is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 84 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. Figures 85 (A) and (B) are top views illustrating a semiconductor device of one embodiment of the present invention. Figures 86 (A) and (B) are a flowchart and a perspective view of a semiconductor device illustrating one embodiment of the present invention. Figures 87 (A) to (C) are perspective views illustrating an electronic device of one embodiment of the present invention. Figures 88 (A) to (E) show planar HAADF-STEM images and EDX mapping images. Figures 89 (A) to (E) show cross-sectional HAADF-STEM images and EDX mapping images. Figure 90 shows the transistor's I d - V g It represents the characteristics. Specific details for implementing the invention

[0033] Hereinafter, embodiments will be described with reference to the drawings. However, it is readily understood by those skilled in the art that embodiments can be executed in many different modes, and that the modes and details thereof can be varied without departing from the spirit and scope of the present invention. Accordingly, the present invention is not to be interpreted as being limited to the description of the embodiments below.

[0034] In the drawings, sizes, layer thicknesses, or areas may be exaggerated for clarity. Accordingly, the embodiments of the present invention are not limited to such scale. Furthermore, the drawings are schematic diagrams illustrating ideal examples, and the embodiments of the present invention are not limited to the shapes or values ​​shown in the drawings.

[0035] In addition, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion among the components, and these terms do not numerically limit the components.

[0036] Furthermore, terms describing arrangements in this specification, such as "above," "on top," "below," and "under," are used for convenience in describing the positional relationships between components with reference to the drawings. Additionally, the positional relationships between components vary appropriately depending on the direction in which each component is described. Therefore, positional relationships are not limited to those described by the terms used in this specification and may be described using other appropriate terms depending on the situation.

[0037] In the present specification and others, a transistor is a device having at least three terminals, a gate, a drain, and a source. Additionally, the transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the drain and the source through the channel region. Furthermore, in the present specification and others, a channel region refers to a region through which current mainly flows.

[0038] In addition, the functions of the source and drain can be switched, for example, by employing transistors having different polarities, or when the direction of current flow changes during circuit operation. Therefore, the terms "source" and "drain" may be switched in this specification, etc.

[0039] Furthermore, in this specification and others, the expression "electrically connected" includes cases where components are connected through "an object having some electrical action." There are no specific limitations on "an object having some electrical action," as long as electrical signals can be transmitted and received between components connected through the object. Examples of "an object having some electrical action" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and components having various functions.

[0040] In this specification and others, the term "parallel" indicates that the angle formed between two straight lines is between -10° and 10°, and thus includes cases where the angle is between -5° and 5°. The term "perpendicular" indicates that the angle formed between two straight lines is between 80° and 100°, and thus includes cases where the angle is between 85° and 95°.

[0041] In this specification and others, the terms "film" and "layer" may be interchangeable. For example, the term "conductive layer" may be changed to the term "conductive film." or, There are cases where the term "insulating film" can be changed to the term "insulating layer."

[0042] Unless otherwise specified, the off-state current in this specification, etc. refers to the drain current of a transistor in the off-state (also referred to as the non-conduction state and cut-off state). Unless otherwise specified, the off-state of an n-channel transistor refers to the voltage between its gate and source ( V gs ) is the threshold voltage ( V th It means lower than ), and the off state of the p-channel transistor is the gate-source voltage ( V gs ) is the threshold voltage ( V th It means that it is higher than ). For example, the off-state current of an n-channel transistor is the gate-source voltage ( V gs ) is the threshold voltage ( V th There are cases where it refers to the drain current flowing when it is lower than ).

[0043] The off-state current of the transistor is V gs There are cases where it depends on. Therefore, "the off-state current of the transistor is I "Below" means, "the off-state current of the transistor I becoming less than Vgs It means that "there is." Also, "transistor off-state current" refers to "a predetermined V gs "Off-state current during the off-state at", "within a predetermined range" V gs "Off-state current during the off-state", or "a sufficiently reduced off-state current is obtained" V gs It means "off-state current during the off-state", etc.

[0044] As an example, threshold voltage ( V th ) is 0.5V, and the drain current is V gs 1×10⁻⁶ at 0.5V -9 A, V gs 1×10⁻⁶ at 0.1V -13 A, V gs 1×10⁻⁶ at -0.5V -19 A, and V gs 1×10⁻⁶ at -0.8V -22 Let us assume an n-channel transistor A. The drain current of the said transistor is V gs At -0.5V or V gs 1×10 in the range of -0.8V to -0.5V -19 Since it is less than or equal to A, the off-state current of the above transistor is 1×10 -19 It can be said to be less than A. The drain current of the above transistor is 1×10 -22 A or less V gs Because of this, the off-state current of the above transistor is 1×10 -22 There are cases where it is said to be A or lower.

[0045] In the present specification, etc., the channel width ( W The off-state current of a transistor with ) channel width ( WThere are cases where the current value is expressed as a value per ) or a value per a predetermined channel width (e.g., 1 μm). In the latter case, the off-state current can be expressed in a unit having the dimension of current per length (e.g., A / μm).

[0046] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60°C, 85°C, 95°C, or 125°C. Alternatively, the off-state current may be an off-state current at a temperature where reliability required for a semiconductor device, etc., including said transistor is guaranteed, or at a temperature in which the semiconductor device, etc., including said transistor is used (e.g., a temperature in the range of 5°C to 35°C). "The off-state current of a transistor I The description "below" refers to the off-state current of the transistor at room temperature, 60°C, 85°C, 95°C, 125°C, a temperature at which reliability required for a semiconductor device including the transistor, etc. is guaranteed, or a temperature at which the semiconductor device including the transistor, etc. is used (e.g., a temperature in the range of 5°C to 35°C). I Lee Ha-in V gs There are cases where it refers to a situation where there is.

[0047] The off-state current of a transistor is the voltage between the drain and the source ( V ds There are cases where it depends on ). Unless otherwise specified, the off-state current in this specification is, V ds There may be cases where the off-state current is at 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, the off-state current is such that the reliability required for a semiconductor device including the transistor is guaranteed. V ds, or used in a semiconductor device including the above transistor, etc. V ds It may be the off-state current at. The statement "the off-state current of the transistor is I or less" is, V ds 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V, a semiconductor device including the above transistor, etc., having required reliability V ds , or a semiconductor device including the above transistor is used V ds In which the transistor's off-state current is less than or equal to I V gs There are cases where it refers to a situation where there is.

[0048] In the above description of the off-state current, the drain can be substituted with the source. That is, the off-state current may refer to the current flowing through the source of a transistor in the off state.

[0049] In this specification and others, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification and others, off-state current may refer, for example, to the current flowing between the source and the drain when the transistor is off.

[0050] In the present specification, etc., the threshold voltage of a transistor refers to the gate voltage at which a channel is formed in the transistor ( V g It refers to ). Specifically, the horizontal axis is the gate voltage ( V g It represents ) and the vertical axis is the drain current ( I d In the graph showing the square root of ), the threshold voltage of the transistor is the drain current ( I d The square root of ) is 0( I d When =0A), and the plotted curve (V g -√ I d Gate voltage at the intersection of the extrapolated line that is the tangent to the maximum slope of the characteristic ( V g ...can be said. Or, the threshold voltage of a transistor is, L set as the channel length and W as the channel width I d [A]× L [μm] / W The value of [μm] is 1×10 -9 [A] gate voltage ( V g Can say ).

[0051] In the present specification, etc., a "semiconductor" may have the characteristics of an "insulator," for example, when its conductivity is sufficiently low. Furthermore, since the boundary between a "semiconductor" and an "insulator" is not clear, there are cases where they cannot be strictly distinguished from one another. Therefore, in the present specification, etc., a "semiconductor" may be referred to as an "insulator." Likewise, in the present specification, etc., an "insulator" may be referred to as a "semiconductor." In the present specification, etc., an "insulator" may be referred to as a "semi-insulator."

[0052] In the present specification, etc., a "semiconductor" may have the characteristics of a "conductor," for example, when its conductivity is sufficiently high. Furthermore, since the boundary between a "semiconductor" and a "conductor" is not clear, there are cases where they cannot be strictly distinguished from one another. Therefore, in the present specification, etc., a "semiconductor" may be referred to as a "conductor." Likewise, in the present specification, etc., a "conductor" may be referred to as a "semiconductor."

[0053] In the present specification and others, impurities in a semiconductor refer to elements that are not the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic% are impurities. If a semiconductor contains impurities, for example, a density of states (DOS) may be formed within the semiconductor, carrier mobility may be reduced, or crystallinity may be degraded. When the semiconductor includes an oxide semiconductor, examples of impurities that change the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specific examples include hydrogen (which is also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is an oxide semiconductor, oxygen vacancies may be formed by the introduction of impurities such as hydrogen, for example. Furthermore, when the semiconductor includes silicon, examples of impurities that change the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements other than oxygen and hydrogen.

[0054] (Embodiment 1)

[0055] In this embodiment, a semiconductor device of one form of the present invention is described with reference to (C) of FIGS. 1 to 35.

[0056] One embodiment of the present invention is a semiconductor device comprising a transistor. The transistor comprises a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film comprises a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other.

[0057] The above transistor has a maximum field-effect mobility of 40 cm at a gate voltage greater than 0 V and less than or equal to 10 V. 2 / Vs over 150cm 2 A first region less than / Vs, a second region where the threshold voltage is between -1V and 1V, a third region where the S value is less than 0.3V / decade, and an off-state current of 1×10 -12 A / cm 2 It includes a fourth region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g When =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) becomes 1 or more and less than 1.5.

[0058] In the above transistor, μ FE (max) / μ FE ( V g There are cases where =2V) is 1.5 or more and less than 3.

[0059] The above structure may also be described as follows. A semiconductor device of one embodiment of the present invention is a transistor in which an oxide semiconductor film is included in the channel region and has excellent field-effect mobility, threshold voltage, off-state current, and S value. Such a semiconductor device can be suitably used as a transistor of a pixel of an organic EL display or as a transistor of a driving circuit of an organic EL display.

[0060] The above transistor has a maximum field-effect mobility of 10 cm at a gate voltage greater than 0 V and less than or equal to 10 V. 2 / Vs over 100cm 2A first region less than / Vs, a second region where the threshold voltage is between -1V and 1V, a third region where the S value is less than 0.3V / decade, and an off-state current of 1×10 -12 A / cm 2 It includes a fourth region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g When =2V) represents the value of the transistor's field-effect mobility at a gate voltage of 2V, μ FE (max) / μ FE ( V g =2V) may be 3 or more and less than 10.

[0061] The above structure may also be described as follows. A semiconductor device of one embodiment of the present invention is a transistor in which an oxide semiconductor film is included in the channel region, and the transistor has high reliability because it has high heat resistance and high stability of physical properties. Such a semiconductor device can be suitably used as a power device. For example, such a semiconductor device can be suitably used as a semiconductor device in a power converter such as an inverter or a converter. As another example, such a semiconductor device can be used for inverter control in electric vehicles, hybrid vehicles, or air conditioners, or for various general-purpose motors. In this embodiment, an oxide semiconductor of one embodiment of the present invention will be described.

[0062] <1-1. Oxide Semiconductor Film>

[0063] First, an oxide semiconductor film that can be used in a transistor of one form of the present invention will be described with reference to FIGS. 4 (A) to FIGS. 13.

[0064] It is preferable that indium be included in the oxide semiconductor film. In particular, it is preferable that indium and zinc be included. It is also preferable that aluminum, gallium, yttrium, or tin be included. In addition, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

[0065] Here, the oxide semiconductor film is indium, element M Consider the case involving , and zinc. Element M These are aluminum, gallium, yttrium, or tin, etc. Element M Other elements that can be used as include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In addition, the element M As such, two or more of the aforementioned elements may be used in combination. Indium included in the oxide semiconductor film, element M , and the terms for the ratio of the number of atoms of zinc are [In], [ M It was represented as ], and [Zn].

[0066] <1-2. Structure of Oxide Semiconductor Films>

[0067] Figures 4 (A) and (B) are schematic diagrams of an oxide semiconductor film in one embodiment of the present invention.

[0068] Figure 4 (A) is a schematic diagram of the upper surface (ab-plane direction) of an oxide semiconductor film, and Figure 4 (B) is a schematic diagram of the cross-section (c-axis direction) of an oxide semiconductor film formed on a substrate (Sub).

[0069] Figures 4 (A) and (B) illustrate examples in which an oxide semiconductor film is formed on a substrate, but one embodiment of the present invention is not limited to this example, and an insulating film such as a lower film or an interlayer film, or other semiconductor films such as an oxide semiconductor film, may be formed between the substrate and the oxide semiconductor film.

[0070] An oxide semiconductor film of one embodiment of the present invention is a composite oxide semiconductor having a structure in which regions (A1) and regions (B1) are mixed, as shown in (A) and (B) of FIG. 4. Therefore, in the following description, the oxide semiconductor film may be referred to as a composite oxide semiconductor.

[0071] The region (A1) shown in (A) and (B) of FIG. 4 is, [In]:[ M ]:[Zn]= x : y : z ( x >0, y In is high (≥0, z≥0). Meanwhile, region (B1) is [In]:[ M ]:[Zn]= a : b : c ( a >0, b ≥0, c In is low as ≥0.

[0072] Also, in this specification, for example, elements of region (A1) M The atomic ratio of In to the elements of region (B1) M When the ratio of the number of atoms of In to the region (A1) is greater than that of the region (B1), the concentration of In in the region (A1) is higher than that of the region (B1). Therefore, in this specification, the region (A1) is also referred to as the In-rich region and the region (B1) is also referred to as the In-poor region.

[0073] For example, the In concentration in region (A1) is at least 1.1 times, preferably 2 to 10 times, the In concentration in region (B1). Region (A1) is an oxide containing at least In, and the element M It is not necessary to include Zn.

[0074] Here, the atomic ratio of elements included in a composite oxide semiconductor of one form of the present invention is described.

[0075] In a composite oxide semiconductor, the region (A1) is In, element M In the case including , and Zn, the phase diagram of FIG. 8 can be used to represent the atomic ratios of the elements. In, element M The ratio of the atomic numbers of , and Zn x : y : z It is represented as. The ratio of atomic numbers is a coordinate ( x : y : z This is shown in Fig. 8. Also, the ratio of oxygen atoms is not shown in Fig. 8.

[0076] In Fig. 8, the dashed line is [In]:[ M ]:[Zn] = ( 1+α):(1-α):1(-1≤α≤1 Line indicating the atomic ratio of ), [In]:[ M ]:[Zn] =( 1+ α) : (1-α):2 Line indicating the atomic ratio of, [In]:[ M ]:[Zn] =( 1+ α) : ( 1- α) : 3 Line indicating the atomic ratio of, [In]:[ M ]:[Zn] =( 1+ α) : (1-α) : 4 Lines indicating the atomic ratio of, and [In]:[ M ]:[Zn] =( 1+ α) : (1-α) : 5 It corresponds to the line representing the atomic ratio of.

[0077] The dashed line is, [In]:[ M ]:[Zn]=1:1:β(β=0) line representing the atomic number ratio, [In]:[ M]:[Zn]=1:2:β line representing the atomic number ratio, [In]:[ M ]:[Zn]=1:3:β line representing the atomic number ratio, [In]:[ M ]:[Zn]=1:4:β line representing the atomic number ratio, [In]:[ M ]:[Zn]=1:7:β line representing the atomic number ratio, [In]:[ M Lines representing the atomic number ratio of ]:[Zn]=2:1:β, and [In]:[ M ]:[Zn]=5:1:β corresponds to the line representing the atomic number ratio.

[0078] In Fig. 8, [In]:[ M Oxide semiconductors with an atomic ratio of ]:[Zn]=0:2:1 or nearby tend to have a spinel crystal structure.

[0079] Region (A2) in FIG. 8 is the indium element included in region (A1). M This shows an example of a desirable range for the ratio of the atomic number of , and zinc. Also, region (A2) is [In]:[ M ]:[Zn]= ( 1+γ ) :0 :(1- γ )(-1≤ γ ≤1) Includes the atomic ratio on the line representing the atomic ratio of.

[0080] Region (B2) in FIG. 8 is the indium element included in region (B1). M This shows an example of a desirable range for the ratio of the atomic number of , and zinc. Also, region (B2) is [In]:[ M ]:[Zn]=4:2:3 to [In]:[ M Includes ]:[Zn]=4:2:4.1 and the atomic number ratios in the vicinity. The above vicinity includes [In]:[ M The atomic ratio of ]:[Zn]=5:3:4 is included. Region (B2) is [In]:[ M ]:[Zn]=5:1:6 and includes the atomic ratios in the vicinity.

[0081] The region (A2) with a high In concentration has higher conductivity than region (B2) and has the function of increasing carrier mobility (field-effect mobility). Therefore, the on-state current and carrier mobility of a transistor using an oxide semiconductor film including region (A1) can be increased.

[0082] Meanwhile, the region (B2) with a low In concentration has lower conductivity than region (A2) and has the function of reducing leakage current. Therefore, the off-state current of a transistor using an oxide semiconductor film including region (B1) can be reduced.

[0083] In an oxide semiconductor film of one embodiment of the present invention, region (A1) and region (B1) form a composite. That is, carrier movement occurs easily in region (A1), while carrier movement does not occur easily in region (B1). Therefore, the oxide semiconductor of one embodiment of the present invention can be used as a material having high carrier mobility, excellent switching characteristics, and good semiconductor characteristics.

[0084] For example, as shown in (A) of FIG. 4, a plurality of regions (A1) exist in a particle shape (cluster shape) in the ab-plane direction and the c-axis direction. Additionally, the clusters may be unevenly and irregularly dispersed. A plurality of clusters may overlap with each other or be connected to each other. For example, a shape containing a cluster that overlaps with another cluster may be connected to each other, and the region (A1) may be observed to expand in a cloud-like manner.

[0085] In addition, if all regions (A1) are connected in the direction of the ab plane, the switching characteristics of the transistor deteriorate (for example, the off-state current of the transistor increases), so as shown in (A) and (B) of FIG. 4, it is preferable for regions (A1) to be located in regions (B1). Accordingly, regions (A1) can exist in a state where they are three-dimensionally surrounded by regions (B1). That is, regions (A1) are surrounded by regions (B1).

[0086] Area (B1) may be considered to have a structure that includes a cluster (also called a first cluster) included in area (A1) and another cluster (also called a second cluster). In the above structure, area (B1) includes a plurality of second clusters and includes a portion where the second clusters are connected to each other. In other words, the first cluster included in area (A1) includes a portion where the first cluster and another first cluster are connected to each other in the cloud, and the second cluster included in area (B1) includes a portion where the second cluster and another second cluster are connected to each other in the cloud.

[0087] Additionally, the proportion of the scattered region (A1) can be adjusted, for example, by changing the formation conditions or composition of the composite oxide semiconductor. For example, a composite oxide semiconductor with a low proportion of region (A1) or a composite oxide semiconductor with a high proportion of region (A1) can be formed. For example, FIGS. 5 (A) and (B) show a composite oxide semiconductor with a lower proportion of region (A1) than the proportion of region (A1) of the composite oxide semiconductor shown in FIGS. 4 (A) and (B). FIGS. 5 (A) is a schematic diagram corresponding to FIGS. 4 (A), and FIGS. 5 (B) is a schematic diagram corresponding to FIGS. 4 (B). In one embodiment of the composite oxide semiconductor of the present invention, the proportion of region (A1) is not always lower than the proportion of region (B1). In a composite oxide semiconductor with a very high proportion of region (A1), region (B1) may be formed in region (A1) depending on the observation range. The size of the particle region of region (A1) can be appropriately adjusted, for example, by changing the formation conditions or composition of the composite oxide semiconductor.

[0088] The boundary between region (A1) and region (B1) may not be clearly observed. The size of region (A1) and region (B1) EDX( energy dispersive X-ray spectroscopy obtained by ) It can be measured using an EDX mapping image. For example, the diameter of the cluster in area (A1) may be 0.1 nm or more and 2.5 nm or less in the EDX mapping image of a cross-sectional or planar photograph. Additionally, it is preferable that the diameter of the cluster be 0.5 nm or more and 1.5 nm or less.

[0089] As described above, an oxide semiconductor of one embodiment of the present invention is a composite oxide semiconductor having a region (A1) and a region (B1) mixed together and having other complementary functions. For example, an oxide semiconductor of one embodiment of the present invention is an element MIn the case where Ga is used as an In-Ga-Zn oxide (hereinafter referred to as IGZO), one form of the oxide semiconductor of the present invention may be called Complementary IGZO (abbreviated as C / IGZO).

[0090] Meanwhile, when region (A1) and region (B1) are stacked in layers, for example, since there is no interaction between region (A1) and region (B1) or it is difficult for such interaction to occur, the function of region (A1) and the function of region (B1) may be performed independently. In this case, even if the carrier mobility is increased by region (A1), the off-state current of the transistor may increase. Therefore, when the oxide semiconductor of one embodiment of the present invention is the aforementioned composite oxide semiconductor or C / IGZO, the function of achieving high carrier mobility and the function of achieving excellent switching characteristics can be obtained simultaneously. This is an advantageous effect obtained by using the composite oxide semiconductor of one embodiment of the present invention.

[0091] Furthermore, when oxide semiconductors are deposited using a sputtering device, a film is formed with an atomic ratio that deviates from that of the target. Particularly for zinc, depending on the substrate temperature during deposition, the atomic ratio of [Zn] in the deposited film may be smaller than that of the target.

[0092] Furthermore, the characteristics of a composite oxide semiconductor of one embodiment of the present invention are not uniquely determined by the atomic ratio. Accordingly, the illustrated region represents the preferred atomic ratio of region (A1) and region (B1) of the composite oxide semiconductor, and the boundary between them is not clear.

[0093] The oxide semiconductor according to the present invention is not limited to the above description. FIGS. 6 (A) and (B) and FIGS. 7 (A) and (B) are schematic diagrams of oxide semiconductor films having a structure different from the oxide semiconductor film structure described above. FIGS. 6 (A) and FIGS. 7 (A) are schematic diagrams of the top surface (ab-plane direction) of a composite oxide semiconductor. FIGS. 6 (B) and FIGS. 7 (B) are schematic diagrams of the cross-section (c-axis direction) of a composite oxide semiconductor formed on a substrate, respectively. In addition, regarding the structure of the oxide semiconductor film shown in FIGS. 6 (A) and (B) and FIGS. 7 (A) and (B), reference may be made to the description of the structure of the oxide semiconductor film shown in FIGS. 4 (A) and (B), excluding the points described later.

[0094] Oxide semiconductors are broadly classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), amorphous-like oxide semiconductor (a-like OS), and amorphous oxide semiconductor.

[0095] CAAC-OS has c-axis orientation, nanocrystals are connected in the ab plane direction, and the crystal structure is strained. Also, In CAAC-OS Deformation is the part where the direction of the grid arrangement changes between a region with a uniform grid arrangement and another region with a uniform grid arrangement.

[0096] In FIG. 6 (A) and FIG. 7 (A), multiple nanocrystals are schematically represented by dashed lines. The shape of the nanocrystals is basically hexagonal. However, the shape is not necessarily a regular hexagon, and there are cases where it is a non-regular hexagon. Variations may include polygonal nanocrystals such as pentagonal nanocrystals or heptagonal nanocrystals.

[0097] Furthermore, distinct grain boundaries cannot be observed even near the deformation of CAAC-OS. In other words, the formation of grain boundaries is suppressed by the deformation of the lattice arrangement. This is thought to be because CAAC-OS allows for deformation due to factors such as the low density of oxygen atoms in the ab plane direction and changes in interatomic bond distances caused by the substitution of metal elements.

[0098] In addition, FIG. 6(B) and FIG. 7(B) schematically illustrate that the nanocrystals have a c-axis orientation and are oriented in a direction substantially perpendicular to the c-axis with respect to the surface on which the CAAC-OS film is formed (also referred to as the formation surface) or the upper surface of the CAAC-OS film. The CAAC-OS has a layered crystal structure (also referred to as a layered structure) having a c-axis orientation, and comprises a layer containing indium and oxygen (hereinafter referred to as the In layer), and an element M A layer containing , zinc, and oxygen (hereinafter, ( M It includes a stacked structure of (called a Zn layer).

[0099] In addition, indium and elements M There are cases where they are substituted for each other. Therefore, ( M Elements of the , Zn) layer M If a portion of is replaced with indium, the above layer (In, M It can also be called a layer (, Zn). In this case, the In layer and (In, M , Zn) layers are stacked in a layered structure.

[0100] In nc-OS, minute regions (e.g., regions of size from 1 nm to 10 nm, particularly regions of size from 1 nm to 3 nm) have a periodic atomic arrangement. In nc-OS, there is no regularity of crystal orientation between different nanocrystals. Therefore, the orientation of the entire film is not observed. Consequently, depending on the analysis method, nc-OS cannot be distinguished from a-like OS or amorphous oxide semiconductors.

[0101] a-like OS has a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. In other words, a-like OS has an unstable structure compared to nc-OS and CAAC-OS.

[0102] Oxide semiconductors have various structures and various properties. The oxide semiconductor of the present invention may be a composite oxide semiconductor comprising two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS. Region (A1) and region (B1) may have different crystallinities.

[0103] For example, it is preferable that the region (A1) is a single crystal. Also, if the region (A1) has crystallinity, and the region (A1) is formed of indium, the region (A1) tends to have a tetragonal structure. Also, if the region (A1) is indium oxide ([In]:[ M ]:[Zn]= x :0:0( x If formed as >0)), the region (A1) tends to have a bixbyite crystal structure. In addition, if the region (A1) is an In-Zn oxide ([In]:[ M ]:[Zn]= x :0: z ( x >0, z When formed as >0)), the region (A1) tends to have a layered crystal structure.

[0104] Region (B1) includes CAAC-OS. Additionally, region (B1) does not need to include only CAAC-OS, but may include regions such as polycrystalline oxide semiconductor or nc-OS.

[0105] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, since distinct grain boundaries cannot be observed in CAAC-OS, a decrease in electron mobility caused by grain boundaries is unlikely to occur. The intrusion of impurities or the formation of defects can degrade the crystallinity of oxide semiconductors. This implies that CAAC-OS contains low amounts of impurities and defects (e.g., oxygen vacancies). Therefore, by incorporating CAAC-OS, the composite oxide semiconductor becomes physically stable, enabling the provision of a heat-resistant and highly reliable composite oxide semiconductor.

[0106] Additionally, the proportion of the scattered region (A1) can be adjusted, for example, by changing the formation conditions or composition of the composite oxide semiconductor. For example, as shown in (A) and (B) of FIG. 7, a composite oxide semiconductor with a low proportion of region (A1) or a composite oxide semiconductor with a high proportion of region (A1) can be formed.

[0107] <1-3. Transistor containing an oxide semiconductor film>

[0108] Next, the case in which the aforementioned oxide semiconductor film is used in a transistor will be explained.

[0109] By using composite oxide semiconductors in transistors, the transistors can have high carrier mobility and high switching characteristics. In addition, the transistors can have high reliability.

[0110] Oxide semiconductor films with low carrier density are desirable for use in transistors. For example, a carrier density of 8×10 11 / cm 3 Less than, preferably 1×10 11 / cm 3 Less than, or more preferably 1×10 10 / cm 3 Less than and 1×10 -9 / cm 3 The oxide semiconductor film of the above is used as an oxide semiconductor film.

[0111] To reduce the carrier density of an oxide semiconductor film, the density of defect levels can be reduced by lowering the impurity concentration of the oxide semiconductor film. In this specification and other contexts, a state in which the impurity concentration is low and the density of defect levels is low is referred to as a state of high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor film that is of high purity intrinsic or substantially high purity intrinsic may have a low carrier density because it has few carrier generation sources. Since an oxide semiconductor film that is of high purity intrinsic or substantially high purity intrinsic has a low density of defect levels, it may have a low density of trap levels.

[0112] Charges trapped by trap levels in oxide semiconductor films take a long time to be emitted and can act like fixed charges. Therefore, transistors in which channel regions are formed in oxide semiconductor films with a high trap level density may exhibit unstable electrical characteristics.

[0113] To obtain stable electrical characteristics of a transistor, it is effective to reduce the impurity concentration within the oxide semiconductor film. To reduce the impurity concentration in the oxide semiconductor film, it is desirable to reduce the impurity concentration in the film adjacent to the oxide semiconductor film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0114] Here, the influence of impurities in oxide semiconductor films is explained.

[0115] When silicon or carbon, which are Group 14 elements, are incorporated into an oxide semiconductor film, defect levels are formed. Therefore, the concentration of silicon or carbon in the oxide semiconductor and near the interface with the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) is 2×10⁻⁶ 18 atoms / cm 3 Below, preferably 2×1017 atoms / cm 3 Set to the following.

[0116] If an oxide semiconductor film contains alkali metals or alkaline earth metals, defect levels may be formed and carriers may be generated. Therefore, a transistor containing an oxide semiconductor film containing alkali metals or alkaline earth metals is prone to becoming a normaly-on. Accordingly, it is desirable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor film. Specifically, the concentration of alkali metals or alkaline earth metals within the oxide semiconductor film measured by SIMS is 1×10⁻⁶ 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 Set to the following.

[0117] If an oxide semiconductor film contains nitrogen, the oxide semiconductor film is prone to becoming n-type due to the generation of electrons functioning as carriers and an increase in carrier density. Therefore, a transistor containing a nitrogen-containing oxide semiconductor is prone to becoming a normal ion. For this reason, it is desirable to reduce the nitrogen in the oxide semiconductor as much as possible, and the nitrogen concentration measured by SIMS is, for example, 5×10 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 Set to the following.

[0118] Since hydrogen contained in oxide semiconductor films reacts with oxygen bonded to metal atoms to form water, oxygen vacancies (V o There are cases where it causes ). Oxygen vacancies (V oThere are cases where electrons functioning as carriers are generated due to hydrogen entering the region. Additionally, there are cases where electrons functioning as carriers are generated when a portion of the hydrogen combines with oxygen bonded to metal atoms. Therefore, transistors containing oxide semiconductors containing hydrogen are prone to becoming normal ions. Consequently, it is desirable to reduce the hydrogen content within the oxide semiconductor as much as possible. Specifically, the hydrogen concentration of the oxide semiconductor measured by SIMS is 1×10⁻⁶ 20 atoms / cm 3 Less than, preferably 1×10 19 atoms / cm 3 Less than, more preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 It is less than.

[0119] By introducing oxygen into the oxide semiconductor film, oxygen vacancies (V) within the oxide semiconductor film are created. o It can reduce ). That is, oxygen vacancies (V o When ) is filled with oxygen, oxygen vacancies (V) within the oxide semiconductor film o ) is eliminated. Therefore, due to the diffusion of oxygen in the oxide semiconductor film, oxygen vacancies (V) within the transistor o It can reduce ) and improve the reliability of the transistor.

[0120] As a method for introducing oxygen into an oxide semiconductor film, for example, an oxide with an oxygen content higher than its stoichiometric composition is provided in contact with the oxide semiconductor film. That is, it is desirable to form a region containing oxygen in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region) in the oxide. In particular, when using an oxide semiconductor film in a transistor, by providing an oxide containing an excess oxygen region to an underlayer or interlayer near the transistor, the oxygen vacancies in the transistor can be reduced, thereby improving reliability.

[0121] If an oxide semiconductor film with a sufficiently reduced impurity concentration is used in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0122] <1-4. Method for Fabricating Composite Oxide Semiconductors>

[0123] An example of a method for fabricating a composite oxide semiconductor shown in FIGS. 4 (A) and (B) will be described with reference to FIGS. 9 (A) and (B), FIGS. 10, FIGS. 11 (A) and (B), FIGS. 12 (A) and (B), and FIGS. 13. A composite oxide semiconductor of one embodiment of the present invention can be formed using a sputtering apparatus.

[0124] <1-5. Sputtering Device>

[0125] FIG. 9 (A) is a cross-sectional view of the deposition chamber (2501) of the sputtering device. FIG. 9 (B) is a plan view of the magnet unit (2530a) and magnet unit (2530b) of the sputtering device.

[0126] The deposition chamber (2501) illustrated in FIG. 9 (A) includes a target holder (2520a), a target holder (2520b), a backing plate (2510a), a backing plate (2510b), a target (2500a), a target (2500b), a member (2542), and a substrate holder (2570). Additionally, the target (2500a) is placed on the backing plate (2510a). The backing plate (2510a) is placed on the target holder (2520a). A magnet unit (2530a) is placed below the target (2500a) via the backing plate (2510a). The target (2500b) is placed on the backing plate (2510b). The backing plate (2510b) is placed on the target holder (2520b). The magnet unit (2530b) is placed below the target (2500b) via a backing plate (2510b).

[0127] As illustrated in FIG. 9 (A) and (B), the magnet unit (2530a) includes a magnet (2530N1), a magnet (2530N2), a magnet (2530S), and a magnet holder (2532). In the magnet unit (2530a), the magnet (2530N1), the magnet (2530N2), and the magnet (2530S) are placed on the magnet holder (2532). The magnet (2530N1), the magnet (2530N2), and the magnet (2530S) are spaced apart. Additionally, the magnet unit (2530b) has a structure similar to that of the magnet unit (2530a). When moving the substrate (2560) to the deposition chamber (2501), the substrate (2560) is placed in contact with the substrate holder (2570).

[0128] The target (2500a), backing plate (2510a), and target holder (2520a) are separated from the target (2500b), backing plate (2510b), and target holder (2520b) by a member (2542). Additionally, the member (2542) is preferably an insulator. The member (2542) may be a conductor or a semiconductor. The member (2542) may be a conductor or a semiconductor whose surface is covered with an insulator.

[0129] The target holder (2520a) and the backing plate (2510a) are fixed to each other by screws (e.g., bolts) and have the same potential. The target holder (2520a) has the function of supporting the target (2500a) via the backing plate (2510a). The target holder (2520b) and the backing plate (2510b) are fixed to each other by screws (e.g., bolts) and have the same potential. The target holder (2520b) has the function of supporting the target (2500b) via the backing plate (2510b).

[0130] The backing plate (2510a) has the function of fixing the target (2500a). The backing plate (2510b) has the function of fixing the target (2500b).

[0131] The magnetic field lines (2580a and 2580b) formed by the magnet unit (2530a) are shown in (A) of FIG. 9.

[0132] As illustrated in FIG. 9 (B), the magnet unit (2530a) has a configuration in which a magnet (2530N1) having a rectangular or substantially rectangular shape, a magnet (2530N2) having a rectangular or substantially rectangular shape, and a magnet (2530S) having a rectangular or substantially rectangular shape are fixed to a magnet holder (2532). The magnet unit (2530a) can be vibrated horizontally as indicated by the arrow in FIG. 9 (B). For example, the magnet unit (2530a) may be vibrated at a beat of 0.1 Hz or more and 1 kHz or less.

[0133] The magnetic field above the target (2500a) changes as the magnet unit (2530a) vibrates. Since the region with a strong magnetic field is a high-density plasma region, sputtering of the target (2500a) is likely to occur near this region. This applies equally to the magnet unit (2530b).

[0134] <1-6. Fabrication Flowchart of Composite Oxide Semiconductors>

[0135] Figure 10 is a process flow diagram showing a method for fabricating a composite oxide semiconductor.

[0136] The composite oxide semiconductors shown in (A) and (B) of FIG. 4 are fabricated through at least the first to fourth processes shown in FIG. 10.

[0137] [Process 1: Process of placing the substrate in the deposition chamber]

[0138] The first process includes the step of placing a substrate in a deposition chamber (see step S101 of FIG. 10).

[0139] In the first process, for example, a substrate (2560) is placed in the substrate holder (2570) of the deposition chamber (2501) shown in (A) and (B) of FIG. 9.

[0140] The temperature of the substrate (2560) can be set from room temperature (25°C) to 200°C, preferably from room temperature to 130°C. The substrate temperature within the above-described range is suitable for using a large glass substrate. In particular, if the substrate temperature during deposition of the composite oxide semiconductor is set to room temperature—that is, if the substrate is not intentionally heated—it is suitable for preventing the substrate from bending or warping.

[0141] The substrate (2560) may be cooled using a cooling mechanism, etc., provided in the substrate holder (2570).

[0142] When the temperature of the substrate (2560) is set to between 100°C and 130°C, the water in the composite oxide semiconductor can be removed. By removing water as an impurity in this way, the composite oxide semiconductor shown in (A) and (B) of FIG. 5 can be easily formed. thus, Field-effect mobility and reliability can be improved simultaneously.

[0143] In addition, if the temperature of the substrate (2560) is set to between 100°C and 130°C, the sputtering device can be prevented from warping due to overheating. Therefore, semiconductor devices can be manufactured with improved productivity. Thus, productivity is stable, making it easy to use large-scale manufacturing devices. Therefore, large display devices including large substrates can be easily manufactured.

[0144] [Process 2: Process of introducing gas into the sedimentation chamber]

[0145] The second process includes the step of introducing gas into a deposition chamber (see step S201 of FIG. 10).

[0146] In the second process, for example, a gas is introduced into the deposition chamber (2501) in (A) and (B) of FIG. 9. As the gas, one or both of argon gas and oxygen gas are introduced. Additionally, inert gases such as helium, xenon, or krypton may be used instead of argon gas.

[0147] When forming a composite oxide semiconductor using oxygen gas, the proportion of oxygen in the total deposited gas is sometimes referred to as the oxygen flow rate ratio. The oxygen flow rate ratio when forming a composite oxide semiconductor is 0% or more and 30% or less, preferably 5% or more and 30% or less, and more preferably 7% or more and 15% or less.

[0148] When depositing the composite oxide semiconductor shown in Fig. 5 (A) and (B), the oxygen flow rate ratio during room temperature deposition is set to be higher than 30% and less than 70%, preferably higher than 30% and less than 50%. Additionally, during heated deposition (e.g., at a temperature of 70°C or higher and 150°C or lower), the oxygen flow rate ratio is set to be 10% or higher and less than 50%, preferably 30% or higher and less than 50%.

[0149] When forming the composite oxide semiconductor shown in Fig. 6 (A) and (B) or the composite oxide semiconductor shown in Fig. 7 (A) and (B), a mixed gas of noble gas and oxygen is used, and the ratio of oxygen to noble gas is set to 70% or more and 100% or less.

[0150] In addition, it is necessary to increase the purity of the gas. For example, as for the oxygen or argon gas used as the gas, by using a highly purified gas with a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, and even more preferably -120°C or lower, the entry of moisture, etc. into the composite oxide semiconductor can be minimized.

[0151] The deposition chamber (2501) is subjected to high vacuum exhaust (5×10) using an adsorption type vacuum exhaust pump, such as a cryopump, to remove as much as possible impurities, such as water, from the composite oxide semiconductor. -7 Pa to 1×10 -4 It is desirable to exhaust to a level of approximately Pa. In particular, gas molecules equivalent to H2O in the deposition chamber (2501) in the standby mode of the sputtering device ( m / z The partial pressure of a gas molecule equivalent to 18 is 1×10 -4 Pa or less is preferable, and 5×10 -5 Pa or less is more desirable.

[0152] [Process 3: Process of applying voltage to the target]

[0153] The third process includes the step of applying voltage to the target (see step S301 of FIG. 10).

[0154] In the third process, for example, a voltage is applied to the target holder (2520a) and the target holder (2520b) in (A) and (B) of FIG. 9. For example, the potential applied to the terminal (V1) connected to the target holder (2520a) is lower than the potential applied to the terminal (V2) connected to the substrate holder (2570). The potential applied to the terminal (V4) connected to the target holder (2520b) is lower than the potential applied to the terminal (V2) connected to the substrate holder (2570). The potential applied to the terminal (V2) connected to the substrate holder (2570) is a ground potential. The potential applied to the terminal (V3) connected to the magnet holder (2532) is a ground potential.

[0155] Additionally, the potential applied to the terminals (V1, V2, V3, and V4) is not limited to the potential described above. It is not necessary to supply potential to all of the target holder (2520), substrate holder (2570), and magnet holder (2532). For example, the substrate holder (2570) may be electrically floating. Additionally, a power source capable of controlling the potential applied to the terminal (V1) is electrically connected to the terminal (V1). As the power source, a DC power source, an AC power source, or an RF power source may be used.

[0156] As targets (2500a) and targets (2500b), indium, element M ( M It is preferable to use a target comprising Al, Ga, Y, or Sn), zinc, and oxygen. For example, an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) or an In-Ga-Zn metal oxide target (In:Ga:Zn=5:1:7 [atomic ratio]) may be used as targets (2500a) and (2500b). In the following description, the case in which an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) is used will be described.

[0157] In addition, by using a sputtering target comprising a polycrystalline oxide having multiple crystal grains as the target (2500a) and the target (2500b), a composite oxide semiconductor having crystallinity as shown in (A) and (B) of FIG. 4 or FIG. 8 is easily obtained.

[0158] [Process 4: Process of depositing a composite oxide semiconductor on a substrate]

[0159] The fourth process includes the step of sputtering particles being emitted from a target and a composite oxide semiconductor being deposited on a substrate (see step S401 of FIG. 10).

[0160] In the fourth process, for example, in the deposition chamber (2501) shown in FIG. 9 (A) and (B), argon gas or oxygen gas is ionized to separate into cations and electrons, and plasma is generated. Then, the cations in the plasma are accelerated toward the target (2500a) and target (2500b) by the potential applied to the target holder (2520a) and target holder (2520b). When the cations collide with the In-Ga-Zn metal oxide target, sputtering particles are generated, and the sputtering particles are deposited on the substrate (2560).

[0161] Additionally, the In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1 or 5:1:7, which is used as the target (2500a and 2500b), may contain multiple crystal grains having different compositions. In most cases, for example, the diameter of each of the multiple crystal grains is 10 μm or less. For example, when crystal grains with a high proportion of In are included in the In-Ga-Zn metal oxide target, the proportion of the region (A1) described above may increase.

[0162] < 1-7. Sedimentation Model>

[0163] In the fourth process, the sedimentation model shown in (A) and (B) of Fig. 11 can be estimated.

[0164] Figures 11 (A) and (B) are cross-sectional views of the vicinity of the target (2500a) shown in Figures 9 (A) and (B). Additionally, in Figures 11 (A) and (B), a backing plate (2510a), a target (2500a), plasma (2190), cations (2192), and sputtering particles (2194) are shown.

[0165] [Stage 1]

[0166] In (A) of FIG. 11, argon gas or oxygen gas is ionized to separate into cations (2192) and electrons (not shown), and plasma (2190) is generated. Then, the cations (2192) in the plasma (2190) are accelerated toward a target (2500a) (here, an In-Ga-Zn metal oxide target). Sputtering particles (2194) are generated by the collision of the cations (2192) with the In-Ga-Zn metal oxide target and are emitted from the In-Ga-Zn metal oxide target. Additionally, Ga and Zn are preferentially sputtered from the In-Ga-Zn metal oxide target as sputtering particles (2194).

[0167] Specifically, when cations (2192) collide with an In-Ga-Zn metal oxide target, Ga and Zn, which have a lower relative atomic mass than In, are preferentially emitted from the In-Ga-Zn metal oxide target. The emitted In, Ga, and Zn combine with oxygen and are then deposited on a substrate, thereby forming the region (B1) shown in (A) and (B) of FIG. 4.

[0168] Additionally, as shown in (A) of FIG. 11, there are cases where In is segregated on the surface of the target (2500a) (here, the surface of an In-Ga-Zn metal oxide target) due to the preferential sputtering of Ga and Zn as sputtering particles (2194). Also, in (A) of FIG. 11, the segregated In is shown as a cluster (2196).

[0169] [Stage 2]

[0170] Then, as shown in (B) of FIG. 11, after In is segregated, that is, after a cluster (2196) is formed, the cluster (2196) (here, a cluster containing In) is sputtered from an In-Ga-Zn metal oxide target.

[0171] Specifically, segregated In on the surface of the In-Ga-Zn metal oxide target is emitted from the In-Ga-Zn metal oxide target as a structure resembling multiple clusters. Segregated In having a structure resembling multiple clusters combines with oxygen and collides with the previously deposited region (B1), causing the region (A1) to be deposited in a cluster shape (particle shape). Additionally, because segregated In is emitted, In, Ga, and Zn on the surface of the In-Ga-Zn metal oxide target exist in a state close to their original atomic ratios.

[0172] In addition, as shown in (B) of FIG. 11, In is segregated in one region of the surface of the target (2500a), and the segregated In is released in another region of the surface of the target (2500a). That is, the mechanism of In segregation and the mechanism of the release of segregated In act simultaneously, so that region (A1) is surrounded by region (B1) and becomes a structure in which it is unevenly and irregularly dispersed.

[0173] By repeating the deposition model including the first and second steps, a composite oxide semiconductor of one form of the present invention shown in (A) and (B) of FIG. 4 can be obtained.

[0174] In addition, the formation method is not limited to the sputtering method, and the PLD (pulsed laser deposition) method, PECVD (plasma-enhanced chemical vapor deposition) method, thermal CVD (thermal chemical vapor deposition) method, ALD (atomic layer deposition) method, or vacuum deposition method may be used. An example of the thermal CVD method is the MOCVD (metal organic chemical vapor deposition) method.

[0175] <1-8. Verification of the Sedimentation Model>

[0176] To verify the sedimentation model described above, sample Z1, described below, was formed.

[0177] [Sample Z1 ]

[0178] In sample Z1, an insulating film (82), an insulating film (84), an oxide semiconductor film (88), and an insulating film (86) were sequentially formed on a glass substrate.

[0179] Insulating film (82) and insulating film (84) function as a substrate. As for the insulating film (82), a silicon nitride film with a thickness of 400 nm was formed using a PECVD device. As for the insulating film (84), a silicon oxynitride film with a thickness of 50 nm was formed using a PECVD device.

[0180] As for the oxide semiconductor film (88), an In-Ga-Zn oxide film with a thickness of 40 nm was formed using a sputtering device. Additionally, the oxide semiconductor film (88) was formed under conditions where the substrate temperature was 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was 0.2 Pa, and 1500 W of AC power was supplied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) located in the sputtering device.

[0181] In addition, in this embodiment, the oxide semiconductor film (88) is assumed to be a sputtering target for forming a composite oxide semiconductor.

[0182] After the oxide semiconductor film (88) is formed, plasma treatment is performed on the surface of the oxide semiconductor film (88) using argon gas. This is assumed to be sputtered in a sputtering device. The plasma treatment was performed under conditions in which argon gas with a flow rate of 100 sccm was introduced into the chamber, the pressure inside the chamber was set to 40 Pa, and 1000 W of power was supplied to the RF power source (27.12 MHz).

[0183] After plasma treatment, an insulating film (86) was formed on the oxide semiconductor film (88). The insulating film (86) functions as a protective insulating film. As the insulating film (86), a silicon oxynitride film with a thickness of 100 nm was formed using a PECVD device.

[0184] Through the above process, sample Z1 was formed to verify the sedimentation model.

[0185] Next, a high-angle annular dark field (HAADF)-STEM image of the cross-section of sample Z1 was observed. Additionally, for the HAADF-STEM observation, a JEM-ARM200F manufactured by JEOL Ltd. was used under conditions of an acceleration voltage of 200 kV.

[0186] Figure 13 shows the HAADF-STEM observation of sample Z1.

[0187] As shown in FIG. 13, the structure (90) is formed on an oxide semiconductor film (88). Also, from HAADF-STEM observation, the thickness of the oxide semiconductor film (88) is about 36 nm, and the thickness of the structure (90) is about 11 nm.

[0188] In order to evaluate the composition of the structure (90), elemental analysis was performed on point 1 shown in the oxide semiconductor film (88) and point 2 shown in the structure (90). In addition, the elemental analysis was performed using an EDX device JET-2300T. The beam diameter of the elemental analysis was set to 0.1 nmφ.

[0189] Table 1 shows the results of the EDX analysis.

[0190] [Table 1]

[0191]

[0192] When the value of point 1 shown in Table 1 is normalized to the value of In in the metal oxide target, the atomic ratio is In:Ga:Zn:O = 4:2:2.4:7.2. Although the ratio of Zn atoms is slightly different from the ratio of Zn atoms in the composition of the metal oxide target, the composition of the oxide semiconductor film (88) is approximately the same as the composition of the metal oxide target. Meanwhile, as shown in Table 1, the structure (90) has a high ratio of In. Therefore, the structure (90) can be said to be a precipitate of In or a precipitate of indium oxide.

[0193] Precipitates of In or precipitates of indium oxide can be assumed as In (i.e., clusters (2196)) segregated on the surface of the In-Ga-Zn metal oxide target of the sedimentation model described above. This indicates that the sedimentation model is very appropriate.

[0194] In addition, when depositing a composite oxide semiconductor of one form of the present invention shown in (A) and (B) of FIG. 6, the deposition model shown in (A) and (B) of FIG. 12 can be estimated in the fourth process.

[0195] Figures 12 (A) and (B) are cross-sectional views of the vicinity of the target (2500a) shown in Figures 9 (A) and (B). Additionally, in Figures 12 (A) and (B), a backing plate (2510a), a target (2500a), plasma (2190), cations (2192), and sputtering particles (2194) are shown.

[0196] In the deposition chamber (2501) illustrated in (A) of FIG. 12, argon gas or oxygen gas is ionized and separated into cations (2192) and electrons (not shown), and plasma (2190) is generated. Then, the cations (2192) in the plasma (2190) are accelerated toward a target (2500a) (here, an In-Ga-Zn metal oxide target). As the cations (2192) collide with the In-Ga-Zn metal oxide target, sputtering particles (2194) are generated and emitted from the In-Ga-Zn metal oxide target.

[0197] Here, the targets (2500a and 2500b) have a polycrystalline structure containing multiple crystal grains. In most cases, the diameter of each of the multiple crystal grains is 10 μm or less. Additionally, for example, the multiple crystal grains may have different compositions in an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn=4:2:4.1 or 5:1:7.

[0198] For example, in (A) of FIG. 12, the target (2500a) includes at least a region (2502a) in which the proportion of In atoms is lower than the proportion of In atoms in the target and a region (2504a) in which the proportion of In atoms is higher than the proportion of In atoms in the target.

[0199] First, the region (2502a) with a low ratio of In in the target (2500a) is described.

[0200] As shown in FIG. 12 (A), cations (2192) generated in a high-density plasma region are accelerated toward the target (2500a) by an electric field and subsequently collide with a region (2502a) contained within the target (2500a). At this time, a cluster (2198), which is a flat nanocrystal, is separated from the region (2502a). In most cases, the cluster consists of two M - It includes a Zn-O layer and an In-O layer between them. Also, depending on the separation of the cluster (2198), Sputtering particles (2194)It is emitted from the target (2500a).

[0201] The cluster (2198) may include a triangular plane, for example, an equilateral triangle plane. The cluster (2198) may include a hexagonal plane, for example, a regular hexagon plane. However, the plane shape of the cluster (2198) is not limited to triangles or hexagons. For example, the plane may have a shape formed by combining two or more triangles. For example, a square (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles) may be formed.

[0202] The thickness of the cluster (2198) is determined according to the type of deposited gas, etc. For example, the thickness of the cluster (2198) is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, the width of the cluster (2198) is 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less.

[0203] When the sputtering particles (2194) pass through the plasma (2190), the surface of the sputtering particles (2194) may be negatively or positively charged. For example, The sputtering particles (2194) O2 present in the plasma (2190) - There are cases where a negative charge is received from. As a result, sputtering particles (2194) Oxygen atoms on the surface can be negatively charged. Also, when passing through plasma (2190), The sputtering particles (2194) In, element in plasma (2190) M There are cases where it grows combined with Zn, oxygen, etc. Therefore, the sputtering particle (2194) has one atom or a collection of several atoms.

[0204] Cluster (2198) that has passed through plasma (2190) and sputtering particles (2194) It reaches the surface of the substrate. Since the cluster (2198) has a flat shape, it is deposited such that the flat surface faces the surface of the substrate. Also sputtering particles (2194) Since its mass is small, by a vacuum pump, etc. sputtering particles (2194) A portion of it is discharged to the outside.

[0205] The sputtering particles (2194) reach the surface of the substrate. The sputtering particles (2194) There is a tendency to be coupled to the side of the cluster (2198) rather than the top surface of the cluster (2198). The sputtering particles (2194) are, It is preferentially deposited on the side of the cluster (2198) to fill the area where the cluster (2198) is not formed. sputtering particles (2194) Because the available bonds are activated, sputtering particles (2194) Is Cluster (2198) It is chemically bonded to form a horizontal growth section. In other words, the sputtering particles (2194) enter the region between one cluster and another cluster.

[0206] The horizontal growth region grows further in a horizontal direction to fill the area between one cluster and another (also called the lateral growth buffer region (LGBR)). The horizontal direction refers, for example, to a direction perpendicular to the c-axis in the cluster.

[0207] A reaction is likely to occur in which sputtered particles attach to the horizontal growth portion of the cluster, oxygen diffused through the LGBR attaches to the sputtered particles, and other sputtered particles attach in the same manner. It is presumed that horizontal solid-state growth occurs through the repetition of this reaction. Such horizontal growth of the cluster can also be referred to as self-assembly.

[0208] The horizontal growth zones grow further sideways and collide with each other. Adjacent clusters are connected using the areas where the horizontal growth zones collide as connection points. In other words, sputtered particles form horizontal growth zones on the sides of clusters and fill the region between one cluster and another by causing horizontal growth. In this way, horizontal growth zones are formed until they fill the areas where clusters are not formed. This mechanism is similar to the deposition mechanism of the ALD method.

[0209] Therefore, even when multiple formed clusters are oriented in different directions, a region (B1) containing CAAC-OS is formed without forming clear grain boundaries because the sputtering particles grow sideways to fill the gap between one cluster and another cluster.

[0210] In addition, the layered crystal structure in CAAC-OS is stable over a wide range of compositions, and the bond strength and equilibrium distance between metal atoms and oxygen atoms depend on the metal atoms. Therefore, it is presumed that the crystal structure of CAAC-OS is resistant to deformation. That is, because clusters are smoothly connected (anchored) by sputtering particles, a crystal structure different from that of single crystals and polycrystalline crystals is formed at the connection points. In other words, a deformed crystal structure is formed at the connection points between adjacent clusters. Accordingly, for example, the shape of the hexagonal upper face of the crystal structure at the connection points may change to a pentagon or a heptagon.

[0211] Next, the region (2504a) with a high ratio of In in the target (2500a) is described.

[0212] Cations (2192) generated in the high-density plasma region are accelerated toward the target (2500a) by an electric field and then collide with the region (2504a) contained within the target (2500a). When using an In-Ga-Zn metal oxide target, Ga and Zn are preferentially sputtered as sputtering particles (2194). That is, as the cations (2192) collide with the In-Ga-Zn metal oxide target, Ga and Zn, which have a lower relative atomic mass than In, are preferentially emitted from the In-Ga-Zn metal oxide target. As described above, the emitted sputtering particles (2194) are deposited on the substrate, and region (B1) is formed by filling the region between the clusters (2198) emitted from region (2502a) and deposited on the substrate.

[0213] Additionally, as shown in FIG. 12 (A), Ga and Zn are preferentially sputtered as sputtering particles (2194), and then a state in which In is segregated is obtained on the surface of a region (2504a) with a high proportion of In. Also, in FIG. 12 (A), the segregated In is shown as a cluster (2196). It is preferable that the diameter of the cluster (2196) be about 0.5 nm or more and 1.5 nm or less.

[0214] As shown in (B) of FIG. 12, after In is segregated, that is, after a cluster (2196) is formed, the cluster (2196) is sputtered from a region (2504a) with a high proportion of In.

[0215] Specifically, segregated In on the surface of an In-Ga-Zn metal oxide target is emitted from the In-Ga-Zn metal oxide target as a structure such as a plurality of granular clusters. The segregated In having a structure such as a plurality of clusters combines with oxygen and collides with the previously deposited region (B1), thereby depositing a region (A1) having granular clusters. Additionally, because segregated In is emitted, the In, Ga, and Zn present on the surface of region (2504a) have an atomic ratio close to the original atomic ratio.

[0216] In addition, as shown in (A) and (B) of FIG. 12, in one area of ​​the surface of the region (2504a) where the ratio of In is high in the target (2500a), In is segregated, and in another area of ​​the surface, the segregated In is released. That is, the mechanism of In segregation and the mechanism of the release of segregated In operate simultaneously.

[0217] Therefore, since clusters (2196) are easily formed in the region (2504a) with a high proportion of In, the region (2504a) tends to form region (A1). Meanwhile, the region (2502a) with a low proportion of In tends to form region (B1) as sputtering particles combined with emitted clusters and oxygen are deposited on the substrate.

[0218] As a result, regions (A1) and (B1) are extended onto the cloud and distributed unevenly and irregularly. A composite oxide semiconductor of one form of the present invention shown in (A) and (B) of FIG. 6 can be obtained by the above formula.

[0219] <1-9. Classification of Oxide Semiconductors>

[0220] Next, the classification of oxide semiconductors will be explained.

[0221] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0222] From another perspective, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0223] For example, amorphous structures are generally considered to be isotropic, non-homogeneous, metastable, with non-fixed atomic arrangements, flexible bond angles, and possess short-range order but not long-range order.

[0224] In other words, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Furthermore, a non-isotropic oxide semiconductor (e.g., an oxide semiconductor with a periodic structure in minute regions) cannot be called a completely amorphous oxide semiconductor. On the other hand, non-isotropic α-like OSs have unstable structures containing cavities. Because of this instability, α-like OSs possess physical properties similar to those of amorphous oxide semiconductors.

[0225] (CAAC-OS)

[0226] First, I will explain CAAC-OS.

[0227] CAAC-OS is one of the oxide semiconductors and has multiple c-axis oriented crystal regions (also called pellets).

[0228] CAAC-OS is a highly crystalline oxide semiconductor. The intrusion of impurities or the formation of defects can degrade the crystallinity of oxide semiconductors. This implies that CAAC-OS has low levels of impurities and defects (e.g., oxygen vacancies).

[0229] Furthermore, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, or transition metals. For example, elements with a higher bonding affinity for oxygen than the metal elements contained in the oxide semiconductor (specifically, silicon, etc.) extract oxygen from the oxide semiconductor, which disrupts the atomic arrangement or degrades its crystallinity. Heavy metals such as iron or nickel, argon, or carbon dioxide, due to their large atomic radii (or molecular radii), also disrupt the atomic arrangement of oxide semiconductors and reduce their crystallinity.

[0230] (nc-OS)

[0231] Next, nc-OS will be explained.

[0232] The analysis of nc-OS by XRD is explained. When the structure of nc-OS is analyzed by the out-of-plane method, no peaks indicating orientation appear. In other words, the crystals of nc-OS do not have orientation.

[0233] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, nc-OS has a lower density of defect levels than a-like OS and amorphous oxide semiconductors. Additionally, there is no regularity of crystal orientation between different pellets in nc-OS. Consequently, nc-OS may have a higher density of defect levels than CAAC-OS.

[0234] [a-like OS]

[0235] a-like OS has a structure between that of nc-OS and the structure of amorphous oxide semiconductors.

[0236] An a-like OS contains cavities or low-density regions. Because an a-like OS contains cavities, it has an unstable structure.

[0237] a-like OS has a lower density than nc-OS and CAAC-OS because it contains cavities. Specifically, the density of a-like OS is between 78.6% and less than 92.3% of the density of a single-crystal oxide semiconductor of the same composition. The densities of nc-OS and CAAC-OS are each between 92.3% and less than 100% of the density of a single-crystal oxide semiconductor of the same composition. Oxide semiconductors with a density of less than 78% of the density of a single-crystal oxide semiconductor are difficult to deposit.

[0238] For example, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a single-crystal InGaZnO4 with a rhombohedral structure is 6.357 g / cm³. 3 .... Therefore, for example, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of the a-like OS is 5.0 g / cm³.3 Above 5.9 g / cm² 3 It is less than. For example, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the densities of nc-OS and CAAC-OS are 5.9 g / cm³, respectively. 3 Above 6.3g / cm² 3 It is less than.

[0239] If an oxide semiconductor with a specific composition does not exist in a single-crystal state, a density equivalent to that of a single-crystal oxide semiconductor with a desired composition can be calculated by combining single-crystal oxide semiconductors with different compositions in appropriate proportions. The density of a single-crystal oxide semiconductor with a desired composition can be calculated using a weighted average of the combination ratios of single-crystal oxide semiconductors with different compositions. Furthermore, it is desirable to calculate the density using as few types of single-crystal oxide semiconductors as possible.

[0240] As described above, oxide semiconductors have various structures and various characteristics. In one embodiment of the present invention, an oxide semiconductor film may be a mixture of two or more of amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0241] Additionally, the aforementioned region (A1) is preferably a single crystal. The region (B1) is preferably a single crystal. Regions (A1) and (B1) may have different crystallinities.

[0242] <1-10. Characteristics of Transistors>

[0243] Next, the general characteristics of a transistor will be explained with reference to (A) and (B) of FIG. 14, FIG. 15, FIG. 16, and (A) to (C) of FIG. 17.

[0244] [Transistor's I d - V g characteristic ]

[0245] First, the drain current-gate voltage characteristics of a transistor ( I d - V g The characteristics) are explained. (A) of FIG. 14 is of a transistor I d - V g An example of the characteristics is illustrated. Fig. 14 (A) shows the case where polycrystalline silicon is used in the active layer of the transistor for easier understanding. In Fig. 14 (A), the vertical axis and the horizontal axis are, respectively I d and V g It represents.

[0246] As shown in (A) of FIG. 14, I d - V g The characteristics are broadly divided into three regions. The first, second, and third regions are also referred to as the OFF region, subthreshold region, and ON region, respectively. The gate voltage at the boundary between the subthreshold region and the ON region is the threshold voltage ( V th It is called ).

[0247] To obtain desirable characteristics of a transistor, the drain current in the off-region (off-state current or I off (also called) is low, and the drain current in the on region (on-state current or I on It is desirable for the value (also known as) to be high. Field-effect mobility is often used as an indicator of a transistor's on-state current. Details regarding field-effect mobility will be explained later.

[0248] In order to drive the transistor at a low voltage, in the subthreshold region I d - V gIt is desirable for the slope of the characteristic to be steep. In the sub-threshold region I d - V g The indicator of the degree of change in characteristics is called the SS (subthreshold swing) or S value. The S value can be expressed by the following equation (1).

[0249] [Equation 1]

[0250]

[0251] The S value is the minimum change in gate voltage required for the drain current to change by a single digit in the sub-threshold region. The smaller the S value, the more rapidly the switching operation between the ON and OFF states can be performed.

[0252] [ transistor's I d - V d characteristic ]

[0253] Next, the drain current-drain voltage characteristics of the transistor ( I d - V d The characteristics) are explained. Figure 14 (B) shows the transistor's I d - V d This illustrates an example of the characteristics. In (B) of FIG. 14, the vertical axis and the horizontal axis are, respectively I d and V d It represents.

[0254] As shown in (B) of FIG. 14, the ON region is further divided into two regions. The first region and the second region are called the linear region and the saturation region, respectively. In the linear region, the drain current increases in a parabolic shape as the drain voltage increases. Meanwhile, in the saturation region, the drain current does not change significantly even if the drain voltage changes. Depending on the vacuum tube, the linear region and the saturation region may be referred to as the triode region and the pentode region.

[0255] A linear region is V g go V d topping( V d < V g There are cases where it refers to a ) state. The saturation region is V d go V g Higher state ( V d > V g There are cases where it refers to ). However, in reality, it is necessary to consider the transistor's threshold voltage. Therefore, the value obtained by subtracting the transistor's threshold voltage from the gate voltage is higher than the drain voltage ( V d < V g - V th ) The state is sometimes referred to as the linear region. Similarly, the state in which the value obtained by subtracting the transistor's threshold voltage from the gate voltage is lower than the drain voltage ( V g - V th < V d There are cases where ) is referred to as the saturated region.

[0256] A transistor with a constant current in the saturation region I d- V d The characteristic is sometimes referred to as "desirable saturation." Desirable saturation of a transistor is particularly important when the transistor is used in an organic EL display. For example, by using a transistor with desirable saturation as a pixel transistor in an organic EL display, changes in the brightness of the pixel can be suppressed even when the drain voltage changes.

[0257] [Analysis Model of Drain Current]

[0258] Next, the analysis model for drain current will be explained. As an analysis model for drain current, an analysis formula / analysis formula based on GCA (gradual channel approximation) is known. Based on GCA, the drain current of a transistor can be expressed by the following equation (2).

[0259] [Equation 2]

[0260]

[0261] In Equation (2), the upper equation is for the drain current in the linear region, and the lower equation is for the drain current in the saturation region. In Equation (2). I d represents the drain current, μ represents the mobility of the active layer, L represents the channel length of the transistor, and W represents the channel width of the transistor, and C OX represents the gate capacitance, and V g represents the gate voltage, and V d represents the drain voltage, V th represents the threshold voltage of the transistor.

[0262] [Electric Field Effect Mobility]

[0263] Next, field-effect mobility will be explained. Field-effect mobility is used as an indicator of a transistor's current driving capability. As described above, the on-region of a transistor is divided into a linear region and a saturation region. Based on the characteristics of these regions, the field-effect mobility of the transistor can be calculated based on the drain current analysis formula based on GCA. If it is necessary to distinguish between the field-effect mobility in the linear region and the field-effect mobility in the saturation region, they are referred to as linear mobility and saturation mobility, respectively. Linear mobility is represented by the following equation (3), and saturation mobility is represented by the following equation (4).

[0264] [Equation 3]

[0265]

[0266] [Equation 4]

[0267]

[0268] In this specification and others, the curve calculated from Equation (3) and Equation (4) is referred to as a mobility curve. FIG. 15 shows a mobility curve calculated from the analysis formula for drain current based on GCA. FIG. 15 shows the case where it is assumed that GCA is effective. V d at =10V I d - V g It shows the characteristics and mobility curves for linear mobility and saturated mobility together.

[0269] In Fig. 15, from the analysis formula of the drain current based on GCA I d - V g Characteristics are calculated. The shape of the mobility curve can help understand the internal state of the transistor.

[0270] For example, FIG. 16 shows the measured FET including CAAC-OS I d - V g This shows the characteristics. In Fig. 16, the FET I d - V g This shows the mobility curves for characteristics, saturation mobility, and linear mobility together. Additionally, an oxide semiconductor (IGZO) film having an atomic ratio of In:Ga:Zn = 1:1:1 is used as the semiconductor layer of the FET. The mobility curves for saturation mobility and linear mobility are, respectively V d at =10V I d - V g It is obtained from the characteristics.

[0271] As shown in Fig. 16, when the shape of the FET follows GCA, the saturation mobility curve becomes plateau in the saturation region and gradually decreases in the linear region.

[0272] <1-11. Fabrication of a Transistor for Characteristic Evaluation>

[0273] Next, the structure of a transistor according to one embodiment of the present invention is described, and the results of evaluating the electrical characteristics of the fabricated transistor are presented.

[0274] [Transistor Structure Example 1]

[0275] FIG. 17 (A) is a top view of a transistor (100A). FIG. 17 (B) is a cross-sectional view taken along the dotted line X1-X2 of FIG. 17 (A). FIG. 17 (C) is a cross-sectional view taken along the dotted line Y1-Y2 of FIG. 17 (A). For clarity, some components, such as the insulating film (110), are not shown in FIG. 17 (A). As with FIG. 17 (A), some components may not be shown in the top view of the transistor described below. Also, the direction of the dotted line X1-X2 may be referred to as the channel length (L) direction, and the direction of the dotted line Y1-Y2 may be referred to as the channel width (W) direction.

[0276] The transistor (100A) illustrated in (A) to (C) of FIG. 17 comprises a conductive film (106) on a substrate (102), an insulating film (104) on the conductive film (106), an oxide semiconductor film (108) on the insulating film (104), an insulating film (110) on the oxide semiconductor film (108), a conductive film (112) on the insulating film (110), and an insulating film (116) on the insulating film (104), the oxide semiconductor film (108), and the conductive film (112). Additionally, the oxide semiconductor film (108) comprises a channel region (108i) overlapping with the conductive film (112), a source region (108s) in contact with the insulating film (116), and a drain region (108d) in contact with the insulating film (116).

[0277] Additionally, the insulating film (116) contains nitrogen or hydrogen. When the insulating film (116) comes into contact with the source region (108s) and the drain region (108d), the nitrogen or hydrogen contained in the insulating film (116) is added to the source region (108s) and the drain region (108d). The carrier density of the source region (108s) and the drain region (108d) increases when nitrogen or hydrogen is added, respectively.

[0278] The transistor (100A) may further include an insulating film (118) on an insulating film (116), a conductive film (120a) electrically connected to a source region (108s) through an opening (141a) provided in the insulating films (116 and 118), and a conductive film (120b) electrically connected to a drain region (108d) through an opening (141b) provided in the insulating films (116 and 118). Additionally, an insulating film (122) may be provided on the insulating film (118), the conductive film (120a), and the conductive film (120b). Although a structure in which an insulating film (122) is provided is shown in (B) and (C) of FIG. 17, one embodiment of the present invention is not limited thereto, and an insulating film (122) is not necessarily provided.

[0279] In the present specification, etc., the insulating film (104) may be referred to as the first insulating film, the insulating film (110) may be referred to as the second insulating film, the insulating film (116) may be referred to as the third insulating film, the insulating film (118) may be referred to as the fourth insulating film, and the insulating film (122) may be referred to as the fifth insulating film. The insulating film (104) functions as the first gate insulating film, and the insulating film (110) functions as the second gate insulating film. The insulating films (116 and 118) function as protective insulating films, and the insulating film (122) functions as a planarizing insulating film.

[0280] The insulating film (110) includes an excess oxygen region. Because the insulating film (110) includes an excess oxygen region, excess oxygen can be supplied to the channel region (108i) included in the oxide semiconductor film (108). Consequently, oxygen vacancies that may be formed in the channel region (108i) can be filled by excess oxygen, thereby providing a highly reliable semiconductor device.

[0281] In order to supply excess oxygen to the oxide semiconductor film (108), excess oxygen may be supplied to the insulating film (104) formed below the oxide semiconductor film (108). In this case, the excess oxygen contained in the insulating film (104) may also be supplied to the source region (108s) and drain region (108d) contained in the oxide semiconductor film (108). When excess oxygen is supplied to the source region (108s) and drain region (108d), the resistance of the source region (108s) and drain region (108d) may increase.

[0282] Meanwhile, in a structure in which an insulating film (110) formed on an oxide semiconductor film (108) contains excess oxygen, the excess oxygen can be selectively supplied only to the channel region (108i). Alternatively, after supplying excess oxygen to the channel region (108i) and the source region and drain region (108s and 108d), the carrier density of the source region and drain region (108s and 108d) can be selectively increased, thereby preventing the resistance of the source region and drain region (108s and 108d) from increasing.

[0283] Additionally, it is preferable that the source region (108s) and drain region (108d) included in the oxide semiconductor film (108) each contain an element that forms an oxygen vacancy or an element that combines with an oxygen vacancy. Representative examples of elements that form an oxygen vacancy or combine with an oxygen vacancy include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and noble gases. Representative examples of noble gas elements include helium, neon, argon, krypton, and xenon. The element that forms an oxygen vacancy diffuses from the insulating film (116) to the source region (108s) and drain region (108d) when the insulating film (116) contains one or more of these elements. Also / or, the element that forms an oxygen vacancy is added to the source region (108s) and drain region (108d) by an impurity addition treatment.

[0284] Impurity elements added to an oxide semiconductor film cleave the bonds between metal elements and oxygen, forming oxygen vacancies. Alternatively, when impurity elements are added to the oxide semiconductor film, oxygen bonded to metal elements in the film bonds to the impurity elements, causing oxygen to detach from the metal elements and form oxygen vacancies. Consequently, the carrier density of the oxide semiconductor film increases, and thus its conductivity improves.

[0285] The conductive film (106) functions as a first gate electrode, and the conductive film (112) functions as a second gate electrode. The conductive film (120a) functions as a source electrode, and the conductive film (120b) functions as a drain electrode.

[0286] As illustrated in (C) of FIG. 17, an opening (143) is provided in the insulating films (104 and 110). The conductive film (106) is electrically connected to the conductive film (112) through the opening (143). Therefore, the same potential is applied to the conductive film (106) and the conductive film (112). Alternatively, different potentials may be applied to the conductive film (106) and the conductive film (112) without providing the opening (143). Or, the conductive film (106) may be used as a light-blocking film without providing the opening (143). For example, if the conductive film (106) is formed using a light-blocking material, light from below irradiated onto the channel region (108i) can be reduced.

[0287] As shown in (B) and (C) of FIG. 17, the oxide semiconductor film (108) is positioned between the two conductive films that function as gate electrodes, facing the conductive film (106) that functions as a first gate electrode and the conductive film (112) that functions as a second gate electrode.

[0288] Additionally, the length of the conductive film (112) in the channel width direction is longer than the length of the oxide semiconductor film (108) in the channel width direction. In the channel width direction, the entire oxide semiconductor film (108) is covered by the conductive film (112) through the insulating film (110). Since the conductive film (112) is connected to the conductive film (106) through the opening (143) provided in the insulating film (104 and 110), the side of the oxide semiconductor film (108) in the channel width direction faces the conductive film (112) through the insulating film (110).

[0289] In other words, in the channel width direction of the transistor (100A), the conductive films (106 and 112) are connected to each other through an opening (143) provided in the insulating films (104 and 110), and the conductive films (106 and 112) surround the oxide semiconductor film (108) through the insulating films (104 and 110).

[0290] With this structure, the oxide semiconductor film (108) included in the transistor (100A) can be electrically surrounded by the electric fields of the conductive film (106) functioning as the first gate electrode and the conductive film (112) functioning as the second gate electrode. A device structure of a transistor in which the electric fields of the first gate electrode and the second gate electrode electrically surround the oxide semiconductor film (108) where the channel region is formed, such as in the transistor (100A), can be called an S-channel (surrounded channel) structure. Additionally, due to the number of gate electrodes, the transistor (100A) may be called a dual-gate transistor.

[0291] Since the transistor (100A) has an S-channel structure, an electric field to induce a channel can be effectively applied to the oxide semiconductor film (108) by means of the conductive film (106) or the conductive film (112), thereby improving the current driving capability of the transistor (100A) and obtaining high on-state current characteristics. Since the on-state current can be increased, the size of the transistor (100A) can be reduced. In addition, since the transistor (100A) has a structure in which the oxide semiconductor film (108) is surrounded by the conductive film (106) and the conductive film (112), the mechanical strength of the transistor (100A) can be increased.

[0292] Additionally, in the channel width direction of the transistor (100A), an opening other than the opening (143) may be formed on the side of the oxide semiconductor film (108) where the opening (143) is not formed.

[0293] In addition, due to the position of the conductive film (112) on the oxide semiconductor film (108) and the method of forming the conductive film (112), the transistor (100A) may also be called a TGSA (top-gate self-aligned) FET. Furthermore, a semiconductor device of one embodiment of the present invention is not limited thereto, and BGTC( bottom-gate top-contact It can be a FET.

[0294] [Formation of Transistors]

[0295] Next, a transistor corresponding to the transistor (100A) described above was formed, and the electrical characteristics of the transistor were evaluated. In this embodiment, samples S1A to S1C described below were fabricated. Samples S1A to S1C are samples in which a transistor having a channel length (L) of 2 μm and a channel width (W) of 3 μm is formed, respectively. Sample S1A includes a composite oxide semiconductor shown in (A) and (B) of FIG. 4 as an oxide semiconductor film (108), sample S1B includes a composite oxide semiconductor shown in (A) and (B) of FIG. 5 as an oxide semiconductor film (108), and sample S1C includes a composite oxide semiconductor shown in (A) and (B) of FIG. 6 as an oxide semiconductor film (108).

[0296] [Sample Method for forming S1A to S1C ]

[0297] First, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering device. Next, the conductive film was processed by photolithography.

[0298] A laminate comprising four insulating films was formed on a substrate and a conductive film. The insulating films were formed continuously in a vacuum using a plasma-enhanced chemical deposition (PECVD) apparatus. As insulating films, a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm were used and laminated in this order.

[0299] Next, an oxide semiconductor film is formed on an insulating film and processed into an island shape, thereby forming a semiconductor layer. As for the oxide semiconductor film (108), an oxide semiconductor film with a thickness of 40 nm is formed. In addition, the oxide semiconductor film is the aforementioned composite oxide semiconductor or C / IGZO.

[0300] The oxide semiconductor film of sample S1A was formed under conditions in which the substrate temperature was set to room temperature (25°C), argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm were introduced into the chamber of the sputtering device, the pressure was set to 0.6 Pa, and 2.5 kW of AC power was applied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic number ratio]) containing indium, gallium, and zinc. The oxygen flow rate ratio during the deposition of the oxide semiconductor film of sample S1A was 10%.

[0301] Next, an insulating film was formed on the insulating film and the oxide semiconductor layer. As the insulating film, a silicon nitride film with a thickness of 150 nm was formed using a PECVD device.

[0302] Next, a heat treatment was performed. This heat treatment was carried out at 350°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

[0303] An opening was formed in a desired area of ​​the insulating film. The opening was formed by dry etching.

[0304] Then, an oxide semiconductor film with a thickness of 100 nm is formed on the insulating film and at the opening, and a conductive film is formed by processing the oxide semiconductor film into an island shape. In addition, after forming the conductive film, an insulating film is formed by processing an insulating film that contacts the lower surface of the conductive film.

[0305] As conductive films, an oxide semiconductor film with a thickness of 10 nm, a titanium nitride film with a thickness of 50 nm, and a copper film with a thickness of 100 nm were formed in this order. The oxide semiconductor film was formed under conditions in which the substrate temperature was set to 170°C, oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering device, the pressure was set to 0.6 Pa, and 2.5 kW AC power was applied to a metal oxide target (having an atomic ratio of In:Ga:Zn = 4:2:4.1) containing indium, gallium, and zinc. The tantalum nitride film and the copper film were formed using a sputtering device.

[0306] After that, plasma treatment was performed from above the oxide semiconductor film, insulating film, and conductive film. This plasma treatment was performed using a PECVD device at a substrate temperature of 220°C in a mixed gas atmosphere containing argon and nitrogen gases.

[0307] Then, an insulating film was formed on an oxide semiconductor film, an insulating film, and a conductive film. The insulating film was formed by stacking a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm using a PECVD device.

[0308] Then, a mask was formed on the formed insulating film, and an opening was formed in the insulating film using this mask.

[0309] A conductive film was formed to fill the opening and processed into an island shape, thereby forming a conductive film that functions as a source electrode and a drain electrode. On the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed using a sputtering device.

[0310] After that, an insulating film was formed on the insulating film and the conductive film. An acrylic photosensitive resin with a thickness of 1.5 μm was used for the insulating film.

[0311] In this way, sample S1A was formed.

[0312] Except for the conditions for forming the oxide semiconductor film, sample S1B was formed in a manner similar to that in which sample S1A was formed. The oxide semiconductor film of sample S1B was formed under conditions in which the substrate temperature was set to room temperature (25°C), argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber of the sputtering device, the pressure was set to 0.6 Pa, and 2.5 kW of AC power was applied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic number ratio]) containing indium, gallium, and zinc. The oxygen flow rate ratio during the deposition of the oxide semiconductor film of sample S1B was 50%.

[0313] Except for the conditions for forming the oxide semiconductor film, sample S1C was formed in a manner similar to that in which sample S1A was formed. The oxide semiconductor film of sample S1C was formed under conditions in which the substrate temperature was set to room temperature (25°C), oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering apparatus, the pressure was set to 0.6 Pa, and 2.5 kW of AC power was applied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic number ratio]) containing indium, gallium, and zinc. The oxygen flow rate ratio during the deposition of the oxide semiconductor film of sample S1C was 100%.

[0314] [Transistor's I d - V g characteristic]

[0315] Next, the transistors of samples S1A to S1C I d - V g The characteristics of each transistor were measured. I d - V g As a condition for measuring the characteristics, the voltage applied to the conductive film functioning as the first gate electrode (hereinafter this voltage is the gate voltage ( V gAlso referred to as ), and the voltage applied to the conductive film functioning as the second gate electrode (hereafter this voltage is the back gate voltage ( V bg The voltage applied to the conductive film functioning as the source electrode (this voltage is the source voltage ( V s Set the voltage applied to the conductive film functioning as the drain electrode (this voltage is the drain voltage ( V d (also called ) was set to 0.1V and 20V.

[0316] Figure 1 shows sample S1A. I d - V g Figure 2 shows the results of the characteristics of sample S1B. I d - V g Figure 3 shows the results of the characteristics of sample S1C. I d - V g This shows the results of the characteristics. In FIGS. 1 to 3, the first vertical axis is I d (A) represents the electric field-effect mobility (μ) on the second vertical axis. FE )(cm 2 Represents / Vs), and the horizontal axis is V g (V) is represented. Also, the electric field-effect mobility is V d It was measured when the voltage was 20V.

[0317] As shown in FIG. 1, a transistor, which is a semiconductor device of one embodiment of the present invention, has good electrical characteristics. Table 2 shows the characteristics of the transistor shown in FIG. 1.

[0318] [Table 2]

[0319]

[0320] As shown in Table 2, for sample S1A, the maximum value of the transistor's field-effect mobility is 40 cm⁻¹ when the gate voltage is higher than 0 V and lower than 10 V. 2 / Vs over 150cm 2 A first region less than / Vs, a second region where the threshold voltage is between -1V and 1V, a third region where the S value is less than 0.3V / decade, and an off-state current of 1×10 -12 A / cm 2 It includes a fourth region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g If =2V) represents the value of the transistor's field-effect mobility when the gate voltage is 2V, then μ FE (max) / μ FE ( V g =2V) is 1 or greater and less than 1.5.

[0321] As shown in FIG. 2, a transistor, which is a semiconductor device of one embodiment of the present invention, has good transistor characteristics. Table 3 shows the transistor characteristics shown in FIG. 2.

[0322] [Table 3]

[0323]

[0324] As shown in Table 3, for sample S1B, the maximum value of the transistor's field-effect mobility is 40 cm⁻¹ when the gate voltage is higher than 0 V and 10 V or lower. 2 / Vs over 150cm 2 A first region less than / Vs, a second region where the threshold voltage is between -1V and 1V, a third region where the S value is less than 0.3V / decade, and an off-state current of 1×10 -12 A / cm 2 It includes a fourth region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μFE ( V g If =2V) represents the value of the transistor's field-effect mobility when the gate voltage is 2V, then μ FE (max) / μ FE ( V g =2V) is 1.5 or greater and less than 3.

[0325] As shown in FIG. 3, a transistor, which is a semiconductor device of one embodiment of the present invention, has good transistor characteristics. Table 4 shows the transistor characteristics shown in FIG. 3.

[0326] [Table 4]

[0327]

[0328] As shown in Table 4, for sample S1C, the maximum value of the transistor's field-effect mobility is 10 cm when the gate voltage is higher than 0 V and 10 V or lower. 2 / Vs over 100cm 2 A first region less than / Vs, a second region where the threshold voltage is between -1V and 1V, a third region where the S value is less than 0.3V / decade, and an off-state current of 1×10 -12 A / cm 2 It includes a fourth region less than, and μ FE (max) represents the maximum value of the transistor's field-effect mobility, and μ FE ( V g If =2V) represents the value of the transistor's field-effect mobility when the gate voltage is 2V, then μ FE (max) / μ FE ( V g =2V) is 3 or more and less than 10.

[0329] The above transistor characteristics can be obtained using the aforementioned composite oxide semiconductor or C / IGZO. In a transistor comprising the aforementioned composite oxide semiconductor or C / IGZO as a semiconductor layer, the function of achieving high carrier mobility and the function of achieving good switching characteristics can be obtained simultaneously.

[0330] <1-12. Evaluation of Mobility Curve Shape by Device Simulation>

[0331] Next, the shape of the field-effect mobility curve of the transistor shown in Fig. 1 was evaluated from various perspectives by device simulation.

[0332] Three factors were assumed to determine the shape of the mobility curve in device simulation: 1. the temperature dependence of mobility, 2. the donor density distribution in the channel region, and 3. the density of shallow defect levels (also called sDOS) within the oxide semiconductor film.

[0333] [1. Temperature Dependence of Mobility]

[0334] In transistors containing oxide semiconductor films, field-effect mobility increases rapidly due to self-heating. Electron mobility (μ) of oxide semiconductor films n The temperature dependence of ) is expressed by the following equation (5).

[0335] [Equation 5]

[0336]

[0337] μ in equation (5) n300 represents the electron mobility of an oxide semiconductor film at room temperature, and T L represents the lattice temperature. As shown in Equation (5), the field-effect mobility of a transistor including an oxide semiconductor film is approximately temperature T It increases in proportion to the 1.5th power of.

[0338] [2. Donor density distribution in the channel region]

[0339] Here, the effective channel length of the transistors of samples S1A to S1C is explained with reference to FIG. 18.

[0340] Figure 18 is a schematic diagram illustrating the concept of the effective channel length of a transistor.

[0341] In FIG. 18, GE, GI, and OS are referred to as the gate electrode, gate insulating film, and oxide semiconductor film, respectively. An n-type region is formed in the oxide semiconductor film. The effective channel length (L) of the transistor. eff ) is represented by the following formula (6).

[0342] [Equation 6]

[0343]

[0344] L in equation (6) g represents the gate length, and △L represents the reduction width of the channel length.

[0345] The effective channel length of a transistor can be obtained, for example, by TLM (transmission line model) analysis.

[0346] In the description below, a model was assumed in which the donor density gradually decreases from the n-type region across the channel region based on the aforementioned effective channel length. That is, the donor decreases toward the channel region according to a Gaussian distribution. Figures 19 (A) to (C) show schematic diagrams illustrating the donor density in the channel region.

[0347] Figures 19 (A), (B), and (C) respectively show the donor density of sample S1A, the donor density of sample S1B, and the donor density of sample S1C.

[0348] In FIG. 19 (A) to (C), GE, GI, and OS are referred to as the gate electrode, gate insulating film, and oxide semiconductor film, respectively. In the oxide semiconductor film illustrated in FIG. 19 (A) to (C), the donor density is 5×10 18 cm-3 Areas with abnormalities are shown in gray, and the donor density is 1×10 16 cm -3 The area below is displayed as a search.

[0349] From the results shown in FIG. 19 (A), (B), and (C), the effective channel lengths of the transistors shown in FIG. 19 (A), (B), and (C) were estimated to be 2.0 μm, 1.2 μm, and 0.8 μm, respectively. In other words, the ΔL of the transistor shown in FIG. 19 (A), the ΔL of the transistor shown in FIG. 19 (B), and the ΔL of the transistor shown in FIG. 19 (C) were estimated to be 0 μm, 0.4 μm, and 0.6 μm, respectively.

[0350] [3. Density of shallow defect levels in oxide semiconductor films]

[0351] Next, the density of shallow defect levels (also known as sDOS) within an oxide semiconductor film is explained. The sDOS of an oxide semiconductor film can be estimated from the electrical characteristics of a transistor containing the oxide semiconductor film. In the following description, the density of interface levels in the transistor was evaluated. Additionally, the density of interface levels, and the number of electrons N trapped at the interface levels... trap A method for estimating subthreshold leakage current is explained by taking this into consideration.

[0352] The number of electrons N trapped at the interface level trap is the actually measured drain current-gate voltage of the transistor ( I d - V g ) and, calculated drain current-gate voltage( I d - V g It can be measured by comparing ) characteristics.

[0353] Figure 20 shows the source voltage ( V s ) is 0V and drain voltage( V dThe ideal obtained by calculation when ) is 0.1V I d - V g Characteristics and actually measured transistor I d - V g This illustrates the characteristics. In addition, among the transistor measurement results, the drain current I d 1×10⁻⁶ that can be easily measured -13 Only values ​​greater than or equal to A were plotted.

[0354] Actually measured I d - V g The characteristics are ideal obtained by calculation I d - V g Gate voltage rather than characteristics ( V g Drain current for ) I d The change in ) is more gradual. This is thought to be because electrons are trapped in shallow interface levels located near the energy of the bottom of the conduction band (denoted as Ec). In this measurement, the Fermi distribution function was used to determine the number of electrons N trapped (per unit area and per unit energy) in shallow interface levels. trap By considering, the density N of the interface levels it You can estimate it more accurately.

[0355] First, the number of electrons N trapped at the interface trap level trap Regarding the evaluation method, the schematic shown in FIG. 21 I d - V g It is explained using properties. The dashed line represents the ideal without trap levels, obtained by calculation. I d - V g It exhibits characteristics. The drain current I dFrom 1 I d Gate voltage when changing to 2 ( V g △V on the dashed line representing the change of ) id It is represented as follows. The solid line represents the actually measured I d - V g It exhibits characteristics. The drain current I d From 1 I d Gate voltage when changing to 2 ( V g △V on the solid line representing the change of ) ex It is represented as. The drain current is I d The potential at the interface of interest and the drain current when it is 1 I d When it is 2, the potential and change amount at the interface of interest are φ, respectively. it1 , φ it2 , and △φ it It is represented as.

[0356] In Fig. 21, the slope of the actually measured value is smaller than the slope of the calculated value, and this is △V ex is always △V id It implies something larger. Here, △V ex wa △V id The difference between them corresponds to the potential difference required to trap electrons at shallow interface levels. Therefore, the change in charge ΔQ due to trapped electrons. trap It can be expressed by the following formula (7).

[0357] [Equation 7]

[0358]

[0359] C tg ε is the combined capacitance of the insulator and semiconductor per unit area. Also, ΔQ trap N is the number of trapped electrons (per unit area and per unit energy). trap It can also be expressed as Equation (8) using . Also qrepresents a small amount of electricity.

[0360] [Equation 8]

[0361]

[0362] Equation (9) is given by solving equations (7) and (8) simultaneously.

[0363] [Equation 9]

[0364]

[0365] Next, △φ in Equation (9) it Equation (10) is given by taking the limit of 0.

[0366] [Equation 10]

[0367]

[0368] In other words, ideal I d - V g Characteristics, actually measured I d - V g Using the characteristics and equation (10), the number of electrons N trapped at the interface trap It can be estimated. In addition, the relationship between the drain current and the potential at the interface can be obtained by calculation using the device simulator described above.

[0369] Number of electrons N per unit area and per unit energy trap and the density N of the interface level it The relationship can be expressed by equation (11).

[0370] [Equation 11]

[0371]

[0372] Here, f(E) is the Fermi distribution function. N obtained from Equation (10) trap By fitting N to Equation (11) it Determines this N it By the device simulator configured, Id Transfer characteristics including <0.1pA can be obtained.

[0373] The actually measured of Fig. 22 I d - V g Apply Equation (10) to the characteristics, and N trap The result of extracting is plotted as a white circle in FIG. 20. The vertical axis of FIG. 22 represents the Fermi energy (Ef) at the bottom of the conduction band (Ec) of the semiconductor. The maximum value is located on the dashed line immediately below Ec. N of Equation (11) it Assuming the tail distribution of Equation (12), N as shown by the dashed line in FIG. 22 trap It can fit well. Consequently, the peak value N as a fitting parameter. ta = 1.67 × 10 13 cm -2 / eV -1 and characteristic width W ta =0.105eV is obtained.

[0374] [Equation 12]

[0375]

[0376] By feeding back the obtained interface level fitting curve to calculations using a device simulator I d - V g The results of inversely calculating the characteristics are shown in Figures 23 (A) and (B). Figure 23 (A) shows the drain voltage ( V d Calculated when ) is 0.1V and 1.8V I d - V g Characteristics, and drain voltage ( V d Actually measured when ) is 0.1V and 1.8V I d - V g It shows the characteristics. Fig. 23 (B) is the drain current of Fig. 23 (A) ( Id It is a graph in logarithmic form.

[0377] The curve obtained by calculation and the plot of the actually measured values ​​roughly coincide, suggesting that the calculated and measured values ​​have high reproducibility. Therefore, the above-described method is very suitable for calculating the density of shallow defect levels.

[0378] [4. Calculation Results of the Mobility Curve]

[0379] The sDOS of the oxide semiconductor film affects the mobility curve of the field-effect mobility. In particular, near the threshold voltage, the shape of the mobility curve changes because electrons are trapped by the sDOS. The sDOS of the oxide semiconductor film is N in Equation (12). ta , W ta , and thickness t OS It is expressed as a product of . Next, the mobility curve was calculated based on Equation (12). Table 5 shows the parameters used in the calculation.

[0380] [Table 5]

[0381]

[0382] In this embodiment, W ta The mobility curves were calculated for cases where the value of was varied. Figure 24 shows W ta This shows the shape of the mobility curve with different values ​​of . In Fig. 24, N ta 2.5×10 19 cm -3 eV -1 And △L is 0. Also W ta The seven conditions were set to 0.015 eV, 0.02 eV, 0.025 eV, 0.03 eV, 0.035 eV, 0.04 eV, and 0.045 eV.

[0383] As shown in FIG. 24, W taThe smaller the value of , that is, the narrower the energy range of sDOS, the steeper the rise in the mobility curve. Additionally, the narrower the energy range of sDOS, the higher the peak value of the mobility curve. V g Low on the side V g I found that it fluctuates and decreases on the side.

[0384] [5. Effect of Diffusion Current on Mobility Curves]

[0385] Next, the effect of the diffusion current on the mobility curve is explained. The drain current of the FET is expressed by the following equation (13).

[0386] [Equation 13]

[0387]

[0388] As shown in Equation (13), the drain current is the sum of the drift current component and the diffusion current component. Also, in Equation (13), terms 1 and 2 represent the drift current and the diffusion current, respectively. FIG. 25 I d - V g This is a schematic diagram illustrating the contribution of the diffusion current and drift current components to the characteristics.

[0389] The influence of the diffusion current component on the mobility curve (saturation) was estimated through device simulation. For the FET, the active layer is an oxide semiconductor, and the source-drain region is n + A dual-gate FET was established in which the region and the channel region are intrinsic. Table 6 shows the calculation conditions. In addition, the interface between the GI and the active layer and the trap levels (e.g., sDOS) within the active layer are not established.

[0390] [Table 6]

[0391]

[0392] Figure 26 is obtained by simulation I d -V g This shows the characteristic and saturation mobility curves. Also, in Fig. 26 I d - V g The characteristics and the saturation mobility curve overlap each other. As shown in Fig. 26, the mobility curve is I d - V g characteristics V th It has a peak nearby.

[0393] Figure 27 is a schematic band diagram in the thickness direction of a dual-gate FET.

[0394] As shown in FIG. 27, because the band is relatively flat in the thickness direction of the semiconductor due to the gate electric field, the current flows through the entire semiconductor film. In a dual-gate FET having such a band, the drain current in the subthreshold region is expressed by the following equation (14).

[0395] [Equation 14]

[0396]

[0397] In equation (14) k represents the Boltzmann constant, and T represents the temperature, n i represents the intrinsic carrier density, t S represents the thickness of the active layer, and △ φ represents the difference between the intrinsic Fermi level and the work function of the gate. Equation (14) suggests that the diffusion current is proportional to the difference between the diffusion current density at the end of the source region and the diffusion current density at the end of the drain region.

[0398] Equation (15) can be obtained by substituting Equation (14) into the equation defining the saturation mobility.

[0399] [Equation 15]

[0400]

[0401] According to equation (15), the saturation mobility curve is V th It has a peak nearby. That is, the saturation mobility curve observed in ideal simulations where trap levels such as sDOS are not assumed. V th The nearby peak appears to be due to the diffusion current flowing through the entire active layer.

[0402] However, in the actual mobility curve of the IGZO-FET V th Such sharp peaks are not observed nearby. Assuming that shallow electron trap levels (e.g., sDOS) exist within the OS film or at the interface between the OS film and the gate insulating film, the mobility curve can be made closer to the shape of the measured mobility curve. Figure 28 shows the results of a device simulation assuming sDOS within the OS film.

[0403] Figure 28 suggests that the mobility curve is affected by the sDOS of the OS film. As the thickness of the OS film increases, the amount of sDOS of the OS film increases. Therefore, as the thickness of the OS film increases, the field-effect mobility decreases. Figure 29 shows the relationship between the field-effect mobility (maximum value) and the thickness of the OS film of the FET.

[0404] In Fig. 29, the vertical axis represents the field-effect mobility (maximum value), and the horizontal axis represents the film thickness of the OS. Also, in Fig. 29, the results of four transistors with different channel lengths L (L = 2 μm, 3 μm, 6 μm, and 10 μm) are superimposed. As shown in Fig. 29, the field-effect mobility decreases as the film thickness of the OS increases.

[0405] Figures 30 (A) and (B) show saturation mobility curves calculated under conditions where the distribution of sDOS is different. Figure 30 (A) shows the sDOS distribution of the OS film, and Figure 30 (B) shows the shape of the mobility curve. As indicated by the arrows in Figures 30 (A) and (B), the shape of the saturation mobility curve changes depending on the amount of energy levels of sDOS or the distribution of sDOS.

[0406] [6. Influence of Parasitic Resistance in Source and Drain Regions]

[0407] Next, the influence of parasitic resistance in the source and drain regions (also called SD regions) of the TGSA OS-FET is explained. The TGSA OS-FET includes source and drain regions on both sides of the channel region, which are formed by reducing the resistance of the active layer. The source and drain regions may act as parasitic resistances in the FET characteristics. In this case, the TGSA OS-FET is represented by a circuit diagram as shown in (A) of FIG. 31.

[0408] In the case of the circuit diagram shown in (A) of Fig. 31, V d As shown in equation (16), it is divided into the voltage applied to the two parasitic resistors and the voltage applied to the FET.

[0409] [Equation 16]

[0410]

[0411] In equation (16), R represents parasitic resistance, V FET represents the potential difference applied to both ends of the FET channel. In the GCA equation V FET = V g - V th satisfying V gThe region above is considered a linear region. Therefore, as shown in (A) of FIG. 31, when parasitic resistance is present, a linear region is formed. V g , in other words V FET = V g - V th satisfying V g It is lower than in the case where parasitic resistance does not exist.

[0412] As shown in Fig. 15, the saturation mobility decreases after entering the linear region. In light of this, the lower limit of the linear region V g It is assumed that it decreases as the resistance value of parasitic resistance increases. Therefore, through device simulations in which the sizes of the source and drain regions are varied, the field-effect mobility and V g The relationship between them was obtained. Figure 31 (B) shows the device simulation results. As shown in Figure 31 (B), by increasing the size of the source and drain regions formed by reducing the resistance of the active layer and thereby increasing the parasitic resistance, the lower limit of the linear region V g , that is, where the saturation mobility curve begins to decrease V g It decreases.

[0413] [7. Effects of Self-Heating]

[0414] Next, the effect of self-heating in FETs is explained. A FET generates heat when current flows through it. As the amount of current increases, the amount of heat generated increases, which is evident from Joule's law. Furthermore, the amount of current in the FET V g As increases, it increases, and the self-heating of the FET follows Joule's law. V g It increases as it increases.

[0415] According to the above-described GCA, the drain current in the saturation region is as shown in Equation (2) ( V g - V th ) 2 It is proportional to. Therefore, when plotting the square root of the drain current, a straight line shape is obtained in the saturation region. The slope of this straight line is calculated by differentiation, and the saturation mobility is obtained by normalizing the calculation result by channel length, channel width, and gate capacitance to convert it into mobility.

[0416] Since no obvious temperature variable is included in the GCA equation, saturation mobility appears not to depend on temperature. However, in OS-FETs, some of the parameters included in the GCA have temperature dependence. Therefore, the shape of the saturation mobility curve changes due to the influence of the FET's self-heating.

[0417] The first parameter that changes with temperature is the electron mobility of IGZO. The electron mobility of IGZO increases as the temperature rises. In other words, if the amount of current flowing through the FET increases and the temperature of the FET rises, the electron mobility of IGZO increases. Therefore V g or V d Under conditions where is high, the FET temperature rises due to self-heating, increasing electron mobility and drain current. Therefore, in the saturation region, √ I d - V g The slope of the characteristic increases, and the saturation mobility increases. The effect of self-heating of the FET is evaluated by device simulation. Figure 32 shows the results of the device simulation. In Figure 32 I d - V g The calculation results of the characteristics and the saturation mobility curve of the TGSA CAAC-OS-FET are shown.

[0418] The effect of self-heating in FETs is particularly pronounced in TGSA FETs. This is because TGSA FETs are more difficult to dissipate heat than BGTC FETs.

[0419] BGTC FETs have excellent heat dissipation characteristics because the source and drain regions are located close to the channel region where heat is generated. On the other hand, TGSA FETs have poor heat dissipation characteristics because the electrodes functioning as heat dissipation paths are located away from the channel region. Consequently, the temperature of TGSA FETs rises easily due to self-heating, and the mobility curve is easily affected by self-heating.

[0420] The second parameter that changes depending on temperature is the number of carrier electrons. The number of electrons per unit area accumulated in the gate capacitance is C ox ( V g - V th It is represented as ). If an electron trap is present, some of the accumulated electrons are trapped in the electron trap, and the carrier electrons decrease. As described above, since the OS contains an electron trap called sDOS, some of the electrons accumulated in the gate capacitance do not function as carriers.

[0421] Since the sDOS level is lower than the bottom of the conduction band, considering the Boltzmann distribution, the ratio of carrier electrons to trapped electrons increases as the temperature rises. As mentioned above, the temperature of the FET is V g Since it rises as increases, the ratio of carrier electrons V g It increases as increases. Therefore, saturation mobility also V g It increases as it increases.

[0422] Under the assumption that sDOS is considered and the electron mobility of CAAC-OS does not depend on temperature, the temperature dependence of the FET's saturation mobility was calculated by device simulation. The calculation results are shown in Fig. 33. As shown in Fig. 33, when electron mobility depends on temperature, compared to when electron mobility does not depend on temperature, the mobility is V g As it increases, it increases more clearly.

[0423] [8. Effects of Reduction in Effective Channel Length]

[0424] The channel length of a CAAC-OS FET corresponds to the distance between the source and drain electrodes in the BGTC structure and to the length of the gate electrode in the TGSA structure. However, in actual FET characteristics, the effective channel length is n of the source region. + n in the region and drain region + It is the distance between regions. Depending on process conditions, n + The boundary between the region and the channel region does not coincide with the end of the gate electrode, and n + There are cases where the region extends beyond the gate electrode end toward the channel. In this case, the field-effect mobility appears to increase. Figure 34 shows the field-effect mobility and V g This represents the relationship between them. In Fig. 34, the vertical axis represents the electric field effect mobility, and the horizontal axis is V g It represents.

[0425] Based on the explanation up to this point, three shapes of the saturation mobility curves of the TGSA OS-FET are obtained. Figures 35 (A) to (C) show the calculated results of the saturation mobility of the TGSA OS-FET. Figure 35 (A) corresponds to sample S1A, Figure 35 (B) corresponds to sample S1B, and Figure 35 (C) corresponds to sample S1C.

[0426] As shown in FIGS. 35 (A) to (C), the shape of the saturation mobility curve varies by setting the parameter of sDOS, in particular, to an appropriate value. In the case of the semiconductor device corresponding to sample S1A, the saturation mobility curve has the shape shown in FIG. 35 (A), which suggests that the sDOS value is small. Similarly, in the case of the semiconductor device corresponding to sample S1B, the saturation mobility curve has the shape shown in FIG. 35 (B), which suggests that the sDOS value is small. In the case of the semiconductor device corresponding to sample S1C, the saturation mobility curve has the shape shown in FIG. 35 (C).

[0427] The transistor shown in Fig. 1 I d - V g Using the properties, the sDOS value of the oxide semiconductor film of sample S1A was measured. From the measurement results, the sDOS of the oxide semiconductor film of sample S1A was 6.4×10⁻⁶. -12 cm -2 was. Therefore, in one embodiment of the present invention, the oxide semiconductor film has a region with a small sDOS value, i.e., a density of shallow defect levels of 1.0 × 10⁻⁶ -12 cm -2 Includes the area less than

[0428] The transistor shown in Fig. 2 I d - V g Using the properties, the sDOS value of the oxide semiconductor film of sample S1B was measured. From the measurement results, the sDOS of the oxide semiconductor film of sample S1B was 1.7×10⁻⁶ -12 cm -2 was. Therefore, in one embodiment of the present invention, the oxide semiconductor film has a region with a small sDOS value, i.e., a density of shallow defect levels of 1.0 × 10⁻⁶ -12 cm -2 At most 2.0×10 -12 cm -2 Includes the area less than

[0429] The transistor shown in Fig. 3 I d - V g Using the properties, the sDOS value of the oxide semiconductor film of sample S1C was measured. From the measurement results, the sDOS of the oxide semiconductor film of sample S1C was 2.4×10⁻⁶ -12 cm -2 was. Therefore, in one embodiment of the present invention, the oxide semiconductor film has a region with a small sDOS value, i.e., a density of shallow defect levels of 2.0 × 10⁻⁶ -12 cm -2 3.0×10 -12 cm -2 Includes the area less than

[0430] <1-13. Components of a Transistor>

[0431] Next, details regarding the components of the transistors in (A) to (C) of FIG. 17 will be explained.

[0432] [Circuit board]

[0433] A material having sufficiently high heat resistance to withstand heat treatment in the manufacturing process can be used for the substrate (102).

[0434] Specifically, alkali-free glass, soda-lime glass, potash glass, crystal glass, quartz, or sapphire may be used. Alternatively, an inorganic insulating film may be used. Examples of such inorganic insulating films include silicon oxide films, silicon nitride films, silicon oxynitride films, and aluminum oxide films.

[0435] For example, it is preferable that the alkali-free glass has a thickness of 0.2 mm or more and 0.7 mm or less. The above-mentioned thickness may also be obtained by polishing the alkali-free glass.

[0436] By using alkali-free glass, large glass substrates of any size from the 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), 8th generation (2200mm × 2400mm), 9th generation (2400mm × 2800mm), and 10th generation (2950mm × 3400mm) can be used. This allows for the production of large display devices.

[0437] Alternatively, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, or an SOI substrate may be used as the substrate (102).

[0438] Alternatively, an inorganic material such as metal may be used as the substrate (102). Examples of inorganic materials such as metal include stainless steel and aluminum.

[0439] Alternatively, the substrate (102) may be made of an organic material such as a resin, a resin film, or a plastic. Examples of this resin film include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and resins having siloxane bonds.

[0440] Alternatively, the substrate (102) may use a composite material that combines an inorganic material and an organic material. Examples of this composite material include a resin film in which a metal plate or a thin glass plate is bonded, a resin film in which fibrous or particulate metal or fibrous or particulate glass is dispersed, and an inorganic material in which fibrous or particulate resin is dispersed.

[0441] Additionally, the substrate (102) can be formed using one or more of an insulating film, a semiconductor film, and a conductive film, provided that it supports at least a film or layer formed above or below it.

[0442] [First insulating layer]

[0443] The insulating film (104) can be appropriately formed by sputtering, CVD, deposition, PLD (pulsed laser deposition), printing, or coating methods. For example, the insulating film (104) can be formed to have a single-layer structure or a stacked structure including an oxide insulating film and / or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film (108), it is preferable to form at least the region of the insulating film (104) in contact with the oxide semiconductor film (108) using an oxide insulating film. If the insulating film (104) is formed using an oxide insulating film that releases oxygen upon heating, the oxygen contained in the insulating film (104) can be transferred to the oxide semiconductor film (108) by heat treatment.

[0444] The thickness of the insulating film (104) can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By making the thickness of the insulating film (104) thicker, the amount of oxygen released from the insulating film (104) can be increased, and the interface level at the interface between the insulating film (104) and the oxide semiconductor film (108), and the oxygen vacancies included in the channel region (108i) of the oxide semiconductor film (108) can be reduced.

[0445] For example, the insulating film (104) can be formed to have a single-layer structure or a stacked structure including silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide. In this embodiment, the insulating film (104) has a stacked structure of a silicon nitride film and a silicon nitride oxide film. By using an insulating film (104) having a layered structure including a silicon nitride film as a lower layer and a silicon nitride oxide film as an upper layer, oxygen can be efficiently introduced into the oxide semiconductor film (108).

[0446] [Oxide semiconductor film]

[0447] As the oxide semiconductor film (108), the above-described composite oxide semiconductor or C / IGZO is suitablely used.

[0448] [Second insulating layer]

[0449] The insulating film (110) has the function of supplying oxygen to the oxide semiconductor film (108), particularly the channel region (108i). The insulating film (110) may be formed to have a single-layer structure or a stacked structure of, for example, an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film (108), it is preferable to form the region within the insulating film (110) and in contact with the oxide semiconductor film (108) using at least an oxide insulating film. For example, silicon oxide, silicon nitride, silicon nitride, or silicon nitride may be used for the insulating film (110).

[0450] The thickness of the insulating film (110) can be 5 nm or more and 400 nm or less, 5 nm or more and 300 nm or less, or 10 nm or more and 250 nm or less.

[0451] It is desirable that the insulating film (110) has few defects, and, typically, that the signal observed by electron spin resonance (ESR) spectroscopy is as small as possible. Examples of the above signal include g The signal includes a signal attributed to an E' center observed at a factor of 2.001. Additionally, the E' center is attributed to the dangling bonds of silicon. For the insulating film (110), the spin density of the signal attributed to the E' center is 3×10 17 spins / cm 3 Less than or equal to, preferably 5×10 16 spins / cm 3 Silicon oxide films or silicon nitride films of the following values ​​may be used.

[0452] In the insulating film (110), in addition to the above-described signal, a signal attributable to nitrogen dioxide (NO2) may be observed. This signal is divided into three signals, a first signal, a second signal, and a third signal, depending on the nuclear spin of N. The first signal is observed when the g-factor is 2.037 or higher and 2.039 or lower. The second signal is observed when the g-factor is 2.001 or higher and 2.003 or lower. The third signal is observed when the g-factor is 1.964 or higher and 1.966 or lower.

[0453] For example, as an insulating film (110), the spin density attributable to nitrogen dioxide (NO2) is 1×10 17 spins / cm 3 1×10 18 spins / cm 3 It is suitable to use an insulating film of less than [amount].

[0454] Also, nitrogen oxides (NO₂) such as nitrogen dioxide (NO₂) x ) forms a level in the insulating film (110). The level is located within the energy gap of the oxide semiconductor film (108). Thus, nitrogen oxide (NO x When ) diffuses to the interface between the insulating film (110) and the oxide semiconductor film (108), electrons can be trapped at the level on the insulating film (110) side. Consequently, because the trapped electrons remain near the interface between the insulating film (110) and the oxide semiconductor film (108), the threshold voltage of the transistor fluctuates in the positive direction. Therefore, if a film with a low nitrogen oxide content is used as the insulating film (110), the fluctuation of the threshold voltage of the transistor can be reduced.

[0455] small amount of nitrogen oxides (NO₂ x As an insulating film that emits ), for example, a silicon nitride film can be used. This silicon nitride film emits nitrogen oxide (NO₂) in thermal desorption spectroscopy (TDS). x It emits more ammonia than ), and the typical ammonia emission amount is 1×10 18 / cm 3 At least 5×10 19 / cm 3 The above amount of ammonia release is the total amount of ammonia released by heat treatment in the range of 50°C to 650°C or 50°C to 550°C in TDS.

[0456] Nitrogen oxides (NO₂) x Since ) reacts with ammonia and oxygen during heat treatment, using an insulating film with a high ammonia emission rate results in nitrogen oxides (NO x ) is reduced.

[0457] Also, when the insulating film (110) is analyzed by SIMS, the nitrogen concentration in the film is 6×10 20 atoms / cm 3 It is desirable that it be less than or equal to this.

[0458] The insulating film (110) is hafnium silicate (HfSiO2). x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen-added hafnium aluminate (HfAl x O y N z It may also be formed using high-k materials such as hafnium oxide, or high-k materials. By using such high-k materials, gate leakage of the transistor can be reduced.

[0459] [Third Insulating Film]

[0460] The insulating film (116) contains nitrogen or hydrogen. The insulating film (116) may also contain fluorine. The insulating film (116) is, for example, a nitride insulating film. The nitride insulating film may be formed using silicon nitride, silicon nitride oxide, silicon nitride oxide, silicon fluoride nitride, or silicon fluoride nitride, etc. The hydrogen concentration of the insulating film (116) is 1×10⁻⁶ 22 atoms / cm3 It is desirable that the above be the case. Additionally, the insulating film (116) is in contact with the source region (108s) and drain region (108d) of the oxide semiconductor film (108). Accordingly, the concentration of impurities (nitrogen or hydrogen) in the source region (108s) and drain region (108d) in contact with the insulating film (116) increases, and the carrier density of the source region (108s) and drain region (108d) increases.

[0461] [Fourth insulating layer]

[0462] As the insulating film (118), an oxide insulating film may be used. Alternatively, as the insulating film (118), a laminate including an oxide insulating film and a nitride insulating film may be used. The insulating film (118) may be formed using, for example, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide.

[0463] In addition, it is desirable that the insulating film (118) functions as a barrier film against hydrogen and water from the outside.

[0464] The thickness of the insulating film (118) can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

[0465] [Fifth Insulating Layer]

[0466] The insulating film (122) has insulating properties and is formed using an inorganic or organic material. Examples of inorganic materials include silicon oxide film, silicon nitride film, silicon nitride film, silicon nitride film, silicon nitride, aluminum oxide, and aluminum nitride. Examples of organic materials include photosensitive resin materials such as acrylic resin and polyimide resin.

[0467] [Challenge]

[0468] The conductive film (106, 112, 120a, and 120b) can be formed by sputtering, vacuum deposition, PLD, or thermal CVD. Additionally, as the conductive film (106, 112, 120a, and 120b), a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light can be used.

[0469] For the conductive metal film, a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, and magnesium may be used. Alternatively, an alloy containing any of the metal elements mentioned above may be used.

[0470] For the conductive metal film, specifically, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a titanium nitride film, a two-layer structure in which a copper film is laminated on a tantalum nitride film, or a three-layer structure in which a titanium film, a copper film, and a titanium film are laminated in this order may be used. In particular, it is desirable to use a conductive film containing copper elements as the resistance can be lowered. An example of a conductive film containing copper elements is an alloy film containing copper and manganese. It is desirable that this alloy film can be processed by a wet etching method.

[0471] It is preferable to use a tantalum nitride film as each of the conductive films (106, 112, 120a, and 120b). Such tantalum nitride films have conductivity and high barrier properties against copper or hydrogen. Since the tantalum nitride film has a low hydrogen emission rate, it can be most preferably used as a metal film in contact with the oxide semiconductor film (108) or as a metal film near the oxide semiconductor film (108).

[0472] As a conductive film having conductivity, a conductive polymer or a conductive polymer may be used.

[0473] For a conductive film having the function of reflecting visible light, a material containing a metal element selected from gold, silver, copper, and palladium may be used. In particular, a conductive film containing a silver element is preferably used because it can improve the reflectivity of visible light.

[0474] For a conductive film having the function of transmitting visible light, a material containing an element selected from indium, tin, zinc, gallium, and silicon may be used. Specifically, In oxide, Zn oxide, In-Sn oxide (also called ITO), In-Sn-Si oxide (also called ITSO), In-Zn oxide, or In-Ga-Zn oxide may be used.

[0475] As a conductive film capable of transmitting visible light, a film containing graphene or graphite may be used. A film containing graphene can be formed by forming a film containing graphene oxide and reducing it. As a reduction method, a heating method or a method using a reducing agent may be employed.

[0476] The conductive film (112, 120a, and 120b) can be formed by electroless plating. As materials that can be formed by this electroless plating, one or more of Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used, for example. In particular, Cu or Ag is preferred as it can reduce the resistance of the conductive film.

[0477] When forming a conductive film by electroless plating, a diffusion barrier may be formed beneath the conductive film to prevent the constituent elements of the conductive film from diffusing outward. Additionally, a seed layer capable of growing the conductive film may be formed between this diffusion barrier and the conductive film. The diffusion barrier may be formed, for example, by a sputtering method. As the diffusion barrier, a tantalum nitride film or a titanium nitride film may be used, for example. The seed layer may be formed by an electroless plating method. Alternatively, the seed layer may be formed using a material similar to the material of the conductive film that can be formed by an electroless plating method.

[0478] In addition, an oxide semiconductor, such as In-Ga-Zn oxide, may be used for the conductive film (112). The carrier density of the oxide semiconductor can be increased when nitrogen or hydrogen is supplied from the insulating film (116). In other words, the oxide semiconductor functions as an oxide conductor (OC). Therefore, the oxide semiconductor can be used for the gate electrode.

[0479] For example, the conductive film (112) may have a single-layer structure of an oxide conductor (OC), a single-layer structure of a metal film, or a stacked structure of an oxide conductor (OC) and a metal film.

[0480] Additionally, the conductive film (112) is suitable for having a single-layer structure of a light-shielding metal film, or a stacked structure of an oxide conductor (OC) and a light-shielding metal film, so that the channel region (108i) formed under the conductive film (112) can be blocked from light. When the conductive film (112) has a stacked structure of an oxide semiconductor or an oxide conductor (OC) and a light-shielding metal film, if a metal film (e.g., a titanium film or a tungsten film) is formed on the oxide semiconductor or an oxide conductor (OC), any of the following effects are produced: the effect of reducing the resistance of the oxide semiconductor or an oxide conductor (OC) by diffusing the constituent elements of the metal film toward the oxide semiconductor or an oxide conductor (OC); the effect of reducing the resistance by damage (e.g., sputtering damage) during the deposition of the metal film; and the effect of reducing the resistance when oxygen vacancies are formed by diffusing oxygen from the oxide semiconductor or an oxide conductor (OC) into the metal film.

[0481] The thickness of the conductive film (106, 112, 120a, and 120b) can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

[0482] At least a part of this embodiment may be implemented in appropriate combination with any of the other embodiments described in this specification.

[0483] (Embodiment 2)

[0484] In this embodiment, transistors of a different type from the transistor of Embodiment 1 will be described with reference to FIG. 36 (A) to FIG. 51 (C).

[0485] <2-1. Example of Transistor Structure 2>

[0486] Figures 36 (A) and (B) are cross-sectional views of transistor (100B). Figures 37 (A) and (B) are cross-sectional views of transistor (100C). Figures 38 (A) and (B) are cross-sectional views of transistor (100D). Top views of transistors (100B, 100C, and 100D) are not shown because they are similar to the top view of transistor (100A) in Figure 17 (A).

[0487] The transistor (100B) shown in (A) and (B) of FIG. 36 is different from the transistor (100A) in that the layered structure of the conductive film (112), the shape of the conductive film (112), and the shape of the insulating film (110) are different.

[0488] The conductive film (112) of the transistor (100B) includes a conductive film (112_1) on an insulating film (110) and a conductive film (112_2) on the conductive film (112_1). For example, excess oxygen can be added to the insulating film (110) by using an oxide conductive film as the conductive film (112_1). This oxide conductive film can be formed by sputtering in an atmosphere containing oxygen gas. As this oxide conductive film, for example, an oxide film containing indium and tin, an oxide film containing tungsten and indium, an oxide film containing tungsten, indium, and zinc, an oxide film containing titanium and indium, an oxide film containing titanium, indium, and tin, an oxide film containing indium and zinc, an oxide film containing silicon, indium, and tin, or an oxide film containing indium, gallium, and zinc may be used.

[0489] As shown in (B) of FIG. 36, the conductive film (112_2) is connected to the conductive film (106) through the opening (143). By forming the opening (143) after forming the conductive film that becomes the conductive film (112_1), the shape shown in (B) of FIG. 36 can be obtained. When an oxide conductive film is used as the conductive film (112_1), the contact resistance between the conductive film (112) and the conductive film (106) can be lowered by the structure in which the conductive film (112_2) is connected to the conductive film (106).

[0490] The conductive film (112) and insulating film (110) of the transistor (100B) have a tapered shape. More specifically, the lower portion of the conductive film (112) is located outside the upper portion of the conductive film (112). The lower portion of the insulating film (110) is located outside the upper portion of the insulating film (110). Additionally, the lower portion of the conductive film (112) is formed at substantially the same position as the upper portion of the insulating film (110).

[0491] If the conductive film (112) and insulating film (110) of the transistor (100B) have a tapered shape, the coverage of the insulating film (116) can be increased compared to the case of the transistor (100A) in which the conductive film (112) and insulating film (110) are rectangular, so it is suitable.

[0492] Other components of the transistor (100B) are similar to the components of the transistor (100A) described above and have similar effects.

[0493] The transistor (100C) shown in (A) and (B) of FIG. 37 is different from the transistor (100A) in that the layered structure of the conductive film (112), the shape of the conductive film (112), and the shape of the insulating film (110) are different.

[0494] The conductive film (112) of the transistor (100C) includes a conductive film (112_1) on an insulating film (110) and a conductive film (112_2) on the conductive film (112_1). The lower portion of the conductive film (112_1) is located outside the lower portion of the conductive film (112_2). For example, the structure described above can be obtained by processing the conductive film (112_1), the conductive film (112_2), and the insulating film (110) as a single mask, processing the conductive film (112_2) by a wet etching method, and processing the conductive film (112_1) and the insulating film (110) by a dry etching method.

[0495] In some cases, a region (108f) is formed in the oxide semiconductor film (108) according to the structure of the transistor (100C). The region (108f) is formed between the channel region (108i) and the source region (108s), and between the channel region (108i) and the drain region (108d).

[0496] The region (108f) functions as a high-resistance region or a low-resistance region. The high-resistance region has a resistance of the same degree as the channel region (108i) and does not overlap with the conductive film (112) that functions as a gate electrode. When the region (108f) is a high-resistance region, the region (108f) functions as an offset region. In order to suppress the reduction of the on-state current of the transistor (100C), it is preferable to make the length of each region (108f) that functions as an offset region in the channel length (L) direction 1 μm or less.

[0497] The low-resistance region has lower resistance than the channel region (108i) and higher resistance than the source region (108s) and the drain region (108d). When region (108f) is a low-resistance region, region (108f) functions as a lightly doped drain (LDD) region. Since the region (108f) functioning as an LDD region can mitigate the electric field of the drain region, it can reduce fluctuations in the threshold voltage of the transistor caused by the electric field of the drain region.

[0498] In addition, when the region (108f) functions as an LDD region, for example, one or more of nitrogen, hydrogen, and fluorine are supplied to the region (108f) from the insulating film (116), or by using the insulating film (110) and the conductive film (112_1) as a mask to add an impurity element from above the conductive film (112_1), the impurity element is added to the oxide semiconductor film (108) through the conductive film (112_1) and the insulating film (110), thereby forming the region (108f).

[0499] As shown in (B) of FIG. 37, the conductive film (112_2) is connected to the conductive film (106) through the opening (143).

[0500] Other components of the transistor (100C) are similar to the components of the transistor (100A) described above and have similar effects.

[0501] The transistor (100D) shown in (A) and (B) of FIG. 38 is different from the transistor (100A) in that the layered structure of the conductive film (112), the shape of the conductive film (112), and the shape of the insulating film (110) are different.

[0502] The conductive film (112) of the transistor (100D) includes a conductive film (112_1) on an insulating film (110) and a conductive film (112_2) on the conductive film (112_1). The lower end of the conductive film (112_1) is located outside the lower end of the conductive film (112_2). Also, the lower end of the insulating film (110) is located outside the lower end of the conductive film (112_1). For example, the conductive film (112_1), the conductive film (112_2), and the insulating film (110) can be processed with a single mask, the conductive film (112_2) and the conductive film (112_1) can be processed by a wet etching method, and the insulating film (110) can be processed by a dry etching method to obtain the above-described structure.

[0503] In the transistor (100D), as in the transistor (100C), a region (108f) may be formed in the oxide semiconductor film (108). The region (108f) is formed between the channel region (108i) and the source region (108s), and between the channel region (108i) and the drain region (108d).

[0504] As shown in (B) of FIG. 38, the conductive film (112_2) is connected to the conductive film (106) through the opening (143).

[0505] Other components of the transistor (100D) are similar to the components of the transistor (100A) described above and have similar effects.

[0506] <2-2. Example of Transistor Structure 3>

[0507] Figures 39 (A) and (B) are cross-sectional views of transistor (100E). Figures 40 (A) and (B) are cross-sectional views of transistor (100F). Figures 41 (A) and (B) are cross-sectional views of transistor (100G). Figures 42 (A) and (B) are cross-sectional views of transistor (100H). Figures 43 (A) and (B) are cross-sectional views of transistor (100J). Top views of transistors (100E, 100F, 100G, 100H, and 100J) are not shown because they are similar to the top view of transistor (100A) in Figure 17 (A).

[0508] The transistors (100E, 100F, 100G, 100H, and 100J) differ from the transistor (100A) described above in that the structure of the oxide semiconductor film (108) is different. Other components are similar to the components of the transistor (100A) and have similar effects.

[0509] The oxide semiconductor film (108) of the transistor (100E) illustrated in (A) and (B) of FIG. 39 comprises an oxide semiconductor film (108_1) on an insulating film (104), an oxide semiconductor film (108_2) on an oxide semiconductor film (108_1), and an oxide semiconductor film (108_3) on an oxide semiconductor film (108_2). Each of the channel region (108i), source region (108s), and drain region (108d) has a three-layer structure of oxide semiconductor film (108_1), oxide semiconductor film (108_2), and oxide semiconductor film (108_3).

[0510] The oxide semiconductor film (108) of the transistor (100F) illustrated in (A) and (B) of FIG. 40 comprises an oxide semiconductor film (108_2) on an insulating film (104) and an oxide semiconductor film (108_3) on an oxide semiconductor film (108_2). Each of the channel region (108i), source region (108s), and drain region (108d) has a two-layer structure of an oxide semiconductor film (108_2) and an oxide semiconductor film (108_3).

[0511] The oxide semiconductor film (108) of the transistor (100G) illustrated in (A) and (B) of FIG. 41 comprises an oxide semiconductor film (108_1) on an insulating film (104) and an oxide semiconductor film (108_2) on an oxide semiconductor film (108_1). Each of the channel region (108i), source region (108s), and drain region (108d) has a two-layer structure of an oxide semiconductor film (108_1) and an oxide semiconductor film (108_2).

[0512] The oxide semiconductor film (108) of the transistor (100H) illustrated in (A) and (B) of FIG. 42 comprises an oxide semiconductor film (108_1) on an insulating film (104), an oxide semiconductor film (108_2) on an oxide semiconductor film (108_1), and an oxide semiconductor film (108_3) on an oxide semiconductor film (108_2). The channel region (108i) has a three-layer structure of oxide semiconductor film (108_1), oxide semiconductor film (108_2), and oxide semiconductor film (108_3). The source region (108s) and the drain region (108d) each have a two-layer structure of oxide semiconductor film (108_1) and oxide semiconductor film (108_2). In addition, in the cross-section in the channel width (W) direction of the transistor (100H), the oxide semiconductor film (108_3) covers the sides of the oxide semiconductor film (108_1) and the oxide semiconductor film (108_2).

[0513] The oxide semiconductor film (108) of the transistor (100J) illustrated in (A) and (B) of FIG. 43 comprises an oxide semiconductor film (108_2) on an insulating film (104) and an oxide semiconductor film (108_3) on an oxide semiconductor film (108_2). The channel region (108i) has a two-layer structure of the oxide semiconductor film (108_2) and the oxide semiconductor film (108_3). The source region (108s) and the drain region (108d) each have a single-layer structure of the oxide semiconductor film (108_2). Additionally, in the cross-section along the channel width (W) direction of the transistor (100J), the oxide semiconductor film (108_3) covers the side of the oxide semiconductor film (108_2).

[0514] The side of the channel region (108i) in the direction of the channel width (W) or the area near that side is susceptible to damage from processing, and as a result, defects (e.g., oxygen vacancies) may occur, or it may be susceptible to contamination by impurities attached thereto. Therefore, even if the channel region (108i) is substantially genuine, stress such as an applied electric field activates the side of the channel region (108i) in the direction of the channel width (W) or the area near that side and easily changes it into a low-resistance (n-type) region. In addition, if the side of the channel region (108i) in the direction of the channel width (W) or the area near that side is an n-type region, a parasitic channel may be formed because the n-type region functions as a carrier path.

[0515] Thus, in transistors (100H) and (100J), the channel region (108i) has a stacked structure, and the side of the channel region (108i) in the channel width (W) direction is covered by one layer of the stack. Having such a structure can suppress defects on the side of the channel region (108i) or nearby, or reduce the attachment of impurities to the side of the channel region (108i) or nearby area.

[0516] [Band Structure]

[0517] Here, the band structure of the insulating film (104), oxide semiconductor films (108_1, 108_2, and 108_3), and insulating film (110), the band structure of the insulating film (104), oxide semiconductor films (108_2 and 108_3), and insulating film (110), and the band structure of the insulating film (104), oxide semiconductor films (108_1 and 108_2), and insulating film (110) will be explained with reference to (A) to (C) of FIG. 44. Additionally, each of (A) to (C) of FIG. 44 is a band structure of the channel region (108i).

[0518] FIG. 44 (A) shows an example of a band structure in the thickness direction of a stack comprising an insulating film (104), oxide semiconductor films (108_1, 108_2, and 108_3), and an insulating film (110). FIG. 44 (B) shows an example of a band structure in the thickness direction of a stack comprising an insulating film (104), oxide semiconductor films (108_2 and 108_3), and an insulating film (110). FIG. 44 (C) shows an example of a band structure in the thickness direction of a stack comprising an insulating film (104), oxide semiconductor films (108_1 and 108_2), and an insulating film (110). For ease of understanding, the band structure includes the bottom of the conduction band of the insulating film (104), oxide semiconductor films (108_1, 108_2, and 108_3), and insulating film (110). E c It represented ).

[0519] In the band structure of (A) of FIG. 44, silicon oxide film is used as each of the insulating film (104 and 110), an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In to Ga to Zn of 1:3:2 is used as the oxide semiconductor film (108_1), an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In to Ga to Zn of 4:2:4.1 is used as the oxide semiconductor film (108_2), and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn of 1:3:2 is used as the oxide semiconductor film (108_3).

[0520] In the band structure of (B) in FIG. 44, silicon oxide film is used as each of the insulating film (104 and 110), an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In to Ga to Zn of 4:2:4.1 is used as the oxide semiconductor film (108_2), and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In to Ga to Zn of 1:3:2 is used as the oxide semiconductor film (108_3).

[0521] In the band structure of (C) in FIG. 44, silicon oxide film is used as each of the insulating film (104 and 110), an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In to Ga to Zn of 1:3:2 is used as the oxide semiconductor film (108_1), and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In to Ga to Zn of 4:2:4.1 is used as the oxide semiconductor film (108_2).

[0522] As illustrated in FIG. 44 (A), the bottom of the conduction band gradually changes between the oxide semiconductor films (108_1, 108_2, and 108_3). As illustrated in FIG. 44 (B), the bottom of the conduction band gradually changes between the oxide semiconductor films (108_2 and 108_3). As illustrated in FIG. 44 (C), the bottom of the conduction band gradually changes between the oxide semiconductor films (108_1 and 108_2). In other words, the bottom of the conduction band changes continuously or is continuously joined. To obtain this band structure, there are no impurities forming defect levels, such as trap centers or recombination centers, at the interface between the oxide semiconductor films (108_1 and 108_2) or at the interface between the oxide semiconductor films (108_2 and 108_3).

[0523] In order to form a continuous junction between oxide semiconductor films (108_1, 108_2, and 108_3), it is necessary to form these films continuously without exposure to the atmosphere using a multi-chamber deposition device (sputtering device) provided with a loadlock chamber.

[0524] If the band structure is as shown in (A), (B), or (C) of FIG. 44, the oxide semiconductor film (108_2) functions as a well, and in a transistor using this stacked structure, a channel region is formed in the oxide semiconductor film (108_2).

[0525] By providing oxide semiconductor films (108_1 and 108_3), the oxide semiconductor film (108_2) can be moved away from the defect level.

[0526] Also, the defect level is the lower end of the conduction band of the oxide semiconductor film (108_2) that functions as a channel region ( E c Since it can be located further away from the vacuum level than ), electrons are likely to accumulate in the defect level. When electrons accumulate in the defect level, the electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate in the positive direction. Therefore, the defect level is at the bottom of the conduction band of the oxide semiconductor film (108_2). E c It is desirable that it be closer to the vacuum level than ). This structure suppresses the accumulation of electrons at defect levels. As a result, the on-state current and field-effect mobility of the transistor can be increased.

[0527] The bottom of the conduction band of each oxide semiconductor film (108_1 and 108_3) is closer to the vacuum level than that of the oxide semiconductor film (108_2). The typical difference between the bottom of the conduction band of the oxide semiconductor film (108_2) and the bottom of the conduction band of each oxide semiconductor film (108_1 and 108_3) is greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV. That is, the electron affinity of the oxide semiconductor film (108_2) is greater than the electron affinity of the oxide semiconductor films (108_1 and 108_3). The difference between the electron affinity of each oxide semiconductor film (108_1 and 108_3) and the electron affinity of the oxide semiconductor film (108_2) is greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV.

[0528] In this structure, the oxide semiconductor film (108_2) functions as the main path for current. In other words, the oxide semiconductor film (108_2) functions as a channel region, and the oxide semiconductor films (108_1 and 108_3) function as oxide insulating films. It is preferable that each of the oxide semiconductor films (108_1 and 108_3) contains one or more metal elements that constitute the oxide semiconductor film (108_2) in which the channel region is formed. With this structure, interfacial scattering is difficult to occur at the interface between the oxide semiconductor film (108_1) and the oxide semiconductor film (108_2) or at the interface between the oxide semiconductor film (108_2) and the oxide semiconductor film (108_3). Therefore, since the movement of carriers is not hindered at this interface, the transistor can have high field-effect mobility.

[0529] To prevent each of the oxide semiconductor films (108_1 and 108_3) from functioning as part of the channel region, a material with sufficiently low conductivity is used for the oxide semiconductor films (108_1 and 108_3). Thus, the oxide semiconductor films (108_1 and 108_3) can be called oxide insulating films due to these properties and / or functions. For the oxide semiconductor films (108_1 and 108_3), a material is used in which the electron affinity (the difference between the vacuum level and the bottom of the conduction band) is smaller than that of the oxide semiconductor film (108_2), and there is a difference (band offset) between each of the oxide semiconductor films (108_1 and 108_3) and the bottom of the conduction band of the oxide semiconductor film (108_2). In addition, to suppress the occurrence of a difference in threshold voltage due to the value of the drain voltage, it is preferable to form oxide semiconductor films (108_1 and 108_3) using a material in which the bottom of the conduction band is closer to the vacuum level than the bottom of the conduction band of the oxide semiconductor film (108_2). For example, the difference between the bottom of the conduction band of the oxide semiconductor film (108_2) and the bottom of the conduction band of each of the oxide semiconductor films (108_1 and 108_3) is preferably 0.2 eV or more, more preferably 0.5 eV or more.

[0530] It is preferable that the oxide semiconductor films (108_1 and 108_3) do not have a spinel crystal structure. This is because if the oxide semiconductor films (108_1 and 108_3) have a spinel crystal structure, the constituent elements of the conductive films (120a and 120b) can diffuse into the oxide semiconductor film (108_2) at the interface between the spinel crystal structure and other regions. Additionally, it is preferable that each of the oxide semiconductor films (108_1 and 108_3) is a CAAC-OS film as described later, so that high blocking properties can be obtained for the constituent elements of the conductive films (120a and 120b), such as copper elements.

[0531] In the present embodiment, an example has been described in which an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In to Ga to Zn of 1:3:2 is used as each of the oxide semiconductor films (108_1 and 108_3), but the present invention is not limited thereto. For example, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In to Ga to Zn of 1:1:1, 1:1:1.2, 1:3:4, 1:3:6, 1:4:5, 1:5:6, or 1:10:1 may be used as each of the oxide semiconductor films (108_1 and 108_3). Alternatively, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of Ga to Zn of 10:1 may be used as the oxide semiconductor film (108_1 and 108_3). In this case, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In to Ga to Zn of 1:1:1 is used as the oxide semiconductor film (108_2), and an oxide semiconductor film formed using a metal oxide target having an atomic ratio of Ga to Zn of 10:1 is used as each of the oxide semiconductor films (108_1 and 108_3), so that the difference between the bottom of the conduction band of the oxide semiconductor film (108_2) and the bottom of the conduction band of the oxide semiconductor film (108_1 or 108_3) can be 0.6 eV or more, which is suitable.

[0532] When oxide semiconductor films (108_1 and 108_3) are formed using a metal oxide target in which the atomic ratio of In to Ga to Zn is 1:1:1, the atomic ratio of In to Ga to Zn in the oxide semiconductor films (108_1 and 108_3) can be 1:β1:β2 (0≤β1≤2, 0≤β2≤2). When oxide semiconductor films (108_1 and 108_3) are formed using a metal oxide target in which the atomic ratio of In to Ga to Zn is 1:3:4, the atomic ratio of In to Ga to Zn in the oxide semiconductor films (108_1 and 108_3) can be 1:β3:β4 (1≤β3≤5, 2≤β4≤6). When oxide semiconductor films (108_1 and 108_3) are formed using a metal oxide target in which the atomic ratio of In to Ga to Zn is 1:3:6, the atomic ratio of In to Ga to Zn in the oxide semiconductor films (108_1 and 108_3) can be 1:β5:β6 (1≤β5≤5, 4≤β6≤8).

[0533] <2-3. Example of Transistor Structure 4>

[0534] FIG. 45 (A) is a top view of a transistor (300A). FIG. 45 (B) is a cross-sectional view taken along the dotted line X1-X2 of FIG. 45 (A). FIG. 45 (C) is a cross-sectional view taken along the dotted line Y1-Y2 of FIG. 45 (A). Also, in FIG. 45 (A), some components of the transistor (300A) (e.g., an insulating film functioning as a gate insulating film) are not shown to avoid complexity. The dotted line X1-X2 direction can be called the channel length direction, and the dotted line Y1-Y2 direction can be called the channel width direction. As in FIG. 45 (A), some components may not be shown in the top view of the transistor described below.

[0535] The transistor (300A) illustrated in (A) to (C) of FIG. 45 comprises a conductive film (304) on a substrate (302), an insulating film (306) on the substrate (302) and the conductive film (304), an insulating film (307) on the insulating film (306), an oxide semiconductor film (308) on the insulating film (307), a conductive film (312a) on the oxide semiconductor film (308), and a conductive film (312b) on the oxide semiconductor film (308). On the transistor (300A), specifically on the conductive films (312a and 312b) and the oxide semiconductor film (308), an insulating film (314), an insulating film (316), and an insulating film (318) are provided.

[0536] In the transistor (300A), insulating films (306 and 307) function as gate insulating films of the transistor (300A), and insulating films (314, 316, and 318) function as protective insulating films of the transistor (300A). In addition, in the transistor (300A), a conductive film (304) functions as a gate electrode, a conductive film (312a) functions as a source electrode, and a conductive film (312b) functions as a drain electrode.

[0537] In the present specification, etc., insulating films (306 and 307) may be referred to as the first insulating film, insulating films (314 and 316) as the second insulating film, and insulating film (318) as the third insulating film.

[0538] The transistor (300A) illustrated in (A) to (C) of FIG. 45 is a channel-etched transistor. An oxide semiconductor film according to one embodiment of the present invention is suitable for a channel-etched transistor.

[0539] <2-4. Example of Transistor Structure 5>

[0540] FIG. 46 (A) is a top view of a transistor (300B). FIG. 46 (B) is a cross-sectional view taken along the dotted line X1-X2 of FIG. 46 (A). FIG. 46 (C) is a cross-sectional view taken along the dotted line Y1-Y2 of FIG. 46 (A).

[0541] The transistor (300B) illustrated in (A) to (C) of FIG. 46 comprises a conductive film (304) on a substrate (302), an insulating film (306) on the substrate (302) and the conductive film (304), an insulating film (307) on the insulating film (306), an oxide semiconductor film (308) on the insulating film (307), an insulating film (314) on the oxide semiconductor film (308), an insulating film (316) on the insulating film (314), a conductive film (312a) electrically connected to the oxide semiconductor film (308) through an opening (341a) provided in the insulating films (314 and 316), and a conductive film (312b) electrically connected to the oxide semiconductor film (308) through an opening (341b) provided in the insulating films (314 and 316). An insulating film (318) is provided on the transistor (300B), specifically on the conductive film (312a and 312b) and the insulating film (316).

[0542] In the transistor (300B), insulating films (306 and 307) function as gate insulating films of the transistor (300B), insulating films (314 and 316) each function as protective insulating films of the oxide semiconductor film (308), and insulating film (318) functions as protective insulating films of the transistor (300B). In addition, in the transistor (300B), conductive film (304) functions as a gate electrode, conductive film (312a) functions as a source electrode, and conductive film (312b) functions as a drain electrode.

[0543] While the transistor (300A) illustrated in FIG. 45 (A) to (C) has a channel etch structure, the transistor (300B) illustrated in FIG. 46 (A) to (C) has a channel protection structure. An oxide semiconductor film of one embodiment of the present invention is also suitable for a channel protection transistor.

[0544] <2-5. Example of Transistor Structure 6>

[0545] FIG. 47 (A) is a top view of a transistor (300C). FIG. 47 (B) is a cross-sectional view taken along the dotted line X1-X2 of FIG. 47 (A). FIG. 47 (C) is a cross-sectional view taken along the dotted line Y1-Y2 of FIG. 47 (A).

[0546] The transistor (300C) illustrated in (A) to (C) of FIG. 47 differs from the transistor (300B) of FIG. 46 (A) to (C) in that the shape of the insulating films (314 and 316) is different. Specifically, the insulating films (314 and 316) of the transistor (300C) have an island shape and are provided over the channel region of the oxide semiconductor film (308). Other components are the same as those of the transistor (300B).

[0547] <2-6. Example of Transistor Structure 7>

[0548] FIG. 48 (A) is a top view of a transistor (300D). FIG. 48 (B) is a cross-sectional view taken along the dotted line X1-X2 of FIG. 48 (A). FIG. 48 (C) is a cross-sectional view taken along the dotted line Y1-Y2 of FIG. 48 (A).

[0549] The transistor (300D) illustrated in (A) to (C) of FIG. 48 comprises a conductive film (304) on a substrate (302), an insulating film (306) on the substrate (302) and the conductive film (304), an insulating film (307) on the insulating film (306), an oxide semiconductor film (308) on the insulating film (307), a conductive film (312a) on the oxide semiconductor film (308), a conductive film (312b) on the oxide semiconductor film (308), an insulating film (314) on the oxide semiconductor film (308) and the conductive films (312a and 312b), an insulating film (316) on the insulating film (314), an insulating film (318) on the insulating film (316), and a conductive film (320a and 320b) on the insulating film (318).

[0550] In the transistor (300D), insulating films (306 and 307) function as the first gate insulating film of the transistor (300D), and insulating films (314, 316, and 318) function as the second gate insulating film of the transistor (300D). In addition, in the transistor (300D), a conductive film (304) functions as the first gate electrode, a conductive film (320a) functions as the second gate electrode, and a conductive film (320b) functions as a pixel electrode used in a display device. A conductive film (312a) functions as the source electrode, and a conductive film (312b) functions as the drain electrode.

[0551] As shown in (C) of FIG. 48, the conductive film (320a) is connected to the conductive film (304) at the openings (342b) and (342c) provided in the insulating films (306, 307, 314, 316, and 318). Thus, the same potential is applied to the conductive film (320a) and the conductive film (304).

[0552] The structure of the transistor (300D) is not limited to the above-described structure in which the conductive film (320a) is connected to the conductive film (304) by providing openings (342b and 342c). For example, a structure in which only one of the openings (342b and 342c) is provided to connect the conductive film (320a) to the conductive film (304), or a structure in which the openings (342b and 342c) are not provided and the conductive film (320a) is not connected to the conductive film (304) may be adopted. In addition, when the conductive film (320a) is not connected to the conductive film (304), different potentials can be applied to the conductive film (320a) and the conductive film (304).

[0553] The conductive film (320b) is connected to the conductive film (312b) through an opening (342a) provided in the insulating films (314, 316, and 318).

[0554] In addition, the transistor (300D) has the S-channel structure described above.

[0555] <2-7. Example of Transistor Structure 8>

[0556] The oxide semiconductor film (308) included in the transistor (300A) of FIG. 45 (A) to (C) may have a stacked structure. FIG. 49 (A) and (B) and FIG. 50 (A) and (B) illustrate examples of such cases.

[0557] (A) and (B) of FIG. 49 are cross-sectional views of a transistor (300E), and (A) and (B) of FIG. 50 are cross-sectional views of a transistor (300F). The top view of the transistors (300E and 300F) is the same as the top view of the transistor (300A) shown in FIG. 45 (A).

[0558] The oxide semiconductor film (308) of the transistor (300E) shown in (A) and (B) of FIG. 49 includes an oxide semiconductor film (308_1), an oxide semiconductor film (308_2), and an oxide semiconductor film (308_3). The oxide semiconductor film (308) of the transistor (300F) shown in (A) and (B) of FIG. 50 includes an oxide semiconductor film (308_2) and an oxide semiconductor film (308_3).

[0559] In addition, the conductive film (304), insulating film (306), insulating film (307), oxide semiconductor film (308), oxide semiconductor film (308_1), oxide semiconductor film (308_2), oxide semiconductor film (308_3), conductive film (312a and 312b), insulating film (314), insulating film (316), insulating film (318), and conductive film (320a and 320b) can each be formed using the materials of the conductive film (106), insulating film (116), oxide semiconductor film (108), oxide semiconductor film (108_1), oxide semiconductor film (108_2), oxide semiconductor film (108_3), conductive film (120a and 120b), insulating film (104), insulating film (118), insulating film (116), and conductive film (112) described above.

[0560] <2-8. Example of Transistor Structure 9>

[0561] FIG. 51 (A) is a top view of a transistor (300G). FIG. 51 (B) is a cross-sectional view taken along the dotted line X1-X2 of FIG. 51 (A). FIG. 51 (C) is a cross-sectional view taken along the dotted line Y1-Y2 of FIG. 51 (A).

[0562] The transistor (300G) illustrated in (A) to (C) of FIG. 51 comprises a conductive film (304) on a substrate (302), an insulating film (306) on the substrate (302) and the conductive film (304), an insulating film (307) on the insulating film (306), an oxide semiconductor film (308) on the insulating film (307), a conductive film (312a) on the oxide semiconductor film (308), a conductive film (312b) on the oxide semiconductor film (308), an insulating film (314) on the oxide semiconductor film (308) and the conductive films (312a and 312b), an insulating film (316) on the insulating film (314), a conductive film (320a) on the insulating film (316), and a conductive film (320b) on the insulating film (316).

[0563] The insulating films (306 and 307) have an opening (351). A conductive film (312c) that is electrically connected to the conductive film (304) through the opening (351) is formed on the insulating films (306 and 307). The insulating films (314 and 316) have an opening (352a) reaching the conductive film (312b) and an opening (352b) reaching the conductive film (312c).

[0564] The oxide semiconductor film (308) includes an oxide semiconductor film (308_2) on the side of the conductive film (304), and an oxide semiconductor film (308_3) on the oxide semiconductor film (308_2).

[0565] An insulating film (318) is provided over the transistor (300G). The insulating film (318) is formed to cover the insulating film (316), the conductive film (320a), and the conductive film (320b).

[0566] In the transistor (300G), insulating films (306 and 307) function as the first gate insulating film of the transistor (300G), insulating films (314 and 316) function as the second gate insulating film of the transistor (300G), and insulating film (318) functions as the protective insulating film of the transistor (300G). In addition, in the transistor (300G), the conductive film (304) functions as the first gate electrode, the conductive film (320a) functions as the second gate electrode, and the conductive film (320b) functions as the pixel electrode used in the display device. In addition, in the transistor (300G), the conductive film (312a) functions as the source electrode, the conductive film (312b) functions as the drain electrode, and the conductive film (312c) functions as the connection electrode.

[0567] In addition, the transistor (300G) has the S-channel structure described above.

[0568] The structures of the transistors (300A to 300G) can be freely combined with each other.

[0569] At least a part of this embodiment may be implemented in appropriate combination with any of the other embodiments described in this specification.

[0570] (Embodiment 3)

[0571] In this embodiment, an example of a display device including a semiconductor device described in the above embodiment will be explained below with reference to FIGS. 52 to 59.

[0572] FIG. 52 is a top view illustrating an example of a display device. The display device (700) of FIG. 52 includes a pixel portion (702) provided on a first substrate (701), a source driving circuit portion (704) and a gate driving circuit portion (706) provided on the first substrate (701), a sealant (712) provided to surround the pixel portion (702), the source driving circuit portion (704), and the gate driving circuit portion (706), and a second substrate (705) provided to face the first substrate (701). The first substrate (701) and the second substrate (705) are sealed with the sealant (712). That is, the pixel portion (702), the source driving circuit portion (704), and the gate driving circuit portion (706) are surrounded by the first substrate (701), the sealant (712), and the second substrate (705). Although not shown in FIG. 52, a display element is provided between the first substrate (701) and the second substrate (705).

[0573] In the display device (700), a flexible printed circuit (FPC) terminal (708) is provided in an area different from the area on the first substrate (701) and surrounded by a sealant (712), and is electrically connected to a pixel section (702), a source driving circuit section (704), and a gate driving circuit section (706). Additionally, an FPC (716) is connected to the FPC terminal (708), and various signals are supplied from the FPC (716) to the pixel section (702), the source driving circuit section (704), and the gate driving circuit section (706). Additionally, a signal line (710) is connected to the pixel section (702), the source driving circuit section (704), the gate driving circuit section (706), and the FPC terminal (708). Various signals are supplied from the FPC (716) to the pixel section (702), source driving circuit section (704), gate driving circuit section (706), and FPC terminal section (708) through the signal line (710).

[0574] A plurality of gate driving circuit sections (706) may be provided in the display device (700). The structure of the display device (700) is not limited to the example shown herein where the source driving circuit section (704) and the gate driving circuit section (706) are formed together with the pixel section (702) on the first substrate (701). For example, only the gate driving circuit section (706) may be formed on the first substrate (701), or only the source driving circuit section (704) may be formed on the first substrate (701). In this case, a substrate on which the source driving circuit or the gate driving circuit, etc. are formed (for example, a driving circuit substrate formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate (701). In addition, there are no special restrictions on the method of connecting the separately prepared driving circuit substrate, and the COG (chip on glass) method or wire bonding method may be used.

[0575] The pixel portion (702), source driving circuit portion (704), and gate driving circuit portion (706) included in the display device (700) include a plurality of transistors.

[0576] The display device (700) may include various elements. Examples of these elements include an electroluminescence (EL) element (e.g., an EL element including organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED), a light-emitting transistor element (a transistor that emits light according to current), an electron emitter, a liquid crystal element, an electronic ink display, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a micro electro mechanical systems (MEMS) display (e.g., a GLV (grating light valve), a DMD (digital micromirror device), a DMS (digital micro shutter) element, or an IMOD (interferometric modulator display) element), and a piezoelectric ceramic display.

[0577] An example of a display device including an EL element is an EL display. Examples of display devices including an electron emitter include field emission displays (FEDs) and surface-conduction electron-emitter displays (SEDs). Examples of display devices including a liquid crystal element include liquid crystal displays (transmissive liquid crystal displays, transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, or projection liquid crystal displays). An example of a display device including an electronic ink display or an electrophoretic element is electronic paper. In a transmissive liquid crystal display or a reflective liquid crystal display, some or all of the pixel electrodes may function as reflective electrodes. For example, some or all of the pixel electrodes may include aluminum or silver, etc. In this case, a memory circuit such as SRAM can be provided under the reflective electrodes, thereby reducing power consumption.

[0578] As a display system of the display device (700), a progressive system or an interlaced system, etc., may be adopted. In addition, the color elements controlled at the pixel during color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, four pixels, such as an R pixel, a G pixel, a B pixel, and a W (white) pixel, may be used. Alternatively, the color elements may be composed of two colors among R, G, and B, such as in a PenTile layout. The two colors may differ depending on the color elements. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. In addition, the size of the display area may differ between the dots of the color elements. One embodiment of the disclosed invention is not limited to a color display device and may be applied to a monochrome display device.

[0579] To obtain a full-color display device using white light (W) in a backlight (e.g., organic EL element, inorganic EL element, LED, or fluorescent lamp), a coloring layer (also called a color filter) may be used. For example, a red (R) coloring layer, a green (G) coloring layer, a blue (B) coloring layer, and a yellow (Y) coloring layer may be appropriately combined. When a coloring layer is used, high color reproduction can be obtained compared to the case where no coloring layer is used. Here, by providing an area with a coloring layer and an area without a coloring layer, the white light in the area without a coloring layer may be used directly for display. By partially providing an area without a coloring layer, the reduction in brightness of bright images caused by the coloring layer can be suppressed, and power consumption may be reduced by about 20% to 30%. When full-color display is performed using a self-emissive element such as an organic EL element or an inorganic EL element, the elements may emit light of R, G, B, Y, and W, respectively. By using a self-emissive element, power consumption may be further reduced compared to the case where a coloring layer is used.

[0580] As a coloring system, any of the following may be used: the coloring system described above that converts a portion of white light into red light, green light, and blue light through a color filter; a tricolor system using red light, green light, and blue light; and a color conversion system or quantum dot system that converts a portion of blue light into red light or green light.

[0581] In this embodiment, a structure including a liquid crystal element as a display element and a structure including an EL element as a display element will be described with reference to FIGS. 53 to 55. FIGS. 53 and FIGS. 54 are cross-sectional views taken along the dotted line QR of FIG. 52 and illustrate a structure including a liquid crystal element as a display element. FIG. 55 is a cross-sectional view taken along the dotted line QR of FIG. 52 and illustrates a structure including an EL element as a display element.

[0582] First, the common parts in FIGS. 53 to 55 will be explained, and then the different parts will be explained.

[0583] <3-1. Common parts of display devices>

[0584] The display device (700) of FIGS. 53 to 55 includes a lead wiring section (711), a pixel section (702), a source driving circuit section (704), and an FPC terminal section (708). The lead wiring section (711) includes a signal line (710). The pixel section (702) includes a transistor (750) and a capacitance element (790). The source driving circuit section (704) includes a transistor (752).

[0585] Each of the transistors (750) and (752) has a structure similar to the transistor (100A) described above. Additionally, each of the transistor (750) and (752) may have the structure of any of the other transistors described in the above-described embodiment.

[0586] The transistor used in this embodiment includes an oxide semiconductor film that is purified and in which the formation of oxygen vacancies is suppressed. This transistor can have a low off-state current. Therefore, electrical signals such as image signals can be maintained for a long time, and the recording interval in the on state can be set to a long length. Consequently, the frequency of refresh operations can be reduced, thereby suppressing power consumption.

[0587] Furthermore, since the transistor used in this embodiment can have a relatively high field-effect mobility, high-speed operation is possible. For example, in a liquid crystal display device including such a transistor capable of high-speed operation, the switching transistor of the pixel section and the driving transistor of the driving circuit section can be formed on a single substrate. That is, since an additional semiconductor device formed using a silicon wafer or the like as a driving circuit is not required, the number of semiconductor device components can be reduced. In addition, by using a transistor capable of high-speed operation in the pixel section, high-quality images can be provided.

[0588] The capacitance element (790) includes a lower electrode and an upper electrode. The lower electrode is formed by processing a conductive film that functions as the first gate electrode of the transistor (750). The upper electrode is formed by processing a conductive film that functions as the source electrode and drain electrode, or as the second gate electrode of the transistor (750). Between the lower electrode and the upper electrode, an insulating film is provided that is formed by processing a insulating film that functions as the first gate insulating film of the transistor (750), and an insulating film that functions as the protective insulating film on the transistor (750). That is, the capacitance element (790) has a stacked structure in which an insulating film that functions as a dielectric film is located between a pair of electrodes.

[0589] In FIGS. 53 to 55, a flattened insulating film (770) is provided over the transistor (750), transistor (752), and capacitive element (790).

[0590] Each of FIGS. 53 to 55 illustrates an example in which a transistor (750) included in the pixel section (702) and a transistor (752) included in the source driving circuit section (704) have the same structure, but the present invention is not limited thereto. For example, the pixel section (702) and the source driving circuit section (704) may include different transistors. Specifically, a structure in which a top gate transistor is used in the pixel section (702) and a bottom gate transistor is used in the source driving circuit section (704), or a structure in which a bottom gate transistor is used in the pixel section (702) and a top gate transistor is used in the source driving circuit section (704), may be adopted. Additionally, the term "source driving circuit section (704)" may be replaced with the term "gate driving circuit section."

[0591] The signal line (710) is formed through the same process as the conductive film that functions as the source electrode and drain electrode of the transistor (750 and 752). When the signal line (710) is formed using a material containing copper elements, signal delay caused by wiring resistance is reduced, making it possible to display a large screen.

[0592] The FPC terminal section (708) includes a connection electrode (760), an anisotropic conductive film (780), and an FPC (716). Additionally, the connection electrode (760) is formed through the same process as the conductive film that functions as the source electrode and drain electrode of the transistors (750 and 752). The connection electrode (760) is electrically connected to a terminal included in the FPC (716) through the anisotropic conductive film (780).

[0593] For example, a glass substrate may be used as the first substrate (701) and the second substrate (705). A flexible substrate may also be used as the first substrate (701) and the second substrate (705). An example of a flexible substrate is a plastic substrate.

[0594] A structure (778) is provided between the first substrate (701) and the second substrate (705). The structure (778) is a pillar-shaped spacer obtained by selective etching of an insulating film and is provided to control the distance (cell gap) between the first substrate (701) and the second substrate (705). Alternatively, a spherical spacer may be used as the structure (778).

[0595] On the side of the second substrate (705), a light-blocking film (738) that functions as a black matrix, a coloring film (736) that functions as a color filter, and an insulating film (734) that contacts the light-blocking film (738) and the coloring film (736) are provided.

[0596] <3-2. Example of a structure of a display device including a liquid crystal element>

[0597] The display device (700) of FIG. 53 includes a liquid crystal element (775). The liquid crystal element (775) includes a conductive film (772), a conductive film (774), and a liquid crystal layer (776). The conductive film (774) is provided on the side of the second substrate (705) and functions as a counter electrode. The display device (700) of FIG. 53 can display an image by controlling the transmission or non-transmission of light by the orientation state of the liquid crystal layer (776), which changes according to the voltage applied between the conductive film (772) and the conductive film (774).

[0598] The conductive film (772) is electrically connected to a conductive film that functions as a source electrode or drain electrode of a transistor (750). The conductive film (772) is formed on a planarizing insulating film (770) and functions as a pixel electrode, that is, one electrode of a display element.

[0599] A conductive film that transmits visible light or a conductive film that reflects visible light can be used as the conductive film (772). For example, a material containing an element selected from indium (In), zinc (Zn), and tin (Sn) is suitable for use as a conductive film that transmits visible light. For example, a material containing aluminum or silver is suitable for use as a conductive film that reflects visible light.

[0600] When a conductive film that reflects visible light is used as the conductive film (772), the display device (700) is a reflective liquid crystal display device. When a conductive film that transmits visible light is used as the conductive film (772), the display device (700) is a transmissive liquid crystal display device.

[0601] By changing the structure on the conductive film (772), the driving method of the liquid crystal element can be changed, and an example of this case is illustrated in FIG. 54. The display device (700) illustrated in FIG. 54 is an example that adopts a horizontal electric field mode (e.g., FFS mode) as the driving mode of the liquid crystal element. In the structure illustrated in FIG. 54, an insulating film (773) is provided on the conductive film (772), and a conductive film (774) is provided on the insulating film (773). In this structure, the conductive film (774) functions as a common electrode, and the electric field generated between the conductive film (772) and the conductive film (774) through the insulating film (773) can control the orientation state of the liquid crystal layer (776).

[0602] Although not illustrated in FIGS. 53 and 54, an alignment layer may be provided on the side of the conductive film (772) and / or conductive film (774) that contacts the liquid crystal layer (776). Although not illustrated in FIGS. 53 and 54, an optical member (optical substrate), such as a polarizing member, a phase difference member, or an anti-reflection member, may be appropriately provided. For example, circularly polarized light may be obtained by using a polarizing substrate and a phase difference substrate. Additionally, a backlight or a side light may be used as a light source.

[0603] When using a liquid crystal element as a display device, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, or anti-ferroelectric liquid crystals may be used. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, smectic phase, cubic phase, chiral nematic phase, or isotropic phase.

[0604] When employing a horizontal electric field mode, liquid crystals exhibiting a blue phase that do not require an alignment layer may be used. The blue phase is one of the liquid crystal phases that occurs just before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal rises. Since the blue phase appears only within a narrow temperature range, a liquid crystal composition containing a chiral agent in a weight percent or greater is used in the liquid crystal layer to extend the temperature range. Liquid crystals exhibiting a blue phase and liquid crystal compositions containing chiral agents have a short response speed and possess optical isotropy, thereby eliminating the need for alignment treatment. Since there is no need to provide an alignment layer, rubbing treatment is unnecessary; thus, electrostatic discharge damage caused by rubbing treatment can be prevented, and defects and damage to the liquid crystal display device during the manufacturing process can be reduced. Furthermore, liquid crystal materials exhibiting a blue phase have low dependence on the viewing angle.

[0605] When using a liquid crystal element as a display element, TN (twisted nematic) mode, IPS (in-plane switching) mode, FFS (fringe field switching) mode, ASM (axially symmetric aligned micro-cell) mode, OCB (optical compensated birefringence) mode, FLC (ferroelectric liquid crystal) mode, or AFLC (anti-ferroelectric liquid crystal) mode can be used.

[0606] In addition, a normal black liquid crystal display, such as a transmissive liquid crystal display in a vertical alignment (VA) mode, may be used. There are several examples of vertical alignment modes, and for instance, multi-domain vertical alignment (MVA) mode, patterned vertical alignment (PVA) mode, or ASV mode may be adopted.

[0607] <3-3. Display device including light-emitting element>

[0608] The display device (700) illustrated in FIG. 55 includes a light-emitting element (782). The light-emitting element (782) includes a conductive film (772), an EL layer (786), and a conductive film (788). The display device (700) illustrated in FIG. 55 can display an image by utilizing light emission from the EL layer (786) of the light-emitting element (782). Additionally, the EL layer (786) includes an organic compound or an inorganic compound such as a quantum dot.

[0609] Examples of materials that can be used for organic compounds include fluorescent materials and phosphorescent materials. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, and core-type quantum dot materials. Materials containing elements belonging to Group 12 and Group 16, elements belonging to Group 13 and Group 15, or elements belonging to Group 14 and Group 16 may be used. Alternatively, materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used.

[0610] The organic and inorganic compounds described above can be deposited by methods such as deposition (including vacuum deposition), droplet discharge (also called inkjet method), coating, or gravure printing. Low molecular weight materials, medium molecular weight materials (including oligomers and dendrimers), or high molecular weight materials may be included in the EL layer (786).

[0611] Here, a method for forming an EL layer (786) by a droplet discharge method is explained with reference to FIGS. 58 (A) to (D). FIGS. 58 (A) to (D) is a cross-sectional view illustrating a method for forming an EL layer (786).

[0612] First, a conductive film (772) is formed on a flattened insulating film (770), and an insulating film (730) is formed to cover a portion of the conductive film (772) (see (A) in FIG. 58).

[0613] Afterward, a droplet (784) is discharged from a droplet discharge device (783) into an exposed portion of the conductive film (772), which is an opening of the insulating film (730), to form a layer (785) containing a composition. The droplet (784) is a composition containing a solvent and is attached to the conductive film (772) (see (B) of FIG. 58).

[0614] In addition, the discharge step of the droplet (784) may be carried out under reduced pressure.

[0615] Next, the solvent is removed from the layer (785) containing the composition, and the layer is solidified to form an EL layer (786) (see (C) in FIG. 58).

[0616] The solvent may be removed by drying or heating.

[0617] Next, a light-emitting element (782) is formed by forming a conductive film (788) on the EL layer (786) (see (D) in FIG. 58).

[0618] As described above, when the EL layer (786) is formed by the droplet discharge method, the composition can be selectively discharged, thereby reducing material waste. In addition, since a lithography process for molding is unnecessary, the process can be simplified and a low cost can be realized.

[0619] The above-described droplet discharge method is a general term for droplet discharge means, such as means including a nozzle having a discharge port for a composition, or a head having one or more nozzles.

[0620] Next, a droplet dispensing device used in the droplet dispensing method will be described with reference to FIG. 59. FIG. 59 is a conceptual diagram illustrating a droplet dispensing device (1400).

[0621] The droplet discharge device (1400) includes a droplet discharge means (1403). Additionally, the droplet discharge means (1403) has a head (1405) and a head (1412).

[0622] The head (1405) and the head (1412) are connected to a control means (1407), and since the control means (1407) is controlled by a computer (1410), it can draw a programmed pattern.

[0623] Drawing may be performed at a timing based, for example, on a marker (1411) formed on a substrate (1402). Alternatively, a reference point may be determined based on the outer edge of the substrate (1402). Here, the marker (1411) is detected by an imaging means (1404) and converted into a digital signal by an image processing means (1409). Then, after the digital signal is recognized by a computer (1410), a control signal is generated and transmitted to a control means (1407).

[0624] As the imaging means (1404), an image sensor using a charge coupling device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used. Additionally, information regarding the pattern to be formed on the substrate (1402) is stored in a storage medium (1408), and based on this information, a control signal is transmitted to a control means (1407), so that each head (1405 and 1412) of the droplet discharge means (1403) can be controlled individually. The material to be discharged is supplied to the heads (1405 and 1412) respectively through piping from the material supply source (1413 and 1414).

[0625] The interior of the head (1405) is provided with a space filled with liquid material, as indicated by the dotted line (1406), and a nozzle serving as an outlet. Although not shown, the internal structure of the head (1412) is the same as the internal structure of the head (1405). If the nozzles of the heads (1405 and 1412) are different in size from each other, different materials can be ejected simultaneously with different widths. Multiple light-emitting materials can be ejected and drawn with each head. When drawing over a large area, the same material can be ejected and drawn simultaneously from multiple nozzles to improve throughput. When using a large substrate, the heads (1405 and 1412) can freely scan the substrate in the direction indicated by the arrows (X, Y, and Z) in FIG. 59 and can freely set the area for drawing patterns. In this way, multiple identical patterns can be drawn on a single substrate.

[0626] In addition, the step of extruding the composition may be performed under reduced pressure. The substrate may be heated when extruding the composition. After extruding the composition, one or both of drying and baking are performed. Although both drying and baking are heat treatments, they differ in purpose, temperature, and duration. The drying and baking steps are performed under atmospheric pressure or reduced pressure by laser irradiation, RTA (rapid thermal annealing), or heating using a furnace. Furthermore, there are no specific restrictions on the timing or frequency of the heat treatments. The temperature required to perform each of the drying and baking steps effectively depends on the material of the substrate and the properties of the composition.

[0627] The EL layer (786) can be formed using a droplet discharge device by the method described above.

[0628] The display device (700) shown in FIG. 55 will be explained again.

[0629] In the display device (700) of FIG. 55, an insulating film (730) is provided over a flattened insulating film (770) and a conductive film (772). The insulating film (730) covers a portion of the conductive film (772). Additionally, the light-emitting element (782) has a top emission structure. Thus, the conductive film (788) is transparent and transmits light emitted from the EL layer (786). Although a top emission structure has been illustrated in this embodiment, the structure is not limited thereto. For example, a bottom emission structure in which light is emitted toward the conductive film (772), or a dual emission structure in which light is emitted toward both the conductive film (772) side and the conductive film (788) side may be adopted.

[0630] A coloring film (736) is provided to overlap with a light-emitting element (782), and a light-blocking film (738) is provided in the lead wiring section (711) and the source driving circuit section (704) to overlap with an insulating film (730). The coloring film (736) and the light-blocking film (738) are covered with an insulating film (734). The space between the light-emitting element (782) and the insulating film (734) is filled with a sealing film (732). The structure of the display device (700) is not limited to the example of FIG. 55 in which the coloring film (736) is provided. For example, if the EL layer (786) is formed by separate coloring, a structure without the coloring film (736) may be adopted.

[0631] <3-4. Example of a display device structure with input / output devices>

[0632] The display device (700) illustrated in FIGS. 54 and 55 may be provided with an input / output device. Examples of input / output devices include a touch panel.

[0633] FIG. 56 illustrates a structure in which the display device (700) shown in FIG. 54 includes a touch panel (791). FIG. 57 illustrates a structure in which the display device (700) shown in FIG. 55 includes a touch panel (791).

[0634] FIG. 56 is a cross-sectional view of a structure in which a touch panel (791) is provided on a display device (700) shown in FIG. 54, and FIG. 57 is a cross-sectional view of a structure in which a touch panel (791) is provided on a display device (700) shown in FIG. 55.

[0635] First, the touch panel (791) shown in FIGS. 56 and 57 will be described below.

[0636] The touch panel (791) illustrated in FIGS. 56 and 57 is a so-called in-cell touch panel provided between the substrate (705) and the coloring film (736). The touch panel (791) is formed on the substrate (705) side before forming the coloring film (736).

[0637] Additionally, the touch panel (791) includes a light-blocking film (738), an insulating film (792), an electrode (793), an electrode (794), an insulating film (795), an electrode (796), and an insulating film (797). For example, when an object such as a finger or a stylus is brought near, a change in the mutual capacitance between the electrode (793) and the electrode (794) can be detected.

[0638] The portion where the electrode (793) intersects the electrode (794) is shown on the upper part of the transistor (750) illustrated in FIGS. 56 and 57. The electrode (796) is electrically connected to two electrodes (793) that insert the electrode (794) through an opening provided in the insulating film (795). Additionally, FIGS. 56 and 57 illustrate a structure in which an area where the electrode (796) is provided is provided to the pixel portion (702) as an example, but one embodiment of the present invention is not limited thereto. For example, an area where the electrode (796) is provided may be provided to the source driving circuit portion (704).

[0639] The electrode (793) and the electrode (794) are provided in an area that overlaps with the light-blocking film (738). As shown in FIG. 56, it is preferable that the electrode (793) does not overlap with the light-emitting element (782). As shown in FIG. 57, it is preferable that the electrode (793) does not overlap with the liquid crystal element (775). In other words, the electrode (793) has an opening in an area that overlaps with the light-emitting element (782) and the liquid crystal element (775). That is, the electrode (793) has a mesh shape. By having this structure, the electrode (793) does not block light emitted from the light-emitting element (782), nor does the electrode (793) block light passing through the liquid crystal element (775). Therefore, even if a touch panel (791) is provided, it is difficult to reduce the brightness, so a display device with high visibility and low power consumption can be obtained. In addition, the electrode (794) may have a structure similar to that of the electrode (793).

[0640] Since the electrode (793) and the electrode (794) do not overlap with the light-emitting element (782), a metal material with low transmittance to visible light can be used for the electrode (793) and the electrode (794). Additionally, since the electrode (793) and the electrode (794) do not overlap with the liquid crystal element (775), a metal material with low transmittance to visible light can be used for the electrode (793) and the electrode (794).

[0641] Therefore, compared to using an oxide material with high transmittance of visible light, the resistance of the electrodes (793 and 794) can be reduced, so the sensor sensitivity of the touch panel can be increased.

[0642] For example, conductive nanowires may be used for the electrodes (793, 794, and 796). These nanowires may have an average diameter of 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. As nanowires, metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires, or carbon nanotubes may be used. For example, when Ag nanowires are used for any one or all of the electrodes (793, 794, and 796), the transmittance of visible light can be 89% or more, and the sheet resistance can be 40 Ω / sq. or more and 100 Ω / sq. or less.

[0643] Although the structure of an in-cell touch panel is illustrated in FIGS. 56 and 57, one embodiment of the present invention is not limited thereto. For example, a touch panel formed on a display device (700), so-called on-cell touch panel, or a touch panel attached to the display device (700), so-called out-cell touch panel may be used.

[0644] In this way, a display device of one form of the present invention can be combined with various types of touch panels.

[0645] At least a part of this embodiment may be implemented in appropriate combination with any of the other embodiments described in this specification.

[0646] (Embodiment 4)

[0647] In this embodiment, a display device including a semiconductor device of one form of the present invention will be described with reference to (A) to (C) of FIG. 60.

[0648] <4. Circuit Configuration of the Display Device>

[0649] The display device illustrated in (A) of FIG. 60 includes a region containing a pixel of a display element (hereinafter referred to as a pixel portion (502)), a circuit portion provided outside the pixel portion (502) and including a circuit for driving the pixel (hereinafter referred to as a driving circuit portion (504)), a circuit having a function to protect the element (hereinafter referred to as a protection circuit (506)), and a terminal portion (507). Additionally, it is not necessary to provide a protection circuit (506).

[0650] It is preferable that part or all of the driving circuit (504) be formed on the substrate on which the pixel portion (502) is formed. This allows for a reduction in the number of components and terminals. If part or all of the driving circuit (504) is not formed on the substrate on which the pixel portion (502) is formed, part or all of the driving circuit (504) can be mounted by COG or TAB (tape automated bonding).

[0651] The pixel section (502) X ( X is a natural number greater than or equal to 2) row and Y ( YIt includes a plurality of circuits for driving display elements arranged in a row (hereafter referred to as pixel circuits (501)), wherein the driving circuit section (504) includes driving circuits such as a circuit for supplying a signal for selecting a pixel (scan signal) (hereafter referred to as gate driver (504a)) and a circuit for supplying a signal for driving a display element of a pixel (data signal) (hereafter referred to as source driver (504b)).

[0652] The gate driver (504a) includes a shift register, etc. The gate driver (504a) receives a signal to drive the shift register through the terminal portion (507) and outputs a signal. For example, the gate driver (504a) receives a start pulse signal or a clock signal, etc. and outputs a pulse signal. The gate driver (504a) is a wiring to which a scan signal is supplied (hereinafter scan lines (GL_1 to GL_ X It has the function of controlling the potential of the (referred to as ). In addition, it provides a plurality of gate drivers (504a) to scan lines (GL_1 to GL_ X ) may be controlled individually. Alternatively, the gate driver (504a) has the function of supplying an initialization signal. It is not limited to this, and other signals may be supplied from the gate driver (504a).

[0653] The source driver (504b) includes a shift register, etc. The source driver (504b) receives not only a signal for driving the shift register through the terminal portion (507), but also a signal (image signal) for generating a data signal. The source driver (504b) has the function of generating a data signal to be recorded in the pixel circuit (501) from the image signal. In addition, the source driver (504b) has the function of controlling the output of the data signal according to a pulse signal generated by an input such as a start pulse signal or a clock signal. In addition, the source driver (504b) has a wiring through which the data signal is supplied (hereinafter data lines (DL_1 to DL_ Y It has the function of controlling the potential of (referred to as ). Or the source driver (504b) has the function of supplying an initialization signal. It is not limited to this, and other signals may be supplied from the source driver (504b).

[0654] The source driver (504b) includes, for example, a plurality of analog switches. The source driver (504b) can output a time-division image signal obtained by sequentially turning on the plurality of analog switches as a data signal. The source driver (504b) may include a shift register, etc.

[0655] A pulse signal and a data signal are input to each of the plurality of pixel circuits (501) through one of the plurality of scan lines (GL) to which a scan signal is supplied and one of the plurality of data lines (DL) to which a data signal is supplied. The recording and maintenance of the data signal in each of the plurality of pixel circuits (501) is controlled by a gate driver (504a). For example m line n tenth ( m silver X It is a natural number less than or equal to, and n silver Y In the pixel circuit (501) of the natural number below), there is a scan line (GL_ mA pulse signal is input from the gate driver (504a) through ), and the scan line (GL_ m Depending on the potential of ), the data line (DL_ n A data signal is input from the source driver (504b) through ).

[0656] The protection circuit (506) of (A) in FIG. 60 is, for example, connected to a scan line (GL) between a gate driver (504a) and a pixel circuit (501). Alternatively, the protection circuit (506) is connected to a data line (DL) between a source driver (504b) and a pixel circuit (501). Alternatively, the protection circuit (506) may be connected to wiring between a gate driver (504a) and a terminal section (507). Alternatively, the protection circuit (506) may be connected to wiring between a source driver (504b) and a terminal section (507). Also, the terminal section (507) refers to a part having terminals for inputting power, control signals, and image signals from an external circuit to a display device.

[0657] The protection circuit (506) electrically connects the wiring connected to the protection circuit to another wiring when a potential outside a specific range is supplied to the wiring connected to the protection circuit.

[0658] As illustrated in FIG. 60 (A), the protection circuit (506) provided to the pixel portion (502) and the driving circuit portion (504) can improve the resistance of the display device to overcurrent caused by ESD (electrostatic discharge), etc. In addition, the configuration of the protection circuit (506) is not limited thereto, and for example, the protection circuit (506) may be connected to a gate driver (504a) or a source driver (504b). Alternatively, the protection circuit (506) may be connected to a terminal portion (507).

[0659] One embodiment of the present invention is not limited to the example of (A) in FIG. 60, in which the driving circuit portion (504) includes a gate driver (504a) and a source driver (504b). For example, only the gate driver (504a) may be formed, or a substrate having a separately prepared source driving circuit formed thereon (for example, a driving circuit substrate formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

[0660] Each of the plurality of pixel circuits (501) of (A) of FIG. 60 may have a configuration as shown in (B) of FIG. 60, for example.

[0661] The pixel circuit (501) of (B) in FIG. 60 includes a liquid crystal element (570), a transistor (550), and a capacitance element (560). As the transistor (550), the transistor described in the above embodiment may be used.

[0662] According to the specifications of the pixel circuit (501), the potential of one of the pair of electrodes of the liquid crystal element (570) is appropriately set. The orientation state of the liquid crystal element (570) depends on the recorded data. A common potential may be supplied to one of the pair of electrodes of the liquid crystal element (570) included in each of the plurality of pixel circuits (501). The potential supplied to one of the pair of electrodes of the liquid crystal element (570) of the pixel circuit (501) may be different for each row.

[0663] Examples of driving methods for a display device including a liquid crystal element (570) include TN mode, STN mode, VA mode, ASM (axially symmetric aligned micro-cell) mode, OCB (optically compensated birefringence) mode, FLC (ferroelectric liquid crystal) mode, AFLC (anti-ferroelectric liquid crystal) mode, MVA mode, PVA (patterned vertical alignment) mode, IPS mode, FFS mode, and TBA (transverse bend alignment) mode. Other examples of driving methods for a display device include ECB (electrically controlled birefringence) mode, PDLC (polymer-dispersed liquid crystal) mode, PNLC (polymer network liquid crystal) mode, and guest-host mode. Various liquid crystal elements and driving methods may be used, not limited thereto.

[0664] m line n In the tenth pixel circuit (501), one of the source electrode and drain electrode of the transistor (550) is a data line (DL_ n It is electrically connected to ), and the other side of the source electrode and drain electrode of the transistor (550) is electrically connected to the other side of the pair of electrodes of the liquid crystal element (570). The gate electrode of the transistor (550) is a scan line (GL_ m It is electrically connected to ). The transistor (550) controls whether a data signal is recorded by turning it on or off.

[0665] One of the pair of electrodes of the capacitance element (560) is electrically connected to a wire to which potential is supplied (hereinafter referred to as the potential supply line (VL)), and the other of the pair of electrodes of the capacitance element (560) is electrically connected to the other of the pair of electrodes of the liquid crystal element (570). The potential of the potential supply line (VL) is appropriately set according to the specifications of the pixel circuit (501). The capacitance element (560) functions as a storage capacitor for storing recorded data.

[0666] For example, in a display device including a pixel circuit (501) of (B) of FIG. 60, the gate driver (504a) of (A) of FIG. 60 sequentially selects the pixel circuit (501) row by row to turn on the transistor (550) and records a data signal.

[0667] When the transistor (550) is turned off, the pixel circuit (501) on which data is recorded remains in a maintained state. By performing this operation sequentially for each row, an image can be displayed.

[0668] Alternatively, each of the plurality of pixel circuits (501) of (A) of FIG. 60 may have a configuration as illustrated in (C) of FIG. 60, for example.

[0669] The pixel circuit (501) of (C) in FIG. 60 includes transistors (552 and 554), a capacitive element (562), and a light-emitting element (572). As transistors (552) and / or transistors (554), transistors described in the above-described embodiment may be used.

[0670] One of the source electrode and drain electrode of the transistor (552) is a wire to which a data signal is supplied (later a data line (DL_ n The gate electrode of the transistor (552) is electrically connected to the wiring (hereinafter referred to as the scan line (GL_)) to which the gate signal is supplied. m It is electrically connected to (called).

[0671] The transistor (552) controls whether the data signal is recorded by turning it on or off.

[0672] One of the pair of electrodes of the capacitance element (562) is electrically connected to a wire to which potential is supplied (hereinafter referred to as the potential supply line (VL_a)), and the other of the pair of electrodes of the capacitance element (562) is electrically connected to the other of the source electrode and drain electrode of the transistor (552).

[0673] The capacitance element (562) functions as a storage capacity element for storing recorded data.

[0674] One of the source electrode and drain electrode of the transistor (554) is electrically connected to the potential supply line (VL_a). The gate electrode of the transistor (554) is electrically connected to the other of the source electrode and drain electrode of the transistor (552).

[0675] One of the positive and negative electrodes of the light-emitting element (572) is electrically connected to the potential supply line (VL_b), and the other of the positive and negative electrodes of the light-emitting element (572) is electrically connected to the other of the source electrode and drain electrode of the transistor (554).

[0676] For example, an organic electroluminescent device (also called an organic EL device) can be used as the light-emitting element (572). In addition, the light-emitting element (572) is not limited to this and may be an inorganic EL device containing an inorganic material.

[0677] High power potential ( V DD ) is supplied, and a low power potential ( V SS ) is supplied.

[0678] In a display device including the pixel circuit (501) of (C) of FIG. 60, the gate driver (504a) of (A) of FIG. 60 sequentially selects the pixel circuit (501) row by row to turn on the transistor (552) and records a data signal.

[0679] When the transistor (552) is turned off, the pixel circuit (501) on which data is recorded remains in a maintained state. Additionally, the amount of current flowing between the source electrode and the drain electrode of the transistor (554) is controlled according to the potential of the recorded data signal. The light-emitting element (572) emits light with a brightness corresponding to the amount of current flowing. By performing this operation sequentially for each row, an image can be displayed.

[0680] At least a part of this embodiment may be implemented in appropriate combination with any of the other embodiments described in this specification.

[0681] (Embodiment 5)

[0682] In this embodiment, a display module and an electronic device each comprising a semiconductor device of one form of the present invention will be described with reference to FIGS. 61, FIGS. 62 (A) to (E), FIGS. 63 (A) to (G), FIGS. 64 (A) to (E), FIGS. 65 (A) and (B), and FIGS. 66 (A) and (B).

[0683] <5-1. Display Module>

[0684] In the display module (7000) illustrated in FIG. 61, a touch panel (7004) connected to an FPC (7003), a display panel (7006) connected to an FPC (7005), a backlight (7007), a frame (7009), a printed circuit board (7010), and a battery (7011) are provided between the upper cover (7001) and the lower cover (7002).

[0685] One form of the semiconductor device of the present invention can be used, for example, in a display panel (7006).

[0686] The shape and size of the upper cover (7001) and the lower cover (7002) can be appropriately changed according to the size of the touch panel (7004) and the display panel (7006).

[0687] The touch panel (7004) may be a resistive touch panel or a capacitive touch panel and may overlap with the display panel (7006). Alternatively, the opposing substrate (sealed substrate) of the display panel (7006) may have a touch panel function. Alternatively, an optical touch panel may be formed by providing a photosensor to each pixel of the display panel (7006).

[0688] The backlight (7007) includes a light source (7008). One embodiment of the present invention is not limited to the structure of FIG. 61 in which the light source (7008) is provided on the backlight (7007). For example, a structure may be adopted in which the light source (7008) is provided at the end of the backlight (7007) and a light diffusion plate is further provided. In addition, when using a self-emissive light-emitting element such as an organic EL element or when employing a reflective panel, it is not necessary to provide the backlight (7007).

[0689] The frame (7009) protects the display panel (7006) and functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the printed circuit board (7010). The frame (7009) may also function as a radiator plate.

[0690] The printed circuit board (7010) includes a power circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power circuit, an external commercial power source or a separate battery (7011) may be used. The battery (7011) may be omitted if a commercial power source is used.

[0691] In addition, a polarizing plate, a phase difference plate, or a prism sheet may be provided to the display module (7000).

[0692] <5-2. Electronic Devices 1>

[0693] Next, Figures 62 (A) to (E) illustrate examples of electronic devices.

[0694] Figure 62 (A) is an external view of a camera (8000) equipped with a finder (8100).

[0695] The camera (8000) includes a housing (8001), a display unit (8002), an operation button (8003), and a shutter button (8004), etc. Additionally, a detachable lens (8006) is mounted on the camera (8000).

[0696] Here, the lens (8006) of the camera (8000) may be removed from the housing (8001) for replacement, but the lens (8006) may be included in the housing (8001).

[0697] You can take an image with the camera (8000) by pressing the shutter button (8004). You can also take an image by touching the display (8002) which functions as a touch panel.

[0698] Since the housing (8001) of the camera (8000) includes a mount containing electrodes, a finder (8100) or a stroboscope, etc., can be connected to the housing (8001).

[0699] The finder (8100) includes a housing (8101), a display (8102), and a button (8103), etc.

[0700] The housing (8101) includes a mount that connects to the mount of the camera (8000), so the finder (8100) can be connected to the camera (8000). This mount includes an electrode and can display an image, etc. received from the camera (8000) through the electrode on the display unit (8102).

[0701] The button (8103) functions as a power button. The display unit (8102) can be turned on and off using the button (8103).

[0702] A display device of one form of the present invention can be used in the display portion (8002) of a camera (8000) and the display portion (8102) of a finder (8100).

[0703] In Fig. 62 (A), the camera (8000) and the finder (8100) are separate and detachable electronic devices, but the housing (8001) of the camera (8000) may include a finder having a display device.

[0704] Figure 62 (B) is an external view of a head-mounted display (8200).

[0705] The head-mounted display (8200) includes a mounting part (8201), a lens (8202), a main body (8203), a display part (8204), and a cable (8205), etc. The mounting part (8201) includes a battery (8206).

[0706] Power is supplied to the main body (8203) from the battery (8206) through the cable (8205). The main body (8203) receives image data, such as video data, including a wireless receiver, and displays it on the display unit (8204). After detecting the movement of the user's eyeball and eyelid by the camera of the main body (8203), the coordinates of the user's viewpoint are calculated using the detected data, thereby utilizing the user's eye as an input means.

[0707] The mounting portion (8201) may include a plurality of electrodes to come into contact with the user. The main body (8203) may detect the current flowing through the electrodes according to the movement of the user's eyeballs to recognize the direction of the user's eyes. The main body (8203) may monitor the user's pulse by detecting the current flowing through the electrodes. The mounting portion (8201) may include sensors such as a temperature sensor, a pressure sensor, or an accelerometer to display the user's biometric information on the display portion (8204). The main body (8203) may detect the movement of the user's head, etc., and move the image displayed on the display portion (8204) in accordance with the movement of the user's head, etc.

[0708] A display device of one form of the present invention can be used in the display unit (8204).

[0709] Figures 62 (C) to (E) are external views of a head-mounted display (8300). The head-mounted display (8300) includes a housing (8301), a display unit (8302), a fastener (8304) such as a band, and a pair of lenses (8305).

[0710] The user can view the display of the display unit (8302) through the lens (8305). It is preferable that the display unit (8302) be curved. When the display unit (8302) is curved, the user can feel a high sense of realism regarding the image. The structure exemplified in this embodiment has one display unit (8302), but the number of display units (8302) provided is not limited to one. For example, two display units (8302) may be provided, and in this case, if one display unit is provided for the user's corresponding eye, a three-dimensional display using parallax is possible.

[0711] A display device of one form of the present invention can be used in a display unit (8302). Since the display device including a semiconductor device of one form of the present invention has a very high resolution, even if the image is enlarged using a lens (8305) as shown in (E) of FIG. 62, the user does not recognize pixels, so a more realistic image can be displayed.

[0712] <5-3. Electronic Devices 2>

[0713] Next, FIGS. 63 (A) to (G) and FIGS. 64 (A) to (E) illustrate examples of electronic devices different from the electronic devices shown in FIGS. 62 (A) to (E).

[0714] The electronic device illustrated in (A) to (G) of FIG. 63 includes a housing (9000), a display unit (9001), a speaker (9003), an operating key (9005) (including a power switch or an operating switch), a connection terminal (9006), a sensor (9007) (a sensor having the function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, smell, or infrared radiation), and a microphone (9008), etc.

[0715] The electronic devices of FIGS. 63 (A) to (G) and FIGS. 64 (A) to (E) have various functions, such as a function to display various information (e.g., still images, video, and text images) on a display unit, a touch panel function, a function to display a calendar, date, and time, a function to control processing with various software (programs), a wireless communication function, a function to connect to various computer networks via a wireless communication function, a function to transmit and receive various data via a wireless communication function, and a function to read programs or data stored on a recording medium and display them on a display unit. Furthermore, the functions of the electronic devices of FIGS. 63 (A) to (G) and FIGS. 64 (A) to (E) are not limited thereto, and the electronic devices may have various functions. Although not illustrated in FIGS. 63 (A) to (G) and FIGS. 64 (A) to (E), each of the electronic devices may have a plurality of display units. In addition, each of the electronic devices may be provided with a camera, etc., and may have a function for capturing still images, a function for capturing video, a function for storing captured images in a storage medium (an external storage medium or a storage medium built into the camera), or a function for displaying captured images on a display unit.

[0716] The electronic devices of FIGS. 63 (A) to (G) and FIGS. 64 (A) to (E) will be described in detail below.

[0717] FIG. 63 (A) is a perspective view illustrating a television device (9100). The television device (9100) may include a display unit (9001) having a large screen size of, for example, 50 inches or more, or 100 inches or more.

[0718] FIG. 63 (B) is a perspective view of a portable information terminal (9101). The portable information terminal (9101) functions as one or more of, for example, a telephone, a notebook, and an information viewing system. Specifically, the portable information terminal (9101) can be used as a smartphone. Additionally, the portable information terminal (9101) may include a speaker, a connection terminal, or a sensor, etc. The portable information terminal (9101) may display text and image information on its multiple surfaces. For example, three operation buttons (9050) (also called operation icons or simply icons) may be displayed on one surface of the display unit (9001). Additionally, information (9051) indicated by a dashed rectangle may be displayed on the other surface of the display unit (9001). Examples of information (9051) include an email, a social networking service (SNS) message, an indication of receiving a phone call, the subject and sender of the email or SNS message, the date, time, the remaining battery level, and the reception strength of the antenna. Alternatively, instead of information (9051), operation buttons (9050), etc., may be displayed.

[0719] FIG. 63 (C) is a perspective view of a portable information terminal (9102). The portable information terminal (9102) has the function of displaying information on three or more surfaces of a display unit (9001). Here, information (9052), information (9053), and information (9054) are displayed on different surfaces. For example, a user of the portable information terminal (9102) can view the display (here, information (9053)) while the portable information terminal (9102) is placed in the chest pocket of their clothing. Specifically, the phone number or name of the caller of an incoming call is displayed in a position visible from above the portable information terminal (9102). The user can view the display and decide whether to answer the call without taking the portable information terminal (9102) out of the pocket.

[0720] FIG. 63 (D) is a perspective view of a watch-type portable information terminal (9200). The portable information terminal (9200) can execute various applications such as mobile phone, email, viewing and editing text, music playback, internet communication, and computer games. The display surface of the display unit (9001) is curved, and a display can be performed on the curved display surface. The portable information terminal (9200) may employ short-range wireless communication that conforms to communication standards. For example, hands-free calling can be realized through mutual communication between the portable information terminal (9200) and a headset capable of wireless communication. In addition, the portable information terminal (9200) includes a connection terminal (9006) and can perform direct data communication with another information terminal through a connector. Charging through the connection terminal (9006) is also possible. Additionally, charging operation may be performed by wireless power supply without using the connection terminal (9006).

[0721] Figures (E), (F), and (G) of FIG. 63 are perspective views illustrating a foldable information terminal (9201) in an unfolded state, a state in the middle of changing from an unfolded state to a folded state or from a folded state to an unfolded state, and a folded state, respectively. When the information terminal (9201) is folded, portability is high. When the information terminal (9201) is unfolded, visibility of a large, seamless display area is high. The display portion (9001) of the information terminal (9201) is supported by three housings (9000) connected by a hinge (9055). By folding at the hinge (9055) between two adjacent housings (9000), the information terminal (9201) can be reversibly deformed from an unfolded state to a folded state. For example, the information terminal (9201) can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0722] FIG. 64 (A) is a perspective view of a television device (9150) different from the television device of FIG. 63 (A). In the television device (9150), a display unit (9152) is built into a housing (9151). Here, the housing (9151) is supported by a stand (9153). Unlike the television device (9100), the television device (9150) has a display unit (9152) and a housing (9151).

[0723] The television device (9150) illustrated in (A) of FIG. 64 can be operated by an operating switch of the housing (9151) or by a separate remote controller (9154). The display unit (9152) may include a touch sensor and can be operated by touching the display unit (9152) with a finger or the like. The remote controller (9154) may be provided with a display unit that displays information output from the remote controller (9154). Channels or volume can be operated by the operation keys or touch panel of the remote controller (9154), and images displayed on the display unit (9152) can be operated.

[0724] Additionally, the television device (9150) is provided with a receiver or a modem, etc. It can receive general television broadcasts using the receiver. Furthermore, by connecting the television device to a communication network via a wired or wireless connection through a modem, it can perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication.

[0725] FIG. 64 (B) is a perspective view illustrating a notebook-type personal computer (9250). The notebook-type personal computer (9250) includes a housing (9251), a display unit (9252), a keyboard (9253), and a pointing device (9254), etc.

[0726] Figure 64 (C) is a perspective view illustrating a stationary slot machine (9300). In the slot machine (9300), a display unit (9303) is built into the housing (9301). Additionally, the slot machine (9300) includes operating means such as a start lever (9304) or a stop switch (9305), a coin slot, a speaker, a light source for a sensor (9306), and a sensor (9302).

[0727] Figure 64 (D) is an exterior view of the automobile (9400). Figure 64 (E) is a view of the driver's seat of the automobile (9400). The automobile (9400) includes a car body (9401), wheels (9402), a windshield (9403), lights (9404), and fog lamps (9405), etc.

[0728] A display device of one form of the present invention can be used in a display unit of a vehicle (9400), etc. For example, a display device of one form of the present invention can be used in a display unit (9410 to 9417) shown in (E) of FIG. 64.

[0729] The display unit (9410) and the display unit (9411) are provided on the windshield of the vehicle. One embodiment of the display device of the present invention may be a so-called see-through device in which the opposite side is visible by using a light-transmitting conductive material on its electrodes. Such a see-through display device does not obstruct the field of view even when driving the vehicle (9400). Therefore, one embodiment of the display device of the present invention may be provided on the windshield of the vehicle (9400). Furthermore, when providing a transistor, etc. to the display device, it is preferable to use a light-transmitting transistor, such as an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor.

[0730] A display unit (9412) is provided on the pillar portion. A display unit (9413) is provided on the dashboard. For example, by displaying an image captured by an imaging means provided on the vehicle body on the display unit (9412), the view obscured by the pillar portion can be supplemented. Similarly, the display unit (9413) can supplement the view obscured by the dashboard, and the display unit (9414) can supplement the view obscured by the door. That is, by displaying an image captured by an imaging means provided on the exterior of the vehicle, blind spots can be eliminated and safety can be enhanced. Additionally, by displaying an image that supplements parts not visible to the driver, the driver can check safety more easily and comfortably.

[0731] A display unit (9417) is provided on the handle. The display unit (9415), display unit (9416), or display unit (9417) can provide various information such as navigation information, speedometer, tachometer, driving distance, fuel level, gear shift indicator, and air conditioner settings. The display items or layout of the display unit can be freely changed by the user as appropriate. The above-mentioned information may also be displayed on the display units (9410 to 9414).

[0732] The display unit (9410 to 9417) may also be used as a lighting device.

[0733] FIG. 65 (A) is a perspective view illustrating a digital signage (9600). The digital signage (9600) may include a display unit (9601), a housing (9602), and a speaker (9603). As shown in FIG. 65 (B), the digital signage (9600) may be mounted on a cylindrical column.

[0734] Next, examples of electronic devices different from the electronic devices shown in FIGS. 62 (A) to (E), FIGS. 63 (A) to (G), and FIGS. 64 (A) to (E) are shown in FIGS. 66 (A) and (B). FIGS. 66 (A) and (B) are perspective views of a display device including a plurality of display panels. Additionally, the plurality of display panels are in a wound state in the perspective view of FIG. 66 (A), and are in an unwound state in the perspective view of FIG. 66 (B).

[0735] The display device (9500) illustrated in (A) and (B) of FIG. 66 includes a plurality of display panels (9501), a hinge (9511), and a bearing (9512). Each of the plurality of display panels (9501) includes a display area (9502) and a light-transmitting area (9503).

[0736] Each of the multiple display panels (9501) is flexible. Two adjacent display panels (9501) are provided to partially overlap each other. For example, the light-transmitting areas (9503) of two adjacent display panels (9501) can be overlapped. A display device having a large screen can be obtained using multiple display panels (9501). This display device has high versatility because the display panels (9501) can be rolled up depending on the application.

[0737] The display device shown in (A) and (B) of FIG. 66 can be easily converted into a face-up screen and can also be used for the digital signage described above.

[0738] In addition, in (A) and (B) of FIG. 66, the display areas (9502) of adjacent display panels (9501) are spaced apart from each other, but this structure is not limited to this, and for example, the display areas (9502) of adjacent display panels (9501) may be overlapped without gaps to obtain a continuous display area (9502).

[0739] Each of the electronic devices described in the present embodiment includes a display unit for displaying some kind of information. In addition, a semiconductor device of one form of the present invention may also be used in electronic devices that do not have a display unit.

[0740] At least a part of this embodiment may be implemented in appropriate combination with any of the other embodiments described in this specification.

[0741] (Embodiment 6)

[0742] In this embodiment, one form of a semiconductor device is described with reference to FIGS. 67 to 69.

[0743] [Structural Example]

[0744] Examples of a semiconductor device (memory device) including a capacitive element of one form of the present invention are illustrated in FIGS. 67 (A) and (B), FIGS. 68, and FIGS. 69. FIGS. 67 (A) is a circuit diagram corresponding to FIGS. 68 and FIGS. 69, respectively.

[0745] Circuit configuration of semiconductor devices

[0746] Each of the semiconductor devices shown in FIG. 67 (A), FIG. 68, and FIG. 69 includes a transistor (3300), a transistor (3200), and a capacitance element (3100).

[0747] The transistor (3200) is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. Since the off-state current of the transistor (3200) is small, by using this transistor (3200) in a semiconductor device (memory device), stored data can be maintained for a long time. In other words, a semiconductor device (memory device) that does not require a refresh operation or has a very low frequency of refresh operations can be obtained, and power consumption is sufficiently reduced.

[0748] In FIG. 67 (A), the first wire (3001) is electrically connected to the source of the transistor (3300). The second wire (3002) is electrically connected to the drain of the transistor (3300). The third wire (3003) is electrically connected to one of the source and drain of the transistor (3200). The fourth wire (3004) is electrically connected to the gate of the transistor (3200). The gate of the transistor (3300) and the other of the source and drain of the transistor (3200) are electrically connected to one electrode of the capacitance element (3100). The fifth wire (3005) is electrically connected to the other electrode of the capacitance element (3100).

[0749] The semiconductor device of Fig. 67 (A) has the characteristic of being able to maintain the potential of the gate of the transistor (3300), so data can be recorded, maintained, and read as follows.

[0750] The recording and maintenance of data is described. First, the potential of the fourth wire (3004) is set to a potential at which the transistor (3200) turns on, thereby turning on the transistor (3200). As a result, the potential of the third wire (3003) is supplied to a node (FG) where the gate of the transistor (3300) and one electrode of the capacitance element (3100) are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor (3300) (recorded). Here, one of two types of charges (hereinafter referred to as low-level charge and high-level charge) providing different potential levels is supplied. Afterward, the potential of the fourth wire (3004) is set to a potential at which the transistor (3200) turns off, thereby turning off the transistor (3200). As a result, the charge is maintained at the node (FG) (maintained).

[0751] When the off-state current of the transistor (3200) is low, the charge of the node (FG) is maintained for a long time.

[0752] Next, the reading of data will be explained. Since an appropriate potential (read potential) is supplied to the fifth wiring (3005) while a predetermined potential (positive potential) is supplied to the first wiring (3001), the potential of the second wiring (3002) varies according to the amount of charge maintained at the node (FG). This is the apparent threshold voltage V when a high-level charge is applied to the gate of the transistor (3300) when an n-channel type transistor is used as the transistor (3300). th_H The apparent threshold voltage V when a low-level charge is applied to the gate of the transistor (3300). th_L This is because it is lower. Here, the apparent threshold voltage refers to the potential of the fifth wire (3005) required to turn on the transistor (3300). Therefore, the potential of the fifth wire (3005) is V th_H and V th_LBy setting the potential between them to V0, the charge supplied to the node (FG) can be determined. For example, in the record, a high-level charge is supplied to the node (FG) and the potential of the fifth wiring (3005) is V0 (>V th_H ) In this case, the transistor (3300) is turned on. Meanwhile, when a low-level charge is supplied to the node (FG) during recording, the potential of the fifth wire (3005) becomes V0 ( <V th_L Even if ), the transistor (3300) remains off. Therefore, the data maintained at the node (FG) can be read by determining the potential of the second wiring (3002).

[0753] A memory device (memory cell array) can be formed by arranging semiconductor devices having the structures shown in (A) of FIG. 67 as a matrix.

[0754] In addition, when memory cells are arranged, it is necessary to read the data of the desired memory cell during the read operation. At the fifth wiring (3005) of the memory cell for which data is not read, the potential V at which the transistor (3300) is turned off regardless of the charge supplied to the node (FG) is applied. th_H It is preferable to adopt a configuration that allows reading only the information of the desired memory cell by supplying a lower potential. Alternatively, for the fifth wiring (3005) of a memory cell that does not read data, a potential V at which the transistor (3300) turns on regardless of the charge supplied to the node (FG) is used. th_L It is advisable to adopt a configuration that allows reading only the information of the desired memory cell by supplying a higher potential.

[0755] <Circuit Configuration of Semiconductor Devices 2>

[0756] The semiconductor device of FIG. 67 (B) differs from the semiconductor device of FIG. 67 (A) in that it is not provided with a transistor (3300). Even in this case, data can be recorded and maintained in a manner similar to that of the semiconductor device of FIG. 67 (A).

[0757] The reading of data of the semiconductor device of FIG. 67 (B) is described. When the transistor (3200) is turned on, the third wiring (3003) and the capacitance element (3100) in a floating state become conductive, and charge is redistributed between the third wiring (3003) and the capacitance element (3100). As a result, the potential of the third wiring (3003) changes. The amount of change in the potential of the third wiring depends on the potential of one electrode of the capacitance element (3100) (or the charge accumulated in the capacitance element (3100)).

[0758] For example, the potential of the third wiring (3003) after charge redistribution is ( C B × V B0 + C × V ) / ( C B + C ) and, V is the potential of one electrode of the capacitive element (3100), C is the capacitance of the capacitance element (3100), C B is the capacitive component of the third wiring (3003), and V B0 It is the potential of the third wiring (3003) before the charge is redistributed. Therefore, the potential of one electrode of the memory cell, the capacitance element (3100) V 1 and V 0( V 1> V Assuming it is in one of the two states where 0), the potential V The potential of the third wiring (3003) when maintaining 1 (=( C B × V B0 + C × V 1) / ( C B + C )) is the potential V The potential of the third wiring (3003) when maintaining 0 (=( CB × V B0 + C × V 0) / ( C B + C It can be seen that it is higher than ))

[0759] And data can be read by comparing the potential of the third wire (3003) with a predetermined potential.

[0760] In this case, a transistor including a first semiconductor is used in the driving circuit for driving the memory cell, and a transistor including a second semiconductor is stacked on the driving circuit as a transistor (3200).

[0761] When using an oxide semiconductor and including a transistor with a low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, power consumption is sufficiently reduced because refresh operations become unnecessary or the frequency of refresh operations can be made very low. Furthermore, stored data can be retained for a long time even when power is not supplied (and the potential is preferably fixed).

[0762] Furthermore, since high voltage is not required for data recording in semiconductor devices, device degradation is unlikely to occur. For example, unlike conventional non-volatile memory, since the injection of electrons into and extraction of electrons from the floating gate is unnecessary, problems such as insulator degradation do not occur. In other words, unlike conventional non-volatile memory, a semiconductor device of one embodiment of the present invention has no limit on the number of times it can be rewritten, and its reliability is significantly improved. In addition, since data is recorded according to the state (on or off) of the transistor, high-speed operation can be easily achieved.

[0763] Structure of Semiconductor Devices 1

[0764] As shown in FIG. 68, a semiconductor device of one embodiment of the present invention comprises a transistor (3300), a transistor (3200), and a capacitance element (3100). The transistor (3200) is provided on the transistor (3300), and the capacitance element (3100) is provided on the transistor (3300) and the transistor (3200).

[0765] A transistor (3300) is provided on a substrate (3311) and includes a conductor (3316), an insulator (3314), a semiconductor region (3312) that is part of the substrate (3311), and low-resistance regions (3318a and 3318b) that function as a source region and a drain region.

[0766] The transistor (3300) may be a p-channel transistor or an n-channel transistor.

[0767] The region where the channel of the semiconductor region (3312) is formed, the region nearby therefrom, and the low-resistance region (3318a and 3318b) functioning as a source region and a drain region, etc., preferably include a semiconductor such as a silicon-based semiconductor, and more preferably include single-crystal silicon. Alternatively, a material including germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or gallium aluminum arsenide (GaAlAs) may be included. Silicon in which the effective mass is controlled by changing the lattice spacing by applying stress to the crystal lattice may be included. Alternatively, the transistor (3300) may be a high-electron-mobility transistor (HEMT) having GaAs and GaAlAs.

[0768] The low-resistance regions (3318a and 3318b) include, in addition to the semiconductor material used in the semiconductor region (3312), an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0769] A conductor (3316) functioning as a gate electrode can be formed using a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0770] In addition, the threshold voltage can be adjusted by determining the work function based on the material of the conductor. Specifically, it is preferable to use titanium nitride or tantalum nitride, etc., as the conductor. Furthermore, to ensure the conductivity and embedment of the conductor, it is preferable to use a lamination of metal materials such as tungsten and aluminum as the conductor. In particular, tungsten is preferred in terms of heat resistance.

[0771] In the transistor (3300) shown in FIG. 68, the semiconductor region (3312) (part of the substrate (3311)) where the channel is formed includes a protrusion. Additionally, a conductor (3316) is provided to cover the side and top surfaces of the semiconductor region (3312) via an insulator (3314). Additionally, the conductor (3316) may be formed using a material for adjusting the work function. A transistor (3300) having this structure is also called a FIN-type transistor because it utilizes a protrusion of the semiconductor substrate. An insulator functioning as a mask for forming the protrusion may be provided to be in contact with the top of the protrusion. Although the case in which a protrusion is formed by processing a part of the semiconductor substrate is illustrated here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate.

[0772] In addition, the transistor (3300) shown in FIG. 68 is merely an example and is not limited to the structure shown therein; a suitable transistor may be used depending on the circuit configuration or driving method. For example, the transistor (3300) may be a planar type transistor as described later. When using the circuit configuration shown in (B) of FIG. 67, the transistor (3300) may be omitted.

[0773] Insulators (3320), insulators (3322), insulators (3324), and insulators (3326) are stacked sequentially and cover the transistor (3300).

[0774] Insulators (3320), insulators (3322), insulators (3324), and insulators (3326) can be formed using, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, or aluminum nitride.

[0775] The insulator (3322) functions as a flattening film that eliminates the step difference caused by the transistor (3300), etc. located beneath the insulator (3322). The upper surface of the insulator (3322) may be flattened by a flattening treatment using a CMP method, etc., to increase the level of flattening.

[0776] The insulator (3324) is preferably formed using a film having barrier properties that prevent hydrogen or impurities from diffusing from, for example, a substrate (3311) or a transistor (3300) into the region where the transistor (3200) is formed.

[0777] Examples of films having barrier properties against hydrogen include silicon nitride formed by the CVD method. As hydrogen diffuses into a semiconductor device containing an oxide semiconductor, such as a transistor (3200), the characteristics of the semiconductor device may deteriorate. Therefore, it is desirable to provide a film that prevents the diffusion of hydrogen between the transistor (3200) and the transistor (3300). Specifically, the film that prevents the diffusion of hydrogen is a film that makes it difficult for hydrogen to be released.

[0778] The amount of hydrogen released can be measured, for example, by TDS. For example, the amount of hydrogen released from the insulator (3324), converted into hydrogen atoms per area of ​​the insulator (3324), is 10×10 in TDS in the range of 50°C to 500°C. 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 It is as follows.

[0779] In addition, it is preferable that the dielectric constant of the insulator (3326) be lower than the dielectric constant of the insulator (3324). For example, the dielectric constant of the insulator (3326) is preferably less than 4, and more preferably less than 3. For example, it is preferable that the dielectric constant of the insulator (3324) be 0.7 times or less of the dielectric constant of the insulator (3326), and more preferable that it be 0.6 times or less of the dielectric constant of the insulator (3326). When a material with a low dielectric constant is used as an interlayer film, the parasitic capacitance between the wires can be reduced.

[0780] Insulators (3320), insulators (3322), insulators (3324), and insulators (3326) have embedded conductors (3328) and conductors (3330), which are electrically connected to a capacitive element (3100) or a transistor (3200). Additionally, each of the conductors (3328) and conductors (3330) functions as a plug or wiring. Furthermore, as described below, there are cases where multiple structures of conductors functioning as plugs or wiring are collectively represented by the same reference numeral. Also, in this specification, wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where a part of the conductor functions as wiring and a part of the conductor functions as a plug.

[0781] As the material for each plug and wiring (e.g., conductor (3328) and conductor (3330)), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials may be used in a single-layer or multilayer structure. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which possess both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, it is preferable to use low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0782] A wiring layer may be provided on the insulator (3326) and the conductor (3330). For example, in FIG. 68, an insulator (3350), an insulator (3352), and an insulator (3354) are stacked sequentially. Additionally, a conductor (3356) is formed on the insulator (3350), the insulator (3352), and the insulator (3354). The conductor (3356) functions as a plug or wiring. Additionally, the conductor (3356) may be formed using a material similar to the material used to form the conductor (3328) and the conductor (3330).

[0783] Additionally, for example, it is preferable to form the insulator (3350) using an insulator that has a barrier property against hydrogen, such as the insulator (3324). Also, it is preferable for the conductor (3356) to include a conductor that has a barrier property against hydrogen. In particular, a conductor that has a barrier property against hydrogen is formed at the opening of the insulator (3350) that has a barrier property against hydrogen. In this structure, since the transistor (3300) and the transistor (3200) can be separated by a barrier layer, the diffusion of...

Claims

Claim 1 A semiconductor device comprising: an oxide semiconductor film including a composite oxide semiconductor, wherein the composite oxide semiconductor comprises a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; and a drain electrode electrically connected to the oxide semiconductor film, wherein each of the plurality of first regions comprises indium, zinc, and element M, and the element M is selected from Al, Ga, Y, and Sn, and the second region comprises indium, zinc, and element M, and the element M is selected from Al, Ga, Y, and Sn, and the atomic number ratio of indium to element M in each of the plurality of first regions is greater than the atomic number ratio of indium to element M in the second region, and the plurality of first regions are scattered in the second region. Claim 2 A semiconductor device comprising: an oxide semiconductor film including a composite oxide semiconductor, wherein the composite oxide semiconductor is a composite oxide semiconductor comprising a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; and a source electrode electrically connected to the oxide semiconductor film. A semiconductor device comprising a drain electrode electrically connected to the oxide semiconductor film, wherein each of the plurality of first regions comprises indium, zinc, and element M, and the element M is selected from Al, Ga, Y, and Sn, and the second region comprises indium, zinc, and element M, and the element M is selected from Al, Ga, Y, and Sn, and the atomic number ratio of indium to element M in each of the plurality of first regions is greater than the atomic number ratio of indium to element M in the second region, and the atomic number ratio of indium to element M in each of the plurality of first regions is at least 1.1 times the atomic number ratio of indium to element M in the second region, and the plurality of first regions are scattered in the second region. Claim 3 A semiconductor device comprising: an oxide semiconductor film including a composite oxide semiconductor, wherein the composite oxide semiconductor is a composite oxide semiconductor comprising a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; and a source electrode electrically connected to the oxide semiconductor film. A semiconductor device comprising a drain electrode electrically connected to the oxide semiconductor film, wherein each of the plurality of first regions comprises indium, zinc, and element M, and the element M is selected from Al, Ga, Y, and Sn, and the second region comprises indium, zinc, and element M, and the element M is selected from Al, Ga, Y, and Sn, and the atomic ratio of indium to element M in each of the plurality of first regions is greater than the atomic ratio of indium to element M in the second region, and the atomic ratio of indium to element M in each of the plurality of first regions is 2 to 10 times the atomic ratio of indium to element M in the second region, and the plurality of first regions are scattered in the second region. Claim 4 A semiconductor device according to any one of claims 1 to 3, wherein each of the plurality of first regions comprises a plurality of clusters, and at least one of the plurality of clusters comprises a portion having a length of 0.1 nm or more and 2.5 nm or less. Claim 5 A semiconductor device according to any one of claims 1 to 3, wherein the atomic number ratio of indium to element M to zinc is [In]:[M]:[Zn] = 4:2:3 or near 4:2:3 in the second region. Claim 6 A semiconductor device according to any one of claims 1 to 3, wherein the atomic number ratio of indium to element M to zinc is [In]:[M]:[Zn] = 5:1:6 or near 5:1:6 in the second region. Claim 7 A display device comprising: a semiconductor device according to any one of claims 1 to 3; and a display element. Claim 8 A display module comprising: a display device according to claim 7; and a touch sensor.

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