Package substrate and semiconductor package including the same

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a base substrate including a redistribution layer; pads disposed on one surface of the base substrate and electrically connected to the redistribution layer; a protective layer having a mounting area disposed therein having first openings that expose first pads among the pads and a second opening that exposes second pads among the pads and a portion of the one surface of the base substrate; a semiconductor chip disposed on the mounting area of ​​the protective layer and electrically connected to the pads through the first openings and the second opening; and a sealant covering a portion of the semiconductor chip and extending into the second opening, wherein four of the first openings are disposed adjacent to each corner of the mounting area, and the second opening is disposed to divide the four first openings into at least two groups.

Description

Technology Field

[0001] The present invention relates to a package substrate and a semiconductor package including the same. Background Technology

[0003] In the case of semiconductor packages containing high-performance semiconductor chips, problems such as system malfunction and performance degradation may occur due to voltage noise generated in the high-frequency band. Therefore, there is a need to develop packaging technology that can improve the Power Integrity (PI) characteristics of semiconductor packages by eliminating voltage noise. To this end, semiconductor chips, such as passive components, are mounted on the back of the semiconductor package. The problem to be solved

[0005] One of the problems to be solved by the present invention is to provide a package substrate that improves the reliability of the semiconductor chip mounted thereon.

[0006] One of the problems to be solved by the present invention is to provide a semiconductor package with improved reliability of a semiconductor chip mounted on a package substrate. means of solving the problem

[0008] One embodiment of the present invention comprises: a base substrate having a front surface and a rear surface opposite to each other and including a redistribution layer; front pads disposed on the front surface and electrically connected to the redistribution layer; rear pads disposed on the rear surface and electrically connected to the redistribution layer; a front protective layer having front openings that expose each of the front pads on the front surface; and a rear protective layer having a mounting area disposed on the rear surface having first rear openings that expose each of the rear pads and second rear openings that expose a portion of the rear surface and second rear pads among the rear pads; a semiconductor chip disposed on the front protective layer and connected to the front pads; a passive component disposed on the mounting area of ​​the rear protective layer and connected to the rear pads; and connection bumps disposed adjacent to the passive component on the rear surface and electrically connected to the redistribution layer. The semiconductor package includes a sealant that is spaced apart from the connection bumps, covers a portion of the passive element, and extends into the second rear opening, wherein four of the first rear openings are each positioned adjacent to each corner of the mounting area, and the second rear opening is positioned to divide the four first rear openings into at least two groups.

[0010] One embodiment of the present invention provides a semiconductor package comprising: a base substrate including a redistribution layer; pads disposed on one surface of the base substrate and electrically connected to the redistribution layer; a protective layer having a mounting area disposed therein having first openings that expose first pads among the pads and a second opening that exposes second pads among the pads and a portion of the one surface of the base substrate; a semiconductor chip disposed on the mounting area of ​​the protective layer and electrically connected to the pads through the first openings and the second opening; and a sealant covering a portion of the semiconductor chip and extending into the second opening, wherein four of the first openings are disposed adjacent to each corner of the mounting area, and the second opening is disposed to divide the four first openings into at least two groups.

[0012] One embodiment of the present invention provides a package substrate having a front surface and a rear surface opposite to each other, comprising a plurality of insulating layers and redistribution layers disposed within the plurality of insulating layers; front pads disposed on the front surface and electrically connected to the redistribution layers; rear pads disposed on the rear surface and electrically connected to the redistribution layers; a front protective layer having front openings that expose each of the front pads on the front surface; and a rear protective layer having a mounting area disposed on the rear surface, wherein first rear openings that expose each of the first rear pads among the rear pads and a second rear opening that exposes a portion of the rear surface and the second rear pads among the rear pads are disposed, wherein four of the first rear openings are disposed adjacent to each corner of the mounting area, and the second rear opening is disposed to divide the four rear openings into at least two groups. Effects of the invention

[0014] According to embodiments of the present invention, a package substrate and a semiconductor package can be provided in which the reliability of the semiconductor chip mounted thereon is improved.

[0016] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0018] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. Figure 2 is a partial enlarged view illustrating area 'A' of Figure 1. Figure 3a is a plan view of the part shown in Figure 2. Figure 3b is a plan view taken after removing the semiconductor device and sealant from Figure 3a. FIGS. 4 to 10 are examples of variations of the package substrate shown in FIG. 3b. FIG. 11 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 12 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. Specific details for implementing the invention

[0019] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0021] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 2 is a partial enlarged view illustrating region 'A' of FIG. 1. FIG. 3a is a plan view of the portion illustrated in FIG. 2, and FIG. 3b is a plan view of FIG. 3a after removing the semiconductor device and sealant.

[0023] Referring to FIGS. 1 and 2, a semiconductor package (100) of one embodiment may include a package substrate (110), a semiconductor chip (120), a passive component (160), and a sealing material (166). According to an embodiment, the semiconductor package (100) of one embodiment may further include a sealing material (150) and a connecting bump (170).

[0025] The package substrate (110) is a support substrate on which a semiconductor chip (120) is mounted, and may be a rewiring structure for rewiring the connection pads (121) of the semiconductor chip (120). For example, the package substrate (110) may be a printed circuit board (PCB). The package substrate (110) may include a base substrate (118) having a front side (S1) and a back side (S2) arranged in opposite directions, front pads (114) and back pads (115) arranged on the front side (S1) and back side (S2), respectively, a front protective layer (116) covering the front side (S1) having front openings (FO) that expose the front pads (114), and a back protective layer (117) covering the back side (S2) having back openings (BO) that expose the back pads (115).

[0027] The base substrate (118) may include a plurality of insulating layers (111) and a plurality of redistribution layers (112) and redistribution vias (113) disposed within the plurality of insulating layers (111).

[0028] The insulating layers (111) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler or / and glass fiber (glass fiber, glass cloth, glass fabric) is impregnated into these resins, for example, a photosensitive resin such as prepreg, ABF, FR-4, BT, or PID (Photo-Imageable Dielectric). The insulating layers (111) may be laminated in a vertical direction (Z-axis direction). Among the plurality of insulating layers (111), the uppermost insulating layer (111a) may provide a front surface (S1), and the lowermost insulating layer (111b) may provide a rear surface (S2). Depending on the process, the boundary between the plurality of insulating layers (111) may be indistinct. In one embodiment, only three insulating layers (111) are shown in the drawings, but embodiments of the present invention are not limited thereto. According to the embodiment, fewer or more insulating layers (111) may be formed than those shown in the drawing. Additionally, for example, a core insulating layer (111c) located in the middle among the plurality of insulating layers (111) may be thicker than the insulating layers (111) stacked above and below it. The core insulating layer (111c) can improve the rigidity of the substrate and suppress bending of the substrate. The core insulating layer (111c) may be formed using, for example, a copper clad laminate (CCL), an unclad copper clad laminate (Unclad CCL), a glass substrate, or a ceramic substrate. According to the embodiment, the package substrate (110) may not include the core insulating layer (111c) (see embodiment of FIG. 11).

[0029] The redistribution layer (112) may include a metallic material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layer (112) may be provided as a plurality of redistribution layers (112) each disposed on a plurality of insulating layers (111). The plurality of redistribution layers (112) may be electrically connected to each other through redistribution vias (113). The number of layers of the redistribution layer (112) may be determined according to the number of layers of the insulating layers (111) and may include more or fewer layers than shown in the drawing.

[0030] The rewiring vias (113) are electrically connected to the rewiring layer (112) and may include signal vias, ground vias, and power vias. The rewiring vias (113) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each rewiring via (113) may have the form of a filled via in which the metallic material is filled inside the via hole, or a conformal via in which the metallic material is formed along the inner wall of the via hole. The rewiring vias (113) may be integrated with the rewiring layer (112), but embodiments of the present invention are not limited thereto.

[0032] Front pads (114) and rear pads (115) may be disposed on the front (S1) and rear (S2) of the base substrate (118), respectively. Additionally, connection pads (119) may be disposed on the rear (S2) of the base substrate (118).

[0033] Front pads (114) may be placed on the front surface (S1) of the base substrate (118) and may be used as landing pads to which a semiconductor chip (120) is connected. Front pads (114) may be electrically connected to a redistribution layer (112) through redistribution vias (113). Front pads (114) may include the same material as the redistribution layer (112). For example, they may include a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Front pads (114) may be placed to protrude on the front surface (S1) of the base substrate (118), but are not limited thereto. According to an embodiment, the front pads (114) may be formed such that their surface forms a co-plane with the front surface (S1) of the base substrate (118).

[0035] Referring to FIGS. 3a and 3b, rear pads (115) may be arranged in rows and columns on the rear surface (S2) of a base substrate (118) and may be used as landing pads to which passive components (160) are connected. The rear pads (115) may be electrically connected to a redistribution layer (112) through redistribution vias (113). The rear pads (115) may contain the same material as the redistribution layer (112). For example, they may contain a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0037] The rear pads (115) may include first rear pads (115A1) and second rear pads (115A2), which are classified according to the areas arranged in the mounting area (AR) where the passive element (160) is mounted. The mounting area (AR) where the passive element (160) is mounted may have first to fourth corners (C1, C2, C3, C4) corresponding to each corner (C) of the passive element (160) and first to fourth edges (E1, E2, E3, E4) connecting the first to fourth corners (C1, C2, C3, C4). The mounting area (AR) may include first areas (AR1) adjacent to each of the first to fourth corners (C1, C2, C3, C4), and second areas (AR2) other than the first areas (AR1). The second region (AR2) may be arranged to divide the first regions (AR1) into at least two groups. For example, if the mounting region (AR) is rectangular, the first regions (AR1) may include four regions adjacent to the first to fourth corners (E1, E2, E3, E4) of the mounting region (AR), and the second region (AR2) may be arranged in a cross shape to divide the first regions (AR1). Additionally, according to an embodiment, the first regions (AR1) may include two regions adjacent to the first to fourth corners (E1, E2, E3, E4) of the mounting region (AR).

[0038] At least one first rear pad (115A1) may be disposed in each of the first regions (AR1). Additionally, at least one first rear pad (115A1) adjacent to each of the first to fourth corners (C1, C2, C3, C4) may be disposed in each of the first regions (AR1). Second rear pads (115A2) may be disposed in the second region (AR2). The placement of the mounting region (AR), the first rear pads (115A1), and the second rear pads (115A2) will be described in detail later.

[0040] Referring again to FIGS. 1 and 2, the connection pads (119) may be placed on the rear surface (S2) of the base substrate (118) and may be used as landing pads to which the connection bumps (170) are connected. The connection pads (119) may be electrically connected to the redistribution layer (112) through redistribution vias (113). The connection pads (119) may contain the same material as the redistribution layer (112). For example, they may contain a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. According to an embodiment, the width of the connection pads (119) may be greater than the width of the rear pads (115). Also, according to an embodiment, the pitch of the connection pads (119) may be greater than the pitch of the rear pads (115). Additionally, according to the embodiment, the lower surface of the connection pads (119) and the lower surface of the lowest insulating layer (111b) (i.e., the rear surface (S2) of the base substrate (118)) may be positioned at different levels. For example, the lower surface of the connection pads (119) may be positioned at a lower level protruding from the rear surface (S2) of the base substrate (118), and the lower surface of the rear pads (115) may be positioned at the same level as the rear surface (S2) of the base substrate (118). However, this is not limited thereto. According to the embodiment, the rear pads (115) may be positioned to protrude from the rear surface (S2) of the base substrate (118), and the lower surface of the connection pads (119) may be positioned at the same level as the rear surface (S2) of the base substrate (118).

[0042] The front protective layer (116) and the rear protective layer (117) may be positioned to cover the front (S1) and rear (S2) of the base substrate (118), respectively. The front protective layer (116) and the rear protective layer (117) may cover the redistribution layer (112) to protect it from external physical / chemical damage. The front protective layer (116) and the rear protective layer (117) may include a solder resist material or a photo solder resist material.

[0043] In the front protective layer (116), front openings (FO) can be formed so that the front pads (114) are exposed on the bottom surface.

[0044] In the rear protective layer (117), first rear openings (BOa1) and second rear openings (BOa2) may be formed so that rear pads (115) are exposed to the bottom surface. Additionally, in the rear protective layer (117), third rear openings (BOb) may be formed so that connecting pads (119) are exposed to the bottom surface.

[0045] Referring to FIG. 3b, the first rear openings (BOa1) and the second rear opening (BOa2) in which the rear pads (115) are exposed on the bottom surface are described in detail.

[0046] First rear openings (BOa1) are each positioned in the first regions (AR1) of the mounting area (AR), and first rear pads (115A1) may be exposed on the bottom surface of each first rear opening (BOa1). That is, each first rear opening (BOa1) may be positioned to correspond to one of the first rear pads (115A1) so as to individually expose the first rear pads (115A1). The width of the first rear openings (BOa1) may be formed to be smaller than the width of the first rear pads (115A1). According to an embodiment, the width of the first rear openings (BOa1) may be substantially the same as the width of the first rear pads (115A1).

[0047] At least one first rear opening (BOa1) may be disposed in each of the first regions (AR1) of the mounting area (AR). This one first rear opening (BOa1) may be disposed adjacent to each corner (C1, C2, C3, C4) of each of the first regions (AR1). The first rear openings (BOa1) may be disposed symmetrically on the mounting area (AR). For example, an equal number of first rear openings (BOa1) may be disposed in each of the first regions (AR1) and may be disposed symmetrically in the X-axis and Y-axis directions with respect to the center of the mounting area (AR).

[0048] The first rear openings (BOa1) can prevent the passive element (160) from tilting or shifting during the process of mounting the passive element (160). Since one of the first rear openings (BOa1) is positioned to fill the bottom surface of each first rear opening (BOa1), the lowest insulating layer (111b) forming the back surface (S2) of the base substrate (118) may not be exposed to the bottom surface of the rear openings (BOa1). Therefore, during the process of mounting the passive element (160), the solder filling the first rear openings (BOa1) can be supported by the side walls of the first rear openings (BOa1). Accordingly, the solder filled in the first rear openings (BOa1) is supported by the side walls of the first rear openings (BOa1) even when pressure is applied during the process of attaching the passive element (160), so the mounted passive element (160) can be stably supported. Therefore, during the process of mounting the passive element (160), the solder flowing due to the passive element (160) can be prevented from tilting or shifting the passive element (160).

[0050] The second rear opening (BOa2) may be positioned in the second region (AR2) of the mounting area (AR) with a shape corresponding to that of the second region (AR2). For example, the second rear opening (BOa2) may be formed in the remaining portion of the mounting area (AR) excluding the first regions (AR1). However, depending on the embodiment, the shape of the second rear opening (BOa2) may not be identical to that of the second region (AR2), may be formed smaller or larger by a predetermined size, or may be formed by dividing it into multiple regions. The second rear pads (115A2) and the lowest insulating layer (111b) forming the rear surface (S2) may be exposed on the bottom surface of the second rear opening (BOa2).

[0051] The second rear opening (BOa2) can provide a filling space for the underfill resin to be filled during the process of applying the underfill resin to form a sealant (166) that seals the mounted passive element (160). If the gap between the passive element (160) mounted in the mounting area (AR) and the rear protective layer (117) is very small, sufficient capillary force may not act on the underfill resin applied to form the sealant (166), and the underfill resin may not flow sufficiently into the lower part of the passive element (160). In this case, a void may occur in the lower part of the passive element (160), which may cause a problem in which a crack easily occurs in the sealant (166). The second rear opening (BOa2) increases the gap between the passive element (160) and the rear protective layer (117), allowing sufficient capillary force to act on the underfill resin applied to form the sealant (166). Thus, defects such as cracks in the sealant (166) caused by voids can be prevented.

[0052] In this way, the reliability of the mounted passive component (160) can be improved by the first rear openings (BOa1) and the second rear opening (BOa2) formed in the rear protective layer (117) of the semiconductor package (100) according to one embodiment.

[0054] A semiconductor chip (120) is placed on the front surface (S1) of a package substrate (110) and may include a connection pad (121) electrically connected to a redistribution layer (112). The semiconductor chip (120) may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs) and may form various types of integrated circuits. The integrated circuit may be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, but is not limited thereto; it may also be a logic chip such as an analog-to-digital converter or an ASIC (application-specific IC), or a memory chip such as a volatile memory (e.g., DRAM) or a non-volatile memory (e.g., ROM and flash memory). For example, the semiconductor chip (120) may be mounted on the package substrate (110) in a flip-chip manner. The semiconductor chip (120) may be connected to the front pads (114) via metal bumps in the form of balls or posts. For example, the semiconductor chip (120) may be electrically connected to the front pads (114) via solder bumps (125), but is not limited thereto. According to an embodiment, the semiconductor chip (120) may be directly connected to the front pads (114) or the rewiring vias (113) without separate bumps, or may be mounted on the package substrate (110) by wire bonding. The connection pad (121) may be a pad of the bare chip (e.g., an aluminum (Al) pad), but according to an embodiment, it may be a pad of the packaged chip (e.g., a copper (Cu) pad).

[0056] The sealing material (150) can seal at least a portion of the semiconductor chip (120) on the front protective layer (116). The sealing material (150) may include, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg including an inorganic filler or / and glass fiber, ABF, FR-4, BT, EMC (Epoxy Molding Compound). The sealing material (150) may have a MUF (molded underfill) structure formed integrally with the underfill resin between the semiconductor chip (120) and the package substrate (110), but is not limited thereto. According to an embodiment, the sealing material (150) may have a CUF (capillary underfill) structure in which the underfill resin below the semiconductor chip (120) is separated.

[0058] A passive element (160) is placed in the mounting area (AR) of the rear protection layer (117) and may have a connection surface (160S1) facing the mounting area (AR) and having a connection terminal (161) placed thereon, a non-connection surface (160S2) located opposite the connection surface (160S1), and a side surface (160S3) between the connection surface (160S1) and the non-connection surface (160S2). Here, the "non-connection surface" may refer to a surface located opposite the surface facing the package substrate (110) and exposed to the outside of the semiconductor package. The passive element (160) may include, for example, a capacitor, an inductor, beads, etc. For example, the passive element (160) may be a chip-type silicon (Si) capacitor having high electrical capacitance. The passive component (160) may include a connection terminal (161) and a connecting member (165) that electrically connects the connection terminal (161) to the rear pads (115). For example, the connecting member (165) may include a pillar portion (162) that contacts the connection terminal (161) and a solder portion (163) that connects the pillar portion (162) to the rear pads (115).

[0060] The sealant (166) may include an insulating resin similar to the sealant (150), for example, EMC. The sealant (166) is spaced apart from the connection bump (170) and can electrically insulate the passive element (160) and the connection bump (170) from each other. The sealant (166) covers the entire connection surface (160S1) of the passive element (160) and may cover at least a portion of the side surface (160S3).

[0062] A connection bump (170) is positioned adjacent to a passive component (160) on the rear surface (S2) of a package substrate (110) and can be electrically connected to a redistribution layer (112). The connection bump (170) can physically and / or electrically connect the semiconductor package (100) to an external device. The connection bump (170) comprises a conductive material and may have the form of a ball, pin, or lead. For example, the connection bump (170) may be a solder ball. The connection bump (170) may have a height (H1) greater than the height (H2) at which the passive component (160) is mounted in a direction perpendicular to the rear protective layer (117).

[0064] Referring to FIGS. 4 to 10, variations of a package substrate that can be employed in a semiconductor package are described. FIGS. 4 to 10 are variations of the package substrate shown in FIG. 3b. The variations of FIGS. 4 to 10 may have a structure substantially identical or similar to the package substrate (110) of FIG. 3b, and identical or similar components are indicated by identical or similar reference numerals, and repeated descriptions of identical components may be omitted.

[0066] Referring to FIG. 4, the package substrate (110A) of one embodiment has a difference from the previously described embodiment in that the number of first rear openings (BOa1) each disposed in the first regions (AR1) is increased. In the package substrate (110) of one embodiment, the area of ​​the second rear opening (BOa2a) is reduced so that the filling space for the underfill resin is reduced, but the number of first rear openings (BOa1) each included in the first regions (AR1) is increased so that the effect of preventing the passive element (160) from tilting or shifting can be improved.

[0068] Referring to FIG. 5, the package substrate (110B) of one embodiment has a difference from the previously described embodiment in that the first regions (AR1) are extended to each contact the two corners of the mounting region (AR). For example, two first regions (AR1) may be arranged and placed on both sides of the second region (AR2). Similar to the embodiment of FIG. 4, the area of ​​the second rear opening (BOa2b) is reduced so that the filling space for the underfill resin is reduced, but the number of first rear openings (BOa1) included in the first regions (AR1) is increased so that the effect of preventing the passive element (160) from tilting or shifting can be improved.

[0070] Referring to FIG. 6, the package substrate (110C) of one embodiment differs from the previously described embodiment in that the second rear opening (BOa2c) has an area (AR3) that extends outward from the mounting area (AR). The extended area (AR3) can be used as an injection port for injecting an underfill resin applied to form a sealant (166). Both ends (RC) of the extended area (AR3) are formed as curved surfaces so that the injected underfill resin can flow smoothly without stagnating at the sidewalls of the extended area (AR3) and be injected into the second rear opening (BOa2c).

[0072] Referring to FIG. 7a, the package substrate (110D) of one embodiment differs from the previously described embodiment in that the side (AR1S) of the first regions (AR1) is formed as a curved surface. If a corner is formed on the side (AR1S) of the first regions (AR1), the underfill resin applied to form the sealant (166) may be stagnated at the corner area of ​​the side (AR1S). In the package substrate (110D) of one embodiment, the side (AR1S) of the first regions (AR1) is formed as a curved surface so that the underfill resin can flow easily without being stagnated into the second rear opening (BOa2d).

[0073] Referring to FIG. 7b, the package substrate (110E) of one embodiment differs from the previously described embodiment in that the corners of the sides (AR1S') of the first regions (AR1) are chamfered. Thus, the package substrate (110E) of one embodiment, similar to the embodiment of FIG. 7a described earlier, allows the underfill resin to flow easily without stagnating into the second rear opening (BOa2e).

[0074] Referring to FIG. 7c, the package substrate (110F) of one embodiment differs from the previously described embodiment in that the side (AR1S) of the first regions (AR1) is formed as a curved surface, and the second rear opening (BOa2f) has a region (AR3) that extends outward from the mounting region (AR). Accordingly, the package substrate (110F) of one embodiment, similar to the embodiment of FIG. 7a described earlier, allows the underfill resin to flow easily without stagnating into the second rear opening (BOa2f).

[0076] Referring to FIG. 8, the package substrate (110G) of one embodiment has a difference from the previously described embodiment in that the width (d1) of the first rear pads (115A1') placed in the first regions (AR1) is increased compared to the width (d2) of the second rear pads (115A2). Since the width (d1) of the first rear pads (115A1') is increased, the width of the first rear openings (BOa1g) can also be increased. Accordingly, the area of ​​the first rear openings (BOa1g) in the first regions (AR1) is increased, thereby enhancing the effect of preventing defects in which the passive element (160) tilts or shifts.

[0078] Referring to FIG. 9, the package substrate (110H) of one embodiment differs from the previously described embodiment in that the first regions (AR1) are arranged in a triangular shape. The sides of the first regions (AR1) are formed only as flat surfaces without corners, so that the underfill resin can flow easily without stagnating into the second rear opening (BOa2h).

[0080] Referring to FIG. 10, the package substrate (110I) of one embodiment differs from the previously described embodiment in that the second rear opening (BOa2i) has an area (AR3) that extends outward from the mounting area (AR). Accordingly, the second rear opening (BOa2i) can be positioned to surround the perimeter of the first areas (AR1). Since an area where underfill resin can be filled is formed around the perimeter of the first areas (AR1), the underfill resin can be effectively injected into each corner of the mounting area (AR), along with the effect of preventing defects such as tilting or shifting of the passive component (160).

[0082] Referring to FIGS. 11 and 12, a semiconductor package according to one embodiment is described. The embodiments of FIGS. 11 and 12 may have a structure substantially identical or similar to the semiconductor package (100) of FIG. 1, and identical or similar components are indicated by identical or similar reference numerals, and a repeated description of identical components may be omitted.

[0084] FIG. 11 is a cross-sectional view illustrating a semiconductor package (100A) according to an embodiment of the present invention. Referring to FIG. 11, in the semiconductor package (100A) of an embodiment, a connection pad (121) and redistribution vias (113) can be directly connected between a semiconductor chip (120) and a package substrate (110) without a separate connecting member, for example, a solder bump (125) of FIG. 1. This structure can be implemented by sealing the semiconductor chip (120) using a sealing material (150) on a temporary carrier, and then forming insulating layers (111), a redistribution layer (112), and redistribution vias (113) directly on the lower surface of the semiconductor chip (120) from which the temporary carrier has been removed and the sealing material (150). Accordingly, the connection pad (121) of the semiconductor chip (120) can come into direct contact with the redistribution vias (113), and the redistribution vias (113) may have a tapered shape on the side so that the width narrows toward the front (S1) of the base substrate (118). According to the present embodiment, the overall thickness of the semiconductor package (100A) can be reduced, and the connection reliability between the semiconductor chip (120) and the redistribution layer (112) or the redistribution vias (113) can be improved.

[0086] FIG. 12 is a cross-sectional view illustrating a semiconductor package (1000) according to an embodiment of the present invention. Referring to FIG. 12, the semiconductor package (1000) of an embodiment may include a first semiconductor package (100B) and a second semiconductor package (200). The first semiconductor package (100B) may be understood to have the same or similar features as the semiconductor package (100) described with reference to FIG. 1 to FIG. 3a, except that it further includes an interposer substrate (130) and a connection structure (140).

[0087] The interposer substrate (130) is a redistribution substrate that provides a redistribution layer on the upper or rear side of the first semiconductor package (100B) and may be located between the lower package and the upper package in a package-on-package structure. The interposer substrate (130) is disposed on the semiconductor chip (120) and may include an upper insulating layer (131), an upper wiring layer (132), and wiring vias (133). Since the upper insulating layer (131), the upper wiring layer (132), and the wiring vias (133) have the same or similar characteristics as the insulating layers (111), the redistribution layer (112), and the redistribution vias (113) of the package substrate (110) described above, a redundant description is omitted. The upper insulating layer (131) may also be provided as a plurality of insulating layers. The uppermost upper insulating layer (131) may include openings that expose at least a portion of the upper wiring layer (132).

[0088] A connecting structure (140) is positioned between a package substrate (110) and an interposer substrate (130) to electrically connect the package substrate (110) and the interposer substrate (130). The connecting structure (140) extends in a vertical direction (Z-axis direction) between the package substrate (110) and the interposer substrate (130) to provide a vertical connecting path that electrically connects the redistribution layer (112) and the upper wiring layer (132). The connecting structure (140) may have a spherical or ball shape made of a low-melting point metal such as, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or an alloy containing these (e.g., Sn-Ag-Cu). According to an embodiment, a core ball made of a polymer material including a thermoplastic resin or a thermosetting resin, or a metal material distinct from solder, may be disposed inside the connecting structure (140).

[0089] The second semiconductor package (200) may include a rewiring substrate (210), a second semiconductor chip (220), and a second sealing material (230). The rewiring substrate (210) may include a lower pad (211) and an upper pad (212) on the lower surface and the upper surface, respectively, which can be electrically connected to the outside. Additionally, the rewiring substrate (210) may include a rewiring circuit (213) that electrically connects the lower pad (211) and the upper pad (212).

[0090] The second semiconductor chip (220) may be mounted on the redistribution substrate (210) by wire bonding or flip-chip bonding. For example, a plurality of second semiconductor chips (220) may be stacked vertically on the redistribution substrate (210) and electrically connected to the upper pad (212) of the redistribution substrate (210) by a bonding wire (WB). For example, the second semiconductor chip (220) may include a memory chip, and the first semiconductor chip (120) of the first semiconductor package (100B) may include an AP chip.

[0091] The second sealing material (230) may include a material identical or similar to the sealing material (150) of the first semiconductor package (100B). The second semiconductor package (200) may be physically and electrically connected to the first semiconductor package (100B) by a metal bump (260). The metal bump (260) may be electrically connected to a redistribution circuit (213) inside the redistribution board (210) through a lower pad (211) of the redistribution board (210). The metal bump (260) may include a low-melting point metal, for example, tin (Sn) or an alloy containing tin (Sn).

[0093] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0095] 100: Semiconductor package 110: Package substrate 120: Semiconductor chip 130: Interposer board 140: Link structure 150: Suture material 160: Passive component 170: Connection bump

Claims

Claim 1 A package substrate comprising: a base substrate having a front surface and a rear surface opposite to each other and including a redistribution layer; front pads disposed on the front surface and electrically connected to the redistribution layer; rear pads disposed on the rear surface and electrically connected to the redistribution layer; a front protective layer having front openings that expose each of the front pads on the front surface; and a rear protective layer having a mounting area disposed on the rear surface having first rear openings that expose each of the first rear pads among the rear pads and a second rear opening that exposes a portion of the rear surface and the second rear pads among the rear pads; a semiconductor chip disposed on the front protective layer and connected to the front pads; a passive component disposed on the mounting area of ​​the rear protective layer and connected to the rear pads; and connection bumps disposed adjacent to the passive component on the rear surface and electrically connected to the redistribution layer. A semiconductor package comprising a sealing material spaced apart from the connection bumps, covering a portion of the passive element, and extending into the second rear opening, wherein four of the first rear openings are each positioned adjacent to each corner of the mounting area, and the second rear opening is positioned to divide the four first rear openings into at least two groups, and the first rear pads and the second rear pads are positioned within the mounting area. Claim 2 A semiconductor package according to claim 1, wherein the mounting area comprises: first areas adjacent to each corner and each including at least one of the four first rear openings; and a second area dividing the first areas and corresponding to the second rear opening. Claim 3 In paragraph 2, the first regions are semiconductor packages having the same shape as each other. Claim 4 In claim 1, the passive element is a semiconductor package having a connection surface facing the mounting area and having a connection terminal disposed thereon, a non-connection surface located opposite the connection surface, and sides located between the connection surface and the non-connection surface. Claim 5 In paragraph 4, the mounting area has first to fourth corners connecting each of the corners, and the first to fourth corners correspond to the sides of the passive element, respectively, in a semiconductor package. Claim 6 In claim 5, the semiconductor package having a side that overlaps with at least two of the first to fourth corners, wherein the second rear opening is a second rear opening. Claim 7 In claim 5, the second rear opening further includes an area extended outwardly to at least one of the first to fourth corners of the mounting area, and the sealant is a semiconductor package extended into the extended area. Claim 8 In claim 7, the extended region is a semiconductor package that encloses the first to fourth corners of the mounting region. Claim 9 In claim 4, the passive element further comprises a connecting member that electrically connects the connection terminal and the rear pads, and the connecting member comprises a pillar portion in contact with the connection terminal and a solder portion connecting the pillar portion and the rear pads, forming a semiconductor package. Claim 10 A semiconductor package according to claim 1, further comprising: connection pads disposed on the rear surface to correspond to each of the connection bumps and electrically connected to the redistribution layer; and connection openings that expose each of the connection pads on the rear surface, wherein each of the connection bumps is connected to the connection pads through the connection openings. Claim 11 In claim 10, the above connection pads are a semiconductor package having a width greater than the width of the above rear pads. Claim 12 In claim 10, the above connection pads are placed at a different level from the above rear pads in a semiconductor package. Claim 13 In claim 1, the above-mentioned rear pads are arranged in rows and columns, and each is a semiconductor package of the same size. Claim 14 In claim 1, the passive element is a semiconductor package including a capacitor. Claim 15 In claim 1, the passive element is a semiconductor package having a maximum height smaller than the maximum height of the connection bump in a direction perpendicular to the rear surface. Claim 16 A semiconductor package according to claim 1, further comprising a sealing material that seals at least a portion of the semiconductor chip on the front protective layer. Claim 17 A package substrate comprising: a base substrate including a redistribution layer; pads disposed on one surface of the base substrate and electrically connected to the redistribution layer; a protective layer having a mounting area disposed therein, wherein first openings each exposing first pads among the pads on the one surface of the base substrate and second openings exposing second pads among the pads and a portion of the one surface are disposed therein; a semiconductor chip disposed on the mounting area of ​​the protective layer and electrically connected to the pads through the first openings and the second openings; and a sealant covering a portion of the semiconductor chip and extending into the second openings, wherein four of the first openings are each disposed adjacent to each corner of the mounting area, and the second openings are disposed to divide the four first openings into at least two groups. Claim 18 In claim 17, the semiconductor chip is a semiconductor package including a silicon capacitor (Si capacitor). Claim 19 A package substrate comprising a plurality of insulating layers and redistribution layers disposed within the plurality of insulating layers, having a front surface and a rear surface opposite to each other, front pads disposed on the front surface and electrically connected to the redistribution layers, rear pads disposed on the rear surface and electrically connected to the redistribution layers, a front protective layer having front openings that expose each of the front pads on the front surface, and a rear protective layer having a mounting area disposed therein having first rear openings that expose each of the first rear pads among the rear pads and a second rear opening that exposes a portion of the rear surface and the second rear pads among the rear pads, wherein four of the first rear openings are disposed adjacent to each corner of the mounting area, and the second rear opening is disposed to divide the four rear openings into at least two groups, and the first rear pads and the second rear pads are disposed within the mounting area. Claim 20 A package substrate according to claim 19, wherein the uppermost insulating layer among the plurality of insulating layers provides the front surface, and the lowermost insulating layer among the plurality of insulating layers provides the rear surface.

Images