Semiconductor device

Abstract

A semiconductor device according to exemplary embodiments comprises a substrate including an active region, a wordline structure extending in a first horizontal direction, a bitline structure extending in a second horizontal direction intersecting the first horizontal direction on the substrate, a bitline contact pattern electrically connecting a first impurity region of the active region and the bitline structure, a storage node contact disposed on a sidewall of the bitline structure and electrically connected to a second impurity region of the active region, a spacer structure on a sidewall of the bitline structure and the bitline contact pattern, and a capacitor structure electrically connected to the storage node contact, wherein the bitline contact pattern comprises a lower portion and an upper portion having a width smaller than that of the lower portion in the first horizontal direction, and the spacer structure comprises a lower spacer structure surrounding the side of the lower portion, and an upper spacer structure disposed on the side of the upper portion and the sidewall of the bitline structure on the lower spacer structure, and the upper end of the lower spacer structure is located at a level substantially equal to or lower than the lower end of the storage node contact.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] Driven by the advancement of the electronics industry and user demands, electronic devices are becoming smaller and higher-performing. Consequently, semiconductor devices used in these devices are also required to be highly integrated and high-performing. To manufacture high-performance semiconductor devices, technology is required to form spacer structures optimized for separating adjacent conductive structures.

[0004] delete Prior art literature

[65535] Published Patent Application No. 10-2014-0052225 The problem to be solved

[0005] One of the technical problems according to the embodiments of the present invention is to provide a semiconductor device with improved electrical characteristics. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises a substrate including an active region, a wordline structure extending in a first horizontal direction, a bitline structure extending in a second horizontal direction intersecting the first horizontal direction on the substrate, a bitline contact pattern electrically connecting a first impurity region of the active region and the bitline structure, a storage node contact disposed on a sidewall of the bitline structure and electrically connected to a second impurity region of the active region, a spacer structure on the sidewall of the bitline structure and the bitline contact pattern, and a capacitor structure electrically connected to the storage node contact, wherein the bitline contact pattern comprises a lower portion and an upper portion having a width smaller than that of the lower portion in the first horizontal direction, and the spacer structure comprises a lower spacer structure surrounding the side of the lower portion, and an upper spacer structure disposed on the side of the upper portion and the sidewall of the bitline structure on the lower spacer structure, and the upper end of the lower spacer structure may be located at a level substantially equal to or lower than the lower end of the storage node contact.

[0009] A semiconductor device according to exemplary embodiments comprises: a substrate including an active region; a wordline structure extending in a first horizontal direction within the substrate; a plurality of conductive pads disposed on the substrate; an insulating pattern separating each of the plurality of conductive pads; a bitline structure extending in a second horizontal direction intersecting the first horizontal direction on the plurality of conductive pads and the insulating pattern; a bitline contact pattern electrically connecting a first impurity region of the active region and the bitline structure; a storage node contact disposed on a sidewall of the bitline structure and electrically connected to a second impurity region of the active region by contacting the plurality of conductive pads; a spacer structure on the sidewall of the bitline structure and the bitline contact pattern; and a capacitor structure electrically connected to the storage node contact, wherein the spacer structure comprises a lower spacer structure covering a portion of the side of the bitline contact pattern and an upper spacer structure between the storage node contact and the bitline structure, and the upper end of the lower spacer structure is located at a level lower than the upper surface of the plurality of conductive pads.

[0011] A semiconductor device according to exemplary embodiments comprises a plurality of conductive pads formed on a substrate, an insulating pattern that separates each of the plurality of conductive pads by penetrating the plurality of conductive pads, a barrier pattern on the plurality of conductive pads and the insulating pattern, a bitline contact pattern that is electrically connected to the substrate by penetrating the plurality of conductive pads and the insulating pattern on the substrate, a storage node contact that contacts the plurality of conductive pads, a lower spacer structure that separates the bitline contact pattern and the plurality of conductive pads, and an upper spacer structure that separates the bitline contact pattern and the storage node contact, wherein the upper end of the lower spacer structure is located at a level lower than the upper surface of the plurality of conductive pads. Effects of the invention

[0013] By optimizing the structure of the spacer structure, a semiconductor device with improved electrical characteristics can be provided.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 3 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 4 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 5 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 10a to 10k are schematic cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0017] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0019] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments.

[0020] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 2 shows a cross-section along the cutting lines I-I' and II-II' of FIG. 1.

[0021] FIG. 3 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 3 illustrates an enlarged view of region 'A' of FIG. 2.

[0023] Referring to FIGS. 1 to 3, a semiconductor device (100) may include a substrate (101) including an active region (ACT), a wordline structure (WLS) embedded and extended within the substrate (101) and including a wordline (WL), a bitline structure (BLS) extending across the wordline structure (WLS) on the substrate (101) and including a bitline (BL), spacer structures (SS) on both sides of the bitline structure (BLS), a capacitor structure (CAP) disposed on top of the bitline structure (BLS), a bitline contact pattern (DC) electrically connecting the bitline structure (BLS) and the active region (ACT), a storage node contact (160) electrically connecting the capacitor structure (CAP) and the active region (ACT), a landing pad (LP) electrically connecting the storage node contact (160) and the capacitor structures (CAP), and a capping insulating layer (180) on the bitline structures (BLS). The semiconductor device (100) may further include device isolation layers (110) defining an active region (ACT), a barrier pattern (130) on a substrate (101), a metal-semiconductor layer (165) on a storage node contact (160), and insulation patterns between bitline structures (BLS). The semiconductor device (100) may be applied, for example, to a cell array of Dynamic Random Access Memory (DRAM), but is not limited thereto.

[0025] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0027] The active region (ACT) may be defined by device isolation layers (110). The active region (ACT) may be in the form of a bar and may be arranged in an island shape extending in one direction, e.g., in the w direction, within the substrate (101). The w direction may be a direction inclined with respect to the extension direction of the word line (WL) and the bit line (BL). The active region (ACT) may intersect with the bit line structure (BLS) and / or the word line structure (WLS).

[0028] The active region (ACT) may have first and second impurity regions (105a, 105b) at a predetermined depth from the upper surface of the substrate (101). The first and second impurity regions (105a, 105b) may be spaced apart from each other. The first and second impurity regions (105a, 105b) may serve as source / drain regions of the transistor. For example, a drain region may be formed between two word lines (WL) crossing one active region (ACT), and a source region may be formed outside of the two word lines (WL). The source region and the drain region are formed by the first and second impurity regions (105a, 105b) formed by doping or ion implanting substantially the same impurities, and may be referred to interchangeably depending on the circuit configuration of the transistor to be finally formed. The above impurities may include dopants having a conductivity type opposite to that of the substrate (101). In exemplary embodiments, the depths of the first and second impurity regions (105a, 105b) in the source region and the drain region may differ from each other.

[0030] The device isolation layers (110) can be formed by a shallow trench isolation (STI) process. The device isolation layers (110) may be field regions that surround active regions (ACTs) and separate them from each other. The device isolation layers (110) may be made of an insulating material, for example, an oxide, a nitride, or a combination thereof. In an exemplary embodiment, each of the device isolation layers (110) may include a plurality of layers.

[0032] Each wordline structure (WLS) may include a gate dielectric layer (120), a wordline (WL), and a buried insulating layer (125).

[0033] Word lines (WL) may be placed within gate trenches extending within the substrate (101). Word lines (WL) may be placed to extend in one direction, e.g., in the x-direction, across an active region (ACT) within the substrate (101). For example, a pair of word lines (WL) may be placed to cross one active region (ACT). Transistors comprising word lines (WL) and first and second impurity regions (105a, 105b) may constitute a buried channel array transistor (BCAT), but are not limited thereto.

[0034] The word line (WL) may be disposed with a predetermined thickness below the gate trenches. The upper surface of the word line (WL) may be located at a lower level than the upper surface of the substrate (101). As used herein, the high and low of the term “level” may be defined with respect to the substantially flat upper surface of the substrate (101). The word line (WL) may comprise at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In exemplary embodiments, the word line (WL) may comprise a plurality of layers.

[0035] A gate dielectric layer (120) may be disposed on the bottom and inner surfaces of the gate trenches. The gate dielectric layer (120) may conformally cover the inner walls of the gate trenches. The gate dielectric layer (120) may be disposed between the word line (WL) and the active region (ACT). The gate dielectric layer (120) may comprise at least one of an oxide, a nitride, and an oxynitride. The gate dielectric layer (120) may be, for example, a silicon oxide film or an insulating film having a high dielectric constant. In exemplary embodiments, the gate dielectric layer (120) may be a layer formed by oxidizing the active region (ACT) or a layer formed by deposition.

[0036] The buried insulating layer (125) may be placed on the word line (WL) and fill the gate trenches. The buried insulating layer (125) may include an insulating material, for example, silicon nitride.

[0038] In an exemplary embodiment, the semiconductor device (100) may include a plurality of conductive pads (171) disposed on a substrate (101) and an insulating pattern (172) separating each of the plurality of conductive pads (171). Each of the plurality of conductive pads (171) may be electrically connected to an active region (ACT). The lower surface of the plurality of conductive pads (171) may be in direct contact with the upper surface of the active region (ACT). Each of the plurality of conductive pads (171) may be electrically connected to a storage node contact (160) and a second impurity region (105b). The plurality of conductive pads (171) may comprise silicon having an N-type conductivity. For example, the plurality of conductive pads (171) may comprise single-crystal silicon formed by Selective Epitaxial Grown (SEG). In another example, the plurality of conductive pads (171) may comprise polysilicon. An insulating pattern (172) may surround each of the conductive pads (171) between the plurality of conductive pads (171). The insulating pattern (172) may penetrate the plurality of conductive pads (171) to achieve electrical isolation of each of the plurality of conductive pads (171). The insulating pattern (172) may include an insulating material different from the device isolation layers (110). The insulating material may be, for example, silicon nitride. In an exemplary embodiment, the insulating pattern (172) may be recessed deeper than the lower surface of the plurality of conductive pads (171) to have a lower surface at a level lower than the lower surface of the plurality of conductive pads (171), but is not limited thereto. The upper surface of the plurality of conductive pads (171) and the upper surface of the insulating pattern (172) may be located at substantially the same level. However, depending on the embodiment, the plurality of conductive pads (171) and the insulating pattern (172) may be omitted.

[0040] A barrier pattern (130) may be disposed on a substrate (101). A barrier pattern (130) may be disposed between the substrate (101) and a bitline structure (BLS). In an exemplary embodiment, a barrier pattern (130) may be disposed on a plurality of conductive pads (171) and an insulating pattern (172). In this case, the lower surface of the barrier pattern (130) may be in contact with the upper surface of the plurality of conductive pads (171) and the insulating pattern (172). A storage node contact (160) may penetrate the barrier pattern (130) and be electrically connected to an active region (ACT). A storage node contact (160) may penetrate the barrier pattern (130) and be in contact with a plurality of conductive pads (171). The barrier pattern (130) may comprise an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0041] In an exemplary embodiment, the barrier pattern (130) may include a first barrier pattern (130a), a second barrier pattern (130b), and a third barrier pattern (130c). For example, the first barrier pattern (130a) may include silicon oxide, the second barrier pattern (130b) may include silicon nitride, and the third barrier pattern (130c) may include silicon oxide. However, depending on the embodiment, the barrier pattern (130) may have a varying number of layers or include other materials, unlike the three layers shown in the drawing.

[0043] The bitline structure (BLS) may be extended in one direction, for example, in the y direction, perpendicular to the wordline (WL). The bitline structure (BLS) may include a bitline (BL) and a bitline capping pattern (BC) on the bitline.

[0045] A bitline (BL) may include a first conductive pattern (141), a second conductive pattern (142), and a third conductive pattern (143) stacked in sequence. A bitline capping pattern (BC) may be placed on the third conductive pattern (143). A barrier pattern (130) may be placed between the first conductive pattern (141) and the substrate (101). The first conductive pattern (141) may be in contact with the barrier pattern (130) on the barrier pattern (130). The first conductive pattern (141) may include a semiconductor material such as polycrystalline silicon. The second conductive pattern (142) may include a metal-semiconductor compound. The metal-semiconductor compound may be, for example, a layer in which a portion of the first conductive pattern (141) has been silicided. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern (143) may include metallic materials such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The number of conductive patterns forming the bitline (BL), the types of materials, and / or the stacking order may vary depending on the embodiments.

[0047] The bitline capping pattern (BC) may include a first capping pattern, a second capping pattern, and a third capping pattern stacked sequentially on the third conductive pattern (143). The first to third capping patterns may each include an insulating material, for example, a silicon nitride film. The first to third capping patterns may be made of different materials, and even if they include the same material, the boundaries may be distinguished by differences in physical properties. The thickness of the second capping pattern may be smaller than the thickness of the first capping pattern and the thickness of the third capping pattern, respectively. The number of capping patterns and / or the types of materials forming the bitline capping pattern (BC) may vary depending on the embodiments.

[0049] The bitline contact pattern (DC) has an upper surface at substantially the same level as the first conductive pattern (141) and can contact the second conductive pattern (142). The bitline contact pattern (DC) can penetrate the barrier pattern (130) and contact the first impurity region (105a) of the active region (ACT). The bitline (BL) can be electrically connected to the first impurity region (105a) through the bitline contact pattern (DC). The lower surface of the bitline contact pattern (DC) can be located at a lower level than the upper surface of the substrate (101) and at a higher level than the upper surface of the wordline (WL).

[0050] In an exemplary embodiment, the bitline contact pattern (DC) may be spaced apart from a plurality of conductive pads (171) and storage node contacts (160) by spacer structures (SS).

[0051] In an exemplary embodiment, the bitline contact pattern (DC) may include a lower portion (DC_LP) having a first width in the x direction and an upper portion (DC_UP) disposed on the lower portion (DC_LP) and having a second width smaller than the first width. In this specification, 'width' may mean the maximum width of the portion or the average width. The lower portion (DC_LP) may be a portion of the bitline contact pattern (DC) that remains unetched during the process of forming the bitline contact pattern (DC) as the semiconductor device becomes highly integrated.

[0053] The spacer structures (SS) may include a lower spacer structure (LS) surrounding a portion of the side of the bitline contact pattern (DC), and an upper spacer structure (US) positioned on each side wall of the bitline structure (BLS) and extending in one direction, for example, in the y direction.

[0054] The lower spacer structure (LS) can separate the bitline contact pattern (DC) and the plurality of conductive pads (171).

[0055] The lower spacer structure (LS) may surround the side of the lower portion (DC_LP) of the bitline contact pattern (DC). The upper surface (LS_US) of the lower spacer structure (LS) may be located at a lower level than the upper surface of the plurality of conductive pads (171). In an exemplary embodiment, the upper surface (LS_US) of the lower spacer structure (LS) may be located at a higher level than the lower surface of the plurality of conductive pads (171). However, depending on the embodiments, the upper surface of the lower spacer structure (LS) may be located at a lower level than the lower surface of the plurality of conductive pads (171).

[0056] The lower spacer structure (LS) may have a portion extending along the side of the plurality of conductive pads (171) from between the lower portion (DC_LP) and the plurality of conductive pads (171). The extended portion of the lower spacer structure (LS) may be located at a higher level than the upper surface of the lower portion (DC_LP) of the bitline contact pattern (DC). Accordingly, the upper end of the lower spacer structure (LS) may be located at a higher level than the lower portion (DC_LP). In this specification, 'upper end' may refer to the portion located at the highest level among the components.

[0057] In an exemplary embodiment, the lower spacer structure (LS) may include a first lower spacer (151) surrounding a lower portion (DC_LP) and a second lower spacer (152) surrounding the outer surface of the first lower spacer (151).

[0058] The lower spacer structure (LS) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric material, or a combination thereof. In an exemplary embodiment, the first lower spacer (151) may include silicon oxide, and the second lower spacer (152) may include silicon nitride.

[0059] The upper spacer structure (US) can separate the storage node contact (160) and the bitline structure (BLS) on the lower spacer structure (LS).

[0060] An upper spacer structure (US) may be positioned to extend along the side walls of the bit line (BL) and the side walls of the bit line capping pattern (BC). A pair of upper spacer structures (US) positioned on both sides of a single bit line structure (BLS) may have an asymmetrical shape with respect to the bit line structure (BLS). The asymmetrical shape may be formed by a capping insulating layer (180).

[0061] In an exemplary embodiment, the lower spacer structure (LS) may be located at a level lower than the bottom of the storage node contact (160). Accordingly, the lower spacer structure (LS) may be spaced apart from the storage node contact (160). In this case, the upper spacer structure (US) may include a portion that extends between the spaced-apart spacer structure (LS) and the storage node contact (160) to space the lower spacer structure (LS) and the storage node contact (160). The upper spacer structure (US) may extend between the spaced-apart space to contact a plurality of conductive pads (171). The upper spacer structure (US) may cover the upper surface and a portion of the side of the lower spacer structure (LS) and the upper surface of the lower portion (DC_LP) of the bitline contact pattern (DC). The lower surface of the upper spacer structure (US) may be located at a higher level than the portion contacting the lower spacer structure (LS) and the portion contacting the bitline contact pattern (DC). This may be because the upper surface of the lower spacer structure (LS) is located at a higher level than the upper surface of the lower portion (DC_LP) of the bitline contact pattern (DC).

[0062] The upper spacer structure (US) may include an insulating material, for example, silicon oxide or silicon nitride. In an exemplary embodiment, the upper spacer structure (US) is shown as a single layer, but the material and the number of layers of the upper spacer structure (US) are not limited thereto and can be changed in various forms.

[0064] In an exemplary embodiment, the semiconductor device (100) may further include an insulating fence. The insulating fence may be spaced apart in one direction, for example, in the y direction, between a plurality of bitline structures (BLS). The insulating fence may overlap with wordline structures (WLS) in a planar view. The insulating fence may include, for example, silicon nitride.

[0066] The storage node contact (160) may be electrically connected to one area of ​​the active region (ACT), for example, the second impurity region (105b). In an exemplary embodiment, the storage node contact (160) may penetrate the barrier pattern (130) and contact a plurality of conductive pads (171), and may be electrically connected to the second impurity region (105b) through the plurality of conductive pads (171). The storage node contact (160) may electrically connect the capacitor structure (CAP) and the second impurity region (105b).

[0067] In an exemplary embodiment, there may be multiple storage node contacts (160). Each of the storage node contacts (160) may be positioned between adjacent bitline structures (BLS) along the x-direction in a planar view, as illustrated in FIG. 1, particularly between spacer structures (SS) on both sides of the bitline structures (BLS). In a planar view, each of the storage node contacts (160) may be positioned between wordline structures (WLS) and between bitline structures (BLS). Each of the storage node contacts (160) may fill the space defined by the adjacent bitline structures (BLS) in the x-direction and the insulating fence adjacent in the y-direction. The storage node contacts (160) may be arranged in columns and rows along the x-direction and y-direction.

[0068] The storage node contact (160) may be made of a conductive material and may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an exemplary embodiment, the storage node contact (160) may include a plurality of layers.

[0069] The bottom of the storage node contact (160) may be located at a higher level than the bottom of the bitline contact pattern (DC). The bottom of the storage node contact (160) may be located at a higher level than the lower spacer structure (LS). The storage node contact (160) may be insulated from the bitline contact pattern (DC) by the lower spacer structure (LS).

[0070] By partially removing the lower spacer structure (LS) through a separate process to relatively lower the height of the upper portion, the difficulty of the contact hole manufacturing process for forming the storage node contact (160) can be improved. This may be because the space required for the process increases by the amount of space secured by removing the lower spacer structure (LS). Accordingly, the storage node contact (160) can be stably formed even if the width between the plurality of conductive pads (171) and the bitline contact pattern (DC) becomes relatively narrow due to the high integration of the semiconductor device.

[0071] A semiconductor device with improved electrical characteristics and production yield can be provided by separating the storage node contact (160) and the bitline contact pattern (DC) while lowering the difficulty of the etching process for forming the storage node contact (160).

[0073] A metal-semiconductor layer (165) may be disposed between the storage node contact (160) and the landing pad (LP). The metal-semiconductor layer (165) may cover the upper surface of the storage node contact (160). The metal-semiconductor layer (165) may be, for example, a layer in which a portion of the storage node contact (160) has been silicided. For example, the metal-semiconductor layer (165) may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. Depending on the embodiments, the metal-semiconductor layer (165) may be omitted.

[0075] The landing pad (LP) can electrically connect the storage node contact (160) and the capacitor structure (CAP).

[0076] A landing pad (LP) may be positioned between a pair of bitline structures (BLS) and on a storage node contact (160). The landing pad (LP) may cover the upper surface of a metal-semiconductor layer (165). The landing pad (LP) may be in contact with the side walls of spacer structures (SS). In an exemplary embodiment, an upper spacer structure (US) may extend from between the bitline structure (BLS) and the storage node contact (160) to between the bitline structure (BLS) and the landing pad (LP). The landing pad (LP) may penetrate the capping insulating layer (180) and be in contact with the capping insulating layer (180).

[0077] In an exemplary embodiment, there may be multiple landing pads (LP), and the multiple landing pads (LP) may be arranged in a grid pattern forming a hexagon or a honeycomb shape. This arrangement of multiple landing pads (LP) may correspond to the arrangement of capacitor structures (CAP).

[0078] In an exemplary embodiment, the landing pad (LP) may have a double-layer structure comprising a conductive layer and a barrier layer covering the bottom surface and sides of the conductive layer. The conductive layer may comprise at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al), and the barrier layer may comprise at least one of a metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). However, the number of layers and the shape of the landing pad (LP) may be varied according to the embodiments.

[0080] A capping insulating layer (180) may be placed on a bitline structure (BLS). The capping insulating layer (180) may be placed in contact with the bitline structure (BLS), spacer structures (SS), and landing pad (LP). In an exemplary embodiment, the capping insulating layer (180) may be placed between a plurality of landing pads (LP). The capping insulating layer (180) may have a bottom end in contact with the top surface of the spacer structures (SS).

[0082] A capacitor structure (CAP) may be positioned on a bitline structure (BLS) to be in contact with a landing pad (LP). The capacitor structure (CAP) may include a lower electrode (192), a capacitor dielectric layer (194), and an upper electrode (196). The lower electrode (192) and the upper electrode (196) may include at least one of a doped semiconductor, a metal nitride, a metal, and a metal oxide. The lower electrode (192) and the upper electrode (196) may include, for example, at least one of polycrystalline silicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), and tungsten nitride (WN). The capacitor dielectric layer (194) may include, for example, at least one of a high dielectric constant material such as zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium oxide (Hf2O3). In FIG. 2, the capacitor structure (CAP) is shown in a pillar shape, but is not limited thereto and may have a cylinder shape.

[0084] FIG. 4 is a partial enlarged cross-sectional view of a semiconductor device (100a) according to exemplary embodiments.

[0085] Referring to FIG. 4, the upper surface (LS_US) of the lower spacer structure (LS) may be located at a higher level as it moves away from the bitline contact pattern (DC). Accordingly, the lower spacer structure (LS) may have an upper surface with an inclined shape in the area in contact with a plurality of conductive pads (171) and / or an insulating pattern (172).

[0086] In an exemplary embodiment, the upper surface (LS_US) of the lower spacer structure (LS) may have a concave shape. This may be a structure that occurs as a portion of the lower spacer structure (LS) isotropically etched and removed, with reference to FIG. 9e.

[0088] FIG. 5 is a partial enlarged cross-sectional view of a semiconductor device (100b) according to exemplary embodiments.

[0089] Referring to FIG. 5, the upper surface (LS_US) of the lower spacer structure (LS) may be located at a higher level as it moves away from the bitline contact pattern (DC). Accordingly, the lower spacer structure (LS) may have an upper surface with an inclined shape in the area in contact with a plurality of conductive pads (171) and / or an insulating pattern (172).

[0090] The upper surface (LS_US) of the lower spacer structure (LS) may have a convex shape, unlike in FIG. 4. This may be a structure that occurs as the corner portion of the lower spacer structure (LS) is etched and removed through a subsequent etching process such as FIG. 9h.

[0092] FIG. 6 is a partial enlarged cross-sectional view of a semiconductor device (100c) according to exemplary embodiments.

[0093] Referring to FIG. 6, the storage node contact (160) and the lower spacer structure (LS) may come into contact. This may be a structure that occurs when the hole for forming the storage node contact (160) is recessed relatively deeply, or alternatively, a structure that occurs when the top of the lower spacer structure (LS) is formed relatively high.

[0094] The top of the lower spacer structure (LS) may be located at substantially the same level as the bottom of the storage node contact (160). The storage node contact (160) may cover the top surface of the lower spacer structure (LS).

[0096] FIG. 7 is a partial enlarged cross-sectional view of a semiconductor device (100d) according to exemplary embodiments.

[0097] Referring to FIG. 7, the upper spacer structure (US) may include a first upper spacer (153) covering the bitline structure (BLS) and the lower spacer structure (LS), and a second upper spacer (154) covering the first upper spacer (153). The first upper spacer (153) has a thinner thickness than the second upper spacer (154) and may be conformally disposed on the side wall of the bitline structure (BLS). However, depending on the embodiments, the thickness of the first upper spacer (153) may be greater than the thickness of the second upper spacer (154). In an exemplary embodiment, the first upper spacer (153) may cover part of the upper surface and side of the lower spacer structure (LS), but may cover only part of the side of the lower spacer structure (LS) when the storage node contact (160) covers the upper surface of the lower spacer structure (LS) as shown in FIG. 6.

[0098] In an exemplary embodiment, the first and second upper spacers (153, 154) may include different insulating materials, for example, the first upper spacer (153) may include silicon oxide and the second upper spacer (154) may include silicon nitride. However, even if the first and second upper spacers (153, 154) include the same material, the boundary may be distinguished due to differences in the manufacturing process.

[0100] FIG. 8 is a partial enlarged cross-sectional view of a semiconductor device (100e) according to exemplary embodiments.

[0101] Referring to FIG. 8, the upper spacer structure (US) may include a first upper spacer (153) covering the bitline structure (BLS) and the lower spacer structure (LS), a third upper spacer (155) covering a portion of the first upper spacer (153), and a fourth upper spacer (156) on the third upper spacer (155). Since the first upper spacer (153) may have the same shape as described in FIG. 7, further description is omitted.

[0102] The third upper spacer (155) can fill a portion of the spaced-apart space between the first upper spacer (155) and the storage node contact (160). The third upper spacer (155) can have an upper surface substantially identical to the upper surface of the barrier pattern (130).

[0103] The fourth upper spacer (156) can fill the space between the storage node contact (160) and the bitline structure (BLS) on the third upper spacer (155). The third and fourth upper spacers (155, 156) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric material, or a combination thereof. The third and fourth upper spacers (155, 156) may include different insulating materials, but are not limited thereto and may include the same material. However, even in this case, the boundary where the third and fourth upper spacers (155, 156) come into contact with each other may be distinguished depending on the manufacturing process conditions.

[0105] FIG. 9 is a schematic cross-sectional view of a semiconductor device (100f) according to exemplary embodiments.

[0106] Referring to FIG. 9, the semiconductor device (100f) may not include a plurality of conductive pads (171) and an insulating pattern (172).

[0107] The barrier pattern (130) can contact the substrate (101) between the bitline structure (BLS) and the substrate (101). The storage node contact (160) can penetrate the barrier pattern (130) and make direct contact with the second impurity region (105b).

[0108] The bitline contact pattern (DC) may be spaced apart from the second impurity region (105b) and / or the storage node contact (160) by spacer structures (SS). The lower spacer structure (LS) may be located at a lower level than the bottom surface of the barrier pattern (130) or the bottom surface of the storage node contact (160).

[0109] As described in FIG. 2, the difficulty of the contact hole forming process for manufacturing the storage node contact (160) can be improved as the top of the lower spacer structure (LS) becomes relatively lower.

[0111] FIGS. 10a to 10k are schematic cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments.

[0113] Referring to FIG. 10a, device isolation layers (110) defining an active region (ACT) within a substrate (101) may be formed, a wordline structure (WLS) may be formed within the substrate (101), a plurality of conductive pads (171) and an insulating pattern (172) may be formed on the substrate (101), and a barrier pattern (130a, 130b, 130c) may be formed.

[0114] First, according to the shallow trench device isolation (STI) process, the substrate (101) is anisotropically etched to form trenches, and then insulating materials are deposited within the trenches, and a planarization process is performed to form device isolation layers (110). Before forming the device isolation layers (110), impurities may be injected into the substrate (101) to form impurity regions (105a, 105b). However, depending on the embodiments, the impurity regions (105a, 105b) may be formed after the formation of the device isolation layers (110) or at another process step.

[0115] Next, the substrate (101) can be anisotropically etched to form gate trenches in which word lines (WL) are disposed. The gate trenches extend in the x-direction and may cross the active region (ACT) and the device isolation layers (110). Within the gate trenches, a gate dielectric layer (120), word lines (WL), and a buried insulating layer (125) may be formed sequentially. The gate dielectric layer (120) may be formed to have a substantially uniform thickness on at least a portion of the inner walls of the gate trenches and on the bottom surface. The gate dielectric layer (120) may be formed by an oxidation process of the active region (ACT) or by a deposition process of a dielectric material. The word lines (WL) may be formed by depositing a conductive material within the gate trenches and recessing from the top to a predetermined depth. The buried insulating layer (125) can be formed by depositing an insulating material to fill the remainder of the gate trench and then performing a planarization process. This allows wordline structures (WLS) to be formed.

[0116] Next, a conductive material layer can be formed on a substrate (101), and a portion of the conductive material layer can be etched to form a trench penetrating the conductive material layer and a plurality of conductive pads (171). An insulating pattern (172) can be formed by filling the trench with an insulating material and performing a flattening process.

[0117] Next, first to third barrier patterns (130a, 130b, 130c) can be deposited sequentially on a plurality of conductive pads (171) and an insulating pattern (172). The first to third barrier patterns (130a, 130b, 130c) may include different insulating materials, for example, the first barrier pattern (130a) may be silicon oxide, the second barrier pattern (130b) may be silicon nitride, and the third barrier pattern (130c) may be silicon oxynitride, but are not limited thereto. That is, the number of layers, thickness, and material of the barrier patterns (130a, 130b, 130c) may be varied.

[0119] Referring to FIG. 10b, a first preliminary conductive layer (141') can be formed on the barrier pattern (130a, 130b, 130c) and a first opening (OP1) can be formed.

[0120] A first preliminary conductive layer (141') can be deposited on the barrier pattern (130a, 130b, 130c). The first preliminary conductive layer (141') may include, for example, polycrystalline silicon.

[0121] Next, a mask (M) is formed on the first preliminary conductive pattern (141'), and an etching process is performed using the mask to form a first opening (OP1) that penetrates the barrier pattern (130a, 130b, 130c), a plurality of conductive pads (171), and an insulating pattern (172). In an exemplary embodiment, the mask (M) may comprise silicon oxide. A portion of the substrate (101) may be exposed by the first opening (OP1).

[0123] Referring to FIG. 10c, first and second lower spacers (151, 152) covering the inner wall of the first opening (OP1) can be formed.

[0124] A second lower spacer (152) conformally covers the inner wall and bottom surface of the first opening (OP1), and a first lower spacer (151) is deposited on the second lower spacer (152). Then, an anisotropic etching process is performed to remove the first and second lower spacers (151, 152) on the bottom surface. Accordingly, the first and second spacers (151, 152) covering the inner wall of the first opening (OP1) can be formed.

[0126] Referring to FIG. 10d, a mold layer (118) can be formed within the first opening (OP1) to a certain depth.

[0127] The mold layer (118) may cover the exposed upper surface of the substrate (101). The mold layer (118) may be formed to have an upper surface lower than the upper surface of the plurality of conductive pads (171). In an exemplary embodiment, the mold layer (118) may include carbon (C), but the material of the mold layer (118) is not limited thereto.

[0129] Referring to FIG. 10e and FIG. 10f, parts of the first and second lower spacers (151, 152) can be removed and the mold layer (118) can be removed.

[0130] First, an isotropic etching process may be performed to remove a portion of the first and second lower spacers (151, 152). In an exemplary embodiment, the isotropic etching process may be performed using fluorine (F) gas. The upper surfaces of the first and second lower spacers (151, 152) may be located at substantially the same level as the upper surface of the mold layer (118). The second lower spacer (152) may have an upper surface at a level lower than the upper surface of the plurality of conductive pads (171) and / or the insulating pattern (172) and may cover a portion of the side of the plurality of conductive pads (171).

[0131] Next, the mold layer (118) can be selectively removed for the first and second lower spacers (151, 152). Accordingly, the first and second lower spacers (151, 152) can be retained without being removed and the top formed through the isotropic etching process can be maintained.

[0133] Referring to Fig. 10g, a bitline contact pattern (DC) can be formed.

[0134] After forming a conductive material covering the first and second lower spacers (151, 152) and the first opening (OP1), a portion of the conductive material can be removed through an etch-back process to form a bitline contact pattern (DC) and the mask (M) can be removed. In an exemplary embodiment, the conductive material may comprise polycrystalline silicon. The first preliminary conductive layer (141') and the bitline contact pattern (DC) may have upper surfaces at substantially the same level.

[0136] Referring to Fig. 10h, a bitline structure (BLS) can be formed.

[0137] First, second and third preliminary conductive layers and a preliminary bitline capping layer are formed sequentially on a bitline contact pattern (DC) and a first preliminary conductive layer (141'), and a second opening (OP2) that penetrates therefrom is formed, thereby forming a first conductive pattern (141), a second conductive pattern (142), a third conductive pattern (143), and a bitline capping pattern (BC) that are stacked sequentially. Accordingly, a bitline (BL) including the first to third conductive patterns (141, 142, 143) and a bitline structure (BLS) including the bitline capping pattern (BC) can be formed.

[0138] In the etching process for forming the second opening (OP2), the bitline contact pattern (DC) is not penetrated to expose the substrate (101), so the bitline contact pattern (DC) may include a lower portion having a first width in the x direction and an upper portion having a second width substantially equal to the second conductive pattern (142) on the lower portion. The first width may be larger than the second width.

[0139] In the etching process for forming the second opening (OP2), as the bitline contact pattern (DC) is selectively removed with respect to the first and second lower spacers (151, 152), the second opening (OP2) may have a lower surface level where the first and second lower spacers (151, 152) are exposed that is higher than the lower surface level where the bitline contact pattern (DC) is exposed.

[0141] Referring to FIG. 10i, an upper spacer structure (US) can be formed within the second opening (OP2).

[0142] The upper spacer structure (US) can cover the inner wall and bottom surface of the second opening (OP2). Accordingly, the upper spacer structure (US) can cover the side wall of the bitline structure (BLS) and cover the bitline contact pattern (DC) and the lower spacers (151, 152).

[0144] Referring to Fig. 10j, a third opening (OP3) can be formed.

[0145] First, an insulating fence can be formed by forming sacrificial patterns between bitline structures (BLS) and etching a portion of the sacrificial patterns to fill the sacrificial patterns with an insulating material other than the sacrificial patterns, such as silicon nitride. The insulating fence can be positioned overlapping the wordline structures (WLS) in the z-direction. The sacrificial patterns and the insulating fence can be positioned alternately along the y-direction.

[0146] Next, an etching process can be performed on the sacrifice patterns and a portion of the upper spacer structure (US) to form a third opening (OP3). The third opening (OP3) can penetrate the barrier patterns (130a, 130b, 130c). Additionally, the third opening (OP3) can expose a plurality of conductive pads (171) by removing a portion of the plurality of conductive pads (171).

[0147] In the above etching process, the difficulty of the process for forming the third opening (OP3) may increase due to reasons such as the width between the bitline structure (BLS) and / or bitline contact pattern (DC) and the lower spacers (151, 152) being narrow, or the etching ratio between the lower spacers (151, 152) and the plurality of conductive pads (171) being different. However, as shown in FIGS. 10d to 10f, by lowering the top of the lower spacers (151, 152) to a level lower than the upper surface of the plurality of conductive pads (171), the width between the bitline structure (BLS) and / or bitline contact pattern (DC) and the plurality of conductive pads (171) becomes relatively wider, and the lower spacers (151, 152) may not affect the etching process. Accordingly, even if the width between the plurality of conductive pads (171) and the bitline contact pattern (DC) is relatively narrow, the third opening (OP3) can be easily formed.

[0148] Additionally, the third opening (OP3) is formed to a relatively deep depth so as to sufficiently expose a plurality of conductive pads (171). That is, the lower spacers (151, 152) can increase the contact area between the plurality of conductive pads (171) and the storage node contact (160, see FIG. 10k) to be formed through a subsequent process, while electrically isolating the plurality of conductive pads (171) and the bitline contact pattern (DC), thereby providing a semiconductor device with improved electrical characteristics.

[0150] Referring to FIG. 10k, a storage node contact (160) and a metal-semiconductor layer (165) can be formed.

[0151] A storage node contact (160) can be formed by filling a third opening (OP3) with a conductive material and performing an etching process. The conductive material may include, for example, at least one of a doped semiconductor material, a metal, or a metal nitride. According to embodiments, the conductive material may include polycrystalline silicon.

[0152] Next, a metal-semiconductor layer (165) can be formed on the storage node contact (160). The metal-semiconductor layer (165) can be formed by reacting the upper surface of the storage node contact (160) with a metal material. The reaction may include, for example, a silicide process.

[0154] Next, referring to FIG. 2, a landing pad (LP) can be formed, a capping insulating layer (180) can be formed, and a capacitor structure (CAP) can be formed.

[0155] First, a landing pad (LP) can be formed on the metal-semiconductor layer (165). The landing pad (LP) extends between the bitline structures (BLS), and the landing pads (LP) connected to each storage node contact (160) can be separated from each other.

[0156] Next, a capping insulating layer (180) can be formed that extends between the landing pads (LP) and contacts the upper spacer structure (US).

[0157] Next, a planarization process and / or an etch-back process can be performed to remove a portion of the capping insulating layer (180), and then a capacitor structure (CAP) can be formed on the landing pad (LP). By doing so, the semiconductor device (100) of FIGS. 1 to 3 can be manufactured.

[0159] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0161] 100: Semiconductor device 105a, 105b: Impurity region 110: Device isolation layers 120: Gate dielectric layer 125: Embedded insulation layer 130: Barrier pattern 141, 142, 143: Challenge Pattern 151, 152: Bottom Spacer 160: Storage node contact 165: Metal-semiconductor layer 180: Capping insulation layer 192: Lower electrode 194: Capacitor dielectric layer 196: Top electrode BL: Bitline BLS: Bitline structure CAP: Capacitor structure LP: Landing pad LS: Lower spacer structure SS: Spacer structure US: Upper spacer structure WL: Wordline WLS: Wordline Structure

Claims

Claim 1 A substrate including an active region; a wordline structure extending in a first horizontal direction; a bitline structure extending in a second horizontal direction intersecting the first horizontal direction on the substrate; a bitline contact pattern electrically connecting a first impurity region of the active region and the bitline structure; a storage node contact disposed on a sidewall of the bitline structure and electrically connected to a second impurity region of the active region; a spacer structure on the sidewall of the bitline structure and the bitline contact pattern; A semiconductor device comprising a capacitor structure electrically connected to the storage node contact, wherein the bitline contact pattern comprises a lower portion and an upper portion having a width smaller than that of the lower portion in the first horizontal direction, and the spacer structure comprises a lower spacer structure surrounding the side of the lower portion, and an upper spacer structure disposed on the side of the upper portion and the side wall of the bitline structure on the lower spacer structure, wherein the upper end of the lower spacer structure is located at a level substantially equal to or lower than the lower end of the storage node contact, and the upper spacer structure extends below the lower surface of the storage node contact and contacts the lower surface of the storage node contact. Claim 2 A semiconductor device according to claim 1, wherein the upper portion of the lower spacer structure is located at a higher level than the lower portion of the bitline contact pattern. Claim 3 A semiconductor device according to claim 1, wherein the lower spacer structure comprises a first lower spacer surrounding the side of the lower portion and a second lower spacer surrounding the outer surface of the first lower spacer. Claim 4 A semiconductor device according to claim 1, wherein the lower spacer structure is spaced apart from the storage node contact, and the upper spacer structure extends between the spaced-apart spacer structure and the storage node contact. Claim 5 A semiconductor device according to claim 1, further comprising: a plurality of conductive pads disposed on the substrate; an insulating pattern separating each of the plurality of conductive pads; and a barrier pattern disposed on the plurality of conductive pads and the insulating pattern, wherein the storage node contact penetrates the barrier pattern and contacts the plurality of conductive pads. Claim 6 In claim 5, the upper portion of the lower spacer structure is located at a lower level than the upper surfaces of the plurality of conductive pads. Claim 7 In claim 5, the upper spacer structure is a semiconductor device in contact with the plurality of conductive pads. Claim 8 A semiconductor device according to claim 1, wherein the upper surface of the lower spacer structure is located at a higher level as it moves away from the bitline contact pattern, and the upper surface of the lower spacer structure has a concave shape. Claim 9 A substrate including an active region; a wordline structure extending in a first horizontal direction within the substrate; a plurality of conductive pads disposed on the substrate; an insulating pattern separating each of the plurality of conductive pads; a bitline structure extending in a second horizontal direction intersecting the first horizontal direction on the plurality of conductive pads and the insulating pattern; a bitline contact pattern electrically connecting a first impurity region of the active region and the bitline structure; a storage node contact disposed on a sidewall of the bitline structure and electrically connected to a second impurity region of the active region by contacting the plurality of conductive pads; and a spacer structure on the sidewall of the bitline structure and the bitline contact pattern. A semiconductor device comprising a capacitor structure electrically connected to the storage node contact, wherein the spacer structure comprises a lower spacer structure covering a portion of the side of the bitline contact pattern and an upper spacer structure between the storage node contact and the bitline structure, wherein the upper end of the lower spacer structure is located at a level lower than the upper surface of the plurality of conductive pads, and the upper spacer structure extends below the lower surface of the storage node contact and contacts the lower surface of the storage node contact. Claim 10 In claim 9, the upper portion of the lower spacer structure is located at a higher level than the lower portion of the plurality of conductive pads.

Images