Sensor device and a semiconductor processing apparatus using the same

Abstract

A semiconductor process apparatus according to one embodiment of the present invention comprises a chamber, an electrostatic chuck installed in an internal space of the chamber, a plurality of grid electrodes each having a plurality of through holes installed on the electrostatic chuck so as to be separated from one another in a first direction perpendicular to the upper surface of the electrostatic chuck, a plurality of reflectors disposed between the plurality of grid electrodes and the electrostatic chuck and reflecting ions passing through the plurality of through holes in each of the plurality of grid electrodes, and a voltage supply unit that outputs a bias voltage having a predetermined period to at least one of the plurality of grid electrodes, wherein each of the plurality of grid electrodes comprises a base plate having a conductive material and a cover layer having a metal oxide covering the surface of the base plate.

Description

Technology Field

[0001] The present invention relates to a semiconductor process apparatus utilizing plasma. Background Technology

[0003] In semiconductor process equipment that performs semiconductor processes using plasma, ions in a plasma state are accelerated to generate a beam, and the ionized beam can be neutralized to generate a neutral beam. The neutral beam can be generated when ions accelerated by a grid electrode collide with a reflector and exchange charges, and the ions can move to the reflector by passing through multiple through-holes included in the grid electrode. During the process of passing through the multiple through-holes, ions may collide with the grid electrode, and particles may be separated from the grid electrode due to these collisions. Particles separated from the grid electrode in this manner can cause a decrease in the yield of the semiconductor process. The problem to be solved

[0005] One of the objectives of the technical concept of the present invention is to improve the yield of the semiconductor process and to improve the reliability and lifespan of the semiconductor process device by minimizing the phenomenon in which particles are separated from the grid electrode or the through-hole of the grid electrode narrows due to collisions between ions and the grid electrode. means of solving the problem

[0007] A semiconductor process apparatus according to one embodiment of the present invention comprises a chamber, an electrostatic chuck installed in an internal space of the chamber, a plurality of grid electrodes each having a plurality of through holes installed on the electrostatic chuck so as to be separated from one another in a first direction perpendicular to the upper surface of the electrostatic chuck, a plurality of reflectors disposed between the plurality of grid electrodes and the electrostatic chuck and reflecting ions passing through the plurality of through holes in each of the plurality of grid electrodes, and a voltage supply unit that outputs a bias voltage having a predetermined period to at least one of the plurality of grid electrodes, wherein each of the plurality of grid electrodes comprises a base plate having a conductive material and a cover layer having a metal oxide covering the surface of the base plate.

[0009] A semiconductor process apparatus according to one embodiment of the present invention comprises an electrostatic chuck installed in the internal space of a chamber, a head providing a plasma space to which process gas is supplied, a bias electrode installed in the head and receiving RF power, a beam source including at least one grid electrode installed below the head and having a plurality of through holes, and a gas supply unit for supplying the process gas, wherein the grid electrode comprises a base plate having a first material having conductivity and a cover layer covering the surface of the base plate and having a second material different from the first material.

[0011] A semiconductor process apparatus according to one embodiment of the present invention comprises an electrostatic chuck installed in the internal space of a chamber, a head providing a plasma space to which process gas is supplied, a bias electrode installed in the head and receiving RF power, a beam source including a plurality of grid electrodes each having a plurality of through holes installed below the head, a gas supply unit for supplying the process gas, and a voltage supply unit for supplying a bias voltage to each of the plurality of grid electrodes, wherein the voltage supply unit supplies a voltage having a predetermined period to at least one of the plurality of grid electrodes and supplies a static voltage to another of the plurality of grid electrodes. Effects of the invention

[0013] According to one embodiment of the present invention, the grid electrode may comprise a base plate formed of a conductive material and a cover layer formed of a metal oxide on the surface of the base plate. Accordingly, the particle separated from the grid electrode is minimized despite collisions with ions accelerated by the voltage applied to the grid electrode in a plasma state, thereby improving the yield of the semiconductor process and the lifespan and reliability of the semiconductor process device. Furthermore, by forming a cover layer, the semiconductor process can be carried out regardless of the type of gas used to form the plasma and the type of conductive material constituting the base plate, thus improving the versatility of the semiconductor process device.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a simplified diagram illustrating a semiconductor process system according to one embodiment of the present invention. FIG. 2 is a simplified diagram showing a semiconductor process apparatus according to one embodiment of the present invention. FIGS. 3 and FIGS. 4 are drawings provided to explain the operation of a semiconductor process apparatus according to an embodiment of the present invention. FIG. 5 is a simplified diagram showing a beam source included in a semiconductor process apparatus according to one embodiment of the present invention. FIGS. 6 and FIGS. 7 are drawings that simply illustrate a grid electrode according to one embodiment of the present invention. FIGS. 8 and 9 are drawings provided to explain the operation of a semiconductor process apparatus according to an embodiment of the present invention. FIGS. 10 and FIGS. 11 are drawings provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention. FIGS. 12 to 14 are drawings provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention. FIGS. 15 and FIGS. 16 are drawings provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention. FIG. 17 is a drawing provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention. Specific details for implementing the invention

[0017] Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings.

[0019] FIG. 1 is a simplified diagram illustrating a semiconductor process system according to one embodiment of the present invention.

[0020] Referring to FIG. 1, a semiconductor process system (10) according to one embodiment of the present invention may include a wafer transfer device (30), a load lock chamber (40), a transfer chamber (50), and a plurality of semiconductor process devices (60). For example, the wafer transfer device (30) may receive a wafer through a container such as a FOUP (Front Open Unified Pod, 20) inside a line where the semiconductor process system (10) is placed. The wafer transfer device (30) may transfer the wafer received through the FOUP (20) to the load lock chamber (40), or receive a wafer from the load lock chamber (40) after the semiconductor process is completed in the process chambers (60) and store it in the FOUP (20).

[0021] A wafer transfer device (30) may include a wafer transfer robot (31) having an arm capable of gripping a wafer, a rail section (32) for moving the wafer transfer robot (31), and an aligner (33) for aligning the wafer. Assuming an operation to transfer a wafer from a FOUP (20) to a load lock chamber (40), the wafer transfer robot (31) can take out a wafer stored in the FOUP (20) and place it on the aligner (33). In the aligner (33), the wafer can be rotated to align the wafer in a predetermined direction. Once the wafer alignment is completed in the aligner (33), the wafer transfer robot (31) can take the wafer out of the aligner (33) and transfer it to the load lock chamber (40).

[0022] The load lock chamber (40) is connected to the wafer transfer device (30) and may include a loading chamber (41) where wafers being brought into the semiconductor process device (60) for semiconductor process progress temporarily stay, and an unloading chamber (42) where wafers being removed from the process chamber (60) after the process is completed temporarily stay. When a wafer aligned in the aligner (33) is brought into the loading chamber (41), the inside of the loading chamber (41) is depressurized to prevent external contaminants from entering.

[0023] The load lock chamber (40) may be connected to the transfer chamber (50), and a plurality of semiconductor process devices (60) may be connected around the transfer chamber (50). A wafer transfer robot (51) for transferring wafers between the load lock chamber (40) and the plurality of process chambers (60) may be disposed inside the transfer chamber (50). The wafer transfer robot (31) of the wafer transfer device (30) may be referred to as the first wafer transfer robot, and the wafer transfer robot (51) of the transfer chamber (50) may be referred to as the second wafer transfer robot.

[0024] Each of the plurality of semiconductor process devices (60) can perform a semiconductor process on a wafer. For example, the semiconductor process performed by the plurality of semiconductor process devices (60) may include a deposition process, an etching process, a photolithography process, an annealing process, a polishing process, an ion implantation process, etc.

[0025] In order to carry out at least some of the aforementioned semiconductor processes, plasma may be formed inside at least one of the plurality of semiconductor process devices (60). The plasma is formed on a wafer, mask, display substrate, etc., which are the targets of the semiconductor process, and, for example, the plasma may be generated by a reaction gas supplied to the internal space of an ion beam source mounted on the semiconductor process device (60).

[0026] When plasma is formed within an ion beam source, ions in the plasma state can be accelerated to a wafer or the like, which is the target of a semiconductor process. For example, ions can be accelerated by a voltage applied to a grid electrode included in the ion beam source, and the voltage applied to the grid electrode may vary depending on the polarity of the ions existing in the plasma state. The grid electrode includes a plurality of through holes, and the accelerated ions can pass through at least one of the plurality of through holes. According to an embodiment, ions that pass through the through hole may lose charge during the process of colliding with a reflector and being reflected, and thus a neutral beam can be accelerated to the wafer or the like.

[0027] However, collisions between ions and grid electrodes may occur as ions pass through the through-holes. These collisions may cause particles to detach from the grid electrodes; if these detached particles recombine with the grid electrodes, the through-holes may narrow, or the detached particles may fall onto wafers or other surfaces, causing contamination. For example, damage to the grid electrodes caused by ion collisions can be exacerbated by the type of conductive material constituting the grid electrodes and the reaction gas supplied to form the plasma. Consequently, the available reaction gases may be limited depending on the material of the grid electrodes included in the semiconductor process equipment, which may consequently reduce the versatility of the semiconductor process equipment.

[0028] In one embodiment of the present invention, the grid electrode may include a base plate formed of a conductive material and a cover layer formed of a dielectric material that covers the base plate. Therefore, even when the grid electrode collides with ions, particles of the conductive material may not detach, and problems such as narrowing of the through hole or contamination of the wafer can be minimized.

[0030] FIG. 2 is a simplified diagram showing a semiconductor process apparatus according to one embodiment of the present invention.

[0031] Referring to FIG. 2, a semiconductor process apparatus (100) according to one embodiment of the present invention may include a beam source (110), a process chamber (120), a first power supply unit (130), a second power supply unit (140), a chuck voltage supply unit (150), a gas supply unit (160), etc. The semiconductor process apparatus (100) may be an apparatus that performs processes such as deposition and etching using a plasma (105) formed in a plasma space provided inside the beam source (110).

[0032] The beam source (110) may include a head (111) in which plasma is formed in a plasma space, a bias electrode (112), a gas channel (113), a grid electrode (114), and a reflector (115), etc. The process chamber (120) includes an electrostatic chuck (121) and a second bias electrode (124), etc., and a process target to be processed on the electrostatic chuck (121) may be placed thereon. In one embodiment illustrated in FIG. 2, the process target is shown as a wafer (W), but the process target may be changed to a display substrate, a mask, etc.

[0033] As illustrated in FIG. 2, the electrostatic chuck (121) is fixed to the filler (123), and a plurality of protrusions (122) having a projection shape may be formed on the upper surface of the electrostatic chuck (121). A wafer (W) is placed on the protrusions (122), and thus a space may be formed between the upper surface of the electrostatic chuck (121) and the wafer (W). For example, the space between the upper surface of the electrostatic chuck (121) and the wafer (W) may be filled with helium gas or the like for the purpose of cooling the wafer (W).

[0034] In one embodiment, a wafer (W) can be fixed to an electrostatic chuck (121) by a Coulomb force generated from the chuck voltage supplied by the chuck voltage supply unit (150) to the electrostatic chuck (121). For example, the chuck voltage supplied by the chuck voltage supply unit (150) to the electrostatic chuck (121) may be a static voltage and may have a magnitude of several hundred to several thousand volts.

[0035] In order to perform a semiconductor process, a reaction gas can be introduced from the beam source (110) into the plasma space provided inside the head (113) through the gas passage (113). A valve (161) can be opened first so that the reaction gas can be introduced through the gas passage (113). A first power supply unit (130) supplies a first high-frequency (RF) power to a first bias electrode (112) included in the beam source (110), and a second power supply unit (140) can supply a second high-frequency power to a second bias electrode (124) located at the bottom of the electrostatic chuck (121). Each of the first power supply unit (130) and the second power supply unit (140) may include a high-frequency power source for supplying high-frequency power.

[0036] Plasma (105), including ions, radicals, and electrons of the reaction gas, is generated in the internal space of the head (113) of the beam source (110) by the first high-frequency power and the second high-frequency power, and the reaction gas can be activated by the plasma (105) to increase reactivity. For example, particles included in the plasma (105) can be accelerated by a voltage applied to the grid electrode (114), collide with the reflector (115), and then move toward the wafer (W). If the semiconductor process device (100) is an etching device, at least some of the semiconductor substrates or layers included in the wafer (W) can be dry-etched by particles that collide with the reflector (115) and then accelerate toward the wafer (W).

[0037] The grid electrode (114) includes a plurality of through holes, and particles included in the plasma (105) can be accelerated and pass through the plurality of through holes under the influence of a field generated by a bias voltage applied to the grid electrode (114). In one embodiment, particles that have passed through the plurality of through holes are neutralized by charge exchange with the reflector (115) during the process of colliding with the reflector (115), and as a result, the beam source (110) can emit a neutral beam moving toward the wafer (W).

[0038] A neutral beam has a higher straightness compared to an ion beam made of charged particles, and thus, the reliability of the semiconductor process can be improved by using a beam source (110) that emits a neutral beam. However, before neutralization, charged particles, such as ions, may collide with the grid electrode (114) while passing through the through holes of the grid electrode (114), and the grid electrode (114) may be damaged due to the collision between the ions and the grid electrode (114). If the grid electrode (114) is damaged, particles detached from the grid electrode (114) may fall onto the wafer (W) and cause contamination issues, or may reattach to the grid electrode (114) and reduce the area of ​​the through holes.

[0039] The above-mentioned issue may be exacerbated depending on the type of conductive material constituting the grid electrode (114) and the type of reaction gas provided by the gas supply unit (160). Consequently, the type of reaction gas may be limited depending on the material of the grid electrode (114), which may be a factor that degrades the versatility of the semiconductor process device (100).

[0040] In one embodiment of the present invention, to resolve the above-mentioned issue, the grid electrode (114) may include a base plate formed of a conductive material and a cover layer covering the surface of at least a portion of the base plate. Unlike the base plate, the cover layer is formed of a dielectric material and may be formed of, for example, Y2O3, Al2O3, etc. By forming the cover layer on at least a portion of the surface of the base plate, damage to the grid electrode (114) can be minimized even when particles accelerating toward the grid electrode (114) collide with the grid electrode (114).

[0041] According to an embodiment, the cover layer may have a laminated structure comprising a plurality of layers. For example, the cover layer may include a first cover layer and a second cover layer that are laminated sequentially from the surface of a base plate. The first cover layer and the second cover layer may be formed of different dielectric materials.

[0042] Meanwhile, in one embodiment of the present invention, a voltage having a predetermined period may be applied to the grid electrode (114) as a bias voltage instead of a constant voltage. By applying a voltage having a waveform such as a square wave or a sawtooth wave to the grid electrode (114), a sufficient field capable of accelerating particles contained in the plasma (105) can be formed around the grid electrode (114) regardless of the material and structure of the grid electrode (114).

[0043] According to an embodiment, the grid electrode (114) may include a first grid electrode and a second grid electrode arranged in a direction approaching the electrostatic chuck (121) from the head (111). In one embodiment of the present invention, a voltage having a period, such as a square wave, sawtooth wave, or triangular wave, is input to one of the first grid electrode and the second grid electrode, and a static voltage is input to the other to form a field around the grid electrode (114) and accelerate particles of the plasma (105) toward the electrostatic chuck (121).

[0045] FIGS. 3 and FIGS. 4 are drawings provided to explain the operation of a semiconductor process apparatus according to an embodiment of the present invention.

[0046] FIGS. 3 and FIGS. 4 may be drawings for explaining the operation of a semiconductor process apparatus (100) that accurately propels a neutral beam, which is emitted from a beam source (110) and has straightness, toward a target area of ​​a wafer (W). In one embodiment shown in FIG. 3, the beam source (110) can be moved to adjust the emission angle of the neutral beam, and in one embodiment shown in FIG. 4, the electrostatic chuck (121) can be moved to change the direction toward which the wafer (W) is facing.

[0047] In one embodiment, the reflector (115) included in the beam source (110) may include a plurality of reflective structures arranged at an angle in a predetermined direction. Particles passing through a plurality of through holes included in the grid electrode (114) may move toward the wafer (W) after being reflected at least once in the space between the plurality of reflective structures.

[0048] Accordingly, the direction of travel of the neutral beam emitted by the beam source (110) can be determined by the angle of incidence of the particle incident on the reflector (115) and the angle of reflection of the particle reflected from the reflector (115). In embodiments of the present invention, as shown in FIGS. 3 and 4, at least one of the beam source (110) and the electrostatic chuck (121) can be moved to align the direction of travel of the neutral beam emitted by the beam source (110) and the wafer (W).

[0050] FIG. 5 is a simplified diagram showing a beam source included in a semiconductor process apparatus according to one embodiment of the present invention.

[0051] Referring to FIG. 5, a beam source (200) according to one embodiment of the present invention may include a head (210), a first bias electrode (211), a gas channel (213), a grid electrode (220), and a reflector (230), etc. A reaction gas is supplied through the gas channel (213), and a plasma (205) may be generated by high-frequency power applied to the first bias electrode (211).

[0052] In one embodiment illustrated in FIG. 5, the grid electrode (220) includes a first grid electrode (221), a second grid electrode (222), and a third grid electrode (223), and each of the first to third grid electrodes (221-223) may include a plurality of through holes. In one embodiment, the plurality of through holes included in each of the first to third grid electrodes (221-223) may be aligned so that particles moving from the plasma (205) can pass through. A reflector (230) is disposed below the plurality of through holes, and the reflector (230) may include a plurality of reflective structures.

[0053] Different bias voltages may be applied to at least some of the first to third grid electrodes (221-223), and the voltage applied to each of the first to third grid electrodes (221-223) may vary depending on the type of particles present in the plasma (205). For example, when there are many positive ions in the plasma (205), a positive voltage may be applied to the first grid electrode (221) as the first bias voltage, a negative voltage may be applied to the second grid electrode (222) as the second bias voltage, and a ground voltage may be applied to the third grid electrode (223) as the third bias voltage. Accordingly, positive ions are accelerated by the field generated between the first grid electrode (221) and the second grid electrode (222), and in the process of colliding with the reflector (230), the positive ions lose their charge and become neutralized, so that a neutral beam may be emitted.

[0054] In one embodiment of the present invention, the grid electrode (220) may have a structure including a base plate and a cover layer so that particles accelerated from the plasma (205) and passing through through holes collide with the grid electrode (220) and the particles do not escape from the grid electrode (220). The base plate is formed of a conductive material capable of applying a bias voltage, and the cover layer may be formed of a metal oxide that covers at least a portion of the surface of the base plate.

[0055] Since the grid electrode (220) includes a cover layer, applying a constant voltage as a bias voltage to the grid electrode (220) alone may not form a sufficient field by the grid electrode (220) to accelerate the particles of the plasma (205). Therefore, in one embodiment of the present invention, a voltage having a predetermined period may be applied as a bias voltage to at least one of the first to third grid electrodes (221-223). To this end, a voltage supply unit connected to the grid electrode (220) may include a circuit that generates voltages of various waveforms.

[0056] In addition, according to the embodiment, a bias voltage may also be applied to the reflector (230). In one embodiment of the present invention, the bias voltage applied to the reflector (230) may also be generated as a voltage having a predetermined period, rather than a constant voltage.

[0058] FIGS. 6 and FIGS. 7 are drawings that simply illustrate a grid electrode according to one embodiment of the present invention.

[0059] First, referring to FIG. 6, a grid electrode (300) according to one embodiment of the present invention may include a plate (310) and a plurality of through holes (320). Although the plurality of through holes (320) are depicted as circular, this is merely one embodiment, and the shape of the plurality of through holes (320) may be varied. As previously described, the plate (310) may include a base plate formed of a conductive material and a cover layer formed of a dielectric material such as a metal oxide. Therefore, particles accelerated from the plasma may not directly collide with the base plate formed of the conductive material.

[0060] Referring to FIG. 7, the grid electrode (400) may include a base plate (401), a cover layer (402) surrounding the base plate (402), and a plurality of through holes (403). Particles (410) present in the plasma may be accelerated as shown in FIG. 7 by being influenced by a field generated by a bias voltage applied to the grid electrode (400). Some of the particles (410) may pass through the plurality of through holes (403), while others may collide with the grid electrode (400).

[0061] In a structure where a base plate (401) formed of a conductive material, for example, metal, is directly exposed to the outside without a cover layer (402), metal particles may be separated from the base plate (401) by impact received from accelerating particles (410). The separated metal particles may be reattached to the base plate (401) by metal bonding, thereby reducing the area of ​​the through holes (403). Alternatively, the separated metal particles may fall directly onto a process target, such as a wafer located below the grid electrode (400), thereby causing a contamination issue.

[0062] In particular, the amount of metal particles generated can be increased depending on the material of the base plate (401) and the type of reaction gas supplied to form the plasma. For example, for a base plate (401) formed of molybdenum (Mo), if sulfur hexafluoride (SF6) and carbon tetrafluoride (CF4) are used as reaction gases, the base plate (401) can be etched to generate metal particles.

[0063] In one embodiment of the present invention, the above problem can be solved by forming a cover layer (402) on the surface of a base plate (401) using a dielectric material, such as a metal oxide. Due to the cover layer (402), the base plate (401) may not collide directly with the particles (410). Therefore, regardless of the type of metal material forming the base plate (401), plasma can be generated using various reaction gases and the semiconductor process can be carried out, thereby improving the versatility of the semiconductor process device.

[0064] The cover layer (402) may be formed to cover the entire surface of the base plate (401) or may be formed to cover only a part of the surface of the base plate (401). The cover layer (402) may be formed of a metal oxide, such as Y2O3, Al2O3, etc.

[0065] The cover layer (402) in contact with the base plate (401) can function as a capacitor having a predetermined capacitance. Therefore, when a constant voltage is applied to the base plate (401) as a bias voltage, a field capable of accelerating the particles (410) may not be formed. In one embodiment of the present invention, a voltage having a waveform such as a square wave or a sawtooth wave can be applied to the base plate (401) as a bias voltage to form a field around the grid electrode (400) that accelerates the particles (410).

[0067] FIGS. 8 and 9 are drawings provided to explain the operation of a semiconductor process apparatus according to an embodiment of the present invention.

[0068] First, referring to FIG. 8, a semiconductor process apparatus according to one embodiment of the present invention may include a voltage supply unit (500) and a plurality of grid electrodes (510-530). The voltage supply unit (500) may apply a predetermined bias voltage to each of the plurality of grid electrodes (510-530). In one embodiment illustrated in FIG. 8, the plurality of grid electrodes (510-530) may include first to third grid electrodes (510-530), a first voltage generator (501) may be connected to the first grid electrode (510), and a second voltage generator (502) may be connected to the second grid electrode (520). However, the number of the plurality of grid electrodes (510-530) and the configuration of the voltage supply unit (500) may be varied according to the embodiment.

[0069] Each of the plurality of grid electrodes (510-530) may have a similar structure. For example, the first grid electrode (510) may include a base plate (511), a cover layer (512), and a plurality of through holes (513), and the second grid electrode (520) may include a base plate (521), a cover layer (522), and a plurality of through holes (523). The third grid electrode (530) may also include a base plate (531), a cover layer (532), and a plurality of through holes (533). However, according to the embodiment, at least one grid electrode with a low probability of collision with particles accelerated from the plasma, for example, the third grid electrode (530), may not include a cover layer (532).

[0070] The first voltage generator (501) can output a first bias voltage to the base plate (511) of the first grid electrode (510), and the second voltage generator (502) can output a second bias voltage to the base plate (521) of the second grid electrode (520). Meanwhile, in one embodiment illustrated in FIG. 8, a ground voltage can be input to the base plate (531) of the third grid electrode (530) as a third bias voltage. However, depending on the embodiment, a third bias voltage other than a ground voltage can also be input to the third grid electrode (530).

[0071] In one embodiment of the present invention, at least one of the first bias voltage and the second bias voltage may not be a constant voltage. For example, the first voltage generator (501) may output a first bias voltage having a waveform such as a square wave, a sawtooth wave, or a triangular wave, and the second voltage generator (502) may output a second bias voltage that is a constant voltage. Alternatively, the first voltage generator (501) may output a first bias voltage that is a constant voltage, and the second voltage generator (502) may output a second bias voltage having a waveform such as a square wave, a sawtooth wave, or a triangular wave. Alternatively, each of the first voltage generator (501) and the second voltage generator (502) may output a voltage having a waveform such as a square wave, a sawtooth wave, or a triangular wave.

[0072] The levels of the first bias voltage and the second bias voltage, respectively, may vary depending on the types of ions present in abundance in the plasma. For example, if positive ions are present in abundance in the plasma, the first bias voltage may be generated as a positive voltage, and the second bias voltage may be generated as a ground voltage or a negative voltage. The levels of the first bias voltage and the second bias voltage, respectively, may be several hundred kV.

[0073] FIG. 9 may be an equivalent circuit diagram simply showing a first voltage generator (501) and a first grid electrode (510). Referring to FIG. 9, the first grid electrode (510) may be represented by a resistor element (R) and a capacitor element (C) connected to the first voltage generator (501). The resistor element (R) corresponds to the base plate (511) of the first grid electrode (510), and the capacitor element (C) corresponds to the cover layer (512) of the first grid electrode (510). The capacitance of the capacitor element (C) may be determined according to the material of the cover layer (512) and the shape of the cover layer (512), etc.

[0074] The first voltage generator (501) can output a voltage having a predetermined period, such as a square wave, sawtooth wave, or triangular wave, as the first bias voltage. Accordingly, a displacement current and a field are generated according to the time constant of an RC series circuit including a resistor element (R) and a capacitor element (C), and ions contained in the plasma can be accelerated by the influence of this field.

[0076] FIGS. 10 and FIGS. 11 are drawings provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention.

[0077] FIG. 10 may be a diagram showing a bias voltage applied to at least one of a plurality of grid electrodes included in a semiconductor process device and a current generated therefrom. Referring to FIG. 10, a square wave bias voltage having a predetermined period (TD) may be applied to at least one grid electrode. The bias voltage may have a first level (V1) during an on time (Ton) of one period and a ground level during an off time (Toff).

[0078] In one embodiment of the present invention, the grid electrode may include a base plate formed of a conductive material and a cover layer formed on the surface of the base plate. The cover layer is formed of a dielectric material, and thus, as previously described with reference to FIG. 9, the grid electrode can be represented as an equivalent circuit including a resistor element and a capacitor element.

[0079] During the on time (Ton) when the voltage of the first level (V1) is applied, the capacitor element provided by the cover layer can be charged. Additionally, during the off time (Toff), the charge charged in the capacitor element can be discharged. In this way, the capacitor element corresponding to the cover layer can repeatedly charge and discharge by the bias voltage, and the acceleration time (TI) during which particles included in the plasma are accelerated can be included in the time during which the charge charged in the cover layer is discharged.

[0081] FIG. 11 may be graphs showing bias voltages that a voltage supply unit can apply to a grid electrode in a semiconductor process apparatus according to one embodiment of the present invention. However, the voltage applied to the grid electrode may have a waveform other than the examples shown in the graphs of FIG. 11.

[0082] First, referring to graph (a) of FIG. 11, the bias voltage applied by the voltage supply unit to the grid electrode may be a square wave. The bias voltage is a voltage having a predetermined period (TD), and may have a first level (V1) during a first on time (Ton1) and a ground level during a first off time (Toff1). A first acceleration time (TI1) during which particles such as ions included in the plasma are accelerated may be included in the first off time (Toff1). However, according to the embodiment, the first acceleration time (TI1) may overlap with the first on time (Ton1) and the first off time (Toff1).

[0083] Next, referring to graph (b) of FIG. 11, the bias voltage applied by the voltage supply to the grid electrode may be sawtooth. The bias voltage may increase to a second level (V2) during the second on time (Ton2) of the period (TD) and then decrease, and may be maintained at a ground level during the second off time (Toff2). The second acceleration time (TI2) during which the plasma particles are accelerated is included in the second off time (Toff2), and according to the embodiment, the second acceleration time (TI2) may begin during the time when the bias voltage decreases during the second on time (Ton2).

[0084] Next, referring to graph (c) of FIG. 11, the bias voltage applied by the voltage supply to the grid electrode may have a waveform that is a mixture of sawtooth and square waves. The bias voltage may have a sawtooth waveform that increases to a third level (V3) and then decreases during the third on time (Ton3) of the period (TD), and a square wave waveform that has a fourth level (V4) during the fourth on time (Ton4). During the fourth on time (Ton4), the bias voltage may have a negative level. Meanwhile, the bias voltage may be maintained at a ground level during the third off time (Toff3).

[0085] By applying a bias voltage with a waveform like that of graph (c) to the grid electrode, the charge stored in the cover layer included in the grid electrode can be discharged more quickly, and the field strength can be increased. However, since the charge is discharged quickly, the third acceleration time (TI3) during which the plasma particles are accelerated can be shorter than the first acceleration time (TI1) and the second acceleration time (TI2).

[0087] FIGS. 12 to 14 are drawings provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention.

[0088] FIGS. 12 to 14 may be drawings showing the waveforms of a first bias voltage applied to a first grid electrode and a second bias voltage applied to a second grid electrode included in a semiconductor process apparatus. In the semiconductor process apparatus, the first grid electrode and the second grid electrode are arranged in sequence, and for example, the second grid electrode may be arranged closer to the electrostatic chuck than the first grid electrode.

[0089] First, referring to FIG. 12, the first bias voltage (600) and the second bias voltage (610) may each be square waves having a predetermined period (TD). The first bias voltage (600) and the second bias voltage (610) may have opposite phases. For example, the first bias voltage (600) may have a first level (V1) during the on time (Ton), and the second bias voltage (610) may have a second level (V2) during the on time (Ton). The first level (V1) and the second level (V2) may have the same magnitude but opposite signs, and during the off time (Toff), both the first bias voltage (600) and the second bias voltage (610) may have a ground level.

[0090] Next, referring to FIG. 13, the first bias voltage (620) may be sawtooth and the second bias voltage (630) may be square. During the on time (Ton) of the cycle (TD), the first bias voltage (620) may have a level that increases to a first level (V1) and then decreases, and the second bias voltage (630) may be maintained at a second level (V2). During the off time (Toff), both the first bias voltage (620) and the second bias voltage (630) may be maintained at ground levels.

[0091] Referring to FIG. 14, the first bias voltage (640) is a voltage of a waveform mixed with a sawtooth wave and a square wave, and the second bias voltage (650) may be a sawtooth wave. The first bias voltage (640) may increase to a first level (V1) during the first on time (Ton1) of the cycle (TD) and then decrease, and may be maintained at a second level (V2) lower than the ground level during the second on time (Ton2). The second bias voltage (650) may decrease to a third level (V3) lower than the ground level during the on time (Ton) of the cycle (TD) and then increase. The first off time (Toff1) during which the first bias voltage (640) is maintained at the ground level may be shorter than the off time (Toff) during which the second bias voltage (650) is maintained at the ground level.

[0092] The bias voltages according to the embodiments described with reference to FIGS. 12 to 14 can be applied to the first grid electrode and the second grid electrode when there are many positive ions in the plasma generated in the semiconductor process apparatus to accelerate the positive ions to the electrostatic chuck. Conversely, when there are many negative ions in the plasma, a first bias voltage having a negative voltage is applied to the first grid electrode and a second bias voltage having a positive voltage is applied to the second grid electrode to accelerate the negative ions to the electrostatic chuck.

[0094] FIGS. 15 and FIGS. 16 are drawings provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention.

[0095] In one embodiment described with reference to FIGS. 15 and 16, the semiconductor process apparatus includes a first grid electrode (710), a second grid electrode (720), and a third grid electrode (730), and the plasma may contain a plurality of positive ions. The plasma is generated in the space above the first grid electrode (710), and the electrostatic chuck may be located below the third grid electrode (730). The plasma generated in the space above the first grid electrode (710) contains a plurality of positive ions, and a negative voltage may be applied as a bias voltage to at least one of the second grid electrode (720) and the third grid electrode (730) so that the positive ions can be sufficiently accelerated toward the electrostatic chuck. Hereinafter, for convenience of explanation, it will be described assuming that a negative voltage is applied to the second grid electrode (720).

[0096] FIG. 15 may be a graph showing the relationship between the voltage applied to the second grid electrode (720) and the radiation angle of the electron beam passing through the grid electrodes (710-730). Referring to FIG. 15, as the absolute value of the bias voltage applied to the second grid electrode (720) increases, the radiation angle of the electron beam may increase.

[0097] Drawing (a) of FIG. 16 may be a diagram showing the path of an electron beam (740) passing through grid electrodes (710-730) when a bias voltage of -2000V is applied to the second grid electrode (720). Meanwhile, drawing (b) of FIG. 16 may be a diagram showing the path of an electron beam (750) passing through grid electrodes (710-730) when a bias voltage of 0V is applied to the second grid electrode (720).

[0098] As illustrated in FIG. 16, as the absolute value of the negative voltage applied to the second grid electrode (720) increases, the radiation angle of the electron beam (740, 750) can increase. Accordingly, in a semiconductor process apparatus according to one embodiment of the present invention, the degree of concentration of the electron beam (740, 750) can be changed by adjusting the bias voltage applied to the second grid electrode (720).

[0100] FIG. 17 is a drawing provided to explain the operation of a semiconductor process apparatus according to one embodiment of the present invention.

[0101] Referring to FIG. 17, a semiconductor process apparatus according to one embodiment of the present invention may include a voltage supply unit (800), a plurality of grid electrodes (810-830), and a reflector (840), etc. The voltage supply unit (800) may apply a predetermined bias voltage to each of the plurality of grid electrodes (810-830) and the reflector (840). In one embodiment illustrated in FIG. 17, a first voltage generator (801) may be connected to the first grid electrode (810), and a second voltage generator (802) may be connected to the second grid electrode (820).

[0102] Each of the plurality of grid electrodes (810-830) may have a similar structure. For example, the first grid electrode (810) may include a base plate (811), a cover layer (812), and a plurality of through holes (813), and the second grid electrode (820) may include a base plate (821), a cover layer (822), and a plurality of through holes (823). The third grid electrode (830) may also include a base plate (831), a cover layer (832), and a plurality of through holes (833). However, according to the embodiment, at least one grid electrode with a low probability of collision with particles accelerated from the plasma, for example, the third grid electrode (830), may not include a cover layer (832).

[0103] The first voltage generator (801) can output a first bias voltage to the base plate (811) of the first grid electrode (810), and the second voltage generator (802) can output a second bias voltage to the base plate (821) of the second grid electrode (820). A ground voltage can be input to the base plate (831) of the third grid electrode (830) as a third bias voltage.

[0104] At least one of the first bias voltage and the second bias voltage is not a constant voltage and may have a waveform such as a square wave, a sawtooth wave, or a triangular wave. In addition, in one embodiment illustrated in FIG. 17, a bias voltage may also be input to the reflector (840) by the third voltage generator (803). For example, the third voltage generator (803) may input a bias voltage having a waveform such as a square wave, a sawtooth wave, or a triangular wave to the reflector (840).

[0106] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0108] 60, 100: Semiconductor process equipment 105, 205: Plasma 110, 200: Beam source 111, 210: Head 114, 220, 310, 400, 510, 520, 530, 710, 720, 730, 810, 820, 830: Grid electrodes 511, 521, 531, 811, 821, 831: Base Plate 512, 522, 532, 812, 822, 832: Cover layer 115, 230, 840: Reflector 120: Process chamber 121: Power outage check 500, 800: Voltage supply

Claims

Claim 1 A semiconductor process apparatus comprising: a chamber; an electrostatic chuck installed in the internal space of the chamber; a plurality of grid electrodes installed on the electrostatic chuck so as to be separated from one another in a first direction perpendicular to the upper surface of the electrostatic chuck, each comprising a plurality of through holes; a plurality of reflectors disposed between the plurality of grid electrodes and the electrostatic chuck and reflecting ions that have passed through the plurality of through holes in each of the plurality of grid electrodes; and a voltage supply unit that outputs a bias voltage having a predetermined period to at least one of the plurality of grid electrodes; wherein each of the plurality of grid electrodes comprises a base plate comprising a conductive material and a cover layer comprising a metal oxide that covers the surface of the base plate. Claim 2 A semiconductor process apparatus according to claim 1, wherein the cover layer comprises at least one of Y2O3 and Al2O3. Claim 3 A semiconductor process apparatus according to claim 1, wherein the cover layer comprises a first cover layer and a second cover layer arranged in order from the surface of the base plate. Claim 4 A semiconductor process apparatus according to claim 1, wherein the thickness of the cover layer disposed on one surface of the base plate is smaller than the thickness of the base plate. Claim 5 A semiconductor process apparatus according to claim 1, wherein the voltage supply unit outputs a bias voltage having a positive voltage level during a first time of the cycle and a ground level during a second time different from the first time in the cycle. Claim 6 A semiconductor process apparatus according to claim 5, wherein the bias voltage has a waveform of a square wave or a sawtooth wave. Claim 7 A semiconductor process apparatus according to claim 1, wherein the voltage supply unit outputs a bias voltage having a positive voltage level during a first time of the cycle, having a negative voltage level during a second time different from the first time in the cycle, and having a ground level during a third time different from the first time and the second time in the cycle. Claim 8 A semiconductor process apparatus according to claim 1, wherein the plurality of grid electrodes include a first grid electrode and a second grid electrode arranged in order along a direction approaching the electrostatic chuck, and the voltage supply unit outputs a first bias voltage to the first grid electrode and outputs a second bias voltage different from the first bias voltage to the second grid electrode. Claim 9 A semiconductor process apparatus comprising: an electrostatic chuck installed in the internal space of a chamber; a head providing a plasma space to which process gas is supplied, a bias electrode installed in the head and receiving RF power, and at least one grid electrode installed below the head and having a plurality of through holes; and a gas supply unit for supplying the process gas, wherein the grid electrode comprises a base plate having a first material having conductivity and a cover layer covering the surface of the base plate and comprising a second material different from the first material. Claim 10 A semiconductor process apparatus comprising: an electrostatic chuck installed in the internal space of a chamber; a head providing a plasma space to which process gas is supplied, a bias electrode installed in the head and receiving RF power, and a plurality of grid electrodes installed below the head and each including a plurality of through holes; a gas supply unit for supplying the process gas; and a voltage supply unit for supplying a bias voltage to each of the plurality of grid electrodes; wherein the voltage supply unit supplies a voltage having a predetermined period to at least one of the plurality of grid electrodes and supplies a static voltage to another of the plurality of grid electrodes.

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