Organic Light Emitting Diode Display Device and Manufacturing method thereof

Abstract

In an organic light-emitting display device using a hybrid type thin-film transistor, the present invention forms an etching barrier layer on top of a semiconductor pattern to solve the problem of over-etching of a semiconductor pattern located at the bottom. Since the thin-film transistor may malfunction due to surface resistance caused by the etching barrier layer, the source / drain electrodes penetrate the etching barrier layer and come into direct contact with the semiconductor pattern to solve this, thereby ensuring the characteristics of the thin-film transistor and promoting process stability.

Description

Technology Field

[0001] The present invention relates to an organic light-emitting display device comprising a hybrid thin-film transistor, and in particular to solving the problem of over-etching occurring during the manufacturing process of a semiconductor pattern located at the bottom.

[0002] The present invention relates to an organic electroluminescent display device, and more particularly to an organic electroluminescent display device capable of realizing a wide range of grayscale expression and fast on-off operation by adjusting the aspect (S-factor) of a specific thin-film transistor among a plurality of thin-film transistors. Background Technology

[0003] Recently, with the advancement of multimedia, the importance of flat-panel displays has been increasing. In response to this, flat-panel displays such as liquid crystal displays, plasma displays, and organic light-emitting diodes (OLEDs) are being commercialized. Among these flat-panel displays, OLEDs are currently widely used due to their high response speed, high brightness, and excellent viewing angles.

[0004] In such an organic light-emitting display device, a plurality of pixels are arranged in a matrix shape, and each pixel is equipped with a light-emitting element portion represented by an organic light-emitting layer and a thin-film circuit portion represented by a thin-film transistor. The thin-film circuit portion includes a plurality of thin-film transistors, such as a driving thin-film transistor (TFT) that operates the organic light-emitting element by supplying a driving current and a switching thin-film transistor (TFT) that supplies a gate signal to the driving thin-film transistor.

[0005] In addition, a gate driving circuit that provides a gate signal to a pixel may be disposed in the non-display area of ​​the organic light-emitting display device.

[0006] As such, since multiple thin-film transistors placed in the pixel circuit portion and the gate driving circuit portion within a pixel, particularly a sub-pixel, perform different functions, their electrical characteristics must also be different. In order to make the electrical characteristics of the multiple thin-film transistors placed within the pixel different, multiple thin-film transistors made of different structures or different semiconductor materials are formed; however, in this case, the semiconductor material layers are formed on different layers and are exposed to different etching conditions during the etching process, resulting in the problem of the semiconductor material located underneath being over-etched. The present invention relates to solving this problem and stably securing the performance of thin-film transistors. The problem to be solved

[0007] The present invention was made by focusing on the above-mentioned problems, and aims to propose a structure that prevents the problem of over-etching of the semiconductor pattern located at the bottom within each pixel and, in addition, can stably realize the performance of the thin-film transistors configured within the pixel. means of solving the problem

[0008] To achieve the above objective, an organic light-emitting display device according to the present invention comprises: a substrate including a display area and a non-display area disposed around the display area; a first thin-film transistor disposed on the substrate and comprising a first semiconductor pattern, an etching barrier formed on the top of the first semiconductor pattern, a first gate electrode, and a first source electrode and a first drain electrode connected to the first semiconductor pattern by penetrating the etching barrier; and a second thin-film transistor disposed on the substrate and comprising a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor pattern is composed of a polycrystalline semiconductor pattern and the second semiconductor pattern is composed of an oxide semiconductor pattern.

[0009] The first thin-film transistor is formed in at least one of the display area and the non-display area, and the second thin-film transistor can be formed in the display area.

[0010] The first gate electrode and the second gate electrode are formed on different layers, and a silicon nitride film and a silicon oxide film may be laminated between the first gate electrode and the second gate electrode.

[0011] A first gate electrode may be placed on a first semiconductor pattern, and a second gate electrode may be placed on a second semiconductor pattern.

[0012] The first semiconductor pattern includes a first source region, a first drain region corresponding to the first source region, and a first channel region located between the first source region and the first drain region, and an etching barrier film is disposed on top of the first source region and the first drain region to cover the first source region and the first drain region.

[0013] The etching barrier film includes a contact hole having a width smaller than that of the first source region and the first drain region, and the first source electrode and the first drain electrode can contact the first source region and the first drain region through the contact hole.

[0014] The first thin-film transistor may be a driving thin-film transistor that drives a sub-pixel placed in a display area.

[0015] Meanwhile, the second thin-film transistor may be a driving thin-film transistor that drives a sub-pixel placed in a display area.

[0016] The organic light-emitting display device of the present invention may further include a first light-blocking pattern that completely overlaps with the first semiconductor pattern at the bottom of the first semiconductor pattern.

[0017] The above-mentioned first light-blocking pattern can be disposed between a substrate and a first semiconductor pattern while interposing an insulating film between it and the first semiconductor pattern.

[0018] In addition, the organic light-emitting display device of the present invention further comprises a third semiconductor pattern disposed on a substrate and composed of an oxide semiconductor pattern, a third light-blocking pattern that completely overlaps the third semiconductor pattern at the bottom of the third semiconductor pattern, a third thin-film transistor including a third gate electrode, a third source electrode, and a third drain electrode, and a second light-blocking pattern that completely overlaps the second semiconductor pattern at the bottom of the second semiconductor pattern, wherein the distance between the second semiconductor pattern and the second light-blocking pattern is closer than the distance between the third semiconductor pattern and the third light-blocking pattern.

[0019] A second light-blocking pattern can be placed between the first gate electrode and the second semiconductor pattern.

[0020] The etching barrier film can be a wear-resistant material and, in particular, titanium nitride (TiN).

[0021] The second light-blocking pattern can be connected to the second source electrode or the second drain electrode.

[0022] The first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the third source electrode, and the third drain electrode may be composed of the same material.

[0023] The non-display area further includes a banding area extending from the display area, and the banding area may include an open portion in which an inorganic film stacked between the substrate and the first source electrode and the first drain electrode is removed to expose the substrate.

[0024] The open portion may include a first open portion in which an inorganic film stacked between the second source / drain electrode and the second semiconductor pattern is removed, and a second open portion in which an inorganic film stacked between the second semiconductor pattern and the substrate is removed. Effects of the invention

[0025] The present invention can form a stable circuit portion by applying thin film transistors using different types of semiconductor patterns to a single pixel, while ensuring that the semiconductor pattern located underneath is not over-etched during the etching process and that the thin film transistors achieve uniform performance. Brief explanation of the drawing

[0026] FIG. 1a is a schematic block diagram of an organic light-emitting display device according to the present invention. FIG. 1b is a cross-sectional view showing a display device cut along the line "G-G'" in FIG. 1. FIG. 2 is a schematic block diagram of a sub-pixel of an organic light-emitting display device according to the present invention. FIG. 3 is a circuit diagram of a sub-pixel of an organic light-emitting display device according to the present invention. FIG. 4a is a cross-sectional view illustrating an example of a thin-film transistor disposed in a gate driving circuit portion of a non-display area and a driving thin-film transistor and a switching thin-film transistor disposed in a display area, as a first embodiment of the present invention. Figure 4b is a cross-sectional view showing a part of the driving thin-film transistor of Figure 4a. Figure 4c is a plan view showing a part of the driving thin-film transistor of Figure 4b. FIG. 4d is a cross-sectional view of a bending area that is part of a non-displayed area in the first embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating an example of a thin-film transistor disposed in a gate driving circuit portion of a non-display area and a driving thin-film transistor and a switching thin-film transistor disposed in a display area using an oxide semiconductor pattern, as a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a configuration as a second embodiment of the present invention, further comprising a thin-film transistor disposed in a gate driving circuit portion of a non-display area, a driving thin-film transistor disposed in a display area using an oxide semiconductor pattern, a switching thin-film transistor disposed in a display area using a polycrystalline semiconductor pattern, and a switching thin-film transistor disposed in a display area using a polycrystalline semiconductor pattern. Specific details for implementing the invention

[0027] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention.

[0028] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0029] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0030] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0031] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0032] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0033] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and driving mechanisms. Each embodiment may be implemented independently of one another or may be implemented together in an interlocking relationship.

[0034] --First Embodiment--

[0035] Hereinafter, a first embodiment of the present invention will be described in detail with reference to the attached drawings.

[0036] FIG. 1a is a schematic block diagram of an organic light-emitting display device (100) according to the present invention, and FIG. 1b shows a cross-sectional view of the organic light-emitting display device (100) with G-G' as the cutting line in FIG. 1a. FIG. 2 is a schematic block diagram of a sub-pixel (SP) shown in FIG. 1a.

[0037] As illustrated in FIG. 1a, the organic light-emitting display device (100) comprises a display panel (PAN) in which an image processing unit (110), a degradation compensation unit (150), a memory (160), a timing control unit (120), a data driving unit (140), a power supply unit (180), and a gate driving unit (130) are formed within the display panel (PAN). In particular, a non-display area (NA) of the display panel (PAN) includes a bending area (BA). The display panel (PAN) can be folded at the bending area (BA) to reduce the bezel.

[0038] The image processing unit (110) outputs a driving signal for driving various devices along with image data supplied from the outside. For example, the driving signal output from the image processing unit (110) may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0039] The degradation compensation unit (150) calculates a degradation compensation gain value for a sub-pixel (SP) of a display panel based on a sensing voltage (Vsen) supplied from a data driving unit (140), calculates a dimming weight value based on the calculated degradation compensation gain value, modulates the input image data (Idata) of each sub-pixel (SP) of the current frame using the calculated degradation compensation gain value and the dimming weight value, and then supplies the modulated image data (Mdata) to the timing control unit (120).

[0040] The timing control unit (120) receives a driving signal, etc., along with modulated image data from the degradation compensation unit (150). Based on the driving signal input from the image processing unit (110), the timing control unit (120) generates and outputs a gate timing control signal (GDC) for controlling the operation timing of the gate driving unit (130) and a data timing control signal (DDC) for controlling the operation timing of the data driving unit (140).

[0041] In addition, the timing control unit (120) controls the operation timing of the gate driving unit (130) and the data driving unit (140) to obtain at least one sensing voltage (Vsen) from each sub-pixel (SP) and supply it to the degradation compensation unit (150).

[0042] The gate driver (130) outputs a scan signal to a display panel (PAN) in response to a gate timing control signal (GDC) supplied from the timing control unit (120). The gate driver (130) outputs a scan signal through a plurality of gate lines (GL1~GLm). At this time, the gate driver (130) may be formed in the form of an IC (Integrated Circuit), but is not limited thereto. In particular, the gate driver (130) may be configured as a GIP (Gate In Panel) structure formed by directly stacking a thin-film transistor on a substrate inside the organic electroluminescent display device (100). The GIP may include a plurality of circuits such as a shift register and a level shifter.

[0043] The data driver (140) outputs a data voltage to a display panel (PAN) in response to a data timing control signal (DDC) input from the timing control unit (120). The data driver (140) samples and latches a digital data signal (DATA) supplied from the timing control unit (120) and converts it into an analog data voltage based on gamma voltage.

[0044] The data driving unit (140) outputs a data voltage through a plurality of data lines (DL1 to DLn).

[0045] Additionally, the data driving unit (140) supplies the sensing voltage (Vsen) input from the display panel (PAN) through the sensing voltage readout line to the degradation compensation unit (150).

[0046] At this time, the data driving unit (140) may be mounted on the upper surface of the passive panel (PAN) in the form of an IC (Integrated Circuit) and may be formed directly on the display panel (PAN), but is not limited thereto.

[0047] The power supply unit (180) outputs a high-potential driving voltage (EVDD) and a low-potential driving voltage (EVSS), etc., and supplies them to the display panel (PAN). The high-potential driving voltage (VDD) and the low-potential driving voltage (EVSS) are supplied to the display panel (PAN) through a power line. At this time, the voltage output from the power supply unit (180) may be output to the data driving unit (140) or the gate driving unit (130) and used for driving them.

[0048] The display panel (PAN) displays an image in response to the data voltage and scan signal supplied from the data driver (140) and gate driver (130) which can be placed in the non-display area (NA), and the power supplied from the power supply unit (180).

[0049] The display area (AA) of the display panel (PAN) is composed of a plurality of sub-pixels (SP) to display an actual image. The sub-pixels (SP) include red, green, and blue sub-pixels, or include white (W), red (R), green (G), and blue (B) sub-pixels. In this case, the W, R, G, and B sub-pixels (SP) may all be formed with the same area, but may also be formed with different areas.

[0050] In the memory (160), not only is a lookup table for the degradation compensation gain stored, but the degradation compensation time of the organic light-emitting element of the sub-pixel (SP) is also stored. At this time, the degradation compensation time of the organic light-emitting element may be the number of driving cycles or driving time of the organic light-emitting display panel.

[0051] Meanwhile, the non-display area (NA) includes a bending area (BA) that can bend or fold the display panel (PAN). The bending area (BA) corresponds to an area that is bent to fold and position non-displaying areas, such as a signal pad (not shown), a gate driver (130), and a data driver (140), to the back of the active area (AA). This bending area (BA) can be positioned between the active area (AA) and the data driver (140), as shown in FIG. 1a. In addition, the bending area (BA) may be positioned within at least one side of the top, bottom, left, or right of the non-display area (NA). Accordingly, the area occupied by the active area (AA) on the entire screen of the display device is maximized, and the non-display area (NA) can be hidden behind the display area (AA).

[0052] A signal link (LK) placed in the bending area (BA) connects the signal pad and the signal line placed in the active area (AA). The signal link (LK) can be positioned to minimize bending stress by extending in a direction intersecting the bending direction and expanding the area.

[0053] Additionally, as illustrated in FIG. 2, at least one open portion (OA1, OA2) is provided in the bending region (BA) to allow the bending region (BA) to be easily bent. This open portion (OA1, OA2) is formed by removing a plurality of crack-inducing inorganic insulating layers (111) placed in the bending region (BA). Specifically, when the substrate (101) is bent, continuous bending stress is applied to the inorganic insulating layers (111) placed in the bending region (BA). Since the inorganic insulating layers (111) have lower elasticity compared to organic insulating materials, cracks are prone to occur in the inorganic insulating layers (111).

[0054] Cracks generated in the inorganic insulating layer (111) propagate along the inorganic insulating layer (111) to the active region (AA), causing line defects and device driving failures. Therefore, at least one flattening layer (PLN) made of an organic insulating material with higher elasticity than the inorganic insulating layer (111) may be disposed in the bending region (BA). This flattening layer (PLN) can relieve bending stress generated as the substrate (101) is bent, thereby preventing cracks from occurring. Since the open portions (OA1, OA2) of the bending region (BA) are formed through the same mask process as at least one of the contact holes among the plurality of contact holes disposed in the active region (AA), the structure and process can be simplified. The present invention proposes a new structure that solves the problem of semiconductor pattern damage when at least one of the contact holes in the display region and the open portions (OA1, OA2) of the bending region (BA) are formed. This will be explained in detail with reference to FIGS. 4a to 4d.

[0055] Meanwhile, as shown in FIG. 2, one sub-pixel (SP) can be connected to a gate line (GL1), a data line (DL1), a sensing voltage readout line (SRL1), and a power line (PL1). The number of transistors and capacitors, as well as the driving method of the sub-pixel (SP), are determined according to the circuit configuration.

[0056] FIG. 3 is a circuit diagram showing a sub-pixel (SP) of an organic light-emitting display device (100) according to the present invention.

[0057] As illustrated in FIG. 3, the organic electroluminescent display device (100) according to the present invention includes a gate line (GL), a data line (DL), a power line (PL), and a sensing line (SL) that intersect to define a sub-pixel (SP), and the sub-pixel (SP) includes a driving thin-film transistor (DT), an organic light-emitting element (D), a storage capacitor (Cst), a first switching thin-film transistor (ST), and a second switching thin-film transistor (ST2).

[0058] The organic light-emitting diode (D) includes an anode electrode connected to a second node (N2), a cathode electrode connected to an input terminal of a low potential driving voltage (EVSS), and an organic light-emitting layer located between the anode electrode and the cathode electrode.

[0059] The driving thin-film transistor (DT) controls the current (Id) flowing through the organic light-emitting diode (D) according to the gate-source voltage (Vgs). The driving thin-film transistor (DT) comprises a gate electrode connected to a first node (N1), a drain electrode connected to a power line (PL) to provide a high potential driving voltage (EVDD), and a source electrode connected to a second node (N2).

[0060] The above storage capacitor (Cst) is connected between the first node (N1) and the second node (N2).

[0061] The first switch thin-film transistor (ST1) responds to a gate signal (SCAN) when driving a display panel (PAN) and applies a data voltage (Vdata) charged in the data line (DL) to the first node (N1) to turn on the driving thin-film transistor (DT). At this time, the first switch thin-film transistor (ST1) has a gate electrode connected to the gate line (GL) to receive a scan signal (SCAN), a drain electrode connected to the data line (DL) to receive a data voltage (Vdata), and a source electrode connected to the first node (N1).

[0062] The second switch thin-film transistor (ST2) stores the source voltage of the second node (N2) in the sensing capacitor (Cx) of the sensing voltage readout line (SRL) by switching the current between the second node (N2) and the sensing voltage readout line (SRL) in response to the sensing signal (SEN). When driving the display panel (PAN), the second switch thin-film transistor (ST2) resets the source voltage of the driving thin-film transistor (DT) to the initialization voltage (Vpre) by switching the current between the second node (N2) and the sensing voltage readout line (SRL) in response to the sensing signal (SEN). At this time, the gate electrode of the second switch thin-film transistor (ST2) is connected to the sensing line (SL), the drain electrode is connected to the second node (N2), and the source electrode is connected to the sensing voltage readout line (SRL).

[0063] Meanwhile, although the drawing describes an organic light-emitting display device with a 3T1C structure including three thin-film transistors and one storage capacitor, the organic light-emitting display device of the present invention is not limited to this structure and can be applied to various structures such as 4T1C, 5T1C, 6T1C, 7T1C, and 8T1C.

[0065] Meanwhile, FIG. 4a is a cross-sectional view illustrating, as a first embodiment of the present invention, a first thin-film transistor (GT) having a polycrystalline semiconductor pattern as a representative thin-film transistor disposed in a non-display area (NA), particularly in a GIP area, a driving thin-film transistor (DT) having a polycrystalline semiconductor pattern disposed within a sub-pixel of a display area (AA) and driving an organic electroluminescent device, a first switch thin-film transistor (ST-1) having an oxide semiconductor pattern, and a storage capacitor (Cst).

[0066] FIG. 4b is an enlarged detailed view of a portion including a semiconductor pattern of the driving thin-film transistor (DT) of FIG. 4a, and FIG. 4c is a plan view of FIG. 4b.

[0067] As shown in FIG. 4a, a driving thin-film transistor (DT) and a first switching thin-film transistor (ST-1) are disposed within a sub-pixel on a substrate (401). At this time, FIG. 4a shows only the driving thin-film transistor (DT) and one switching thin-film transistor (ST-1), but this is for convenience of explanation only, and multiple switching thin-film transistors may be disposed on the actual substrate (401).

[0068] Additionally, a plurality of first thin-film transistors (GT) constituting a gate driving circuit may be disposed in the non-display area (NA) of the substrate (401).

[0069] Meanwhile, a driving thin film transistor (DT) having the same structure as the first thin film transistor (GT) may be disposed within a pixel in the display area (AA) of the substrate (401).

[0070] Hereinafter, assuming that the first thin-film transistor (GT) and the second thin-film transistor, the driving thin-film transistor (DT), have the same structure, the configuration of the first thin-film transistor (GT) will be described.

[0071] However, the first thin-film transistor (GT) and the second driving thin-film transistor may be configured differently as N-TYPE thin-film transistors or P-TYPE thin-film transistors because the types of impurities doped in them are different.

[0072] The first thin-film transistor (GT) comprises a first polycrystalline semiconductor pattern (414) disposed on a lower buffer layer (402) formed on a substrate (401), a first gate insulating layer (442) insulating the first polycrystalline semiconductor pattern (414), a first gate electrode (416) disposed on the first gate insulating layer (442) and overlapping with the first polycrystalline semiconductor pattern (414), a plurality of insulating layers formed on the first gate electrode (416), and a first source electrode (417S) and a first drain electrode (417D) disposed on the plurality of insulating layers.

[0073] The first thin-film transistor (GT) may further have a first light-blocking pattern (BSM-1) formed below the first polycrystalline semiconductor pattern (414) to protect the first polycrystalline semiconductor pattern (414) from light introduced from the outside. The first light-blocking pattern (BSM-1) may be formed optionally rather than being an essential component.

[0074] The first light-blocking pattern (BSM-1) can be formed as a metal pattern on the lower buffer layer (402). The material of the first light-blocking pattern (BSM-1) is not limited to a metal thin film.

[0075] The first light-blocking pattern (BSM-1) is preferably larger than the first polycrystalline semiconductor pattern (414) so ​​that it is formed below the first polycrystalline semiconductor pattern (414) and can completely block external light entering the first polycrystalline semiconductor pattern (414). Therefore, the first light-blocking pattern (BSM-1) can completely overlap with the first polycrystalline semiconductor pattern (414).

[0076] The substrate (401) may be composed of a multi-layer in which an organic film and an inorganic film are alternately stacked. For example, the substrate (401) may be formed by alternately stacking an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2).

[0077] A first lower buffer layer (402) is formed on a substrate (401). The first lower buffer layer (402) is intended to block moisture, etc., that may penetrate from the outside, and may be used by stacking silicon oxide (SiO2) films, etc., in multiple layers.

[0078] A first light-blocking pattern (BSM-1) can be formed on the first lower buffer layer (402).

[0079] A second lower buffer layer (411) may be further formed on the first light-blocking pattern (BSM-1). The second lower buffer layer (411) may be composed of the same material as the first lower buffer layer (402).

[0080] A first polycrystalline semiconductor pattern (414) is formed on the second lower buffer layer (411). The first polycrystalline semiconductor pattern (414) is composed of a polycrystalline semiconductor and includes a first channel region (414a) through which charge moves, and a first source region (414b) and a first drain region (414c) adjacent to the first channel region (414a) with the first channel region (414a) in between. The first source region (414b) and the first drain region (414c) may be regions that have been made conductive by doping impurity ions, such as phosphorus or boron, within the intrinsic polycrystalline semiconductor pattern.

[0081] In particular, referring to FIGS. 4b and 4c, an etching barrier layer (415) is further formed on the top of the first polycrystalline semiconductor pattern (414) of the first thin-film transistor (GT). Specifically, the etching barrier layer (415) may be formed on the top of the first source region (414b) and the first drain region (414c). The etching barrier layer (415) may be formed on the upper surface of the first source region (414b) and the first drain region (414c) in contact with the first polycrystalline semiconductor pattern (414).

[0082] The above etching barrier (415) may be composed of a metallic material that is hardly etched when the inorganic insulating film constituting the first lower buffer layer (402), the second lower buffer layer (422), and the interlayer insulating layers is etched. In particular, the above etching barrier (415) may use a titanium compound, particularly titanium nitride (TiN), which is hardly etched when the inorganic insulating film is dry-etched.

[0083] Additionally, referring to FIG. 4c, the etching barrier (415) is formed on the top of the first source region (414b) and the first drain region (414c) and includes a contact hole (CH-ES) that exposes a portion of the first source region (414b) and the first drain region (414c).

[0084] It is preferable that the contact hole (CH-ES) is smaller than the width of the first source region (414b) and the first drain region (414c). Through the contact hole (CH-ES), the first source electrode (417S) and the first drain electrode (417D) come into direct contact with the first source region (414b) and the first drain region (414c), respectively.

[0085] The above etching barrier (415) may be a metallic material that withstands dry etching better than inorganic insulating films. In this case, ohmic contact is not made between the etching barrier (415) and the first source region (414b) and the first drain region (414c), which are polycrystalline semiconductor patterns, so the surface resistance may be high. In this case, since the reliability of the first thin-film transistor (GT) cannot be ensured, the contact area between the first source electrode (417S) and the first source region (414b) and between the first drain electrode (417D) and the first drain region (414c) can be reduced to decrease the sheet resistance.

[0086] Meanwhile, referring to FIG. 4a, the first polycrystalline semiconductor pattern (414) on which the etching barrier film (415) is formed is insulated by the first gate insulating layer (442).

[0087] The first gate insulating layer (442) is formed by depositing an inorganic insulating layer, such as silicon oxide (SiO2), on the entire surface of the substrate (401) on which the first polycrystalline semiconductor pattern (414) is formed. The first gate insulating layer (442) protects and insulates the first polycrystalline semiconductor pattern (414) from the outside.

[0088] A first gate electrode (416) may be formed on the first gate insulating layer (442) that overlaps with the first channel region (414a) of the first polycrystalline semiconductor pattern (414).

[0089] The first gate electrode (416) may be composed of a metallic material. For example, the first gate electrode (416) may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0090] A plurality of insulating layers may be formed between the first gate electrode (416), the first source electrode (417S), and the first drain electrode (417D).

[0091] Referring to FIG. 4a, the plurality of insulating layers may include a first interlayer insulating layer (443) in contact with the upper surface of the first gate electrode (416), a second interlayer insulating layer (444) sequentially stacked thereon, an upper buffer layer (445), a second gate insulating layer (446), and a third interlayer insulating layer (447).

[0092] The first source electrode (417S) and the first drain electrode (417D) are placed on the third interlayer insulating layer (447). The first source electrode (417S) and the first drain electrode (417D) are directly connected to the first source region (414b) and the first drain region (414c), respectively, through a first contact hole (CH1) and a second contact hole (CH2) penetrating the first gate insulating layer (442), the first interlayer insulating layer (443), the second interlayer insulating layer (444), the upper buffer layer (445), the second gate insulating layer (446), and the third interlayer insulating layer (447).

[0093] As a result, the first source electrode (417S) and the first drain electrode (417D) can contact the first source region (414b) and the first drain region (414c) respectively in a narrower area than when they contact the first source region (414b) and the first drain region (414c) respectively through the etching barrier film (415), thereby reducing electrical resistance.

[0094] Meanwhile, a driving thin-film transistor (DT), a first switching thin-film transistor (ST-1), and a storage capacitor (Cst) are disposed in the sub-pixel of the display area (AA).

[0095] The driving thin-film transistor (DT) has the same structure as the first thin-film transistor (GT) formed in the non-display area (NA). However, a different symbol is used to distinguish it from the components of the first thin-film transistor (GT).

[0096] That is, the driving thin film transistor (DT) comprises a second light-blocking pattern (BSM-2) located on the same layer and composed of the same material as the first light-blocking pattern (BSM-1), a second polycrystalline semiconductor pattern (424) located on the same layer and composed of the same material as the first polycrystalline semiconductor pattern (414), an etching barrier film (425) located on the top of the second source region (424b) and the second drain region (424c) of the second polycrystalline semiconductor pattern (424), a second gate electrode (426) located on the same layer and composed of the same material as the first gate electrode (416), and a second source electrode (427S) and a second drain electrode (427D) located on the same layer and composed of the same material as the first source electrode (417S) and the first drain electrode (417D).

[0097] The second source electrode (427S) and the second drain electrode (427D) are directly connected to the second source region (424b) and the second drain region (424c), respectively, through the third contact hole (CH3) and the fourth contact hole (CH4). A second channel region (424a) may be disposed between the second source region (424b) and the second drain region (424c).

[0098] Therefore, the first to fourth contact holes (CH1~CH4) can have the same depth.

[0099] Additionally, the sub-pixel includes a first switching thin-film transistor (ST-1) comprising an oxide semiconductor pattern. Although one switching thin-film transistor is shown in FIG. 4a, at least one switching thin-film transistor may be placed within the sub-pixel. That is, depending on various configurations of the pixel circuit within the sub-pixel, such as 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, etc., one or more switching thin-film transistors may be placed.

[0100] The first switch thin film transistor (ST-1) includes a second oxide semiconductor pattern (432), a third gate electrode (433), a third source electrode (434S), and a third drain electrode (434D).

[0101] The second oxide semiconductor pattern (432) includes a third channel region (432a), a third source region (432b) adjacent to the third channel region (432a) with the third channel region in between, and a third drain region (432c).

[0102] A third gate electrode (433) is positioned on the second oxide semiconductor pattern (432) with the second gate insulating layer (447) interposed therein.

[0103] A third source electrode (434s) and a third drain electrode (434D) are positioned on the third gate electrode (433) with a third interlayer insulating layer (447) interposed therebetween.

[0104] The third source electrode (434S) and the third drain electrode (434D) are connected to the third source region (432b) and the third drain region (432c), respectively, through the sixth contact hole (CH6) and the seventh contact hole (CH7) penetrating the second gate insulating layer (446) and the third interlayer insulating layer (447).

[0105] Additionally, a third light-blocking pattern (BSM-3) may be placed below the second oxide semiconductor pattern (432).

[0106] The third light-blocking pattern (BSM-3) is placed below the second oxide semiconductor pattern (432) while overlapping with the second oxide semiconductor pattern (432) to protect the second oxide semiconductor pattern (432) from light entering from the outside.

[0107] A third light-blocking pattern (BSM-3) can be formed on the first gate insulating layer (442) or the first interlayer insulating layer (443).

[0108] Meanwhile, referring to FIG. 4a, the sub-pixel further includes a storage capacitor (Cst).

[0109] The storage capacitor (Cst) stores the data voltage applied through the data line for a certain period and then provides it to the organic light-emitting diode.

[0110] A storage capacitor (Cst) comprises two corresponding electrodes and a dielectric placed between them. The storage capacitor (Cst) includes a first electrode (450A) of the storage capacitor placed on the same layer as the first gate electrode (416) and a second electrode (450B) of the storage capacitor corresponding to the first electrode (450A) of the storage capacitor.

[0111] A first interlayer insulating layer (443) may be interposed between the first electrode (450A) of the storage capacitor and the second electrode (450B) of the storage capacitor.

[0112] The second electrode (450B) of the storage capacitor can be electrically connected to the second source electrode (479S).

[0113] Since the first embodiment of the present invention includes a plurality of metal patterns and a plurality of contact holes, it may be necessary to reduce the mask process.

[0114] Accordingly, referring to FIG. 4a, the first light-blocking pattern (BSM-1) and the second light-blocking pattern (BSM-2) can be formed through a single mask process using the same mask.

[0115] In addition, the first gate electrode (416), the second gate electrode (426), the first electrode (450A) of the storage capacitor, and the third light-blocking pattern (BSM-3) can be formed on the same layer using the same material. That is, they can be formed in a single mask process.

[0116] Additionally, the first source electrode (417S), the first drain electrode (417D), the second source electrode (427S), the second drain electrode (427D), the third source electrode (434S), and the third drain electrode (434D) can be formed in a single mask process.

[0117] A single mask process refers to a photolithography process that includes a series of processes such as deposition, exposure, etching, and cleaning.

[0118] Meanwhile, in order to form the first source electrode (417S), the first drain electrode (417D), the second source electrode (427S), the second drain electrode (427D), the third source electrode (434S), and the third drain electrode (434D) in a single mask process and to connect them to the source and drain regions of each corresponding semiconductor pattern, it is necessary to form the first to seventh contact holes (CH1~CH7) in a single mask process.

[0119] However, since the first polycrystalline semiconductor pattern (414) is located in a layer below the second oxide semiconductor pattern (432), if the first contact hole (CH1) to the seventh contact hole (CH7) are formed simultaneously, the second oxide semiconductor pattern (432) is exposed to the etching gas for a longer period of time than the first polycrystalline semiconductor pattern (414), and the second oxide semiconductor pattern (432) may be damaged.

[0120] In addition, when forming the first contact hole (CH1) to the seventh contact hole (CH7), a plurality of inorganic insulating films formed in the bending region (BA) are etched and removed together.

[0121] Accordingly, the step of forming the sixth contact hole (CH6) and the seventh contact hole (CH7) formed on the second oxide semiconductor pattern (432) formed above the first polycrystalline semiconductor pattern (414), and the step of forming the first contact hole (CH1) and the second contact hole (CH2) can be performed separately.

[0122] The following is a more detailed explanation with reference to FIGS. 4a and FIGS. 4d.

[0123] After forming the third interlayer insulating layer (447), the first contact hole (CH1) to the seventh contact hole (CH7) must be formed to connect the source electrode and the drain electrode to the semiconductor pattern. Additionally, the inorganic insulating layers stacked in the bending region (BA) must be removed.

[0124] The step of etching inorganic insulating layers disposed between the first polycrystalline semiconductor pattern (414), the first source electrode (417S), and the first drain electrode (417D) includes a first step of removing an inorganic insulating layer of depth d1 shown in FIG. 4a and FIG. 4d, and a second step of removing an inorganic insulating layer disposed between the second oxide semiconductor pattern (432) and the substrate (401) shown as d2.

[0125] That is, the second gate insulating layer (446) and the third interlayer insulating layer (447) are removed in the display area (AA) to form the sixth and seventh contact holes (CH6, CH7), and at the same time, the second gate insulating layer (446) and the third interlayer insulating layer (447) corresponding to a depth of d1 in the OA1 area of ​​the bending area (BA) are simultaneously removed.

[0126] Then, the 6th contact hole (CH6) and the 7th contact hole (CH7) are covered with a photosensitive film, etc., and the 1st to 5th contact holes (CH1~CH5) and the OA2 area of ​​the bending region (BA) are simultaneously removed, along with the 1st lower buffer layer (402), the 2nd lower buffer layer (411), the 1st gate insulating layer (442), the 1st interlayer insulating layer (443), the 2nd interlayer insulating layer (444), and the 1st upper buffer layer (445) corresponding to a depth of d2.

[0127] At this time, when the non-solid insulating layer at a depth of d2 in the bending region (BA) is etched, the first polycrystalline semiconductor pattern (414) may be exposed to the etching gas for a longer period of time and be damaged. However, the present invention can prevent damage to the first polycrystalline semiconductor pattern (414) by forming an etching barrier film (415) on the first polycrystalline semiconductor pattern (414).

[0128] It is preferable that the etching barrier (415) be made of a metal material that is hardly etched while the inorganic insulating films are etched.

[0129] Meanwhile, when the fifth contact hole (CH5) is formed, the second electrode (450B) of the metal storage capacitor is located at the bottom of the fifth contact hole (CH5) to prevent etching.

[0130] Next, the inorganic insulating layers of the first contact hole (CH1) to the seventh contact hole (CH7) and the bending region (BA) are removed, and then a portion of the etching barrier film (415) is etched to expose the semiconductor pattern placed underneath. At this time, the etching barrier film (415) made of metal material can be etched by a wet etching method.

[0131] Next, a conductive layer is deposited and patterned on a marking area (AA) where contact holes are formed and a bending area (BA) where inorganic insulating layers have been removed, thereby simultaneously forming a first source electrode (417S), a second drain electrode (417D), a second source electrode (427S), a second drain electrode (427D), a third source electrode (434S), a third drain electrode (434D), and link wirings (451) located in the bending area (BA). This process can be accomplished in a single mask process.

[0133] Meanwhile, referring to FIG. 4a, a first flattening layer (PLN1) is formed on a substrate (401) on which a driving thin-film transistor (DT) and a first switching thin-film transistor (ST-1) are placed. The first flattening layer (PLN1) may be formed from an organic material such as photoacrylic, but may also be composed of multiple layers consisting of an inorganic layer and an organic layer. A connecting electrode (445) is formed on the first flattening layer (PLN1). The connecting electrode (445) electrically connects the anode electrode (456), which is a component of the light-emitting element part (460), and the driving thin-film transistor (DT) to each other through an eighth contact hole (CH8) formed within the first flattening layer (PLN1).

[0134] Additionally, the conductive film used to form the connecting electrode (445) can form part of another link wiring (452) in the bending region (BA).

[0135] A second flattening layer (PLN2) may be formed on the connecting electrode (445). The second flattening layer (PLN2) may be formed of an organic material such as photoacrylic, like the first flattening layer (PLN1), but may also be composed of multiple layers consisting of an inorganic layer and an organic layer.

[0136] An anode electrode (456) is formed on the second flattening layer (PLN2). The anode electrode (456) is electrically connected to a connecting electrode (445) through a ninth contact hole (CH9) formed within the second flattening layer (PLN2).

[0137] The above anode electrode (456) is made of a single layer or multiple layers of metals such as Ca, Ba, Mg, Al, Ag, etc. or alloys thereof, and is connected to the second drain electrode (427D) of the driving thin-film transistor (DT) so that an image signal is applied from the outside.

[0138] In addition to the anode electrode (456), the non-display area (NA) may further be provided with an anode connecting electrode (457) that electrically connects the common voltage wiring (VSS) and the cathode electrode (463).

[0139] A bank layer (461) is formed on the second flattening layer (PLN2). The bank layer (461) acts as a partition to divide each sub-pixel, thereby preventing light of a specific color output from adjacent sub-pixels from being mixed and output.

[0140] An organic light-emitting layer (462) is formed on the surface of the anode electrode (456) and on a portion of the inclined surface of the bank layer (461). The organic light-emitting layer (462) may be an R-organic light-emitting layer that emits red light, a G-organic light-emitting layer that emits green light, and a B-organic light-emitting layer that emits blue light, formed in each sub-pixel. Additionally, the organic light-emitting layer (461) may be a W-organic light-emitting layer that emits white light.

[0141] The above organic light-emitting layer (462) may include not only a light-emitting layer but also an electron injection layer and a hole injection layer that respectively inject electrons and holes into the light-emitting layer, and an electron transport layer and a hole transport layer that respectively transport the injected electrons and holes into the organic layer.

[0142] A cathode electrode (463) is formed on the above organic light-emitting layer (462). The cathode electrode (463) may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) or a thin metal that transmits visible light, but is not limited thereto.

[0143] A sealing layer portion (470) is formed on the cathode electrode (463). The sealing layer (470) may be composed of a single layer of an inorganic layer, a two-layer structure of an inorganic layer and an organic layer, or a three-layer structure of an inorganic layer, an organic layer, and an inorganic layer. The inorganic layer may be composed of inorganic materials such as SiNx and SiX, but is not limited thereto. Additionally, the organic layer may be composed of organic materials such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, and polyarylate, or a mixture thereof, but is not limited thereto.

[0144] FIG. 4 discloses that, as an example of the bag layer portion (470), it is composed of three layers: an inorganic layer (471), an organic layer (472), and an inorganic layer (473).

[0145] A cover glass (not shown) is placed on the above-mentioned bag layer portion (470) and can be attached by an adhesive layer (not shown in the drawing). Any material with good adhesion, heat resistance, and water resistance can be used as the adhesive layer, but in the present invention, a thermosetting resin such as an epoxy compound, an acrylate compound, or an acrylic rubber can be used. Additionally, a photocurable resin may be used as the adhesive, in which case the adhesive layer is cured by irradiating the adhesive layer with light such as ultraviolet light.

[0146] The adhesive layer can not only bond the substrate (401) and the cover glass (not shown) but also serve as a sealant to prevent moisture from penetrating into the organic electroluminescent display device.

[0147] The above cover glass (not shown) is an encapsulation cap for encapsulating an organic light-emitting display device, and may use a protective film such as a PS (Polystyrene) film, PE (Polyethylene) film, PEN (Polyethylene Naphthalate) film or PI (Polyimide) film, or may use glass.

[0149] --Second Embodiment--

[0150] Next, a second embodiment of the present invention will be described with reference to FIG. 5.

[0151] The second embodiment is characterized by using an oxide semiconductor pattern as a driving thin-film transistor (DT) for driving a sub-pixel, and the configuration of the first thin-film transistor (GT) formed in the non-display area (NA) and the first switch thin-film transistor (ST-1) formed in the sub-pixel may be the same as that of the first embodiment. Therefore, a description of the configuration identical to that of the first embodiment will be omitted.

[0152] In the second embodiment, the pixel circuit portion (430) of the sub-pixel may include one driving thin-film transistor (DT) and at least one switching thin-film transistor (ST). Here, when there is one or more switching thin-film transistors (ST), all switching thin-film transistors may include an oxide semiconductor pattern, or they may be of a hybrid form in which some include an oxide semiconductor pattern and the rest include a polycrystalline semiconductor pattern.

[0153] Figure 5 illustrates, as an example, one driving thin-film transistor (DT) including an oxide semiconductor pattern and one switching thin-film transistor including an oxide semiconductor pattern. Figure 6 illustrates one driving thin-film transistor (DT) including an oxide semiconductor pattern, one switching thin-film transistor including an oxide semiconductor pattern, and one switching thin-film transistor including a polycrystalline semiconductor pattern.

[0154] Referring to FIG. 5, in the second embodiment, the driving thin film transistor (DT) includes a first oxide semiconductor pattern (474), a second gate electrode (478) that overlaps with the first oxide semiconductor pattern (474), a second source electrode (479S), and a second drain electrode (479D).

[0155] Oxide semiconductors can be composed of oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. More specifically, oxide semiconductors may include zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO), etc.

[0156] In the first embodiment, a polycrystalline semiconductor pattern advantageous for high-speed operation was used as the active layer for the driving thin-film transistor. However, a driving thin-film transistor containing a polycrystalline semiconductor pattern may experience power consumption due to leakage current occurring in the off state. In particular, the problem of power consumption in the off state becomes more problematic during low-speed operation, such as when a display device displays a still image on a document screen. Accordingly, in the second embodiment of the present invention, a driving thin-film transistor is proposed that uses an oxide semiconductor pattern advantageous for blocking leakage current generation as the active layer.

[0157] However, in the case of thin-film transistors using an oxide semiconductor pattern as the active layer, due to the material properties of the oxide semiconductor, the current fluctuation value for a unit voltage fluctuation value is large, and defects often occur in the low-gradation region where precise current control is required. Therefore, in the second embodiment, a driving thin-film transistor is proposed in which the current fluctuation value in the active layer is relatively insensitive to the voltage fluctuation value applied to the gate electrode.

[0158] Referring to FIG. 5, the driving thin-film transistor (DT) includes a first oxide semiconductor pattern (474) located on an upper buffer layer (445), a second gate insulating layer (446) covering the first oxide semiconductor pattern (474), a second gate electrode (478) formed on the second gate insulating layer (446) and overlapping with the first oxide semiconductor pattern (474), a third interlayer insulating layer (447) covering the second gate electrode (478), and a second source electrode (479S) and a second drain electrode (479D) disposed on the third interlayer insulating layer (447).

[0159] Additionally, the first oxide semiconductor pattern (474), which is the active layer, includes a second channel region (474a) through which charge moves, and a second source region (474b) and a second drain region (474c) adjacent to the second channel region (474a) with the second channel region (474a) in between.

[0160] The second channel region (474a) may be composed of an intrinsic oxide semiconductor that is not doped with impurities. Additionally, the second source region (474b) and the second drain region (474c) may be regions that are conductive by doping the intrinsic oxide semiconductor with group 3 or group 5 impurity ions.

[0161] Meanwhile, a fourth light-blocking pattern (BSM-4) is formed on the lower portion of the first oxide semiconductor pattern (474). The fourth light-blocking pattern (BSM-4) may be a metal pattern that blocks external light to prevent the first oxide semiconductor pattern (474) from malfunctioning when external light is irradiated onto the first oxide semiconductor pattern (474).

[0162] In the second embodiment, the fourth light-blocking pattern (BSM-1) may be a metal layer containing a titanium (Ti) material having excellent hydrogen particle capture ability. For example, it may be a single layer of titanium, a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, it is not limited thereto, and other metal layers containing titanium (Ti) are also possible.

[0163] Titanium (Ti) can capture hydrogen particles diffusing into the upper buffer layer (445) to prevent the hydrogen particles from reaching the first oxide semiconductor pattern (474).

[0164] It is preferable to form the fourth light-blocking pattern (BSM-4) vertically below the first oxide semiconductor pattern (474) so ​​as to overlap with the first oxide semiconductor pattern (474). Additionally, the first light-blocking pattern (BSM-1) may be formed larger than the first oxide semiconductor pattern (310) so as to completely overlap with the first oxide semiconductor pattern (310).

[0165] Meanwhile, the second source electrode (479S) of the driving thin-film transistor (DT) can be electrically connected to the fourth light-blocking pattern (474). Electrically connecting the fourth light-blocking pattern (BSM-4) to the second source electrode (479S) can yield the following additional effects.

[0166] As the fourth oxide semiconductor pattern (474) has a second source region (474b) and a second drain region (474c) doped with impurities, the parasitic capacitance C inside the first oxide semiconductor pattern (474) act is occurring , There is a parasitic capacitance C between the second gate electrode (478) and the first oxide semiconductor pattern (474). gi A parasitic capacitance C occurs between the fourth light-blocking pattern (BSM-4) electrically connected to the second source electrode (479S) and the first oxide semiconductor pattern (474). buf It occurs.

[0167] The first oxide semiconductor pattern (474) and the fourth light-blocking pattern (BSM-4) are electrically connected by the second source electrode (479S) so that the parasitic capacitance C act and parasitic capacitance C buf They are connected in parallel with each other, and the parasitic capacitance C act and parasitic capacitance C gi are connected in series. Also, V on the second gate electrode (478) gat of When a gate voltage is applied, the effective voltage V applied to the actual first oxide semiconductor pattern (474) eff The following mathematical equation 1 holds.

[0168]

[0169] Accordingly, the effective voltage V applied to the second channel region (474a) eff parasitic capacitance C buf Parasitic capacitance C in an inverse relationship with bufThe effective voltage applied to the first oxide semiconductor pattern (474) can be controlled by adjusting it.

[0170] That is, by placing the fourth light-blocking layer (BSM-4) near the first oxide semiconductor pattern (474), the parasitic capacitance C buf If the value is increased, the actual current flowing through the first oxide semiconductor pattern (474) can be reduced.

[0171] The fact that the effective current value flowing through the first oxide semiconductor pattern (474) is reduced means that the s-factor can be increased, and the voltage V applied to the actual second gate electrode (478) gat This means that the control range of the driving thin-film transistor (DT) that can be controlled through this is widened.

[0172] That is, by electrically connecting the second source electrode (479S) of the driving thin-film transistor (DT) and the fourth light-blocking pattern (BSM-4), the organic light-emitting diode can be precisely controlled even at low gradations, thereby solving the problem of screen stains that frequently occur at low gradations.

[0173] For reference, the s-factor is commonly referred to as the "subthreshold slope" and represents the voltage required to increase the current tenfold; it is the reciprocal of the slope of the subthreshold voltage region graph in the IV curve, which represents the characteristics of drain current with respect to gate voltage.

[0174] When the aspect is small, it means that the slope of the characteristic graph (IV) of drain current with respect to gate voltage is large, so the thin-film transistor turns on even with a small voltage, and thus the switching characteristics of the thin-film transistor improve. On the other hand, since the threshold voltage is reached in a short time, it becomes difficult to express sufficient gradation.

[0175] When the aspect is large, it means that the slope of the characteristic graph (IV) of drain current with respect to gate voltage is small, so the on / off response speed of the thin-film transistor is reduced. Consequently, although the switching characteristics of the thin-film transistor are degraded, it is possible to achieve sufficient grayscale expression because the threshold voltage is reached over a relatively long period of time.

[0176] In particular, the fourth light-blocking pattern (BMS-4) is inserted into the upper buffer layer (445) and positioned close to the second oxide semiconductor pattern (474). However, the second embodiment exemplifies the use of multiple sub-upper buffer layers. That is, the upper buffer layer (445) may have a structure in which the first sub-upper buffer layer (445a), the second sub-upper buffer layer (445b), and the third sub-upper buffer layer (445c) are stacked in sequence. The fourth light-blocking pattern (BSM-4) is formed on the first sub-upper buffer layer (445a) which is positioned on the second interlayer insulating layer (444). Then, the second sub-upper buffer layer (445b) completely covers the fourth light-blocking pattern (BSM-4). Then, the third sub-upper buffer layer (445c) is formed on the second sub-upper buffer layer (445b).

[0177] The first sub-upper buffer layer (445a) and the third sub-upper buffer layer (445c) may be composed of silicon oxide (SiO2).

[0178] The first sub-upper buffer layer (445a) and the third sub-upper buffer layer (445c) are composed of silicon oxide (SiO2) that does not contain hydrogen particles, thereby protecting the oxide semiconductor pattern, which may have its reliability compromised due to the penetration of hydrogen particles during the heat treatment process.

[0179] On the other hand, the second sub-upper buffer layer (445b) may be composed of silicon nitride (SiNx), which has excellent hydrogen particle capture ability. The second sub-upper buffer layer (445b) may be partially formed on the first sub-upper buffer layer (445a) to completely seal the fourth light-blocking pattern (BSM-4) by covering both the upper and side surfaces of the fourth light-blocking pattern (BSM-4), or the second sub-upper buffer layer (445b) may be formed on the entire surface of the first sub-upper buffer layer (445a) on which the fourth light-blocking pattern (BSM-4) is formed.

[0180] Silicon nitride (SiNx) exhibits superior hydrogen particle trapping capabilities compared to silicon oxide (SiO2). When hydrogen particles penetrate the oxide semiconductor pattern, it causes problems such as different threshold voltages or varying channel conductivity depending on the formation location. In particular, for driving thin-film transistors, ensuring reliability is critical as they directly contribute to the operation of light-emitting devices.

[0181] Accordingly, in an embodiment of the present invention, by forming a second sub-upper buffer layer (445b) covering the fourth light-blocking pattern (BMS-4) on the first sub-upper buffer layer (445a) in part or in whole, the reliability of the driving thin-film transistor (DT) can be prevented by hydrogen particles.

[0182] Additionally, in the second embodiment, the fourth light-blocking pattern (BSM-4) may be composed of a metal layer containing a titanium (Ti) material having excellent hydrogen particle capture ability. For example, it may be a single layer of titanium, a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, it is not limited thereto, and other metal layers containing titanium (Ti) are also possible.

[0183] Titanium (Ti) captures hydrogen particles diffusing within the upper buffer layer (445) to prevent the hydrogen particles from reaching the first oxide semiconductor pattern (474). Accordingly, the driving thin-film transistor (DT) according to an embodiment of the present invention can improve the problem of the reliability of the oxide semiconductor pattern being compromised by hydrogen particles by forming a fourth light-blocking pattern (BSM-4) with a metal layer such as titanium having the ability to capture hydrogen particles, and also covering the fourth light-blocking pattern (BSM-4) with a silicon nitride (SiNx) layer having the ability to capture hydrogen particles.

[0184] Since the second sub-upper buffer layer (445b) is formed of a different material, namely a silicon nitride (SiNx) film, from the first sub-upper buffer layer (445a), film lifting may occur if it is deposited on the entire surface of the display area. To compensate for this, the second sub-upper buffer layer (445b) may be selectively formed only in the necessary parts, that is, only at the location where the fourth light-blocking pattern (BSM-4) is formed.

[0185] It is preferable to form the fourth light-blocking pattern (BSM-4) vertically below the first oxide semiconductor pattern (474) so ​​as to overlap it functionally. Additionally, the fourth light-blocking pattern (BSM-4) may be formed larger than the first oxide semiconductor pattern (474) so ​​as to completely overlap it.

[0186] Additionally, a driving thin-film transistor (DT) has a second gate electrode (478) disposed on a first oxide semiconductor pattern (474). The second gate electrode (478) may overlap with a second channel region (474a). A second gate insulating layer (446) is interposed between the second gate electrode (478) and the first oxide semiconductor pattern (474).

[0187] A second source electrode (479S) and a second drain electrode (479D) are formed on the second gate electrode (478).

[0188] A third interlayer insulating layer (447) may be interposed between the second source electrode (479S), the second drain electrode (479D), and the second gate electrode (478).

[0189] The second source electrode (479S) is connected to the second source region (474b) through a 10th contact hole (CH10) penetrating the second gate insulating layer (446) and the third interlayer insulating layer (447), and the second drain electrode (479D) is connected to the second drain region (474c) through a 11th contact hole (CH4) penetrating the second gate insulating layer (446) and the third interlayer insulating layer (447).

[0190] Meanwhile, the second source electrode (474S) can be electrically connected to the fourth light-blocking pattern (BSM-4) through a 12th contact hole (CH12) that penetrates the upper buffer layer (445), the second gate insulating layer (446), and the third interlayer insulating layer (447).

[0191] Meanwhile, in the second embodiment, the first thin-film transistor (GT) placed in the non-display area (NA) includes a polycrystalline semiconductor pattern and is placed closer to the substrate than the oxide semiconductor pattern, so it is exposed to more etching gas when forming contact holes; therefore, as in the first embodiment, an etching barrier film (415) is placed on the polycrystalline semiconductor pattern.

[0192] Referring to FIG. 6, when a second switch thin film transistor (ST-2) including a polycrystalline semiconductor pattern is placed within a pixel of a display area (AA), a third polycrystalline semiconductor pattern (421) of the second switch thin film transistor (ST-2) may also have an etching barrier film (415) placed on top thereof.

[0193] The configuration of the second switch thin film transistor (ST-2) may be the same as that of the first thin film transistor (GT).

[0194] However, depending on the case, the type of impurity doped into the polycrystalline semiconductor pattern may be different, so that the thin film transistor including the polycrystalline semiconductor pattern placed in the non-display area (NA) and the thin film transistor including the polycrystalline semiconductor pattern placed in the display area may be configured differently as an N-TYPE thin film transistor or a P-TYPE thin film transistor.

[0195] FIG. 6 illustrates a configuration in which a second switch thin-film transistor (ST-2) including a polycrystalline semiconductor pattern is added to a sub-pixel in the second embodiment shown in FIG. 5.

[0196] The second switch thin-film transistor (ST-2) is disposed on the same layer as the first polycrystalline semiconductor pattern (414) and comprises a third polycrystalline semiconductor pattern (421) including a channel region, a fifth channel region (421a), a fifth source region (421b), and a fifth drain region (421c); a fifth gate electrode (422) overlapping with the fifth channel region (421a); ​​a fifth source electrode (423S) and a fifth drain electrode (423D) connected to the fifth source region (421b) and the fifth drain region (421c) respectively through a 13th contact hole (CH13) and a 14th contact hole (CH14); a fifth light-blocking pattern (BSM-5) blocking the third polycrystalline semiconductor pattern (421) from external light from the bottom of the third polycrystalline semiconductor pattern (421); and the fifth source region (421b) and the fifth drain It includes an etching barrier (415) placed on top of the region (421c).

[0197] The foregoing description and the attached drawings are merely illustrative of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications or variations, such as combining, separating, substituting, and changing the components, within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0198] GT: First thin-film transistor DT: Driving thin-film transistor ST-1, ST-2: Switch thin-film transistors 415,4125: Etching barrier 416,426,433,478, 422: Gate electrode 414, 424, 474, 432, 421: Semiconductor patterns BSM: Shading pattern 417S, 427S, 479S, 434S, 423S: Source electrode 417D, 427D, 479D, 434D, 423D: Drain electrodes 456: Anode electrode 462: Organic light-emitting layer, 463: Cathode electrode 430: Pixel circuit portion, 460: Light-emitting element portion, 470: Encapsulation layer portion

Claims

Claim 1 An organic light-emitting display device comprising: a substrate including a display area and a non-display area disposed around the display area; a first thin-film transistor disposed on the substrate and including a first semiconductor pattern, an etching barrier formed on the top of the first semiconductor pattern, a first gate electrode, and a first source electrode and a first drain electrode connected to the first semiconductor pattern by penetrating the etching barrier; and a second thin-film transistor disposed on the substrate and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor pattern is composed of a polycrystalline semiconductor pattern and the second semiconductor pattern is composed of an oxide semiconductor pattern, and the etching barrier is not disposed on the top of the second semiconductor pattern. Claim 2 An organic light-emitting display device according to claim 1, wherein the first thin-film transistor is formed in at least one of the display area and the non-display area, and the second thin-film transistor is formed in the display area. Claim 3 An organic light-emitting display device according to claim 1, wherein the first gate electrode and the second gate electrode are formed on different layers, and a silicon nitride film and a silicon oxide film are laminated between the first gate electrode and the second gate electrode. Claim 4 An organic light-emitting display device according to claim 1, wherein the first gate electrode is disposed on the first semiconductor pattern and the second gate electrode is disposed on the second semiconductor pattern. Claim 5 An organic light-emitting display device according to claim 1, wherein the first semiconductor pattern comprises a first source region, a first drain region corresponding to the first source region, and a first channel region located between the first source region and the first drain region, and the etching barrier film is disposed on top of the first source region and the first drain region to cover the first source region and the first drain region. Claim 6 An organic light-emitting display device according to claim 5, wherein the etching barrier film comprises a contact hole having a width smaller than that of the first source region and the first drain region, and the first source electrode and the first drain electrode contact the first source region and the first drain region through the contact hole. Claim 7 An organic light-emitting display device according to claim 1, wherein the first thin-film transistor is a driving thin-film transistor that drives a sub-pixel disposed in the display area. Claim 8 In paragraph 2, the organic light-emitting display device wherein the second thin-film transistor is a driving thin-film transistor that drives a sub-pixel placed in the display area. Claim 9 An organic light-emitting display device according to claim 7, further comprising a first light-blocking pattern that completely overlaps with the first semiconductor pattern below the first semiconductor pattern. Claim 10 In claim 9, the first light-blocking pattern is an organic light-emitting display device disposed between the substrate and the first semiconductor pattern, with an insulating film interposed between the first semiconductor pattern and the first light-blocking pattern. Claim 11 An organic light-emitting display device according to claim 8, further comprising a third semiconductor pattern disposed on the substrate and composed of an oxide semiconductor pattern, a third light-blocking pattern that completely overlaps the third semiconductor pattern at the bottom of the third semiconductor pattern, a third thin-film transistor including a third gate electrode, a third source electrode, and a third drain electrode, and a second light-blocking pattern that completely overlaps the second semiconductor pattern at the bottom of the second semiconductor pattern, wherein the distance between the second semiconductor pattern and the second light-blocking pattern is closer than the distance between the third semiconductor pattern and the third light-blocking pattern. Claim 12 In claim 11, the second light-blocking pattern is an organic light-emitting display device disposed between the first gate electrode and the second semiconductor pattern. Claim 13 In claim 1, the above-mentioned etching barrier is an organic light-emitting display device made of a wear-resistant material. Claim 14 In paragraph 13, the above-mentioned etching barrier is titanium nitride (TiN) in the organic light-emitting display device. Claim 15 In claim 11, the second light-blocking pattern is an organic light-emitting display device connected to the second source electrode or the second drain electrode. Claim 16 In claim 11, the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the third source electrode, and the third drain electrode are composed of the same material in an organic light-emitting display device. Claim 17 An organic light-emitting display device according to claim 1, wherein the non-display area further includes a banding area extending from the display area, and the banding area includes an open portion in which an inorganic film stacked between the substrate and the first source electrode and the first drain electrode is removed to expose the substrate. Claim 18 In claim 17, the organic light-emitting display device comprises an open portion having a first open portion in which an inorganic film stacked between the second source electrode, the second drain electrode, and the second semiconductor pattern is removed, and a second open portion in which an inorganic film stacked between the second semiconductor pattern and the substrate is removed.

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