Storage device and operating method thereof

Abstract

The present invention relates to an electronic device, and a storage device having an enhanced operating speed according to the present invention comprises a memory device including a plurality of memory blocks connected to a plurality of word lines and included in a super block, and a sudden power off management unit that, when a sudden power off occurs, controls the memory device to perform a read operation for one of the plurality of word lines in one of the memory blocks, and determines one of the word line areas based on data read from one of the word lines, among a first word line area located above one of the word lines and a second word line area located below one of the word lines, and controls the memory device to perform read operations for a plurality of selected word lines among the word lines included in the determined word line area in parallel in the remaining memory blocks excluding one of the plurality of memory blocks, and detects an initial erase page located at the boundary between a program page and an erase page based on data read from the plurality of selected word lines.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a storage device and a method of operating the same. Background Technology

[0002] A storage device is a device that stores data under the control of a host device, such as a computer or a smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices can be classified into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices may be memory devices that store data only while power is supplied and lose the stored data when the power supply is cut off. Volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc.

[0004] Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory. The problem to be solved

[0005] An embodiment of the present invention provides a storage device having an improved operating speed and a method of operating the same. means of solving the problem

[0006] A storage device according to an embodiment of the present invention comprises a memory device including a plurality of memory blocks connected to a plurality of word lines and included in a super block, and a sudden power off management unit that, when a sudden power off occurs, controls the memory device to perform a read operation for one of the plurality of word lines in one of the memory blocks, determines one of the word line areas based on data read from one of the word lines, among a first word line area located above one of the word lines and a second word line area located below one of the word lines, controls the memory device to perform a read operation for a plurality of selected word lines among the word lines included in the determined word line area in parallel in the remaining memory blocks excluding one of the plurality of memory blocks, and detects an initial erase page located at the boundary between a program page and an erase page based on data read from the plurality of selected word lines.

[0007] A method for operating a storage device that controls the operation of a super block comprising a plurality of memory blocks connected to a plurality of word lines according to an embodiment of the present invention comprises: detecting a sudden power off; performing a read operation for a first word line located at an intermediate point among the plurality of word lines in a first memory block in which data is first programmed among the plurality of memory blocks; determining one word line area among a first word line area located above the first word line and a second word line area located below the first word line based on data read from the first word line; performing a read operation in parallel for a plurality of selected word lines among the word lines included in the determined word line area in second memory blocks excluding the first memory block among the plurality of memory blocks; and detecting an initial erase page located at the boundary between a program page and an erase page based on the result of the read operation for the plurality of selected word lines. Effects of the invention

[0008] According to the present technology, a storage device having an enhanced operating speed and a method of operating the same are provided. Brief explanation of the drawing

[0009] FIG. 1 is a drawing for explaining a storage device according to one embodiment of the present invention. Figure 2 is a drawing for explaining the memory device of Figure 1. Figure 3 is a diagram showing an example of the memory cell array of Figure 2. FIG. 4 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 3. FIG. 5 is a circuit diagram showing another embodiment of a memory block (BLKb) among the memory blocks (BLK1~BLKz) of FIG. 3. FIG. 6 is a diagram exemplarily showing the connection relationship between the memory controller of FIG. 1 and a plurality of memory devices. Figure 7 is a diagram illustrating the concept of a super block, super page, or stripe. FIG. 8 is a drawing for explaining another embodiment of the super block of FIG. 7. FIG. 9 is a drawing for explaining an example of an operation for determining the first erase page according to an embodiment of the present invention. FIG. 10 is a drawing for explaining another example of an operation to determine the first erase page according to one embodiment of the present invention. FIG. 11 is a diagram illustrating the configuration of a data set according to one embodiment of the present invention. FIG. 12 is a diagram illustrating the program state of memory cells according to one embodiment of the present invention. FIG. 13 is a diagram illustrating an area where page information is stored in a memory block according to an embodiment of the present invention. FIG. 14 is a diagram for explaining data values ​​corresponding to a plurality of program states included in page information according to an embodiment of the present invention. FIG. 15 is a diagram illustrating page information values ​​according to page status according to an embodiment of the present invention. FIG. 16 is a flowchart for explaining the operation method of a storage device according to one embodiment of the present invention. FIG. 17 is a diagram illustrating the operation of determining the first erase page according to an embodiment of the present invention. FIG. 18 is a drawing for explaining a memory controller according to one embodiment of the present invention. FIG. 19 is a block diagram showing a memory card system to which a storage device according to one embodiment of the present invention is applied. FIG. 20 is a block diagram showing a Solid State Drive (SSD) system to which a storage device according to one embodiment of the present invention is applied. FIG. 21 is a block diagram showing a user system to which a storage device according to one embodiment of the present invention is applied. Specific details for implementing the invention

[0010] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0012] FIG. 1 is a drawing for explaining a storage device according to an embodiment of the present invention.

[0013] Referring to FIG. 1, the storage device (50) may include a memory device (100) and a memory controller (200) that controls the operation of the memory device. The storage device (50) may be a device that stores data under the control of a host (300), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0014] The storage device (50) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (300). For example, the storage device (50) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc.

[0015] The storage device (50) can be manufactured in any one of various types of package forms. For example, the storage device (50) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0016] The memory device (100) can store data. The memory device (100) operates in response to the control of the memory controller (200). The memory device (100) may include a memory cell array (not shown) comprising a plurality of memory cells that store data.

[0017] Memory cells can be configured as a Single Level Cell (SLC) that stores one data bit, a Multi Level Cell (MLC) that stores two data bits, a Triple Level Cell (TLC) that stores three data bits, or a Quad Level Cell (QLC) that can store four data bits.

[0018] A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A single memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in a memory device (100) or reading data stored in a memory device (100). A memory block may be a unit for erasing data.

[0019] In the embodiment, the memory device (100) may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0020] A memory device (100) receives a command (CMD) and an address (ADDR) from a memory controller (200) and is configured to access an area selected by the address among memory cell arrays. The memory device (100) can perform operations instructed by the command (CMD) on the area selected by the address (ADDR). For example, the memory device (100) can perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the memory device (100) will program data into the area selected by the address (ADDR). During a read operation, the memory device (100) will read data from the area selected by the address (ADDR). During an erase operation, the memory device (100) will erase data stored in the area selected by the address (ADDR).

[0021] Meanwhile, although the memory device (100) is depicted as a single unit in FIG. 1, the storage device (50) may include a plurality of memory devices according to the embodiment. The connection relationship between the plurality of memory devices and the memory controller (200) will be explained with reference to FIG. 2.

[0022] The memory controller (200) can control the overall operation of the storage device (50).

[0023] When power is applied to the storage device (50), the memory controller (200) can execute firmware (FW). If the memory device (100) is a flash memory device, the firmware (FW) may include a Host Interface Layer (HIL) that controls communication with the host (300), a Flash Translation Layer (FTL) that controls communication between the host (300) and the memory device (100), and a Flash Interface Layer (FIL) that controls communication with the memory device (100).

[0024] In an embodiment, the memory controller (200) receives data and a logical block address (LBA) from the host (300) and can convert the logical block address into a physical block address (PBA) representing the addresses of memory cells to which data included in the memory device (100) will be stored. In this specification, the logical block address (LBA) and “logical address” or “logical address” may be used interchangeably. In this specification, the physical block address (PBA) and “physical address” or “physical address” may be used interchangeably.

[0025] The memory controller (200) can control the memory device (100) to perform a program operation, a read operation, or an erase operation, etc., according to a request from the host (300). When performing a program operation, the memory controller (200) can provide a write command, a physical block address, and data to the memory device (100). When performing a read operation, the memory controller (200) can provide a read command and a physical block address to the memory device (100). When performing an erase operation, the memory controller (200) can provide an erase command and a physical block address to the memory device (100).

[0026] In one embodiment, the memory controller (200) may be connected to the memory device (100) through a channel. For example, the memory controller (200) may control the memory device (100) to perform a program operation, a read operation, or an erase operation, etc., by providing a command and an address to the memory device (100) through the channel.

[0027] In an embodiment, the memory controller (200) can independently generate commands, addresses, and data and transmit them to the memory device (100) regardless of a request from the host (300). For example, the memory controller (200) can provide commands, addresses, and data to the memory device (100) for performing read operations and program operations involved in performing wear leveling, read reclaim, garbage collection, etc.

[0028] In an embodiment, the memory controller (200) can control at least two memory devices (100). In this case, the memory controller (200) can control the memory devices (100) according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling the operation of at least two memory devices (100) so that it overlaps.

[0029] The host (300) can communicate with the storage device (50) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0030] In one embodiment, the memory controller (200) may include a program operation control unit (210) and a sudden power off management unit (220).

[0031] The program operation control unit (210) can control the memory device (100) to perform a program operation in response to a write request from the host (300).

[0032] In one embodiment, the program operation control unit (210) can generate program data by scrambling and decoding data received from the host (300) during program operation. In one embodiment, the memory controller (200) can generate read data by using an Error Correcting Code (ECC) to detect and correct errors in data received from the memory device (100) during a read operation, and by descramble.

[0033] Additionally, the program operation control unit (210) may generate at least one data set using program data and page information data. At this time, the page information data may include basic information of the page to be stored in the data set (e.g., a programming method such as SLC, MLC, TLC, etc.), the number of erase / program cycles, and status data for determining the program state of the page. When a read operation is performed, the memory device (100) reads the page information data among the data sets and uses the status data among the read page information data to determine whether the page is in a state where programming is completed, in an erase state, or in a state where an SPO has occurred during the program operation. In one embodiment, the status data may include data values ​​corresponding to each of the multiple program states in which the program data is programmed into memory cells included in the multiple pages. At this time, the data values ​​corresponding to each of the multiple program states may include data values ​​corresponding to the program cell state of the memory cells or data values ​​corresponding to the erase cell state of the memory cells.

[0034] In one embodiment, the program operation control unit (210) can control the memory device (100) to program at least one data set into a plurality of pages included in a plurality of memory blocks.

[0035] The sudden power off management unit (220) can detect the occurrence of a sudden power off when a sudden power off occurs and perform a sudden power off recovery operation.

[0036] At this time, the sudden power off recovery operation may be an operation to determine how many pages the program operation performed before the sudden power off situation occurred was programmed up to, and to continue performing the program operation of the memory device (100) that was performed before the sudden power off occurred.

[0037] For example, a sudden power-off may occur in which power is suddenly cut off to the storage device (50) while the memory device (100) is performing a program operation. When power is supplied again after the sudden power-off situation occurs, that is, when the power-on situation is reached, the sudden power-off management unit (220) can perform a sudden power-off recovery operation.

[0038] The sudden power-off management unit (220) can determine the page where a sudden power-off occurred while the program operation is being executed. To do this, the sudden power-off management unit (220) can determine the program state or erase state of each page included in the memory block. The sudden power-off management unit (220) can search for the initial erase page. The initial erase page may be an erase page adjacent to the program page where data is stored among the erase pages that are empty of data. To search for the initial erase page, the sudden power-off management unit (220) can perform a read operation on some of the pages included in the memory block.

[0039] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to perform a read operation on a specific page included in a memory block. If the read data resulting from the read operation contains program data, the page may be determined to be a program page. If the read data resulting from the read operation contains only erase data, the page may be determined to be an erase page.

[0040] In one embodiment, the sudden power off management unit (220) may control the memory device (100) to perform a read operation on one of a plurality of word lines in one of a plurality of memory blocks when a sudden power off occurs. At this time, the plurality of memory blocks may be included in one super block. The description of the super block will be explained in detail with reference to FIGS. 7 and 8, which will be described later. In one embodiment, one of the memory blocks may be the memory block where data is first programmed among the plurality of memory blocks. Also, one of the word lines may be a word line located at an intermediate point among the plurality of word lines.

[0041] In one embodiment, the Sudden Power Off Management Unit (220) may determine one of the word line areas based on data read from one of the word line areas, either the first word line area or the second word line area. At this time, the first word line area may be an area located above the one word line. The first word line area may include word lines from the start word line corresponding to the page where data is first programmed among the plurality of word lines to one of the word lines. Additionally, the second word line area may be an area located below the one word line. The second word line area may include word lines from the last word line corresponding to the page where data is last programmed among the plurality of word lines to one of the word lines.

[0042] Additionally, the sudden power-off management unit (220) can control the memory device (100) to perform read operations on multiple selected word lines in parallel in the remaining memory blocks, excluding any one of the multiple memory blocks. At this time, the multiple selected word lines may be included in a word line area determined based on data read from one word line. For example, the sudden power-off management unit (220) may select a first word line area when a page corresponding to one word line is determined to be an erased page based on data read from one word line. In this case, the sudden power-off management unit (220) may determine multiple selected word lines among the word lines included in the first word line area. Additionally, the sudden power-off management unit (220) can control the memory device (100) to perform read operations on multiple selected word lines included in the first word line area in the remaining memory blocks. As another example, the sudden power off management unit (220) may select a second word line area when, based on data read from a word line, a page corresponding to a word line is determined to be a program page. In this case, the sudden power off management unit (220) may determine a plurality of selected word lines among the word lines included in the second word line area. Additionally, the sudden power off management unit (220) may control the memory device (100) to perform a read operation for the plurality of selected word lines included in the second word line area in the remaining memory blocks.

[0043] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to perform read operations on different selected word lines among a plurality of selected word lines in each of the remaining memory blocks in parallel according to an interleaving technique.

[0044] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to read page information data during a read operation for any one word line and a read operation for a plurality of selected word lines. For example, the memory device (100) can read page information data from a plurality of memory blocks using a half page sensing method.

[0045] Additionally, the sudden power off management unit (220) can detect the first erased page based on data read from a plurality of selected word lines.

[0046] In one embodiment, the sudden power off management unit (220) can determine that the page corresponding to the word line from which the page information data was read is a program page if the read page information data includes a data value corresponding to a program cell state for a plurality of program states. Additionally, the sudden power off management unit (220) can determine that the page corresponding to the word line from which the page information data was read is an erase page if the read page information data includes a data value corresponding to an erase cell state for a plurality of program states. Additionally, the sudden power off management unit (220) can determine that the page corresponding to the word line from which the page information data was read is the first erase page if the read page information data includes both a data value corresponding to a program cell state and a data value corresponding to an erase cell state.

[0047] In addition, in one embodiment, the sudden power off management unit (220) may determine the erase page as the first erase page when the word line corresponding to the program page and the word line corresponding to the erase page among a plurality of selected word lines are adjacent to each other.

[0048] In other words, the Sudden Power Off Management Unit (220) can determine the direction of the operation for determining the first erase page based on data read from any one word line. For example, if the page corresponding to any one word line is an erase page, the Sudden Power Off Management Unit (220) can determine the first erase page according to an up-turn method. In this case, the up-turn method may determine the first erase page in a first word line area located above any one word line. As another example, if the page corresponding to any one word line is a program page, the Sudden Power Off Management Unit (220) can determine the first erase page according to a down-turn method. In this case, the down-turn method may determine the first erase page in a second word line area located below any one word line.

[0049] In one embodiment, the memory device (100) may include a page information detection unit (131).

[0050] The page information detection unit (131) receives status data among page information data read from a plurality of memory blocks and can determine whether the corresponding page is a program completed page, an erased page, or an initial erased page based on the data value of the received status data. The page information detection unit (131) can update and store the status data for the corresponding page based on the determination result and can output information about the initial erased page to the memory controller (200).

[0052] FIG. 2 is a drawing for explaining the memory device (100) of FIG. 1.

[0053] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0054] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to a row decoder (121) via row lines (RL). The plurality of memory blocks (BLK1 to BLKz) may be connected to a page buffer group (123) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. In an example, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line may be defined as a single page. Thus, a single memory block may include a plurality of pages.

[0055] Row lines (RL) may include at least one source selection line, a plurality of word lines, and at least one drain selection line.

[0056] The memory cells included in the memory cell array (110) can each be configured as a single level cell (SLC) that stores one data bit, a multi level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quad level cell (QLC) that can store four data bits.

[0057] The peripheral circuit (120) may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array (110) under the control of the control logic (130). The peripheral circuit (120) may drive the memory cell array (110). For example, the peripheral circuit (120) may apply various operating voltages to row lines (RL) and bit lines (BL1~BLm) or discharge the applied voltages under the control of the control logic (130).

[0058] The peripheral circuit (120) may include a row decoder (121), a voltage generator (122), a page buffer group (123), a column decoder (124), and an input / output circuit (125).

[0059] A row decoder (121) is connected to a memory cell array (110) through row lines (RL). The row lines (RL) may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines (RL) may further include a pipe selection line.

[0060] The row decoder (121) is configured to operate in response to the control of the control logic (130). The row decoder (121) receives a row address (RADD) from the control logic (130).

[0061] The row decoder (121) is configured to decode a row address (RADD). The row decoder (121) selects at least one memory block among the memory blocks (BLK1 to BLKz) according to the decoded address. Additionally, the row decoder (121) can select at least one word line of the selected memory block to apply voltages generated by the voltage generator (122) to at least one word line (WL) according to the decoded address.

[0062] For example, during a program operation, the row decoder (121) will apply a program voltage to the selected word lines and a program pass voltage at a level lower than the program voltage to the unselected word lines. During a program verification operation, the row decoder (121) will apply a verification voltage to the selected word lines and a verification pass voltage higher than the verification voltage to the unselected word lines. During a read operation, the row decoder (121) will apply a read voltage to the selected word lines and a read pass voltage higher than the read voltage to the unselected word lines.

[0063] In an embodiment, the erase operation of the memory device (100) is performed in units of memory blocks. During the erase operation, the row decoder (121) can select one memory block according to the decoded address. During the erase operation, the row decoder (121) can apply a ground voltage to the word lines connected to the selected memory block.

[0064] The voltage generation unit (122) operates in response to the control of the control logic (130). The voltage generation unit (122) is configured to generate multiple voltages using the external power supply voltage supplied to the memory device (100). Specifically, the voltage generation unit (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG). For example, the voltage generation unit (122) can generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage, etc., in response to the control of the control logic (130).

[0065] As an example, the voltage generating unit (122) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (122) is used as the operating voltage of the memory device (100).

[0066] As an example, the voltage generating unit (122) can generate multiple voltages using an external power supply voltage or an internal power supply voltage.

[0067] For example, the voltage generation unit (122) includes a plurality of pumping capacitors that receive an internal power supply voltage, and will selectively activate the plurality of pumping capacitors in response to the control of the control logic (130) to generate a plurality of voltages.

[0068] The generated multiple voltages can be supplied to the memory cell array (110) by the row decoder (121).

[0069] The page buffer group (123) includes first to m page buffers (PB1 to PBm). The first to m page buffers (PB1 to PBm) are each connected to a memory cell array (110) through first to m bit lines (BL1 to BLm). The first to m page buffers (PB1 to PBm) operate in response to the control of the control logic (130). Specifically, the first to m page buffers (PB1 to PBm) can operate in response to page buffer control signals (PBSIGNALS). For example, the first to m page buffers (PB1 to PBm) can temporarily store data received through the first to m bit lines (BL1 to BLm), or sense the voltage or current of the bit lines (BL1 to BLm) during a read or verification operation.

[0070] Specifically, during a program operation, the first to m-th page buffers (PB1 to PBm) will transmit data (DATA) received through the input / output circuit (125) to selected memory cells through the first to m-th bit lines (BL1 to BLm) when a program pulse is applied to a selected word line. The memory cells of the selected page are programmed according to the transmitted data (DATA). Memory cells connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied will have an elevated threshold voltage. The threshold voltage of memory cells connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied will be maintained. During a program verification operation, the first to m-th page buffers (PB1 to PBm) read page data from the selected memory cells through the first to m-th bit lines (BL1 to BLm).

[0071] When a read operation is performed, the first to m page buffers (PB1~PBm) read data (DATA) from the memory cells of the selected page through the first to m bit lines (BL1~BLm), and output the read data (DATA) to the input / output circuit (125) under the control of the column decoder (124).

[0072] During an erase operation, the first to m-page buffers (PB1~PBm) can float the first to m-bit lines (BL1~BLm).

[0073] The column decoder (124) can transfer data between the input / output circuit (125) and the page buffer group (123) in response to a column address (CADD). For example, the column decoder (124) can exchange data with the first to m page buffers (PB1 to PBm) through data lines (DL) or exchange data with the input / output circuit (125) through column lines (CL).

[0074] The input / output circuit (125) can transmit a command (CMD) and an address (ADDR) received from the memory controller (200) described with reference to FIG. 1 to the control logic (130), or exchange data (DATA) with the column decoder (124).

[0075] The sensing circuit (126) can generate a reference current in response to an allow bit signal (VRYBIT) during a read operation or a verify operation, and output a pass signal (PASS) or fail signal (FAIL) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current.

[0076] The control logic (130) can control peripheral circuits (120) by outputting an operation signal (OPSIG), a row address (RADD), page buffer control signals (PBSIGNALS), and an allow bit (VRYBIT) in response to a command (CMD) and an address (ADDR). Additionally, the control logic (130) can determine whether a verification operation has passed or failed in response to a pass or fail signal (PASS or FAIL).

[0077] In one embodiment, the control logic (130) may include a page information detection unit (131).

[0078] The page information detection unit (131) receives state data among the page information data read by the page buffer group (123) and can store the state data. The page information detection unit (131) can determine whether the corresponding page is a program completed page, an erased page, or an initial erased page based on the state data. For example, the page information detection unit (131) can determine the corresponding page as an erased page if all data values ​​corresponding to multiple program states included in the state data have a value of "1". Additionally, the page information detection unit (131) can determine the corresponding page as a program completed page if all data values ​​corresponding to multiple program states included in the state data have a value of "0". Additionally, the page information detection unit (131) can determine the corresponding page as an initial erased page if at least one of the data values ​​corresponding to multiple program states included in the state data has a value of "0".

[0079] Additionally, the page information detection unit (131) can provide information that the page is a program completed page, or that the page is an erased page, or that the page is the first erased page to the memory controller (200) of FIG. 1.

[0081] Figure 3 is a diagram showing an example of the memory cell array of Figure 2.

[0082] Referring to FIG. 3, the memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block is described in more detail with reference to FIG. 4 and FIG. 5.

[0084] FIG. 4 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 3.

[0085] Referring to FIG. 4, the memory block (BLKa) includes a plurality of memory cell strings (CS11–CS1m, CS21–CS2m). As an example, each of the plurality of memory cell strings (CS11–CS1m, CS21–CS2m) may be formed in a 'U' shape. Within the memory block (BLKa), m memory cell strings are arranged in the row direction (i.e., +X direction). In FIG. 4, two memory cell strings are shown arranged in the column direction (i.e., +Y direction). However, this is for convenience of explanation, and it will be understood that three or more memory cell strings may be arranged in the column direction.

[0086] Each of the plurality of memory cell strings (CS11~CS1m, CS21~CS2m) includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), a pipe transistor (PT), and at least one drain select transistor (DST).

[0087] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each memory cell string.

[0088] The source select transistor (SST) of each memory cell string is connected between the common source line (CSL) and the memory cells (MC1~MCp).

[0089] As an example, source select transistors of memory cell strings arranged in the same row are connected to a source select line extending in the row direction, and source select transistors of memory cell strings arranged in different rows are connected to different source select lines. In FIG. 4, source select transistors of memory cell strings (CS11–CS1m) of the first row are connected to a first source select line (SSL1). Source select transistors of memory cell strings (CS21–CS2m) of the second row are connected to a second source select line (SSL2).

[0090] As another embodiment, the source selection transistors of the memory cell strings (CS11~CS1m, CS21~CS2m) can be commonly connected to a single source selection line.

[0091] The first to nth memory cells (MC1 to MCn) of each memory cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0092] The first to n memory cells (MC1 to MCn) can be divided into the first to p memory cells (MC1 to MCp) and the p+1 to n memory cells (MCp+1 to MCn). The first to p memory cells (MC1 to MCp) are arranged sequentially in the +Z direction and in the reverse direction and are connected in series between a source select transistor (SST) and a pipe transistor (PT). The p+1 to n memory cells (MCp+1 to MCn) are arranged sequentially in the +Z direction and are connected in series between a pipe transistor (PT) and a drain select transistor (DST). The first to p memory cells (MC1 to MCp) and the p+1 to n memory cells (MCp+1 to MCn) are connected through a pipe transistor (PT). The gates of the first to nth memory cells (MC1~MCn) of each memory cell string are each connected to the first to nth word lines (WL1~WLn).

[0093] The gate of the pipe transistor (PT) of each memory cell string is connected to the pipeline (PL).

[0094] The drain select transistor (DST) of each memory cell string is connected between the corresponding bit line and the memory cells (MCp+1 to MCn). Memory cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of the memory cell strings of the first row (CS11 to CS1m) are connected to the first drain select line (DSL1). The drain select transistors of the memory cell strings of the second row (CS21 to CS2m) are connected to the second drain select line (DSL2).

[0095] Memory cell strings arranged in a column direction are connected to bit lines extending in a column direction. In FIG. 4, memory cell strings of the first column (CS11, CS21) are connected to the first bit line (BL1). Memory cell strings of the m-th column (CS1m, CS2m) are connected to the m-th bit line (BLm).

[0096] Memory cells connected to the same word line within memory cell strings arranged in a row direction constitute one page. For example, memory cells connected to the first word line (WL1) among the memory cell strings (CS11–CS1m) of the first row constitute one page. Memory cells connected to the first word line (WL1) among the memory cell strings (CS21–CS2m) of the second row constitute another page. Memory cell strings arranged in a row will be selected by selecting either of the drain selection lines (DSL1, DSL2). One page among the selected memory cell strings will be selected by selecting any of the word lines (WL1–WLn).

[0097] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). And among the memory cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the even-numbered memory cell strings may be connected to the even bit lines, and among the memory cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the odd-numbered memory cell strings may be connected to the odd bit lines.

[0098] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCp). Or, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MCp+1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKa) is improved, while the size of the memory block (BLKa) increases. As fewer memory cells are provided, the size of the memory block (BLKa) decreases, while the reliability of operation for the memory block (BLKa) may decrease.

[0099] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKa). If an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0101] FIG. 5 is a circuit diagram showing another embodiment of a memory block (BLKb) among the memory blocks (BLK1~BLKz) of FIG. 3.

[0102] Referring to FIG. 5, the memory block (BLKb) includes a plurality of memory cell strings (CS11'~CS1m', CS21'~CS2m'). Each of the plurality of memory cell strings (CS11'~CS1m', CS21'~CS2m') is extended along the +Z direction. Each of the plurality of memory cell strings (CS11'~CS1m', CS21'~CS2m') includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), and at least one drain select transistor (DST), which are stacked on a substrate (not shown) below the memory block (BLK1').

[0103] The source select transistor (SST) of each memory cell string is connected between the common source line (CSL) and the memory cells (MC1 to MCn). The source select transistors of memory cell strings arranged in the same row are connected to the same source select line. The source select transistors of memory cell strings (CS11' to CS1m') arranged in the first row are connected to the first source select line (SSL1). The source select transistors of memory cell strings (CS21' to CS2m') arranged in the second row are connected to the second source select line (SSL2). In another embodiment, the source select transistors of memory cell strings (CS11' to CS1m', CS21' to CS2m') may be commonly connected to a single source select line.

[0104] The first to nth memory cells (MC1 to MCn) of each memory cell string are connected in series between a source select transistor (SST) and a drain select transistor (DST). The gates of the first to nth memory cells (MC1 to MCn) are each connected to the first to nth word lines (WL1 to WLn).

[0105] The drain select transistor (DST) of each memory cell string is connected between the corresponding bit line and the memory cells (MC1 to MCn). The drain select transistors of the memory cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the memory cell strings of the first row (CS11' to CS1m') are connected to the first drain select line (DSL1). The drain select transistors of the memory cell strings of the second row (CS21' to CS2m') are connected to the second drain select line (DSL2).

[0106] Consequently, the memory block (BLKb) of FIG. 5 has an equivalent circuit similar to the memory block (BLKa) of FIG. 4, except that the pipe transistor (PT) is excluded from each memory cell string.

[0107] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). And among the memory cell strings arranged in the row direction (CS11'~CS1m' or CS21'~CS2m'), the even-numbered memory cell strings may be connected to the even bit lines, and among the memory cell strings arranged in the row direction (CS11'~CS1m' or CS21'~CS2m'), the odd-numbered memory cell strings may be connected to the odd bit lines.

[0108] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCn). Or, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MC1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKb) is improved, while the size of the memory block (BLKb) increases. As fewer memory cells are provided, the size of the memory block (BLKb) decreases, while the reliability of operation for the memory block (BLKb) may decrease.

[0109] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKb). If an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0111] FIG. 6 is a diagram exemplarily showing the connection relationship between the memory controller of FIG. 1 and a plurality of memory devices.

[0112] Referring to FIG. 6, the memory controller (200) may be connected to a plurality of memory devices (memory device_11 to memory device_24) through a plurality of channels (CH1 to CH2). It will be well understood that in the embodiment, the number of channels or the number of memory devices connected to each channel may vary. However, for convenience of explanation, it is assumed in this specification that the memory controller (200) is connected to memory devices through two channels, and that four memory devices are connected to each channel.

[0113] For the convenience of explanation, the operation of memory devices_11,_12,_13, and_14 connected to the first channel (CH1) is described. It will be understood that the memory devices (memory devices_21 to_24) connected to the remaining channel (CH2) operate in the same manner.

[0114] Memory devices_11 to_14 may be commonly connected to the first channel (CH1). Memory devices_11 to_14 may communicate with the memory controller (200) through the first channel (CH1). Since memory devices_11 to_14 are commonly connected to the first channel (CH1), only one memory device may be able to communicate with the memory controller (200) at a time. However, memory devices_11 to_14 may each perform internal operations simultaneously.

[0115] A storage device using multiple memory devices can improve performance by using the interleaving method described in FIG. 1. For the interleaving method, memory devices can be managed in units of channels and ways. To maximize the parallelization of memory devices connected to each channel, a memory controller (200) can distribute and allocate contiguous logical memory regions across channels and ways.

[0116] For example, the memory controller (200) can transmit control signals and data, including commands and addresses, to the memory device_11 through the first channel (CH1). While the memory device_11 programs the transmitted data into the memory cells contained within, the memory controller (200) can transmit control signals and data, including commands and addresses, to the memory device_12.

[0117] In FIG. 6, a plurality of memory devices may be composed of four ways (WAY1 to WAY4). The first way (WAY1) may include memory device_11 and memory device_21. The second way (WAY2) may include memory device_12 and memory device_22. The third way (WAY3) may include memory device_13 and memory device_23. The fourth way (WAY4) may include memory device_14 and memory device_24.

[0118] Each channel (CH1 and CH2) may be a bus of signals shared by memory devices connected to that channel.

[0119] Although interleaving in a 2-channel / 4-way structure is illustrated in Fig. 6, the efficiency of interleaving can be more efficient as the number of channels and ways increases.

[0121] Figure 7 is a diagram illustrating the concept of a super block, super page, or stripe.

[0122] Referring to FIG. 7, four memory devices, memory devices_11 to memory devices_14, can be commonly connected to the first channel (CH1).

[0123] In FIG. 7, each memory device may include a plurality of planes. However, for convenience of explanation, it is assumed in this specification that one memory device includes one plane. One plane included in each memory device (memory device_11 to memory device_14) may include first memory blocks to z-th memory blocks (BLK1 to BLKz), and one memory block may include first pages to n-th pages (Page 1 to Page n).

[0124] The memory controller (200) can control memory blocks included in a plurality of memory devices (memory device_11 to memory device_14) that are commonly connected to one channel in units of super blocks. For example, the first memory blocks (BLK1) included in memory devices_11 to memory devices_14 can form a first super block (Super Block 1). Accordingly, memory devices_11 to memory devices_14 connected to the first channel (CH1) may include first to z super blocks (Super Block 1 to Super Block z).

[0125] In an embodiment, the super block may include at least two memory blocks that are included in each of the memory devices (memory device_11 to memory device_14) among the memory blocks included in each of the memory devices. A storage device (50) that stores data in units of super blocks may perform operations on the multiple memory devices (memory device_11 to memory device_14) simultaneously. For example, the storage device (50) may perform operations on the multiple memory devices (memory device_11 to memory device_14) in parallel using an interleaving method.

[0126] A single super block can be composed of multiple stripes. The term "stripe" may be used interchangeably with "super page."

[0127] A single stripe or super page may include multiple pages. For example, the first pages (Page 1) included in each of the multiple first memory blocks (BLK1) included in the first super block (Super Block 1) may constitute the first stripe (Stripe 1) or the first super page (Super Page 1).

[0128] Accordingly, one super block may include a first stripe (Stripe 1) to an nth stripe (Stripe n). Or, one super block may include a first super page (Super Page 1) to an nth super page (Super page n).

[0129] The memory controller (200) can store or read data in stripe units or super page units when storing data in memory devices_11 to memory devices_14 or reading stored data.

[0130] In an embodiment, the memory controller (200) may first program the page corresponding to the lower number among the first stripe (Stripe 1) to the nth stripe (Stripe n) included in the super block.

[0131] For example, the memory controller (200) can store data in a plurality of first pages (Page 1) included in a first stripe (Stripe 1). Subsequently, if there is no space to store data in the plurality of first pages (Page 1), the memory controller (200) can store data in a plurality of second pages included in a plurality of first memory blocks. Accordingly, the memory controller (200) can sequentially store data from the first stripe (Stripe 1) included in the super block to the nth stripe (Stripe n) through the method described above.

[0133] FIG. 8 is a drawing for explaining another embodiment of the super block of FIG. 7.

[0134] Referring to FIG. 8, memory device_11 represents memory device_11 among the plurality of memory devices (memory devices_11 to memory devices_14) described with reference to FIG. 2.

[0135] Memory device_11 may include a plurality of planes (Plane 1 to Plane n). One plane may include a plurality of memory blocks (BLK1 to BLKz).

[0136] A plane may be a unit that independently performs a program operation, a read operation, or an erase operation. Accordingly, the memory device_11 may include an address decoder and read and write circuits described below for each plane.

[0137] In an embodiment, a super block (SUPBK) may include at least two memory blocks included in different planes among memory blocks included in each of the multiple planes included in a single memory device. A memory device_11 that stores data in units of super blocks (SUPBK) can perform operations on multiple planes (Plane 1 to Plane n) simultaneously (Multi-Plane Operation). For example, the memory device_11 can perform operations on multiple planes (Plane 1 to Plane n) in parallel using an interleaving method.

[0138] Meanwhile, a sudden power off may occur while the storage device (50) is sequentially storing data in multiple pages (Page 1 to Page n) included in the super block. In this case, the storage device (50) can perform a sudden power off recovery operation through the sudden power off management unit (220) included in the memory controller (200).

[0139] At this time, conventional technology searches for the first erase page using a binary search method. A binary search method refers to a method of searching for the first erase page by dividing multiple word lines into two. However, this binary search method has the problem that the speed of the erase page search operation slows down as the number of word lines included in the memory block increases.

[0140] To solve these problems, the storage device (50) according to the embodiment utilizes a binary method, and can perform read operations for erasing page search in parallel in each of the multiple memory blocks. This will be explained in detail in FIGS. 9 and 10.

[0142] FIG. 9 is a drawing for explaining an example of an operation for determining the first erase page according to an embodiment of the present invention.

[0143] Referring to FIG. 9, the memory device (100) may include a super block. The super block (SB) may include at least two memory blocks (BLK1 to BLKz) that are included in different planes among memory blocks included in a plurality of planes. In one embodiment, the plurality of memory blocks (BLK1 to BLKz) may each be included in different planes. However, depending on the embodiment, the plurality of memory blocks (BLK1 to BLKz) may each be included in different memory devices. In an embodiment, the memory device (100) may first program pages corresponding to the word line having the lower number among the plurality of word lines (WL1 to WLn) in the super block (SB). Additionally, the memory device (100) may first program the memory block corresponding to the lower number among the plurality of memory blocks (BLK1 to BLKz) in the super block (SB).

[0144] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to perform a read operation on the h1 word line (WL_h1) located at an intermediate point among the plurality of word lines (WL1~WLn) in the first memory block (BLK) where data is first programmed among the plurality of memory blocks (BLK1~BLKz). The memory device (100) can perform a read operation on the h1 word line (WL_h1) in the first memory block (BLK1).

[0145] When a page corresponding to the h1 word line (WL_h1) is determined to be an erased page based on data read from the h1 word line (WL_h1), the Sudden Power Off Management Unit (220) may determine the first word line area (area 1) as an area for detecting the first erased page. At this time, the first word line area (area 1) is an area located above the h1 word line (WL_h1) and may include word lines from the first word line (WL1) where data is first programmed to the h1 word line (WL_h1). The second word line area (area 2) is an area located below the h1 word line (WL_h1) and may include word lines from the nth word line (WLn) where data is last programmed to the h1 word line (WL_h1).

[0146] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to perform a read operation on a plurality of selected word lines (WL_h2~WL_hn) in the remaining memory blocks (BLK2~BLKz) excluding the first memory block (BLK1) among the plurality of memory blocks (BLK1~BLKz). Each of the plurality of selected word lines (WL_h2~WL_hn) may be a word line located at an intermediate point between the first word line (WL1) and the h1 word line (WL_h1), or a word line located at an intermediate point between the first word line (WL1) and each of the plurality of selected word lines (WL_h2~WL_hn) and a different selected word line. For example, the second memory block (BLK2) may perform a read operation on the h2 word line (WL_h2). The h2 word line (WL_h2) may be a word line located at an intermediate point between the first word line (WL1) and the h1 word line (WL_h1). Additionally, the third memory block (BLK3) may perform a read operation on the h3 word line (WL_h3). The h3 word line (WL_h3) may be a word line located at an intermediate point between the first word line (WL1) and the h2 word line (WL_h2) where a read operation is to be performed in the previous memory block (BLK2). Additionally, the z memory block (BLKz) may perform a read operation on the hz word line (WL_hz). The hz word line (WL_hz) may be a word line located at an intermediate point between the first word line (WL1) and the hz-1 word line (WL_hz-1) where a read operation is to be performed in the previous memory block (BLKz-1). In other words, a specific memory block can perform a read operation on a word line located at an intermediate point between the first word line (WL1) and the word line to be performed in the previous memory block of the specific memory block.

[0147] Additionally, the memory device (100) can perform read operations on a plurality of selected word lines (WL_h2~WL_hn) in parallel from the remaining memory blocks (BLK2~BLKz). The memory device (100) can detect the first erased page based on the data read from the plurality of selected word lines (WL_h2~WL_hn).

[0149] FIG. 10 is a drawing for explaining another example of an operation to determine the first erase page according to one embodiment of the present invention.

[0150] A memory device (100) may include a super block. The super block (SB) may include at least two memory blocks (BLK1 to BLKz) that are included in different planes among memory blocks included in a plurality of planes. In one embodiment, the plurality of memory blocks (BLK1 to BLKz) may each be included in different planes. However, depending on the embodiment, the plurality of memory blocks (BLK1 to BLKz) may each be included in different memory devices. In an embodiment, the memory device (100) may first program pages corresponding to the word line having the lower number among the plurality of word lines (WL1 to WLn) in the super block (SB). Additionally, the memory device (100) may first program the memory block corresponding to the lower number among the plurality of memory blocks (BLK1 to BLKz) in the super block (SB).

[0151] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to perform a read operation on the h1 word line (WL_h1) located at an intermediate point among the plurality of word lines (WL1~WLn) in the first memory block (BLK) where data is first programmed among the plurality of memory blocks (BLK1~BLKz). The memory device (100) can perform a read operation on the h1 word line (WL_h1) in the first memory block (BLK1).

[0152] When a page corresponding to the h1 word line (WL_h1) is determined to be a program page based on data read from the h1 word line (WL_h1), the Sudden Power Off Management Unit (220) may determine the second word line area (area 2) as an area for detecting the first erased page. At this time, the first word line area (area 1) is an area located above the h1 word line (WL_h1) and may include word lines from the first word line (WL1) where data is first programmed to the h1 word line (WL_h1). The second word line area (area 2) is an area located below the h1 word line (WL_h1) and may include word lines from the n-th word line (WLn) where data is last programmed to the h1 word line (WL_h1).

[0153] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to perform a read operation on a plurality of selected word lines (WL_h2'~WL_hn') in the remaining memory blocks (BLK2~BLKz) excluding the first memory block (BLK1) among the plurality of memory blocks (BLK1~BLKz). Each of the plurality of selected word lines (WL_h2'~WL_hn') may be a word line located at an intermediate point between the n-th word line (WLn) and the h1-th word line (WL_h1), or a word line located at an intermediate point between the n-th word line (WLn) and a different selected word line among the plurality of selected word lines (WL_h2'~WL_hn'). For example, the second memory block (BLK2) may perform a read operation on the h2'-th word line (WL_h2'). The h2' word line (WL_h2') may be a word line located midway between the n word line (WLn) and the h1 word line (WL_h1). Additionally, the third memory block (BLK3) may perform a read operation on the h3' word line (WL_h3'). The h3' word line (WL_h3') may be a word line located midway between the n word line (WLn) and the h2' word line (WL_h2') where a read operation is to be performed in the previous memory block (BLK2). Additionally, the z memory block (BLKz) may perform a read operation on the hz' word line (WL_hz'). The hz' word line (WL_hz') may be a word line located at an intermediate point between the n word line (WLn) and the hz-1' word line (WL_hz-1') where a read operation is to be performed in the previous memory block (BLKz-1). In other words, a specific memory block may perform a read operation on a word line located at an intermediate point between the n word line (WLn) and the word line where a read operation is to be performed in the previous memory block of the specific memory block.

[0154] Additionally, the memory device (100) can perform read operations on a plurality of selected word lines (WL_h2'~WL_hn') in parallel from the remaining memory blocks (BLK2~BLKz). The memory device (100) can detect the first erased page based on the data read from the plurality of selected word lines (WL_h2'~WL_hn').

[0156] FIG. 11 is a diagram illustrating the configuration of a data set according to one embodiment of the present invention.

[0157] Referring to FIG. 11, the data set may be configured to include a Page Information area and a Data area.

[0158] The Page Information area can be generated by the program operation control unit (210) and may be composed of page information data. For example, the Page Information area may be composed of basic information of the page (Page Inform), status data (PV1 to PV7), and data on the number of erase / program cycles of the corresponding page (EW Cycle).

[0159] The data area may be composed of user data, Cyclic Redundancy Code (CRC), and ECC parity.

[0160] Additionally, the data area is scrambled by the program operation control unit (210), and the page information area may not be scrapable.

[0162] FIG. 12 is a diagram illustrating the program state of memory cells according to one embodiment of the present invention.

[0163] Referring to FIG. 12, the triple level cell (TLC) has a threshold voltage distribution of an erase state (PV0) and a plurality of programmed states (PV1 to PV7). The plurality of programmed states (PV1 to PV7) can be programmed sequentially during programming operations.

[0164] Accordingly, each of the state data (PV1 to PV7) in FIG. 11 is a data value corresponding to a plurality of program states in FIG. 12, and the state data (PV1 to PV7) can be set to a value of "0" corresponding to the program state during program operation. The state data (PV1 to PV7) can be programmed together when user data included in the data area is programmed on the selected page. For example, when data corresponding to PV1 among the user data is programmed, the state data (PV1) can be programmed; when data corresponding to PV2 among the user data is programmed, the state data (PV2) can be programmed; and when data corresponding to PV7 among the user data is programmed, the state data (PV7) can be programmed. Accordingly, the data values ​​included in the state data of a completed program page can indicate whether the program is executed and whether a sudden power-off occurs during the program operation. For example, if all the data values ​​included in the read state data have a value of "0", the corresponding page can be determined as a completed program page. Additionally, if all data values ​​included in the read state data are "1", the corresponding page may be determined as an erased page. Furthermore, if the data values ​​included in the read state data contain a mixture of "0" and "1" values, the corresponding page may be determined as an initial erased page.

[0165] Meanwhile, although FIGS. 11 and 12 describe the memory cell as a triple-level cell, the same applies when the memory cell is a single-level cell (SLC), a multi-level cell (MLC), or a quad-level cell (QLC).

[0167] FIG. 13 is a diagram illustrating an area where page information is stored in a memory block according to an embodiment of the present invention.

[0168] Referring to FIG. 13, a memory block (e.g., BLK1) can be divided into a first block area (B0) and a second block area (B1), and the first block area (B0) and the second block area (B1) can be divided by dividing each of the multiple pages included in the memory block in half.

[0169] In one embodiment, the sudden power off management unit (220) can control the memory device (100) to read a portion of the area based on a half-page sensing method during a read operation for any one word line and a read operation for a plurality of selected word lines. For example, during a read operation using a half-page sensing method, only a portion of the first block area (B0) and the second block area (B1) (e.g., B0) may be selected and the read operation may be performed.

[0170] In addition, some areas among the multiple memory blocks may store status data during program operation. For example, a portion of the first block area (B0) selected during a half-page sensing read operation may be defined as a Status Cell Area, and the status data (PV1 to PV7) of FIG. 11 corresponding to each page may be stored in the Status Cell Area. Additionally, each of the status data (PV1 to PV7) may have a column address (Col 1 to Col 7) assigned to it and be stored in memory cells included in the Status Cell Area corresponding to the column address.

[0172] FIG. 14 is a diagram illustrating data values ​​corresponding to a plurality of program states included in page information according to an embodiment of the present invention. FIG. 15 is a diagram illustrating page information values ​​according to page states according to an embodiment of the present invention.

[0173] Referring to FIGS. 14 and 15, data values ​​included in the status data during program operation may be initially set to "0". Data values ​​included in the status data read from a page where the program has been completed normally may all have a value of "0". Data values ​​included in the status data read from a page where the program operation has not been performed may all have a value of "1". On the other hand, data values ​​included in the status data read from a page where a sudden power off occurred during the program operation may contain a mixture of "0" and "1" values. For example, if an SPO occurs during the program operation corresponding to PV4, the data values ​​corresponding to PV1, PV2, and PV3 may have a value of "0", and the data values ​​corresponding to PV4, PV5, PV6, and PV7 may have a value of "1".

[0175] FIG. 16 is a flowchart for explaining the operation method of a storage device according to one embodiment of the present invention.

[0176] The method illustrated in FIG. 16 can be performed, for example, by the storage device of FIG. 1.

[0177] Referring to FIG. 16, in step S1601, the storage device (50) can detect a sudden power off.

[0178] In step S1603, the storage device (50) can perform a read operation on a first word line located at an intermediate point among a plurality of word lines in a first memory block where data is first programmed among a plurality of memory blocks.

[0179] In one embodiment, the storage device (50) can read a portion of the first memory block based on a half-sensing method. At this time, the portion may include state data.

[0180] In step S1605, the storage device (50) may determine one of the first word line areas and the second word line area based on data read from the first word line. At this time, the first word line area may include word lines from the start word line to the first word line among a plurality of word lines. The second word line area may include word lines from the last word line to the first word line among a plurality of word lines.

[0181] In step S1607, the storage device (50) can perform read operations in parallel on a plurality of selected word lines among the word lines included in a word line area determined in the second memory blocks, excluding the first memory block among the plurality of memory blocks. In one embodiment, the storage device (50) can read a portion of the second memory blocks based on a half-sensing method. At this time, the portion may include state data.

[0182] In step S1609, the storage device (50) can detect the first erased page based on the result of a read operation for a plurality of selected word lines. For example, if the read state data includes a data value corresponding to a program cell state for a plurality of program states, the storage device (50) can determine that the page corresponding to the word line from which the state data was read is a program page. Additionally, if the read state data includes a data value corresponding to an erase cell state for a plurality of program states, the storage device (50) can determine that the page corresponding to the word line from which the state data was read is an erased page. Additionally, if the read state data includes both a data value corresponding to a program cell state and a data value corresponding to an erase cell state, the storage device (50) can determine that the page corresponding to the word line from which the state data was read is the first erased page.

[0184] FIG. 17 is a diagram illustrating the operation of determining the first erase page according to an embodiment of the present invention.

[0185] In one embodiment, FIG. 17 may be a drawing illustrating step S1605 of FIG. 16.

[0186] The method illustrated in FIG. 17 can be performed, for example, by the storage device of FIG. 1.

[0187] Referring to FIG. 17, in step S1701, the storage device (50) can determine whether the page corresponding to the first word line is an erase page. For example, the storage device (50) can determine the page corresponding to the first word line as an erase page or a program page based on data read from the first word line.

[0188] According to the result of the determination in step S1701, if the page corresponding to the first word line is an erased page, in step S1703, the storage device (50) may determine the first word line area as any one word line area. In this case, a plurality of selected word lines may be included in the first word line area. For example, each of the plurality of selected word lines may be a word line located at an intermediate point between the start word line and the first word line, or a word line located at an intermediate point between the start word line and a different selected word line among the plurality of selected word lines.

[0189] According to the result of the determination in step S1701, if the page corresponding to the first word line is not an erased page, in step S1705, the storage device (50) may determine the second word line area as any one of the word line areas. In this case, a plurality of selected word lines may be included in the second word line area. For example, each of the plurality of selected word lines may be a word line located at an intermediate point between the last word line and the first word line, or a word line located at an intermediate point between the last word line and a selected word line different from each of the plurality of selected word lines.

[0191] FIG. 18 is a drawing for explaining a memory controller according to one embodiment of the present invention.

[0192] The memory controller (1000) of FIG. 18 may represent the memory controller (200) of FIG. 1.

[0193] Referring to FIGS. 1 and FIGS. 18, the memory controller (1000) may include a processor (1010), RAM (1020), an error correction circuit (1030), ROM (1040), a host interface (1050), and a flash interface (1060).

[0194] The processor (1010) can control the general operations of the memory controller (1000). The RAM (1020) can be used as a buffer memory, cache memory, operation memory, etc. of the memory controller (1000).

[0195] The error correction circuit (1030) can perform error correction. The error correction circuit (1030) can perform error correction encoding (ECC encoding) based on data to be written to the memory device through the flash interface (1060). The error correction encoded data can be transmitted to the memory device through the flash interface (1060). The error correction circuit (1030) can perform error correction decoding (ECC decoding) on ​​data received from the memory device through the flash interface (1060). For example, the error correction circuit (1030) can be included in the flash interface (1060) as a component of the flash interface (1060).

[0196] The ROM (1040) can store various information required for the operation of the memory controller (1000) in the form of firmware. In one embodiment, the program operation control unit (210) and the sudden power off management unit (220) described with reference to FIG. 1 can be implemented as firmware stored in the ROM (1040).

[0197] The memory controller (1000) can communicate with an external device (e.g., a host (300), an application processor, etc.) through the host interface (1050).

[0198] The memory controller (1000) can communicate with the memory device (100) through the flash interface (1060). The memory controller (1000) can transmit commands, addresses, and control signals, etc., to the memory device (100) and receive data through the flash interface (1060). For example, the flash interface (1060) may include a NAND interface.

[0200] FIG. 19 is a block diagram showing a memory card system to which a storage device according to one embodiment of the present invention is applied.

[0201] Referring to FIG. 19, the memory card system (2000) includes a memory controller (2100), a memory device (2200), and a connector (2300).

[0202] The memory controller (2100) is connected to the memory device (2200). The memory controller (2100) is configured to access the memory device (2200). For example, the memory controller (2100) may be configured to control the read, write, erase, and background operations of the memory device (2200). The memory controller (2100) is configured to provide an interface between the memory device (2200) and a host. The memory controller (2100) is configured to run firmware for controlling the memory device (2200). The memory controller (2100) may be implemented in the same way as the memory controller (200) described with reference to FIG. 1. The memory device (2200) may be implemented in the same way as the memory device (100) described with reference to FIG. 1.

[0203] For example, the memory controller (2100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0204] The memory controller (2100) can communicate with an external device through a connector (2300). The memory controller (2100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller (2100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (2300) may be defined by at least one of the various communication standards described above.

[0205] For example, the memory device (2200) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque-Magnetic RAM), etc.

[0206] The memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card. For example, the memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash card (CF), Smart Media card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0208] FIG. 20 is a block diagram showing a Solid State Drive (SSD) system to which a storage device according to one embodiment of the present invention is applied.

[0209] Referring to FIG. 20, the SSD system (3000) includes a host (3100) and an SSD (3200). The SSD (3200) transmits and receives signals with the host (3100) through a signal connector (3001) and receives power through a power connector (3002). The SSD (3200) includes an SSD controller (3210), a plurality of flash memories (3221 to 322n), an auxiliary power supply (3230), and a buffer memory (3240).

[0210] According to an embodiment of the present invention, the SSD controller (3210) can perform the function of the memory controller (200) described with reference to FIG. 1.

[0211] The SSD controller (3210) can control a plurality of flash memories (3221 to 322n) in response to a signal received from the host (3100). For example, the signal may be a signal based on an interface between the host (3100) and the SSD (3200). For example, the signal may be a signal defined by at least one of interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0212] The auxiliary power unit (3230) is connected to the host (3100) via a power connector (3002). The auxiliary power unit (3230) receives power from the host (3100) and can charge. The auxiliary power unit (3230) can provide power to the SSD (3200) when power supply from the host (3100) is not smooth. For example, the auxiliary power unit (3230) may be located inside the SSD (3200) or outside the SSD (3200). For example, the auxiliary power unit (3230) may be located on the main board and provide auxiliary power to the SSD (3200).

[0213] The buffer memory (3240) operates as a buffer memory of the SSD (3200). For example, the buffer memory (3240) may temporarily store data received from the host (3100) or data received from a plurality of flash memories (3221 to 322n), or may temporarily store metadata (e.g., mapping tables) of the flash memories (3221 to 322n). The buffer memory (3240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0215] FIG. 21 is a block diagram showing a user system to which a storage device according to one embodiment of the present invention is applied.

[0216] Referring to FIG. 21, the user system (4000) includes an application processor (4100), a memory module (4200), a network module (4300), a storage module (4400), and a user interface (4500).

[0217] The application processor (4100) can run components included in the user system (4000), an operating system (OS), or user programs, etc. For example, the application processor (4100) may include controllers, interfaces, graphics engines, etc. that control components included in the user system (4000). The application processor (4100) may be provided as a system-on-chip (SoC).

[0218] The memory module (4200) can operate as the main memory, operational memory, buffer memory, or cache memory of the user system (4000). The memory module (4200) may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc. or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. For example, the application processor (4100) and the memory module (4200) may be packaged based on POP (Package on Package) and provided as a single semiconductor package.

[0219] The network module (4300) can communicate with external devices. For example, the network module (4300) can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the network module (4300) can be included in the application processor (4100).

[0220] The storage module (4400) can store data. For example, the storage module (4400) can store data received from the application processor (4100). Alternatively, the storage module (4400) can transfer data stored in the storage module (4400) to the application processor (4100). For example, the storage module (4400) can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, or a three-dimensional NAND flash. For example, the storage module (4400) can be provided as a removable storage medium such as a memory card or an external drive of the user system (4000).

[0221] For example, the storage module (4400) may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as the memory device (100) described with reference to FIG. 1. The storage module (4400) may operate in the same manner as the storage device (50) described with reference to FIG. 1.

[0222] The user interface (4500) may include interfaces for inputting data or commands to the application processor (4100) or outputting data to an external device. For example, the user interface (4500) may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, etc. The user interface (4500) may include user output interfaces such as an LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display, AMOLED (Active Matrix OLED) display, LED, speaker, monitor, etc. Explanation of the symbols

[0223] 50: Storage device 100: Memory device 131: Page Information Detector 200: Memory controller 210: Program operation control unit 220: Sudden Power Off Management Department 300: Host

Claims

Claim 1 A storage device comprising: a plurality of memory blocks connected to a plurality of word lines and included in a plurality of different planes; and a sudden power-off management unit that, when a sudden power-off occurs, controls the memory device to perform a read operation for one of the plurality of word lines in one of the memory blocks, determines one of the word line regions based on data read from one of the word lines, among a first word line region located above the one of the word lines and a second word line region located below the one of the word lines, controls the memory device to perform read operations for a plurality of selected word lines among the word lines included in the determined word line region in parallel for the remaining memory blocks excluding the one of the plurality of memory blocks according to an interleaving method, and detects an initial erase page located at the boundary between a program page and an erase page based on data read from the plurality of selected word lines. Claim 2 In claim 1, the storage device wherein any one of the memory blocks is the memory block among the plurality of memory blocks where data is first programmed. Claim 3 In claim 1, the storage device wherein any one of the word lines is a word line located at an intermediate point among the plurality of word lines. Claim 4 A storage device according to claim 1, wherein the first word line area comprises word lines from a start word line corresponding to the page where data is first programmed among the plurality of word lines to any one word line, and the second word line area comprises word lines from a last word line corresponding to the page where data is last programmed among the plurality of word lines to any one word line. Claim 5 In claim 4, the sudden power off management unit controls the remaining memory blocks to perform a read operation for a plurality of selected word lines among the word lines included in the first word line area in the remaining memory blocks when the page corresponding to any one word line is determined to be an erased page based on data read from any one word line. Claim 6 A storage device according to claim 5, wherein each of the plurality of selected word lines is a word line located at an intermediate point between the start word line and any one of the word lines, or a word line located at an intermediate point between the start word line and a selected word line different from each of the plurality of selected word lines. Claim 7 In claim 4, the sudden power off management unit controls the remaining memory blocks to perform a read operation for a plurality of selected word lines among the word lines included in the second word line area in the remaining memory blocks when the page corresponding to any one word line is determined to be a program page based on data read from any one word line. Claim 8 A storage device according to claim 7, wherein each of the plurality of selected word lines is a word line located at an intermediate point between the last word line and any one of the word lines, or a word line located at an intermediate point between a selected word line different from each of the plurality of selected word lines and the last word line. Claim 9 delete Claim 10 A storage device further comprising: a program operation control unit in claim 1, which generates program data by scrambling and decoding data received from a host during program operation, generates at least one data set using the program data and page information data, and controls the plurality of memory blocks to program the at least one data set into the plurality of pages included in the plurality of memory blocks. Claim 11 A storage device according to claim 10, wherein the page information data includes basic information of the page to be stored in which the data set is stored, the number of erase / program cycles, and status data for determining the program state of the page, and wherein the status data includes data values ​​corresponding to each of the multiple program states in which the program data is programmed into memory cells included in the plurality of pages, and wherein the data values ​​corresponding to each of the multiple program states include data values ​​corresponding to the program cell state of the memory cells or data values ​​corresponding to the erase cell state of the memory cells. Claim 12 A storage device according to claim 11, wherein a portion of the plurality of memory blocks stores state data during the program operation, and the sudden power-off management unit controls the plurality of memory blocks to read the portion based on a half-sensing method during a read operation for any one word line and a read operation for the plurality of selected word lines. Claim 13 In claim 11, the sudden power off management unit is a storage device that controls the plurality of memory blocks to read the page information data during a read operation for any one word line and a read operation for the plurality of selected word lines. Claim 14 A storage device according to claim 13, wherein the sudden power off management unit determines that if the read page information data includes a data value corresponding to the program cell state for the plurality of program states, the page corresponding to the word line from which the page information data was read is a program page; if the read page information data includes a data value corresponding to the erase cell state for the plurality of program states, the page corresponding to the word line from which the page information data was read is an erase page; and if the read page information data includes both the data value corresponding to the program cell state and the data value corresponding to the erase cell state, the page corresponding to the word line from which the page information data was read is the initial erase page. Claim 15 A method of operation of a storage device for controlling the operation of multiple memory blocks connected to multiple word lines and included in different planes, comprising: a step of detecting a sudden power off; a step of performing a read operation for a first word line located at an intermediate point among the multiple word lines in a first memory block in which data is first programmed among the multiple memory blocks; a step of determining one word line area among a first word line area located above the first word line and a second word line area located below the first word line based on data read from the first word line; a step of performing a read operation for a plurality of selected word lines among the word lines included in the determined word line area in second memory blocks excluding the first memory block among the multiple memory blocks according to an interleaving method; and a step of detecting an initial erase page located at the boundary between a program page and an erase page based on the result of the read operation for the plurality of selected word lines. Claim 16 A method of operation of a storage device according to claim 15, wherein the first word line area comprises word lines from a start word line corresponding to the page where data is first programmed among the plurality of word lines to the first word line, and the second word line area comprises word lines from a last word line corresponding to the page where data is last programmed among the plurality of word lines to the first word line. Claim 17 A method of operation of a storage device according to claim 16, wherein the step of determining any one word line area comprises: determining a page corresponding to the first word line as an erase page based on data read from the first word line; and determining the first word line area as any one word line area in response to the fact that the page corresponding to the first word line is an erase page. Claim 18 A method of operation of a storage device according to claim 17, wherein each of the plurality of selected word lines is a word line located at an intermediate point between the start word line and the first word line, or a word line located at an intermediate point between the start word line and a selected word line different from each of the plurality of selected word lines. Claim 19 A method of operation of a storage device according to claim 16, wherein the step of determining any one word line area comprises: determining a page corresponding to the first word line as a program page based on data read from the first word line; and determining a second word line area as any one word line area in response to the fact that the page corresponding to the first word line is the program page. Claim 20 A method of operation of a storage device according to claim 19, wherein each of the plurality of selected word lines is a word line located at an intermediate point between the last word line and the first word line, or a word line located at an intermediate point between the last word line and a selected word line different from each of the plurality of selected word lines.

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