Method and system for testing and manufacturing semiconductor device

Abstract

A method for testing a semiconductor device may include: a step of obtaining first data generated by testing wafers each containing a plurality of chips based on a plurality of first items; a step of obtaining second data generated by testing packages each containing a packaged chip based on a plurality of second items; a step of detecting correlations between a plurality of first items and a plurality of second items based on the first data and the second data; a step of identifying at least one first item that affects variations of packages based on the correlations; and a step of verifying at least one identified first item.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a semiconductor device, and more specifically, to a method and system for testing and manufacturing a semiconductor device. Background Technology

[0002] Semiconductor devices can be manufactured through various sub-processes included in the semiconductor manufacturing process. As the integration density of semiconductor devices increases, the complexity of the semiconductor process may increase, and even when manufactured using the same process, devices may exhibit variations due to various factors. To detect these variations, the semiconductor process may include sub-processes for testing the devices; however, testing every single device can incur significant time and cost. Accordingly, there is a need for methods to test semiconductor devices accurately and efficiently. The problem to be solved

[0003] The technical concept of the present disclosure provides a method and system for accurately and efficiently testing a semiconductor device and manufacturing a semiconductor by detecting factors that affect variations in a semiconductor device. means of solving the problem

[0004] A method for testing a semiconductor device according to one aspect of the technical concept of the present disclosure may include: obtaining first data generated by testing wafers each comprising a plurality of chips based on a plurality of first items; obtaining second data generated by testing packages each comprising a packaged chip based on a plurality of second items; detecting correlations between a plurality of first items and a plurality of second items based on the first data and the second data; and identifying at least one first item that affects variations of the packages based on the correlations.

[0005] A system according to one aspect of the technical concept of the present disclosure may include at least one processor and a non-transient computer-readable medium storing a series of instructions, and the at least one processor may perform the steps of: obtaining first data generated by testing wafers each comprising a plurality of chips based on a plurality of first items by executing a series of instructions; obtaining second data generated by testing packages each comprising a packaged chip based on a plurality of second items; detecting correlations between a plurality of first items and a plurality of second items based on the first data and the second data; and identifying at least one first item that affects variations of packages based on the correlations.

[0006] According to one aspect of the technical concept of the present disclosure, a non-transient computer readable medium storing a series of instructions executed by at least one processor, wherein the series of instructions, when executed by at least one processor, can cause at least one processor to perform a method of testing a semiconductor device, and the method of testing a semiconductor device may include the steps of: obtaining first data generated by testing wafers each comprising a plurality of chips based on a plurality of first items; obtaining second data generated by testing packages each comprising a packaged chip based on a plurality of second items; detecting correlations between a plurality of first items and a plurality of second items based on the first data and the second data; and identifying at least one first item that affects variations of packages based on the correlations. Effects of the invention

[0007] According to the method and system of the exemplary embodiment of the present disclosure, factors causing variation in a semiconductor device can be accurately detected, and the time and cost of the semiconductor process can be reduced by predicting variation in the semiconductor device at an early stage.

[0008] In addition, according to the method and system of the exemplary embodiment of the present disclosure, factors corresponding to various requirements for variations in a semiconductor device can be accurately detected, and by selecting an appropriate factor among the detected factors, a semiconductor process optimal for the requirements of the semiconductor device can be designed.

[0009] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0010] FIG. 1 is a drawing showing a semiconductor process according to an exemplary embodiment of the present disclosure. FIG. 2 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 3 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 4 is a diagram illustrating an operation of processing second data according to an exemplary embodiment of the present disclosure. FIG. 5 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. FIGS. 6a and FIGS. 6b are graphs showing package defect rates according to exemplary embodiments of the present disclosure. FIG. 7 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. FIGS. 8a and FIGS. 8b are drawings illustrating examples of categories according to exemplary embodiments of the present disclosure. FIGS. 9a and 9b are graphs showing package defect rates according to exemplary embodiments of the present disclosure. FIG. 10 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 11 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 12 shows a graph of receiver operating characteristics (ROC) according to an exemplary embodiment of the present disclosure. FIGS. 13a to 13d are graphs showing examples of ROC curves according to exemplary embodiments of the present disclosure. FIG. 14 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 15 is a block diagram showing a computer system according to an exemplary embodiment of the present disclosure. FIG. 16 is a block diagram showing a system according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0011] FIG. 1 is a drawing illustrating a semiconductor process (10) according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 1, a plurality of packages (P) may be produced from a wafer (W) in the semiconductor process (10). In this specification, the semiconductor device may collectively refer to a wafer (W), a chip (or die) included in the wafer (W), and a package representing a packaged chip.

[0012] A wafer (W) may include a plurality of chips. For example, as illustrated in FIG. 1, a chip (C) may be formed through various sub-processes and may be referred to as a die. For example, the front-end-of-line (FEOL) may include steps such as planarizing and cleaning the wafer (W), forming a trench, forming a well, forming a gate electrode, forming a source and a drain, and individual components, such as transistors, capacitors, resistors, etc., may be formed by the FEOL. Additionally, the back-end-of-line (BEOL) may include steps such as silicidating gate, source, and drain regions, adding a dielectric, planarizing, forming holes, adding a metal layer, forming vias, and forming a passivation layer, and through the BEOL, individual devices, such as transistors, capacitors, resistors, etc., may be interconnected. In some embodiments, a middle-of-line (MOL) may be performed between the front-end-of-line (FEOL) and the back-end-of-line (BEOL), and contacts may be formed on the individual devices.

[0013] Referring to FIG. 1, a wafer test (12) may be performed on a wafer (W). Unlike the package test (16) described later, the wafer test (12) may be performed on a wafer (W) containing a plurality of chips. As illustrated in FIG. 1, the wafer test (12) may be performed based on first items (ITM1). The first items (ITM1) may refer to test items of the wafer (W) and may include thousands of test items in some embodiments. For example, the first items (ITM1) may include functional test items and parametric test items. Functional test items may be used to test the operation of the chip and may define, for example, input signals applied to the chip and corresponding output signals. Parameter test items can be used to test the electrical characteristics of the chip, and for example, input voltage applied to the chip and corresponding output current, input current applied to the chip and corresponding output voltage, etc. can be defined.

[0014] A first data (TD1) may be generated by a wafer test (12), and the first data (TD1) may include the test results of the wafer (W). For example, the first data (TD1) may include values ​​corresponding to each of the first items (ITM1). The values ​​included in the first data (TD1) may correspond to the wafer (W) and may represent the attributes of the wafer (W). In some embodiments, if the first data (TD1) containing a value outside the normal range occurs, the wafer (W) corresponding to the first data (TD1) may be determined to be defective and may be excluded from the packaging (14) described below.

[0015] Packaging (14) may be performed on a plurality of chips contained in a wafer (W), and a plurality of packages (P) may be created. Through packaging (14), protective layers and electrical connections may be added to each of the plurality of chips. In some embodiments, a plurality of chips may be separated from the wafer (W) by dicing, and a plurality of packages (P) may be created by performing packaging (14) on the separated plurality of chips. In some embodiments, packaging (14) may be performed on a plurality of chips contained in a wafer (W), and a plurality of packages (P) may be created by dicing. Packaging (14) followed by dicing may be referred to as wafer-level packaging.

[0016] Package testing (16) may be performed on a plurality of packages (P). Unlike the wafer testing (12) described above, package testing (16) may be performed on a plurality of packages (P) corresponding to each of the plurality of chips included in the wafer (W). As illustrated in FIG. 1, package testing (16) may be performed based on second items (ITM2). The second items (ITM2) may refer to test items for each of the plurality of packages (P) and may include hundreds of test items in some embodiments. For example, the second items (ITM2) may include functional test items and parameter test items. Functional test items may be used to test the operation of the package, and, for example, if the package is a semiconductor memory device, may define programming time, erase time, write cycle timing, etc. Parameter test items can be used to test the electrical characteristics of the package and may include, for example, open tests, short tests, input / output leakage tests, etc.

[0017] Second data (TD2) may be generated by a package test (16), and the second data (TD2) may include test results of a plurality of packages (P). For example, the second data (TD2) may include values ​​corresponding to each of the second items (ITM2) in each of the plurality of packages (P). The values ​​included in the second data (TD2) may correspond to the plurality of packages (P) and may represent the attributes of the plurality of packages (P). In some embodiments, if the second data (TD2) containing a value outside the normal range occurs, the package corresponding to the value may be determined to be defective and excluded from shipment.

[0018] Sampling tests, which select and test only a portion of the semiconductor devices, may have limitations in supplying semiconductor devices with high reliability required by the user. For example, in order to continuously monitor quality deviations among wafers that have passed the wafer test (12), additional tests may be performed on wafers sampled from wafers within the statistical bin limit (SBL) based on the first data (TD1). However, such sampling may have limitations in testing semiconductor devices with high reliability (e.g., a defect rate of less than a few ppm). On the other hand, testing all semiconductor devices, such as all packages that have passed the packaging (14), may consume a lot of cost and time, and consequently reduce the efficiency of the semiconductor process (10).

[0019] As described below with reference to the drawings, a method for testing and manufacturing a semiconductor device can detect a correlation between first items (ITM1) used for wafer testing (12) and second items (ITM2) used for package testing (16), and based on the detected correlation, at least one first item that affects the variation of a plurality of packages (P) among the first items (ITM1) can be identified. Through the identified at least one first item, the quality of the semiconductor device can be effectively controlled prior to packaging (14), unnecessary packaging (14) and package testing (16) can be eliminated, and consequently, the efficiency of the semiconductor process (10) can be increased. Furthermore, the semiconductor process (10) can be efficiently monitored even while manufacturing the semiconductor devices, and accordingly, quality degradation that may occur within the SBL due to unforeseen factors can be detected, and the quality deviation of the semiconductor devices can be effectively managed.

[0020] FIG. 2 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 2, the method for testing a semiconductor device may include a plurality of steps (S20, S40, S60). Hereinafter, FIG. 2 will be described with reference to FIG. 1.

[0021] In some embodiments, the method of FIG. 2 may be implemented by a computing system described below with reference to FIG. 15 and FIG. 16. For example, each of the blocks illustrated in the drawings of this specification may correspond to hardware, software, or a combination of hardware and software included in the computing system. In some embodiments, the hardware may include at least one of a programmable component such as a CPU (central processing unit), a DSP (digital signal processor), a GPU (graphics processing unit), a reconfigurable component such as a field programmable gate array (FPGA), and a component providing fixed functions such as an IP (intellectual property) block. In some embodiments, the software may include at least one of a series of instructions executable by the programmable component and code convertible into a series of instructions by a compiler, etc., and may be stored on a non-transitory storage medium.

[0022] Referring to FIG. 2, in step S20, first data (TD1) and second data (TD2) may be obtained. As described above with reference to FIG. 1, the first data (TD1) may be generated by performing a wafer test (12) based on first items (ITM1), and the second data (TD2) may be generated by performing a package test (16) based on second items (ITM2). In FIG. 2, the first data (TD1) may refer to data generated by testing a plurality of wafers, and the second data (TD2) may refer to data generated by testing a plurality of packages generated from a plurality of wafers.

[0023] In step S40, correlations between the first items (ITM1) and the second items (ITM2) may be detected. For example, correlations between the first items (ITM1) and the second items (ITM2) may be detected based on the first data (TD1) and the second data (TD2) obtained in step S20. In this specification, a correlation between the first item and the second item may mean that the value of the second item and the value of the first item have a relationship (e.g., dependency). In step S40, a plurality of correlations may be detected, and each of the plurality of correlations may include a pair of the first item and the second item. Examples of step S40 will be described later with reference to FIGS. 3 and FIGS. 5.

[0024] In step S60, at least one first item affecting package variation may be identified. For example, among the correlations detected in step S40, at least one correlation affecting package defect may be identified, and at least one first item corresponding to at least one correlation may be identified. The identified at least one first item may be used in the testing and manufacturing of a semiconductor device. For example, as described below with reference to FIGS. 13a through 13d, the first item may affect package variation in various ways, and accordingly, at least one first item advantageous for screening package defects may be identified. An example of step S60 will be described below with reference to FIG. 11.

[0025] FIG. 3 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure, and FIG. 4 is a diagram illustrating an operation for processing second data (TD2) according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 3 illustrates an example of step S40 of FIG. 2, and FIG. 4 illustrates an example of an operation performed by step S44 of FIG. 3. As described above with reference to FIG. 2, correlations between first items (ITM1) and second items (ITM2) can be detected in step S40' of FIG. 3. Hereinafter, FIG. 3 and FIG. 4 will be described with reference to FIG. 1.

[0026] Referring to FIG. 3, step S40' may include steps S42 and S44. In step S42, the first data (TD1) and the second data (TD2) may be filtered. For example, noise may be removed from the first data (TD1) and the second data (TD2). In some embodiments, at least one first item among the first items (ITM1) that is unrelated to package variation may be identified, and values ​​among the values ​​included in the first data (TD1) that correspond to the identified at least one first item may be removed. Similarly, at least one second item among the second items (ITM2) that is unrelated to wafer test (12) (e.g., a second item for testing an effect purely caused by packaging (14)) may be identified, and values ​​among the values ​​included in the second data (TD2) that correspond to the identified at least one second item may be removed. In some embodiments, outliers among the values ​​included in the first data (TD1) and the second data (TD2) that are caused by test errors, etc., may be removed. For example, outliers may be detected based on statistical values ​​(e.g., mean, variance, etc.) of the first items (ITM1) and the second items (ITM2).

[0027] In step S44, values ​​included in the second data (TD2) may be grouped. As described above with reference to FIG. 2, the first data (TD1) collected in the method for testing a semiconductor device may correspond to a plurality of wafers, and the second data (TD2) may correspond to a plurality of packages generated from the plurality of wafers. In order to detect correlations between the first items (ITM1) and the second items (ITM2), the values ​​included in the second data (TD2) may be grouped such that the values ​​of packages corresponding to the same wafer are included in the same group.

[0028] Referring to FIG. 4, a plurality of first packages (P1) to a plurality of n packages (Pn) may each be generated from a first wafer (W1) to an n wafer (Wn) (n is an integer greater than 1). A second data (TD2) may be generated by performing a package test (16) on the plurality of first packages (P1) to a plurality of n packages (Pn). As illustrated in FIG. 4, the values ​​of the second data (TD2) may be grouped into a first group (G1) to an n group (Gn) corresponding to each of the plurality of first packages (P1) to a plurality of n packages (Pn), and accordingly, the second data (TD2) may include the first group (G1) to the n group (Gn). In some embodiments, the grouping of values ​​included in the second data (TD2) may be performed by adding the same label to values ​​included in the same group. For example, the values ​​included in the first group (G1) may include a label representing the first group (G1).

[0029] FIG. 5 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 5 illustrates an example of step S40 of FIG. 2. As described above with reference to FIG. 2, correlations between first items (ITM1) and second items (ITM2) may be detected in step S40" of FIG. 5. As illustrated in FIG. 5, step S40" may include steps S46 and S48. In some embodiments, steps S46 and S48 of FIG. 5 may be performed following step S44 of FIG. 3. Step S40" of FIG. 5 may be performed for a selected first item among the first items (ITM1) and may be repeated for each of the first items (ITM1). Hereinafter, FIG. 5 will be described with reference to FIG. 1.

[0030] In step S46, multiple categories may be established in the first item. For example, multiple categories may be established in each of the first items (ITM1) based on the first data (TD1). The values ​​included in the first data (TD1) may have various distributions depending on the first item. Multiple categories may be established based on the values ​​of the first item, and the values ​​of the second items (ITM2) corresponding to each of the multiple categories may be analyzed. An example of step S46 will be described later with reference to FIG. 7, and examples of categories will be described later with reference to FIG. 8a and FIG. 8b.

[0031] In step S48, correlations between the first item and the second items (ITM2) can be identified. For example, wafers can be grouped based on multiple categories set in step S46, and values ​​corresponding to different wafer groups among the values ​​of the second items (ITM2) included in the second data (TD2) can be separated. Accordingly, as described below with reference to FIGS. 6a and 6b, the influence of the first items (ITM1) used in the wafer test (12) on package variation can be detected. An example of step S48 will be described below with reference to FIG. 10.

[0032] FIGS. 6a and 6b are graphs showing package defect rates according to exemplary embodiments of the present disclosure. Specifically, the graphs of FIGS. 6a and 6b represent test results measured in a semiconductor process each week. The graph in FIG. 6a represents the package defect rate measured in the semiconductor process, and the graph in FIG. 6b represents the defect rates of packages corresponding to each wafer group. That is, the defect rate represented by the curve in FIG. 6a may correspond to the sum of the defect rates represented by the curves in FIG. 6b. Although the wafers in FIG. 6b are grouped into five groups based on five categories, it is noted that the wafers may be grouped into two or more wafer groups.

[0033] Referring to FIG. 6a, it may not be easy to detect changes in the package defect rate over time. Furthermore, even if a change in the package defect rate, such as a slight increasing trend, is detected, it may not be easy to detect the cause of the package defect rate. On the other hand, referring to FIG. 6b, wafer groups may have similar package defect rates up to time point (T6), while having different package defect rates from time point (T6). As described above with reference to FIG. 5, wafer groups may correspond to categories set based on the values ​​of the first item, and accordingly, wafer groups may each include a different number of wafers. For example, in FIG. 6b, if the number of wafers included in the first wafer group (WG1) and the second wafer group (WG2), where the package defect rate increases significantly from time point (T6), is less than 5% of the total wafers, and the number of wafers included in the fifth wafer group (WG5), where the increase in the defect rate is weak, is more than 90% of the total wafers, then the increase in the overall package defect rate may not be easily detected, as shown in the curve of FIG. 6b. However, as illustrated in FIG. 6b, when wafers are grouped based on categories, the first wafer group (WG1) and the second wafer group (WG2) can be detected, and accordingly, the first item of the categories can be identified as affecting the package defect.

[0034] FIG. 7 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure, and FIGS. 8a and 8b are drawings illustrating examples of categories according to exemplary embodiments of the present disclosure. Specifically, the flowchart of FIG. 7 illustrates an example of step S46 of FIG. 5, and FIGS. 8a and 8b illustrate examples of categories set in different first items, respectively. As described above with reference to FIG. 5, a plurality of categories of the first item may be set in step S46' of FIG. 7. Hereinafter, FIGS. 7, FIGS. 8a, and 8b will be described with reference to FIG. 1.

[0035] Referring to FIG. 7, step S46' may include a plurality of steps (S46_2, S46_4, S46_6). In step S46_2, a distribution of wafers according to the value of the first item may be obtained. For example, as shown in FIG. 8a, the wafers may have values ​​of the first item concentrated between 0 and 10, and most of the wafers may have the lowest value. On the other hand, as shown in FIG. 8b, the wafers may have values ​​of the first item distributed between 0 and 100, and may be distributed relatively more widely than in the example of FIG. 8a.

[0036] Referring again to FIG. 7, threshold values ​​can be calculated in step S46_4, and multiple categories can be generated in step S46_4. The threshold values ​​can be used as criteria for generating multiple categories. For example, the threshold values ​​can divide the distribution of wafers into multiple bands, and the multiple bands can correspond to each of the multiple categories. Referring to FIG. 8a, if the wafers have values ​​of the first item concentrated within a limited range, the bands can also be concentrated within the values ​​of the first item within a limited range. Accordingly, as illustrated in FIG. 8a, the first to third categories (C1 to C3) can be concentrated within the values ​​of the first item between 0 and 10, and the fourth category (C4), which includes a relatively small number of wafers, can correspond to a wide band. Referring to FIG. 8b, if the wafers have values ​​of the first item distributed over a wide range, the bands can also be distributed over a wide range. Accordingly, as illustrated in FIG. 8b, the first to fourth categories (C1 to C4) can be defined relatively equally among the values ​​of the first item between 0 and 100.

[0037] In some embodiments, threshold values ​​may be calculated based on ratios. For example, based on the values ​​of a first item, a first threshold value corresponding to the top k1% of wafers (e.g., from the lower value of the first item) may be calculated, and a band defined according to the first threshold value may be set as a first category. Additionally, based on the values ​​of the first item, a second threshold value corresponding to k2% of the remaining (1-k1%) wafers (e.g., from the lower value of the first item) may be calculated, and a band defined according to the second threshold value may be set as a second category. In some embodiments, k1% and k2% may be determined based on experiments and / or simulations, etc., and the number of bands (i.e., the number of categories) may also be determined based on experiments and / or simulations, etc.

[0038] FIGS. 9a and 9b are graphs showing package defect rates according to exemplary embodiments of the present disclosure. Specifically, the graphs of FIGS. 9a and 9b show package defect rates measured for two wafer groups in a semiconductor process each week. In FIGS. 9a and 9b, the first wafer group (WG1) may correspond to the top 80% of wafers, and the second wafer group (WG2) may correspond to the bottom 20% of wafers. As previously described, if package defect rates are detected differently in the wafer groups, the first item defined for the wafer groups may be determined to be correlated with package defects.

[0039] Referring to FIG. 9a, the difference between the package defect rate of the first wafer group (WG1) and the package defect rate of the second wafer group (WG2) at time point (T91) may increase compared to before time point (T91). That is, package defects may increase due to factors occurring before and after time point (T91), and such factors may have a correlation with the first item defined for the first wafer group (WG1) and the second wafer group (WG2) of FIG. 9a.

[0040] Referring to FIG. 9b, a relatively high number of package defects may occur in the semiconductor process due to various factors up to time point (T92). From time point (T92), the semiconductor process can be stabilized and the package defect rate can be reduced by removing these factors. However, as shown in FIG. 9b, as time progresses, the difference between the package defect rate of the first wafer group (WG1) and the package defect rate of the second wafer group (WG2) may gradually increase, and in particular, an increase in the package defect rate of the second wafer group (WG2) may be detected.

[0041] As described above with reference to FIG. 1, the number of first items (ITM1) used in wafer testing (12) may be thousands or more, and a method for managing the quality of the semiconductor device with respect to the first items (ITM1) according to a certain standard may be required. Below, with reference to FIG. 10, a method of using a certain standard for the first items (ITM1) will be described later.

[0042] FIG. 10 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 10 illustrates an example of step S48 of FIG. 5. As described above with reference to FIG. 5, correlations between the first item and the second item can be identified in step S48' of FIG. 10. Referring to FIG. 10, step S48' may include a plurality of steps (S48_1 to S48_6). In some embodiments, step S48' may be performed periodically (e.g., weekly). Hereinafter, FIG. 10 will be described with reference to FIG. 1.

[0043] Referring to FIG. 10, the null hypothesis and the alternative hypothesis can be tested in step S48_1. In some embodiments, a statistical hypothesis test may be employed to apply a certain criterion to thousands of first items (ITM1). A statistical hypothesis test may refer to a method of determining the validity of a hypothesis using sample information regarding a hypothesis (i.e., the null hypothesis) that defines the actual value of the population, and may be simply referred to as a hypothesis test. For example, to employ a statistical hypothesis test, the null hypothesis H0 and the alternative hypothesis H1 may be defined as shown in [Equation 1] below.

[0044]

[0045]

[0046] In [Mathematical Equation 1], μ i may be the average of the package defect rates corresponding to the i-th wafer group, and μ j may be the average of the package defect rates corresponding to the j-th wafer group. In some embodiments, the j-th wafer group may include wafers superior to the i-th wafer group in the first item. Also, in some embodiments, unlike [Equation 1], the null hypothesis H0 is μ i ga μ j It can be defined as being within a certain range that includes.

[0047] In step S48_2, it can be determined whether to reject the null hypothesis. As illustrated in FIG. 10, if the null hypothesis is rejected, i.e., the average μ of the package defect rate of the i-th wafer group i a. Average μ of the package defect rate of the j-th wafer group j If it exceeds, the variable k may be increased by 1 in step S48_4. On the other hand, if the test of the null hypothesis is successful, the variable k may be reset to zero in step S48_3. The variable k may represent the number of times the null hypothesis is rejected consecutively, and accordingly, it may be increased by 1 when the null hypothesis is rejected, while it may be initialized when the null hypothesis is rejected.

[0048] If the null hypothesis is rejected, the variable k in step S48_5 may be compared with a predefined constant M. As illustrated in FIG. 10, if the variable k is different from the constant M, i.e., if the variable k is smaller than the constant M, step S48' may be terminated. On the other hand, if the variable k is the same as the constant M, i.e., if the null hypothesis is rejected M times in succession, step S48_6 may be performed subsequently.

[0049] In step S48_6, a correlation between the first item and the second item can be identified. The fact that the null hypothesis is rejected M times consecutively may mean that a difference has occurred between the package defect rate of the i-th wafer group and the package defect rate of the j-th wafer group. Accordingly, it may be determined that the second item defining the package defect rate has a dependency on the first item defined for the i-th wafer group and the j-th wafer group, and accordingly, it may be determined that there is a correlation between the first item and the second item.

[0050] FIG. 11 is a flowchart illustrating a method for testing a semiconductor device according to an exemplary embodiment of the present disclosure, and FIG. 12 illustrates a receiver operating characteristics (ROC) graph according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 11 illustrates an example of step S60 of FIG. 2, and FIG. 12 illustrates an example of an ROC graph used in step S60' of FIG. 11. As described above with reference to FIG. 2, at least one first item affecting the variation of the package can be identified in step S60' of FIG. 11. Hereinafter, FIG. 11 and FIG. 12 will be described with reference to FIG. 1.

[0051] Referring to FIG. 11, step S60' may include steps S62 and S64. In step S62, an ROC graph may be created. An ROC graph (or ROC space) may refer to a graph with the true positive rate on the Y-axis and the false positive rate on the X-axis. In some embodiments, an ROC curve may be drawn on the modified ROC graph to identify at least one first item affecting the package failure rate. In this specification, the modified ROC graph may be referred to as an S(screen-ability)-chart.

[0052] Referring to FIG. 12, the X-axis of the S-chart may represent the ratio of wafers predicted to have package failures in the first category, i.e., the predicted failure rate (PFR). The Y-axis of the S-chart may represent the ratio of packages screened out through predicted failures out of the total failures of the packages. The diagonal (RAN) of the graph may represent a random case, and the first region (R1) above the diagonal (RAN) may represent a case worse than the random case. Additionally, the second region (R2) above the diagonal (RAN) may indicate a more favorable result as it is further from the diagonal (RAN). For example, the third S-chart curve (ROC3) may indicate a more favorable result than the first S-chart curve (ROC1) and the second S-chart curve (ROC2).

[0053] Referring again to FIG. 11, the diagonal of the S-chart and the S-chart curve can be compared in step S64. As described above with reference to FIG. 12, the S-chart space can be divided into a lower first region (R1) and an upper second region (R2) of the diagonal (RAN), and if the S-chart curve is included in the diagonal (RAN) and the first region (R1), the first item can be determined not to affect package variation. On the other hand, if the S-chart curve is included in the second region (R2), the first item can be determined to affect package variation. The S-chart curve can be interpreted and utilized in various ways depending on its shape, and examples of S-chart curves will be described later with reference to FIG. 13a to 13d.

[0054] FIGS. 13a to 13d are graphs showing examples of S-chart curves according to exemplary embodiments of the present disclosure. As described above with reference to FIGS. 11 and 12, an S-chart curve can be drawn in an S-chart space having the ratio of wafers predicted to have package failures in the first item, i.e., the predicted failure rate (PFR), on the X-axis, and the ratio of the total failures of packages screened through the predicted failures on the Y-axis.

[0055] Referring to FIG. 13a, the S-chart curve may be located below the diagonal of the S-chart space. The diagonal of the S-chart space represents a random case, and the S-chart curve of FIG. 13a may represent a case worse than the random case. Accordingly, the first item corresponding to the S-chart curve of FIG. 13a may be determined not to affect package defects.

[0056] Referring to Fig. 13b, the S-chart curve may be located on the diagonal of the S-chart space. Although the S-chart curve in Fig. 13b shows better results than the random case, it may show results similar to the random case in the low PFR range. Accordingly, the first item corresponding to the S-chart curve can be determined not to affect package defects.

[0057] Referring to FIGS. 13c and 13d, S-chart curves may lie on the diagonal of the S-chart space across the entire range of PFR, while corresponding to different types. For example, the S-chart curve in FIG. 13c may be spaced further from the diagonal in the range of PFR higher than in the range of PFR lower, whereas the S-chart curve in FIG. 13d may be spaced further from the diagonal in the range of PFR lower than in the range of PFR higher. The S-chart curves corresponding to different types can be utilized appropriately as needed. For example, if the goal is to screen for less than 25% package defects, less than 10% of wafers can be determined as defective through the first item corresponding to the S-chart curve in FIG. 13c. On the other hand, if the goal is to screen for more than 50% package defects, fewer wafers can be determined as defective through the first item corresponding to the S-chart curve in FIG. 13d.

[0058] FIG. 14 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 14, the method for manufacturing a semiconductor device may include steps S82 and S84. In some embodiments, steps S82 and S84 of FIG. 14 may be performed subsequently to step S60 of FIG. 2. Hereinafter, FIG. 14 will be described with reference to FIG. 1.

[0059] Referring to FIG. 14, in step S82, chips predicted to be defective among a plurality of chips can be identified. For example, as described above with reference to the drawings, at least one first item (ITM1) that affects package defects among the first items used in wafer testing (12) can be identified. Chips predicted to be defective can be identified according to the value of the identified at least one first item, and accordingly, defects in the packages can be detected early before packaging (14).

[0060] In step S84, chips excluding the identified chips may be packaged. For example, chips predicted to be defective in step S82 may be excluded from packaging (14). Accordingly, unnecessary packaging may be excluded, and the efficiency of packaging (14) and the semiconductor process (10) may be increased.

[0061] FIG. 15 is a block diagram illustrating a computer system (150) according to an exemplary embodiment of the present disclosure. In some embodiments, the computer system (150) of FIG. 15 may perform at least a portion of the method for testing and manufacturing a semiconductor device described above with reference to the drawings.

[0062] The computer system (150) may refer to any system including a general-purpose or special-purpose computing system. For example, the computer system (150) may include a personal computer, a server computer, a laptop computer, a home appliance, etc. As illustrated in FIG. 15, the computer system (150) may include at least one processor (151), memory (152), a storage system (153), a network adapter (154), an input / output interface (155), and a display (156).

[0063] At least one processor (151) can execute a program module containing computer system executable instructions. The program module may include routines, programs, objects, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types.

[0064] The memory (152) may include a computer system readable medium in the form of volatile memory, such as RAM (random access memory). At least one processor (151) can access the memory (152) and execute instructions loaded into the memory (152) or process data loaded into the memory (152).

[0065] The storage system (153) may include at least one program product comprising a program module configured to perform the method for testing and manufacturing the semiconductor device described above with reference to the drawings in some embodiments, and which can store information non-volatilely. The program may include, as a non-limiting example, an operating system, at least one application, other program modules, and program data. In some embodiments, the storage system (153) may store data used for testing and manufacturing the semiconductor device. For example, the storage system (153) may store the first items (ITM1), first data (TD1), second items (ITM2), and / or second data (TD2) of FIG. 1.

[0066] The network adapter (154) can provide access to a LAN (local area network), WAN (wide area network) and / or a public network (e.g., the Internet). The input / output interface (155) can provide a communication channel with peripheral devices such as a keyboard, a pointing device, an audio system, etc. The display (156) can output various information for the user to view.

[0067] In some embodiments, the method for testing and manufacturing a semiconductor device described above with reference to the drawings may be implemented as a computer program product. The computer program product may include a non-transient computer-readable medium (or storage medium) comprising computer-readable program instructions for at least one processor (151) to perform the method for testing and manufacturing a semiconductor device. Computer-readable instructions may be, as a non-limiting example, assembler instructions, ISA (instruction set architecture) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in at least one programming language.

[0068] A computer-readable medium may be any type of medium capable of non-temporarily holding and storing instructions executed by at least one processor (151) or any instruction execution device. A computer-readable medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination thereof. For example, a computer-readable medium may be a mechanically encoded device such as a portable computer diskette, a hard disk, RAM (random access memory), ROM (read-only memory), EEPROM (electrically erasable read-only memory), flash memory, SRAM (static random access memory), CD, DVD, memory stick, floppy disk, punch card, or any combination thereof.

[0069] FIG. 16 is a block diagram illustrating a system (160) according to an exemplary embodiment of the present disclosure. In some embodiments, at least a portion of the method for testing and manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure may be executed in the system (160).

[0070] Referring to FIG. 16, the system (160) may include at least one processor (161), memory (163), an AI (Artificial Intelligence) accelerator (165), and a hardware accelerator (167), and at least one processor (161), memory (163), AI accelerator (165), and hardware accelerator (167) may communicate with each other through a bus (169). In some embodiments, at least one processor (161), memory (163), AI accelerator (165), and hardware accelerator (167) may be included in a single semiconductor chip. Also, in some embodiments, at least two of at least one processor (161), memory (163), AI accelerator (165), and hardware accelerator (167) may each be included in two or more semiconductor chips mounted on a board.

[0071] At least one processor (161) can execute instructions. For example, at least one processor (161) may execute an operating system by executing instructions stored in memory (163) and may execute applications running on the operating system. In some embodiments, at least one processor (161) may instruct an AI accelerator (165) and / or a hardware accelerator (167) to perform work by executing instructions and may obtain the result of the work from the AI ​​accelerator (165) and / or the hardware accelerator (167). In some embodiments, at least one processor (161) may be an Application Specific Instruction set Processor (ASIP) customized for a specific use and may support a dedicated instruction set.

[0072] The memory (163) may have any structure for storing data. For example, the memory (163) may include volatile memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and may include non-volatile memory devices such as flash memory and RRAM (Resistive Random Access Memory). At least one processor (161), an AI accelerator (165), and a hardware accelerator (167) can store data in the memory (163) or read data from the memory (163) through the bus (169).

[0073] The AI ​​accelerator (165) may refer to hardware designed for AI applications. In some embodiments, the AI ​​accelerator (165) may include a Neural Processing Unit (NPU) for implementing a neuromorphic structure, and may generate output data by processing input data provided from at least one processor (161) and / or hardware accelerator (167), and may provide output data to at least one processor (161) and / or hardware accelerator (167). In some embodiments, the AI ​​accelerator (165) may be programmable and may be programmed by at least one processor (161) and / or hardware accelerator (167).

[0074] A hardware accelerator (167) may refer to hardware designed to perform specific tasks at high speed. For example, a hardware accelerator (167) may be designed to perform data conversions such as demodulation, modulation, encoding, and decoding at high speed. A hardware accelerator (167) may be programmable and may be programmed by at least one processor (161) and / or the hardware accelerator (167).

[0075] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of the present disclosure and are not intended to limit the meaning or the scope of the present disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom.

Claims

Claim 1 A method for testing a semiconductor device, comprising: a step of obtaining first data generated by testing wafers each containing a plurality of chips based on a plurality of first items; a step of obtaining second data generated by testing packages each containing a packaged chip based on a plurality of second items; a step of detecting correlations between the plurality of first items and the plurality of second items based on the first data and the second data; and a step of identifying at least one first item that affects the variation of the packages based on the correlations, wherein the step of identifying at least one first item includes a step of identifying the first item based on a receiver operating characteristics (ROC) graph, wherein the x-axis of the ROC graph is the ratio of wafers predicted to have package defects in the first item, and the y-axis of the ROC graph is the ratio screened through predicted defects among the total defects of the packages. Claim 2 A method according to claim 1, wherein the step of detecting the correlations comprises the step of removing noise by filtering the first data and the second data. Claim 3 A method according to claim 1, wherein the step of detecting the correlations comprises the step of grouping the values ​​included in the second data such that the values ​​corresponding to a plurality of packages packaged from a plurality of chips included in the same wafer are included in the same group. Claim 4 A method according to claim 1, wherein the step of detecting the correlations comprises: a step of setting a plurality of categories in each of the plurality of first items based on the first data; and a step of identifying the correlations based on the values ​​of the second data corresponding to each of the plurality of categories. Claim 5 A method according to claim 4, wherein the step of setting the plurality of categories comprises: obtaining a distribution of the wafers according to the value of the first item; calculating threshold values ​​of the first item based on the distribution; and generating the plurality of categories based on the threshold values. Claim 6 A method according to claim 4, wherein the step of identifying the correlations comprises: a step of testing a null hypothesis and an alternative hypothesis for a first item and a second item based on a statistical hypothesis test; and a step of identifying the correlation between the first item and the second item when the null hypothesis is rejected consecutively a predetermined number of times. Claim 7 delete Claim 8 A method according to claim 1, wherein the step of identifying the first item based on the ROC graph comprises: a step of determining that the first item does not affect package variation when the ROC curve is below the diagonal of the ROC graph; and a step of determining that the first item affects package variation when the ROC curve is above the diagonal. Claim 9 A method according to claim 1, further comprising the steps of: identifying chips predicted to be defective among a plurality of chips included in a wafer based on at least one identified first item; and packaging the chips excluding the identified chips. Claim 10 A system comprising at least one processor; and a non-transient computer readable medium storing a series of instructions, wherein the at least one processor is configured to perform the steps of: obtaining first data generated by testing wafers each comprising a plurality of chips based on a plurality of first items by executing the series of instructions; obtaining second data generated by testing packages each comprising a packaged chip based on a plurality of second items; detecting correlations between the plurality of first items and the plurality of second items based on the first data and the second data; and identifying at least one first item that affects the variation of the packages based on the correlations, wherein the number of the plurality of first items is greater than the number of the plurality of second items.

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