Method of manufacturing display apparatus

Abstract

The present invention provides a method for manufacturing a display device comprising: a step of forming a semiconductor layer on a substrate; a step of forming an insulating layer on the semiconductor layer; a step of forming a photoresist pattern on the insulating layer; a step of etching the insulating layer to form a contact hole that exposes at least a portion of the semiconductor layer; and a step of first cleaning the insulating layer on which the contact hole is formed using a cleaning gas comprising a fluorine-containing gas and a hydrogen-containing gas.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a display device. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] A display device includes multiple pixels that receive electrical signals and emit light to display an image externally. Each pixel includes a display element; for example, in the case of an organic light-emitting display device, it includes an organic light-emitting diode (OLED) as the display element. Generally, an organic light-emitting display device forms thin-film transistors and organic light-emitting diodes on a substrate, and operates by the organic light-emitting diode emitting light on its own.

[0004] Recently, as the applications of display devices have become more diverse, various designs are being attempted to improve the quality of display devices. Related prior art documents include Korean Published Patent Application No. 10-2019-0073848 (Title of Invention: Display Device), Korean Published Patent Application No. 10-2018-0085807 (Title of Invention: Cleaning Method), Korean Published Patent Application No. 10-2019-0063940 (Title of Invention: Dry Cleaning Apparatus and Method for Highly Selective Removal of Silicon Oxide), and US Patent Application Published US2002 / 0081859 (Title of Invention: Post-cleaning method of a via etching process). The problem to be solved

[0005] The present invention aims to provide a display device and a method for manufacturing the same, which can prevent or minimize damage to an insulating layer including a silicon insulating film by performing dry cleaning when forming a contact hole that exposes at least a portion of a semiconductor layer. However, this objective is exemplary and does not limit the scope of the present invention. means of solving the problem

[0006] According to one aspect of the present invention, a method for manufacturing a display device is provided, comprising: a step of forming a semiconductor layer on a substrate; a step of forming an insulating layer on the semiconductor layer; a step of forming a photoresist pattern on the insulating layer; a step of etching the insulating layer to form a contact hole that exposes at least a portion of the semiconductor layer; and a step of first cleaning the insulating layer on which the contact hole is formed using a cleaning gas comprising a fluorine-containing gas and a hydrogen-containing gas.

[0007] In this embodiment, the insulating layer may be provided with a structure in which a plurality of silicon oxides and a plurality of silicon nitrides are alternately stacked.

[0008] In this embodiment, in the first cleaning step, the plurality of silicon oxides and the plurality of silicon nitrides may each be etched at least partially.

[0009] In this embodiment, the width of the contact hole after the first cleaning step is performed may be larger than the width of the contact hole before the first cleaning step is performed.

[0010] In this embodiment, in the first cleaning step, the difference between the etching rate of the silicon oxide and the etching rate of the silicon nitride may be 5% or less.

[0011] In the present embodiment, in the first cleaning step, the fluorine-containing gas may include at least one of hydrofluoric acid gas or nitrogen trifluoride gas, and the hydrogen-containing gas may include at least one of ammonia gas or hydrogen gas.

[0012] In this embodiment, the cleaning gas includes hydrofluoric acid gas and ammonia gas, and the flow rate ratio of the hydrofluoric acid gas and the ammonia gas may be 0.5:1 to 1:0.5.

[0013] In this embodiment, the cleaning gas may be provided together with an inert gas.

[0014] In this embodiment, the inert gas may be provided at a flow rate of 2 to 8 times that of the fluorine-containing gas.

[0015] In this embodiment, the first cleaning step can be performed at a process pressure of 1500 mTorr to 2000 mTorr.

[0016] In this embodiment, the first cleaning step can be performed at a process temperature of 30°C to 90°C.

[0017] In this embodiment, the first cleaning step may be performed for 20 to 80 seconds.

[0018] In the present embodiment, after the step of forming a semiconductor layer on the substrate, the method may further include the step of forming a gate insulating layer on the semiconductor layer; and the step of forming a gate electrode on the gate insulating layer.

[0019] In the present embodiment, after the first cleaning step, the method may further include a second cleaning step using pure water to clean the insulating layer having the contact hole formed therein, and a step of removing the photoresist pattern formed on the insulating layer.

[0020] In the present embodiment, after the step of removing the photoresist pattern, the method may further include the step of forming a connecting electrode on the insulating layer; and the step of forming a light-emitting element comprising a first electrode, a light-emitting layer, and a second electrode on the connecting electrode.

[0021] According to another aspect of the present invention, a method for manufacturing a display device is provided, comprising: a step of first cleaning an insulating layer having a contact hole formed therein using a cleaning gas comprising a fluorine-containing gas and a hydrogen-containing gas; and a step of secondarily cleaning the insulating layer having the contact hole formed therein, which was first cleaned, using pure water.

[0022] In this embodiment, the insulating layer may be provided with a structure in which a plurality of silicon oxides and a plurality of silicon nitrides are alternately stacked.

[0023] In the present embodiment, in the first cleaning step, at least a portion of the plurality of silicon oxides and the plurality of silicon nitrides are each etched, and the difference between the etching rate of the silicon oxide and the etching rate of the silicon nitride may be 5% or less.

[0024] In this embodiment, the first cleaning step may be performed at a process pressure of 1500 mTorr to 2000 mTorr, a substrate temperature of 30°C to 90°C, and for 20 seconds to 80 seconds.

[0025] In this embodiment, after the second cleaning step, a step of removing the photoresist pattern formed on the insulating layer may be further included.

[0026] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention. Effects of the invention

[0027] According to one embodiment of the present invention as described above, by performing dry cleaning when forming a contact hole, a display device and a method for manufacturing the same can be realized, which can prevent or minimize damage to an insulating layer including a silicon insulating film. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0028] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention. Figure 3 is an enlarged cross-sectional view of part A of Figure 2. FIGS. 4 to 13 are cross-sectional views schematically illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 14 is a graph showing the measurement results of the etching amount of silicon oxide and silicon nitride according to process time. Figure 15 is a graph showing the measurement results of the amount of silicon oxide etched according to process time and process temperature. Figure 16 is a graph showing the results of measuring the amount of silicon nitride etched according to process time and process temperature. Figure 17 is a graph schematically illustrating the change in the etching rate of silicon oxide and silicon nitride according to the process temperature. Figure 18 is a graph showing the results of measuring the amount of silicon oxide etched according to process time and the flow rate of hydrofluoric acid gas. Figure 19 is a graph showing the results of measuring the amount of silicon nitride etched according to process time and the flow rate of hydrofluoric acid gas. Figure 20 is a graph showing the measurement results of the etching amount of silicon oxide and silicon nitride according to process pressure. Specific details for implementing the invention

[0029] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0030] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0031] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0033] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0034] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0035] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. Additionally, in this specification, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0036] In the following embodiments, the meaning of "the wiring extends in a first direction or a second direction" includes not only extending in a straight line shape, but also extending in a zigzag or curved shape along the first direction or the second direction.

[0037] In the following embodiments, "planar" refers to the view of the target part from above, and "cross-sectional" refers to the view of the cross-section obtained by vertically cutting the target part from the side. In the following embodiments, "superimposition" includes the superposition of the "planar" and "cross-sectional" views.

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings, and when describing with reference to the drawings, identical or corresponding components will be given the same reference numerals.

[0039] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment of the present invention.

[0040] Referring to FIG. 1, a display device (1) may include a display area (DA) that implements an image and a peripheral area (PA) placed around the display area (DA). The display device (1) may provide an image to the outside using light emitted from the display area (DA).

[0041] The substrate (100) may be provided with glass or a polymer resin. In one embodiment, the substrate (100) may include a flexible material. Here, the flexible material may be a material that can be easily bent, folded, or rolled. For example, the flexible material may be composed of ultra-thin glass, metal, or plastic.

[0042] Pixels (PX) equipped with various display elements, such as organic light-emitting diodes (OLEDs), may be arranged in the display area (DA) of the substrate (100). The pixels (PX) may be composed of multiple pixels, and the multiple pixels (PX) may be arranged in various forms, such as a stripe array, a pentile array, or a mosaic array, to create an image.

[0043] In one embodiment, when the display area (DA) is viewed as a planar shape, the display area (DA) may be provided in a rectangular shape as shown in FIG. 1. Alternatively, the display area (DA) may be provided in a polygonal shape such as a triangle, pentagon, or hexagon, or in a circular shape, elliptical shape, irregular shape, etc.

[0044] The peripheral area (PA) of the substrate (100) is an area placed around the display area (DA) and may be an area where no image is displayed. Various wirings that transmit electrical signals applied to the display area (DA), and pads to which printed circuit boards or driver IC chips are attached may be located in the peripheral area (PA).

[0045] FIG. 2 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.

[0046] Referring to FIG. 2, the display device (1) may include a substrate (100), a thin-film transistor (TFT), and a light-emitting element (OLED).

[0047] The substrate (100) may be provided with glass or a polymer resin. In this case, the polymer resin may include at least one of polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The substrate (100) may have a structure in which layers containing organic material and layers containing inorganic material are alternately stacked. For example, the substrate (100) may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer that are sequentially stacked.

[0048] A buffer layer (110) may be disposed on a substrate (100). The buffer layer (110) may reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100). The buffer layer (110) may include inorganic materials such as silicon oxide, silicon oxynitride, and silicon nitride, and may be provided as a single layer or a multilayer containing the aforementioned materials.

[0049] A thin-film transistor (TFT) may be disposed on the buffer layer (110). The thin-film transistor (TFT) may include a semiconductor layer (Act), a gate electrode (GE), and a connecting electrode. At this time, the connecting electrode may include a source electrode (SE) and a drain electrode (DE).

[0050] In one embodiment, a semiconductor layer (Act) may be disposed on the buffer layer (110). The semiconductor layer (Act) may include a channel region, a source region, and a drain region. The source region and the drain region may be located on both sides of the channel region. The source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities.

[0051] In one embodiment, the semiconductor layer (Act) may include at least one of an oxide semiconductor material and a silicon semiconductor material. When the semiconductor layer (Act) includes an oxide semiconductor material, the semiconductor layer (Act) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer (Act) may include IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O), in which metals such as indium (In), gallium (Ga), and tin (Sn) are contained in ZnO. When the semiconductor layer (Act) includes a silicon semiconductor material, the semiconductor layer (Act) may include amorphous silicon or polysilicon.

[0052] In one embodiment, a gate electrode (GE) may be disposed on a semiconductor layer (Act). The gate electrode (GE) may overlap with the semiconductor layer (Act) with a gate insulating layer (111) in between. That is, the semiconductor layer (Act) and the gate electrode (GE) may be insulated through the gate insulating layer (111). The gate electrode (GE) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multilayer of one or more materials.

[0053] In one embodiment, the gate insulating layer (111) may be patterned to overlap a portion of the semiconductor layer (Act) disposed below it. For example, the gate insulating layer (111) may be patterned so that at least a portion of the source region and / or drain region of the semiconductor layer (Act) is exposed. That is, the gate insulating layer (111) may be patterned to correspond to the channel region of the semiconductor layer (Act). Additionally, the gate insulating layer (111) may be patterned to correspond to the gate electrode (GE) disposed above it. However, the present invention is not limited thereto. For example, the gate insulating layer (111) may cover the semiconductor layer (Act) and / or the buffer layer (110).

[0054] The gate insulating layer (111) is silicon oxide (SiO2) or silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO X It may include at least one of ), etc. At this time, zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0055] In one embodiment, an interlayer insulating layer (113, e.g., an insulating layer) may be disposed on the gate electrode (GE). The interlayer insulating layer (113) may be silicon oxide (SiO2) or silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO X It may include at least one of ), etc. At this time, zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0056] FIG. 3 is an enlarged cross-sectional view of portion A of FIG. 2. Specifically, FIG. 3 is a drawing illustrated to explain that the interlayer insulation layer (113) is provided in a plurality of layers (e.g., multilayer), and is an enlarged cross-sectional view of portion A of FIG. 2.

[0057] Referring to FIGS. 2 and 3, the interlayer insulating layer (113) may include a plurality of silicon oxides (113a) and a plurality of silicon nitrides (113b). For example, as shown in FIG. 3, the interlayer insulating layer (113) may be provided with a structure in which a plurality of silicon oxides (113a) and a plurality of silicon nitrides (113b) are alternately stacked. In FIG. 3, three silicon oxides (113a) and two silicon nitrides (113b) are shown as being alternately stacked, but the present invention is not limited thereto. For example, various variations are possible, such as two silicon oxides (113a) and one silicon nitride (113b) being alternately stacked, or five silicon oxides (113a) and three silicon nitrides (113b) being alternately stacked.

[0058] Referring again to FIG. 2, a contact hole (CNT) may be defined in the interlayer insulating layer (113). The contact hole (CNT) defined in the interlayer insulating layer (113) may penetrate the interlayer insulating layer (113) in the thickness direction of the substrate (100). At least a portion of the semiconductor layer (Act) may be exposed through the contact hole (CNT) defined in the interlayer insulating layer (113). The contact hole (CNT) defined in the interlayer insulating layer (113) may be formed by removing a portion of the interlayer insulating layer (113). This will be explained in more detail in the method of manufacturing a display device.

[0059] In one embodiment, a connecting electrode may be disposed on the interlayer insulating layer (113). The connecting electrode may be a source electrode (SE) and / or a drain electrode (DE). The source electrode (SE) and / or the drain electrode (DE) may be electrically connected to a semiconductor layer (Act) through a contact hole (CNT) defined in the interlayer insulating layer (113). The source electrode (SE) and the drain electrode (DE) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), etc., and may be formed as a single layer or a multilayer of one or more materials. For example, the source electrode (SE) and drain electrode (DE) may be provided with a triple layer of titanium, aluminum, and titanium (Ti / Al / Ti).

[0060] An organic insulating layer (120) may be disposed on the source electrode (SE) and the drain electrode (DE). The organic insulating layer (120) may be formed as a single layer or a multilayer film made of organic material and provides a flat upper surface. Such an organic insulating layer (120) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0061] A light-emitting element (OLED) may be disposed on an organic insulating layer (120). The light-emitting element (OLED) may include a first electrode (160), a light-emitting layer (170), and a second electrode (180). In this case, the first electrode (160) may be an anode and the second electrode (180) may be a cathode. However, the present invention is not limited thereto.

[0062] A first electrode (160) may be disposed on the organic insulating layer (120). Although not illustrated, the first electrode (160) may be electrically connected to a connecting electrode through a via hole defined in the organic insulating layer (120). Through this, a thin-film transistor (TFT) and a light-emitting device (OLED) may be electrically connected.

[0063] The first electrode (160) may be a (semi)transparent electrode or a reflective electrode. In one embodiment, the first electrode (160) may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the first electrode (160) may be provided as ITO / Ag / ITO.

[0064] A pixel defining film (130) may be disposed on the first electrode (160), wherein an opening (OP) is defined to expose at least a portion of the first electrode (160). A light emission region of light emitted from a light-emitting element (OLED) may be defined through the opening (OP) defined in the pixel defining film (130). For example, the size / width of the opening (OP) defined in the pixel defining film (130) may correspond to the size / width of the light emission region.

[0065] The pixel defining film (130) can prevent arcs from occurring at the edge of the first electrode (160) by increasing the distance between the edge of the first electrode (160) and the second electrode (180) above the first electrode (160). The pixel defining film (130) can be formed by a method such as spin coating using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0066] A light-emitting layer (170) may be disposed on the first electrode (160). A light-emitting layer (170) may be disposed within an opening (OP) defined in the pixel defining film (130). The light-emitting layer (170) may include a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a predetermined color. Alternatively, the light-emitting layer (170) may include an inorganic light-emitting material or quantum dots.

[0067] Although not illustrated, a first functional layer may be provided below the light-emitting layer (170), and a second functional layer may be provided above the light-emitting layer (170). The first functional layer may, for example, include a hole transport layer (HTL) or include a hole transport layer and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). However, the present invention is not limited thereto. The first functional layer and / or the second functional layer may be a common layer formed to cover the entire substrate (100), similar to the second electrode (180) to be described later.

[0068] Additionally, although not illustrated, the light-emitting element (OLED) may include a plurality of light-emitting layers (170), and functional layers such as a hole transport layer, a hole generation layer, an electron generation layer, and an electron transport layer may be disposed between the plurality of light-emitting layers (170).

[0069] The second electrode (180) is disposed on the first electrode (160) and may overlap with the first electrode (160). The second electrode (180) may be made of a conductive material with a low work function. For example, the second electrode (180) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the second electrode (180) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer comprising the aforementioned materials. The second electrode (180) may be integrally formed to cover the entire substrate (100).

[0070] Although not illustrated, an encapsulation member may be disposed on the light-emitting element (OLED). For example, a thin film encapsulation layer or an encapsulation substrate may be disposed on the light-emitting element (OLED). When a thin film encapsulation layer is disposed on the light-emitting element (OLED), the thin film encapsulation layer may include at least one inorganic film layer and at least one organic film layer.

[0071] FIGS. 4 to 13 are cross-sectional views schematically illustrating a method for manufacturing a display device according to an embodiment of the present invention. FIGS. 4 to 13 illustrate cross-sections of a display device exemplarily, and some components may be omitted.

[0072] Referring to FIGS. 4 to 13, a method for manufacturing a display device may include the steps of forming a semiconductor layer (Act) on a substrate (100), forming an interlayer insulating layer (113) on the semiconductor layer (Act), forming a photoresist pattern (PR) on the interlayer insulating layer (113), etching the interlayer insulating layer (113) to form a contact hole (CNT) that exposes at least a portion of the semiconductor layer (Act), and performing a first cleaning of the interlayer insulating layer (113) with the contact hole (CNT) formed using a cleaning gas comprising a fluorine-containing gas and a hydrogen-containing gas.

[0073] First, referring to FIG. 4, a buffer layer (110) may be formed on a substrate (100), and a semiconductor layer (Act) may be formed on the buffer layer (110). The substrate (100) may be composed of various materials such as glass, metal, or plastic. The buffer layer (110) may include an inorganic material and may be provided as a single layer or a multilayer. The semiconductor layer (Act) may include at least one of an oxide semiconductor material and a silicon semiconductor material.

[0074] Subsequently, referring to FIG. 5, a gate insulating layer (111) may be formed on a semiconductor layer (Act), and a gate electrode (GE) may be formed on the gate insulating layer (111). As described above, the gate electrode (GE) and the semiconductor layer (Act) may overlap each other with the gate insulating layer (111) in between. The gate insulating layer (111) may be patterned to correspond to the gate electrode (GE) placed on top thereof. However, the present invention is not limited thereto.

[0075] Referring to FIG. 6, an interlayer insulating layer (113) may be formed on a semiconductor layer (Act). Specifically, an interlayer insulating layer (113) may be formed on a gate electrode (GE), a gate insulating layer (111), a semiconductor layer (Act), and a buffer layer (110). The interlayer insulating layer (113) may cover the gate electrode (GE), the gate insulating layer (111), the semiconductor layer (Act), and the buffer layer (110).

[0076] In one embodiment, the interlayer insulating layer (113) may include a silicon insulating film. Specifically, the interlayer insulating layer (113) may include silicon oxide and / or silicon nitride.

[0077] Figure 7 is an enlarged view of part B of Figure 6.

[0078] Referring to FIG. 7, the interlayer insulating layer (113) may include a plurality of silicon oxides (113a) and a plurality of silicon nitrides (113b). For example, the interlayer insulating layer (113) may be provided with a structure in which a plurality of silicon oxides (113a) and a plurality of silicon nitrides (113b) are alternately stacked.

[0079] Referring to FIG. 8, a photoresist pattern (PR) can be formed on the interlayer insulating layer (113). The photoresist pattern (PR) can be formed on the interlayer insulating layer (113) through the following process.

[0080] First, a photoresist is coated over the entire interlayer insulating layer (113), and an exposure process can be performed using a photomask. At this time, the density of the photoresist may differ between the portion exposed to light and the portion not exposed to light. Subsequently, the photoresist overlapping with the portion intended to form a contact hole can be removed through a development process using a developer. The photoresist may include a positive type and a negative type. In the case of the positive type, the portion exposed to light can be removed, and in the case of the negative type, the portion not exposed to light can be removed. Accordingly, a photoresist pattern (PR) is formed on the interlayer insulating layer (113), but the photoresist pattern (PR) may not overlap with the portion intended to form a contact hole among the interlayer insulating layer (113), and may overlap with the remaining portion.

[0081] Figure 10 is an enlarged view of section C of Figure 9.

[0082] Referring to FIGS. 9 and 10, a contact hole (CNT) can be formed by etching an interlayer insulating layer (113) to expose at least a portion of a semiconductor layer (Act). A contact hole (CNT) can be formed by etching a portion of the interlayer insulating layer (113). At this time, a photoresist pattern (PR) can be used as a mask. Additionally, at least a portion of the semiconductor layer (Act) can be exposed through the contact hole (CNT).

[0083] In one embodiment, the width (w1) of the contact hole (CNT) may be about 2 μm. For example, the width (w1) of the contact hole (CNT) may be the lower reference diameter of the contact hole (CNT) or the lower reference width / size.

[0084] A dry etching method may be used for etching the interlayer insulating layer (113). When etching the interlayer insulating layer (113), an etching gas capable of etching both silicon oxide (113a) and silicon nitride (113b) may be used. For example, when etching the interlayer insulating layer (113), etching gases such as CF4, SF6, BCl3, Cl2, Ar, and O2 may be used.

[0085] Additionally, when the interlayer insulating layer (113) is etched, a portion of the photoresist pattern (PR) formed on the interlayer insulating layer (113) may be chemically or physically decomposed, so that photoresist residue may exist in the sidewall (113c) of the interlayer insulating layer (113) defining the contact hole (CNT) and / or in the contact hole (CNT). At this time, the thickness of the photoresist residue present in the sidewall (113c) of the interlayer insulating layer (113) may be about 20 nm to about 80 nm.

[0086] Figure 12 is an enlarged view of section D of Figure 11.

[0087] Referring to FIGS. 11 and 12, after the contact hole (CNT) is formed, a step of cleaning the interlayer insulation layer (113) (e.g., a first cleaning step) may be performed. That is, the interlayer insulation layer (113) may be cleaned first. Specifically, the interlayer insulation layer (113) in which the contact hole (CNT) is formed may be cleaned first using a cleaning gas containing a fluorine-containing gas and a hydrogen-containing gas.

[0088] In one embodiment, the cleaning gas may include a fluorine-containing gas and a hydrogen-containing gas. In this case, the fluorine-containing gas may include at least one of hydrofluoric acid gas or nitrogen trifluoride gas. Additionally, the hydrogen-containing gas may include at least one of ammonia gas or hydrogen gas. In this case, the fluorine-containing gas and the hydrogen-containing gas may be provided at a flow rate ratio of about 0.5:1 to about 1:0.5. Alternatively, the fluorine-containing gas and the hydrogen-containing gas may be provided at a flow rate ratio of about 0.8:1 to about 1:0.8. Alternatively, the fluorine-containing gas and the hydrogen-containing gas may be provided at a flow rate ratio of about 1:1. If the content of the fluorine-containing gas is low, the etching amount of silicon oxide and silicon nitride may be reduced. Additionally, even if the content of the fluorine-containing gas increases, in the case of silicon nitride, the etching amount may not increase and may reach saturation. Therefore, when the flow rate ratio of the fluorine-containing gas and the hydrogen-containing gas satisfies the aforementioned range, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride is reduced, so that the difference between the etching rate of silicon oxide and the etching rate of silicon nitride can be about 5% or less.

[0089] The cleaning gas can be supplied into the reaction chamber along with an inert gas. In this case, argon gas can be used as the inert gas. The inert gas can be supplied at a flow rate of about 2 to about 8 times the flow rate of the fluorine-containing gas. Additionally, the cleaning gas can be plasmafied at a distance or inside the reaction chamber and supplied to the interlayer insulation layer (113).

[0090] In one embodiment, at least a portion of the interlayer insulating layer (113) may be etched during the first cleaning step. For example, during the first cleaning step, at least a portion of each of the silicon oxide (113a) and silicon nitride (113b) contained in the interlayer insulating layer (113) may be etched.

[0091] In one embodiment, the interlayer insulating layer (113) may be etched to a depth of approximately 10 nm to approximately 500 nm during the first cleaning step. Accordingly, the width of the contact hole (CNT) (w2, see FIG. 12) after the first cleaning step may be larger than the width of the contact hole (CNT) (w1, see FIG. 10) before the first cleaning step. For example, etching of approximately 0.1 μm radially may proceed through the first cleaning step. Accordingly, the width of the contact hole (CNT) (w1) before the first cleaning step is approximately 2 μm, but the width of the contact hole (CNT) (w2) after the first cleaning step is approximately 2.2 μm. At this time, the amount of etching during the first cleaning step may vary depending on process conditions such as the flow rate of the cleaning gas, process temperature, and process pressure. This will be described later.

[0092] At this time, the etching in the first cleaning step may be due to a salt reaction caused by hydrofluoric acid as follows.

[0093] 1) HF + NH3 → NH4F

[0094] 2) 6NH4F + SiO2→ (NH4)2SiF6+ H2O + 4NH3

[0095] By such a salt reaction, the surface condition of the sidewall (113c) of the interlayer insulating layer (113) defining the contact hole (CNT) can be improved, the width of the contact hole (CNT) can be increased, and photoresist residue present in the contact hole (CNT) can be removed.

[0096] In one embodiment, the difference between the etching rate of silicon oxide (113a) and the etching rate of silicon nitride (113b) in the first cleaning step may be about 5% or less. When the first cleaning step is performed using a cleaning gas with a high etching selectivity ratio for silicon oxide (113a) and silicon nitride (113b), the etching may be concentrated on either silicon oxide or silicon nitride, and the surface of the sidewall (113c) of the interlayer insulating layer (113) defining the contact hole (CNT) may be uneven, which may cause a disconnection in the connecting electrode (e.g., source electrode and / or drain electrode) placed within the contact hole (CNT) and increase the contact resistance.

[0097] However, the inventors of the present invention have discovered through repeated experiments that by controlling process conditions such as process time (or cleaning time), process gas (or cleaning gas), process temperature (or substrate temperature), and process pressure, the difference between the etching rate of silicon oxide (113a) and the etching rate of silicon nitride (113b) can be made to be 5% or less.

[0098] Figure 14 is a graph showing the measurement results of the etching amount of silicon oxide and silicon nitride according to process time. In Figure 14, 14a is a graph showing the etching amount of silicon oxide according to process time (or, cleaning time), and 14b is a graph showing the etching amount of silicon nitride according to process time (or, cleaning time). In Figure 14, the etching amount was measured through SEM image analysis.

[0099] All process conditions except for the process time (or cleaning time) were fixed, and the process conditions are as follows:

[0100] 1) HF : NH3 flow ratio 1 : 1 (HF : 75 sccm)

[0101] 2) HF : Ar flow rate ratio 1 : 3

[0102] 3) Process pressure: 2000 mTorr

[0103] 4) Process temperature (or substrate temperature): 70 ℃

[0104] Referring to FIG. 14, it can be seen that as the first cleaning proceeds, the etching amount of silicon oxide (13a) and the etching amount of silicon nitride (13b) increase. However, in the case of the etching amount of silicon oxide (13a), the etching amount does not increase further after about 80 seconds, but in the case of the etching amount of silicon nitride (13b), the etching amount continues to increase up to about 120 seconds.

[0105] In one embodiment, the process time (or cleaning time) during which the first cleaning step is performed may be about 20 seconds to about 80 seconds. If the process time (or cleaning time) during which the first cleaning step is performed is less than about 20 seconds, the amount of silicon oxide and silicon nitride etched is small, and photoresist residues remaining in the contact hole (CNT) may not be removed. On the other hand, if the process time (or cleaning time) during which the first cleaning step is performed is greater than about 80 seconds, the difference between the amount of silicon oxide etched (13a) and the amount of silicon nitride etched (13b) increases, and the difference between the etching rate of silicon oxide and the etching rate of silicon nitride may increase. Accordingly, by performing the first cleaning step for about 20 seconds to about 80 seconds, the difference between the etching amount of silicon oxide (13a) and the etching amount of silicon nitride (13b) can be reduced, and the difference between the etching rate of silicon oxide and the etching rate of silicon nitride can be about 5% or less.

[0106] Figure 15 is a graph showing the measurement results of the etching amount of silicon oxide according to process time and process temperature. In Figure 15, 15a is a graph showing the etching amount of silicon oxide according to process time (or cleaning time) when the process temperature (or substrate temperature) is 70°C, 15b is a graph showing the etching amount of silicon oxide according to process time (or cleaning time) when the process temperature (or substrate temperature) is 80°C, and 15c is a graph showing the etching amount of silicon oxide according to process time (or cleaning time) when the process temperature (or substrate temperature) is 90°C. In Figure 15, the etching amount was measured through SEM image analysis.

[0107] All process conditions except for process time (or cleaning time) and process temperature (or substrate temperature) were fixed, and the process conditions are as follows:

[0108] 1) HF : NH3 flow ratio 1 : 1 (HF : 75 sccm)

[0109] 2) HF : Ar flow rate ratio 1 : 3

[0110] 3) Process pressure: 2000 mTorr

[0111] Referring to Fig. 15, when cleaning of silicon oxide is performed for the same amount of time, it can be seen that the amount of etching is greatest when the process temperature (or substrate temperature) is 70°C and the amount of etching is least when the process temperature (or substrate temperature) is 90°C. In other words, in the case of silicon oxide, it can be seen that the amount of silicon oxide etched decreases as the process temperature (or substrate temperature) increases.

[0112] Figure 16 is a graph showing the measurement results of the etching amount of silicon nitride according to process time and process temperature. In Figure 16, 16a is a graph showing the etching amount of silicon nitride according to process time (or cleaning time) when the process temperature (or substrate temperature) is 70°C, 16b is a graph showing the etching amount of silicon nitride according to process time (or cleaning time) when the process temperature (or substrate temperature) is 80°C, and 16c is a graph showing the etching amount of silicon nitride according to process time (or cleaning time) when the process temperature (or substrate temperature) is 90°C. In Figure 16, the etching amount was measured through SEM image analysis.

[0113] All process conditions except for process time (or cleaning time) and process temperature (or substrate temperature) were fixed, and the process conditions are as follows:

[0114] 1) HF : NH3 flow ratio 1 : 1 (HF : 75 sccm)

[0115] 2) HF : Ar flow rate ratio 1 : 3

[0116] 3) Process pressure: 2000 mTorr

[0117] Referring to Fig. 16, when cleaning of silicon nitride is performed for the same amount of time, it can be seen that the amount of etching is smallest when the process temperature (or substrate temperature) is 70°C and the amount of etching is largest when the process temperature (or substrate temperature) is 90°C. In other words, in the case of silicon nitride, it can be seen that the amount of silicon nitride etched increases as the process temperature (or substrate temperature) increases.

[0118] FIG. 17 is a graph schematically illustrating the change in the etching rate of silicon oxide and silicon nitride according to the process temperature. Specifically, FIG. 17 is a graph schematically illustrating the change in the etching rate of silicon oxide and silicon nitride according to the process temperature (or substrate temperature) based on the results of FIG. 15 and FIG. 16.

[0119] Referring to FIGS. 15, 16, and 17, it can be seen that for silicon oxide, the etching rate decreases as the process temperature (or substrate temperature) increases, whereas for silicon nitride, the etching rate increases as the process temperature (or substrate temperature) increases. Additionally, it can be seen that the difference between the etching rate of silicon oxide and the etching rate of silicon nitride at low temperatures is greater than the difference between the etching rate of silicon oxide and the etching rate of silicon nitride at high temperatures.

[0120] In one embodiment, the process temperature (or substrate temperature) at which the first cleaning step is performed may be about 30°C to about 90°C. If the process temperature (or substrate temperature) at which the first cleaning step is performed is less than about 30°C or more than about 90 seconds, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride increases, and the difference between the etching rate of silicon oxide and the etching rate of silicon nitride may increase. Therefore, by performing the first cleaning step at a process temperature (or substrate temperature) of about 30°C to about 90°C, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride is reduced, so that the difference between the etching rate of silicon oxide and the etching rate of silicon nitride may be about 5% or less.

[0121] Figure 18 is a graph showing the measurement results of the etching amount of silicon oxide according to the process time and the flow rate of hydrofluoric acid gas. In Figure 18, 18a is a graph showing the etching amount of silicon oxide according to the process time (or cleaning time) when the flow rate of hydrofluoric acid gas in the cleaning gas is 75 sccm, 18b is a graph showing the etching amount of silicon oxide according to the process time (or cleaning time) when the flow rate of hydrofluoric acid gas in the cleaning gas is 50 sccm, and 18c is a graph showing the etching amount of silicon oxide according to the process time (or cleaning time) when the flow rate of hydrofluoric acid gas in the cleaning gas is 25 sccm. In Figure 18, the etching amount was measured through SEM image analysis.

[0122] All process conditions except for the process time (or cleaning time) and the flow rate of hydrofluoric acid gas were fixed, and the process conditions are as follows:

[0123] 1) HF : NH3 = 1 : 1

[0124] 2) Ar : 200 sccm

[0125] 3) Process pressure: 2000 mTorr

[0126] 4) Process temperature (or substrate temperature): 80 ℃

[0127] Referring to Fig. 18, it can be seen that the amount of silicon oxide etched increases as the flow rate of the hydrofluoric acid gas increases. Additionally, when the flow rate of the hydrofluoric acid gas is 25 sccm, the difference in the amount of etched according to the process time (or cleaning time) is not significant and is almost the same, whereas when the flow rate of the hydrofluoric acid gas is 50 sccm and 75 sccm, the difference in the amount of etched according to the process time (or cleaning time) is significant. In other words, it can be seen that the difference in the amount of silicon oxide etched increases as the flow rate of the hydrofluoric acid gas increases.

[0128] Figure 19 is a graph showing the measurement results of the etching amount of silicon nitride according to the process time and the flow rate of hydrofluoric acid gas. In Figure 19, 19a is a graph showing the etching amount of silicon nitride according to the process time (or cleaning time) when the flow rate of hydrofluoric acid gas in the cleaning gas is 75 sccm, 19b is a graph showing the etching amount of silicon nitride according to the process time (or cleaning time) when the flow rate of hydrofluoric acid gas in the cleaning gas is 50 sccm, and 19c is a graph showing the etching amount of silicon nitride according to the process time (or cleaning time) when the flow rate of hydrofluoric acid gas in the cleaning gas is 25 sccm. In Figure 19, the etching amount was measured through SEM image analysis.

[0129] All process conditions except for the process time (or cleaning time) and the flow rate of hydrofluoric acid gas were fixed, and the process conditions are as follows:

[0130] 1) HF : NH3 = 1 : 1

[0131] 2) Ar : 200 sccm

[0132] 3) Process pressure: 2000 mTorr

[0133] 4) Process temperature (or substrate temperature): 80 ℃

[0134] Referring to Figure 19, it can be seen that the amount of silicon nitride etched increases as the flow rate of the hydrofluoric acid gas increases. Additionally, it can be seen that there is not a significant difference in the amount of silicon nitride etched when the flow rate of the hydrofluoric acid gas is 50 sccm and when the flow rate of the hydrofluoric acid gas is 75 sccm. In other words, in the case of the silicon nitride film, it can be seen that the etching amount approaches saturation at a flow rate of 50 sccm or higher.

[0135] Figure 20 is a graph showing the measurement results of the etching amount of silicon oxide and silicon nitride according to process pressure. In Figure 20, 20a is a graph showing the etching amount of silicon oxide according to process pressure, and 20b is a graph showing the etching amount of silicon nitride according to process pressure. In Figure 20, the etching amount was measured through SEM image analysis.

[0136] All process conditions except for the process pressure were fixed, and the process conditions are as follows:

[0137] 1) HF: NH3= 1:1 (HF: 75 sccm)

[0138] 2) Ar : 200 sccm

[0139] 3) Process temperature (or substrate temperature): 80 ℃

[0140] 4) Process time (or cleaning time): 80 sec

[0141] Referring to Fig. 20, it can be seen that as the process pressure increases, the etching amount of silicon oxide and silicon nitride decreases. However, when the process pressure is 1000 mTorr, the etching amount of silicon nitride is greater than that of silicon oxide, but when the process pressure is 2000 mTorr, the etching amount of silicon nitride is smaller than that of silicon oxide. In other words, as the process pressure increases, the etching amount of both silicon nitride and silicon oxide decreases, but the etching amount of silicon nitride decreases significantly compared to that of silicon nitride.

[0142] In one embodiment, the process pressure at which the first cleaning step is performed may be approximately 1500 mTorr to approximately 2000 mTorr. If the process pressure at which the first cleaning step is performed is less than approximately 1500 mTorr and / or greater than approximately 2000 mTorr, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride increases, and the difference between the etching rate of silicon oxide and the etching rate of silicon nitride may increase. Therefore, by performing the first cleaning step at a process pressure of approximately 1500 mTorr to approximately 2000 mTorr, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride is reduced, so that the difference between the etching rate of silicon oxide and the etching rate of silicon nitride can satisfy approximately 5% or less.

[0143] In one embodiment, when the cleaning gas used in the first cleaning step comprises hydrofluoric acid gas and ammonia gas, and the flow rate ratio of hydrofluoric acid gas to ammonia gas satisfies 0.8:1 to 1:0.8, and the first cleaning step is performed under process conditions of a process time (or cleaning time) of about 20 seconds to about 80 seconds, a process temperature (or substrate temperature) of about 30°C to about 90°C, and a process pressure of about 1500 mTorr to about 2000 mTorr, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride can be reduced. At this time, the difference between the etching rate of silicon oxide and the etching rate of silicon nitride may be about 5% or less.

[0144] In addition, by reducing the difference between the etching rate of silicon oxide and the etching rate of silicon nitride, the surface condition of the sidewall (113c) of the interlayer insulating layer (113) defining the contact hole (CNT) can be improved, thereby preventing or minimizing defects such as open circuits.

[0145] Referring again to FIG. 13, after a first cleaning step is performed, a second cleaning step (e.g., a second cleaning step) may be performed on the interlayer insulation layer (113) and contact hole (CNT) that underwent the first cleaning step. In the second cleaning step, the interlayer insulation layer (113) and contact hole (CNT) that underwent the first cleaning step may be cleaned using pure water. Specifically, in the second cleaning step, the interlayer insulation layer (113) and contact hole (CNT) that underwent the first cleaning step may be cleaned using ultrapure water. Through the second cleaning step, the HF salt reactants and residual fluoride generated by the first cleaning step can be removed.

[0146] In one embodiment, after the first cleaning step is performed, a second cleaning step may be performed using a heat treatment method.

[0147] Additionally, after the second cleaning step is performed, a step of removing the photoresist pattern (PR) formed on the interlayer insulating layer (113) may be performed. In the step of removing the photoresist pattern (PR), the photoresist pattern (PR) formed on the interlayer insulating layer (113) may be removed using a solution capable of selectively dissolving the photoresist (e.g., Merck’s AZ 910, etc.).

[0148] In one embodiment, after the step of removing the photoresist pattern (PR) formed on the interlayer insulating layer (113), the step of forming a connecting electrode on the interlayer insulating layer (113) may be performed. For example, a source electrode (SE, see FIG. 2) and a drain electrode (DE, see FIG. 2), which are connecting electrodes, may be formed on the interlayer insulating layer (113).

[0149] Subsequently, an organic insulating layer (120, see FIG. 2) may be formed on a source electrode (SE) and a drain electrode (DE), and a light-emitting device (OLED, see FIG. 2) including a first electrode (160, see FIG. 2), a light-emitting layer (170, see FIG. 2), and a second electrode (180, see FIG. 2) may be formed on the organic insulating layer (120). Specifically, an organic insulating layer (120) may be formed on the source electrode (SE) and the drain electrode (DE), a first electrode (160) may be formed on the organic insulating layer (120), a light-emitting layer (170) may be formed on the first electrode (160), and a second electrode (180) may be formed on the light-emitting layer (170). Additionally, a pixel defining film (130) may be formed on the first electrode (160) with an opening (OP) that exposes at least a portion of the first electrode (160).

[0150] When a part of the interlayer insulating layer (113) is etched to form a contact hole (CNT) through dry etching, and then a photoresist pattern (PR) formed on the interlayer insulating layer (113) is removed and the interlayer insulating layer (113) is wet-cleaned, unwanted etching may occur on the upper surface of the interlayer insulating layer (113), and etching byproducts, salt-forming reactants, and photoresist residues may react with each other to generate a large amount of byproducts.

[0151] Additionally, when dry cleaning an interlayer insulating layer (113) in which a plurality of silicon oxides and a plurality of silicon nitrides are alternately stacked, etching may be concentrated on either the silicon oxide or the silicon nitride, and the surface of the sidewall of the interlayer insulating layer defining the contact hole may be uneven, which may cause a disconnection in the connecting electrode (e.g., source electrode and / or drain electrode) placed in the contact hole and increase the contact resistance.

[0152] In one embodiment, after the interlayer insulating layer (113) having the contact hole (CNT) formed therein is cleaned in a first and second step, the photoresist pattern (PR) formed on the interlayer insulating layer (113) can be removed.

[0153] In addition, if the process conditions in the first cleaning step satisfy the aforementioned conditions, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride can be reduced. Specifically, if the cleaning gas used in the first cleaning step includes hydrofluoric acid gas and ammonia gas, and the flow rate ratio of hydrofluoric acid gas to ammonia gas satisfies 0.8:1 to 1:0.8, and the process time (or cleaning time), process temperature (or substrate temperature), and process pressure satisfy the aforementioned conditions, the difference between the etching amount of silicon oxide and the etching amount of silicon nitride can be reduced. Accordingly, the difference between the etching rate of silicon oxide and the etching rate of silicon nitride can be about 5% or less.

[0154] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0155] Act: Semiconductor layer CNT: Contact hole 1: Display device 100: Substrate 113: Interlayer insulation layer

Claims

Claim 1 A method for manufacturing a display device, comprising: a step of forming a semiconductor layer on a substrate; a step of forming an insulating layer on the semiconductor layer; a step of forming a photoresist pattern on the insulating layer; a step of etching the insulating layer to form a contact hole that exposes at least a portion of the semiconductor layer; and a step of performing a first cleaning of the insulating layer having the contact hole formed thereon using a cleaning gas comprising a fluorine-containing gas and a hydrogen-containing gas; wherein the first cleaning step is performed for 20 to 80 seconds. Claim 2 A method for manufacturing a display device according to claim 1, wherein the insulating layer is provided with a structure in which a plurality of silicon oxides and a plurality of silicon nitrides are alternately stacked. Claim 3 A method for manufacturing a display device according to claim 2, wherein in the first cleaning step, the plurality of silicon oxides and the plurality of silicon nitrides are each etched at least partially. Claim 4 A method for manufacturing a display device according to claim 3, wherein the width of the contact hole after the first cleaning step is performed is greater than the width of the contact hole before the first cleaning step is performed. Claim 5 A method for manufacturing a display device according to claim 3, wherein, in the first cleaning step, the difference between the etching rate of the silicon oxide and the etching rate of the silicon nitride is 5% or less. Claim 6 A method for manufacturing a display device according to claim 1, wherein in the first cleaning step, the fluorine-containing gas comprises at least one of hydrofluoric acid gas or nitrogen trifluoride gas, and the hydrogen-containing gas comprises at least one of ammonia gas or hydrogen gas. Claim 7 A method for manufacturing a display device according to claim 6, wherein the cleaning gas comprises hydrofluoric acid gas and ammonia gas, and the flow rate ratio of the hydrofluoric acid gas to the ammonia gas is 0.5:1 to 1:0.

5. Claim 8 A method for manufacturing a display device according to claim 6, wherein the cleaning gas is provided together with an inert gas. Claim 9 A method for manufacturing a display device according to claim 8, wherein the inert gas is provided at a flow rate of 2 to 8 times that of the fluorine-containing gas. Claim 10 A method for manufacturing a display device according to claim 1, wherein the first cleaning step is performed at a process pressure of 1500 mTorr to 2000 mTorr. Claim 11 A method for manufacturing a display device according to claim 1, wherein the first cleaning step is performed at a process temperature of 30℃ to 90℃. Claim 12 delete Claim 13 A method for manufacturing a display device according to claim 1, further comprising: a step of forming a gate insulating layer on the semiconductor layer after the step of forming a semiconductor layer on the substrate; and a step of forming a gate electrode on the gate insulating layer. Claim 14 A method for manufacturing a display device according to claim 1, further comprising: a step of secondarily cleaning the insulating layer having the contact hole formed thereon, which was first cleaned using pure water, after the first cleaning step; and a step of removing the photoresist pattern formed on the insulating layer. Claim 15 A method for manufacturing a display device according to claim 14, further comprising: a step of forming a connecting electrode on an insulating layer after the step of removing the photoresist pattern; and a step of forming a light-emitting element including a first electrode, a light-emitting layer, and a second electrode on the connecting electrode. Claim 16 A method for manufacturing a display device, comprising: a step of first cleaning an insulating layer having a contact hole formed therein using a cleaning gas including a fluorine-containing gas and a hydrogen-containing gas; and a step of secondarily cleaning the insulating layer having the contact hole formed therein, which was first cleaned using pure water; wherein the first cleaning step is performed for 20 to 80 seconds. Claim 17 A method for manufacturing a display device according to claim 16, wherein the insulating layer is provided with a structure in which a plurality of silicon oxides and a plurality of silicon nitrides are alternately stacked. Claim 18 A method for manufacturing a display device according to claim 17, wherein in the first cleaning step, the plurality of silicon oxides and the plurality of silicon nitrides are each etched at least partially, and the difference between the etching rate of the silicon oxide and the etching rate of the silicon nitride is 5% or less. Claim 19 A method for manufacturing a display device according to claim 16, wherein the first cleaning step is performed at a process pressure of 1500 mTorr to 2000 mTorr and a substrate temperature of 30℃ to 90℃. Claim 20 A method for manufacturing a display device according to claim 16, further comprising the step of removing a photoresist pattern formed on the insulating layer after the second cleaning step.

Images