Semiconductor devices and data storage systems including the same

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a first substrate; circuit elements disposed on the first substrate; a lower wiring structure electrically connected to the circuit elements; a lower bonding structure connected to the lower wiring structure; an upper bonding structure joined to the lower bonding structure; an upper wiring structure connected to the upper bonding structure; a second substrate on the upper wiring structure; gate electrodes disposed between the upper wiring structure and the second substrate and stacked spaced apart from each other; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate at the outside of the second substrate and having an upper surface at a level higher than the upper surface of the second substrate relative to the upper surface of the first substrate and a lower surface at a level lower than the lower surface of the lowest gate electrode among the gate electrodes; and a source connection pattern in contact with the upper surface of each of the via patterns and the upper surface of the source contact plug.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a data storage system including the same. Background Technology

[0003] In data storage systems that require data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0005] One of the technical problems that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability.

[0006] One of the technical problems that the present invention aims to solve is to provide a data storage system including a semiconductor device with improved electrical characteristics and reliability. means of solving the problem

[0008] A semiconductor device according to exemplary embodiments comprises: a first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure; The second semiconductor structure comprises a second substrate disposed on the first semiconductor structure, gate electrodes stacked spaced apart from each other along a vertical direction perpendicular to the lower surface of the second substrate, channel structures each including a channel layer that penetrates the gate electrodes and extends in the vertical direction, an upper wiring structure disposed below the gate electrodes and the channel structures, and an upper bonding structure connected to the upper wiring structure and bonded to the lower bonding structure, wherein the second semiconductor structure further comprises via patterns on the second substrate, a source contact plug spaced apart from the second substrate, and a source connection pattern that contacts the upper surface of each of the via patterns and electrically connects the via patterns and the source contact plug to each other, wherein the source connection pattern comprises an overlapping portion that overlaps with the second substrate in the vertical direction and an extension portion that extends from the overlapping portion in a horizontal direction parallel to the lower surface of the second substrate, and the source contact plug may overlap with the extension portion of the source connection pattern in the vertical direction.

[0009] A semiconductor device according to exemplary embodiments may include: a first substrate; circuit elements disposed on the first substrate; a lower wiring structure electrically connected to the circuit elements; a lower bonding structure connected to the lower wiring structure; an upper bonding structure joined to the lower bonding structure; an upper wiring structure connected to the upper bonding structure; a second substrate on the upper wiring structure; gate electrodes disposed between the upper wiring structure and the second substrate and stacked spaced apart from each other; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate at the outside of the second substrate and having an upper surface at a level higher than the upper surface of the second substrate relative to the upper surface of the first substrate and a lower surface at a level lower than the lower surface of the lowest gate electrode among the gate electrodes; and a source connection pattern in contact with the upper surface of each of the via patterns and the upper surface of the source contact plug.

[0010] A data storage system according to exemplary embodiments comprises: a first semiconductor structure including a first substrate and circuit elements on the first substrate; a second semiconductor structure including a second substrate, gate electrodes stacked spaced apart from each other below the second substrate, and channel structures penetrating the gate electrodes; a semiconductor storage device including an input / output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device through the input / output pad and controlling the semiconductor storage device, wherein the first semiconductor structure further comprises a lower wiring structure electrically connected to the circuit elements; and a lower bonding structure connected to the lower wiring structure, and the second semiconductor structure comprises an upper bonding structure bonded to the lower bonding structure; an upper wiring structure connected to the upper bonding structure; via patterns on the second substrate; and a source connection pattern in contact with the upper surface of each of the via patterns, and comprising an overlapping portion that overlaps the second substrate in a vertical direction perpendicular to the lower surface of the second substrate and an extension portion that extends from the overlapping portion in a horizontal direction parallel to the lower surface of the second substrate. and may further include a source contact plug that is connected to the upper wiring structure, is spaced apart from the second substrate on the outside of the second substrate, extends in the vertical direction, and contacts the extended portion of the source connection pattern. Effects of the invention

[0012] A semiconductor device with improved electrical characteristics and reliability and a data storage system including the same can be provided by arranging via patterns and source connection patterns on a substrate including a common source line, and by arranging source contact plugs to extend vertically from the outside of the substrate and directly connect with the source connection patterns.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1 is a schematic exploded perspective view showing a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 3 is a plan view illustrating some components of a semiconductor device according to exemplary embodiments. FIGS. 4a and FIG. 4b are partial enlarged cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 6 is a plan view illustrating some components of a semiconductor device according to exemplary embodiments. FIG. 7 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 8a through 8f are plan views illustrating some components of a semiconductor device according to exemplary embodiments. FIG. 9 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 10 to 16 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIG. 17 is a schematic diagram illustrating a data storage system including a semiconductor device according to exemplary embodiments. FIG. 18 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment. FIG. 19 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment. Specific details for implementing the invention

[0016] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. In the following, terms such as 'top', 'upper part', 'upper surface', 'top', 'lower', 'lower part', 'lower surface', 'below', 'side', etc., may be understood as referring to the drawings unless otherwise indicated by drawing symbols.

[0018] FIG. 1 is a schematic exploded perspective view showing a semiconductor device according to exemplary embodiments.

[0019] Referring to FIG. 1, a semiconductor device (100) according to exemplary embodiments may include a peripheral circuit region (PERI) and a memory cell region (CELL) stacked in a vertical direction (Z). The peripheral circuit region (PERI) and the memory cell region (CELL) may be joined and combined. The memory cell region (CELL) may include a memory cell array region (MCA), a connection region (CA) adjacent to the memory cell array region (MCA), and an outer region (PA) disposed outside of them. A conductive pad (300), which is an input / output pad, may be disposed on the outer region (PA). A plurality of memory cell structures including the memory cell array region (MCA) and the connection region (CA) may be disposed.

[0020] The peripheral circuit area (PERI) may include a row decoder (DEC), a page buffer (PB), and other peripheral circuits (PC). In the peripheral circuit area (PERI), the row decoder (DEC) can decode an input address to generate and transmit driving signals for word lines. The page buffer (PB) is connected to the memory cell array area (MCA) via bit lines to read information stored in memory cells. The other peripheral circuits (PC) may be an area including control logic and a voltage generator, and may include, for example, a latch circuit, a cache circuit, and / or a sense amplifier. The peripheral circuit area (PERI) may further include a separate pad area, in which case the pad area may include an electrostatic discharge (ESD) element or a data input / output circuit. The ESD element or data input / output circuit of the pad area may be electrically connected to a conductive pad (300) of the outer area (PA). Various circuit regions (DEC, PB, PC) within the peripheral circuit region (PERI) can be arranged in various forms.

[0021] Hereinafter, an example of a semiconductor device (100) will be described with reference to FIGS. 2 to 4b. In FIG. 2, the area marked 'A' may schematically represent a cross-sectional shape obtained by cutting the semiconductor device (100) along the X direction, covering a part of the memory cell array area (MCA), the connection area (CA), and the outer area (PA) shown in FIG. 1, and the area marked 'B' may schematically represent a cross-sectional shape obtained by cutting the semiconductor device (100) along the Y direction, covering a part of the memory cell array area (MCA) shown in FIG. 1.

[0023] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. The area marked 'A' in FIG. 2 may correspond to a cross-section of the semiconductor device cut along the cutting line I-I' in FIG. 3.

[0024] FIG. 3 is a plan view illustrating some components of a semiconductor device according to exemplary embodiments. FIG. 3 exemplarily illustrates the shape and arrangement relationship of a second substrate (201), via patterns (215), a source contact plug (253), and a source connection pattern (260) to show the electrical connection relationship between a second substrate (201) including a common source line and a source contact plug (253).

[0025] FIGS. 4a and 4b are partial enlarged cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 4a shows an enlarged view of region 'C' of FIG. 2, and FIG. 4b shows an enlarged view of region 'D' of FIG. 2.

[0027] Referring to FIGS. 2 through 4b, a semiconductor device (100) may include a peripheral circuit region (PERI) and a memory cell region (CELL). The memory cell region (CELL) may be placed on the peripheral circuit region (PERI). The peripheral circuit region (PERI) and the memory cell region (CELL) may be joined to each other through a bonding structure (180, 280). The peripheral circuit region (PERI) may be referred to as a first semiconductor structure, and the memory cell region (CELL) may be referred to as a second semiconductor structure.

[0029] The peripheral circuit region (PERI) may include a first substrate (101), circuit elements (120) on the first substrate (101), a lower wiring structure (130), a lower bonding structure (180), and a lower capping layer (190).

[0031] The first substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate (101) may be provided as a bulk wafer or an epitaxial layer. An active region may be defined in the first substrate (101) by device isolation layers. Source / drain regions (128) containing impurities may be disposed in a part of the active region.

[0033] The circuit elements (120) may include transistors. Each circuit element (120) may include a circuit gate dielectric layer (122), a circuit gate electrode (124), and a source / drain region (128). Source / drain regions (128) containing impurities may be disposed within the first substrate (101) on both sides of the circuit gate electrode (124). Spacer layers (126) may be disposed on both sides of the circuit gate electrode (124). The circuit gate dielectric layer (122) may include silicon oxide, silicon nitride, or a high-k dielectric material. The circuit gate electrode (124) may comprise at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), and tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), and ruthenium (Ru). The circuit gate electrode (124) may comprise a semiconductor layer, for example, a doped polycrystalline silicon layer. In an exemplary embodiment, the circuit gate electrode (124) may be composed of two or more multilayers.

[0035] The lower wiring structure (130) may be electrically connected to the circuit gate electrodes (124) and source / drain regions (128) of the circuit elements (120). The lower wiring structure (130) may include lower contact plugs (135) in the shape of a cylinder or a truncated cone and lower wiring lines (137) in which at least one region is in the form of a line. Some of the lower contact plugs (135) may be connected to the source / drain regions (128), and although not illustrated, other parts of the lower contact plugs (135) may be connected to the gate electrodes (124). The lower contact plugs (135) may electrically connect the lower wiring lines (137) that are positioned at different levels from the upper surface of the first substrate (101). The lower wiring structure (130) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier layer comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). In exemplary embodiments, the number of layers and arrangement of the lower contact plugs (135) and lower wiring lines (137) constituting the lower wiring structure (130) may be varied.

[0037] The lower bonding structure (180) can be connected to the lower wiring structure (130). The lower bonding structure (180) may include a lower bonding via (182), a lower bonding pad (184), and a lower bonding insulating layer (186). The lower bonding via (182) can be connected to the lower wiring structure (130). The lower bonding pad (184) can be connected to the lower bonding via (182). The lower bonding via (182) and the lower bonding pad (184) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier layer. The lower bonding insulating layer (186) may also function as a diffusion barrier layer for the lower bonding pad (184) and may include at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The lower bonding insulating layer (186) may have a thickness thinner than that of the lower bonding pad (184), but is not limited thereto. The lower bonding structure (180) may be joined or connected to the upper bonding structure (280) by direct contact through hybrid bonding. For example, the lower bonding pad (184) may be joined to the upper bonding pad (284) by copper (Cu)-to-copper bonding, and the lower bonding insulating layer (186) may be joined to the upper bonding insulating layer (286) by dielectric-to-dielectric bonding. Together with the upper bonding structure (280), the lower bonding structure (180) may provide an electrical connection path between the peripheral circuit region (PERI) and the memory cell region (CELL).

[0039] The lower capping layer (190) is disposed on the first substrate (101) and can cover the circuit elements (120) and the lower wiring structure (130). The lower capping layer (190) may include a plurality of insulating layers. The lower capping layer (190) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0041] A memory cell region (CELL) may include a second substrate (201), first and second horizontal conductive layers (202, 204) below the second substrate (201), via patterns (215) on the second substrate (201), gate electrodes (230) stacked below the second substrate (201), a separation region (MS) extending through the stacked structure of the gate electrodes (230), channel structures (CH) arranged to penetrate the stacked structure, contact plugs (252, 253, 254) for electrical connection with a peripheral circuit region (PERI), a source connection pattern (260) connected to a source contact plug (253) among the contact plugs (252, 253, 254), an upper wiring structure (270) below the stacked structure, and an upper bonding structure (280) connected to the upper wiring structure (270). The memory cell region (CELL) may further include an outer insulating layer (205) in contact with the outer end of the second substrate (201), first to third horizontal sacrificial layers (211, 212, 213) between the second substrate (201) and the second horizontal conductive layer (204), interlayer insulating layers (220) alternately stacked with gate electrodes (230) under the second substrate (201), a peripheral contact pad (265) and a peripheral contact via (267) on a peripheral contact plug (254) among contact plugs (252, 253, 254), an upper capping layer (290) covering the stacked structure, upper insulating layers (210, 295) on the second substrate (201), and a conductive pad (300) on the peripheral contact via (267).

[0043] In the memory cell region (CELL), the memory cell array region (MCA), connection region (CA), and outer region (PA) can be defined, for example, based on the second substrate (201) and its surrounding components.

[0044] The memory cell array region (MCA) may be a region in which gate electrodes (230) are stacked spaced apart from each other in a vertical direction, e.g., the Z direction, as shown in FIG. 2, and channel structures (CH) are arranged. The connection region (CA) may be a region in which gate electrodes (230) are extended at different lengths to provide contact pads for electrically connecting memory cells to a peripheral circuit region (PERI), as shown in FIG. 2. The memory cell array region (MCA) and the connection region (CA) may be understood as regions including the second substrate (201) and encompassing both the lower region and the upper region of the second substrate (201).

[0045] The outer region (PA) may refer to an area from the outer end of the second substrate (201) to the edge of the semiconductor device (100), as illustrated in FIG. 2, and may be an area where a conductive pad (300), a source contact plug (253), and a peripheral contact plug (254) are placed. The outer region (PA) may be an area other than the area where the memory cell array area (MCA) and the connection area (CA) are placed in the memory cell area (CELL). The outer region (PA) may refer to an area where an outer insulating layer (205) placed on the outside of the second substrate (201) is placed, or may refer to an area including the outer insulating layer (205) and including both the area below and the area above the outer insulating layer (205).

[0047] The second substrate (201) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The second substrate (201) may further include impurities. The second substrate (201) may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or as an epitaxial layer.

[0049] The first and second horizontal conductive layers (202, 204) may be stacked and disposed on the lower surface of the second substrate (201) in the memory cell array region (MCA). The first horizontal conductive layer (202) may function as part of the common source line of the semiconductor device (100), for example, as a common source line together with the second substrate (201). The first horizontal conductive layer (202) may penetrate the gate dielectric layer (245) and come into contact with the channel layer (240). The first horizontal conductive layer (202) may not extend into the connection region (CA), and the second horizontal conductive layer (204) may also be disposed in the connection region (CA). The second horizontal conductive layer (204) may include a portion bent to contact the end of the first horizontal conductive layer (202), and said portion may extend to contact the second substrate (201).

[0050] The first and second horizontal conductive layers (202, 204) may include a semiconductor material, for example, polycrystalline silicon. In this case, at least the first horizontal conductive layer (202) may be a layer doped with impurities of the same conductivity type as the second substrate (201), and the second horizontal conductive layer (204) may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer (202). However, the material of the second horizontal conductive layer (204) is not limited to a semiconductor material and may be replaced with an insulating layer.

[0052] The first to third horizontal sacrificial layers (211, 212, 213) may be disposed below the second substrate (201) in parallel with the first horizontal conductive layer (202) in a part of the connection region (CA). The first to third horizontal sacrificial layers (211, 212, 213) may be stacked sequentially below the second substrate (201). The first to third horizontal sacrificial layers (211, 212, 213) may be layers remaining after a portion of them is replaced by the first horizontal conductive layer (202) during the manufacturing process of the semiconductor device (100). However, in exemplary embodiments, the arrangement of the region where the first to third horizontal sacrificial layers (211, 212, 213) remain in the connection region (CA) may be varied.

[0053] The first and third horizontal sacrificial layers (211, 213) and the second horizontal sacrificial layer (212) may contain different insulating materials. The first and third horizontal sacrificial layers (211, 213) may contain the same material. For example, the first and third horizontal sacrificial layers (211, 213) may be made of the same material as the interlayer insulating layers (220), and the second horizontal sacrificial layer (212) may be made of the same material as the sacrificial insulating layers (218). The first and third horizontal sacrificial layers (211, 213) may contain silicon oxide, and the second horizontal sacrificial layer (212) may contain silicon nitride.

[0055] The outer insulating layer (205) may be disposed in an area where a portion of the second substrate (201) has been removed, and may be disposed to be in contact with the outer end of the second substrate (201). The lower surface of the outer insulating layer (205) may substantially co-plane with the lower surface of the second substrate (201), but is not limited thereto. The outer insulating layer (205) may be made of an insulating material and may include, for example, silicon oxide, silicon oxynitride, or silicon nitride.

[0057] Via patterns (215) can be placed on the second substrate (201). The via patterns (215) can be arranged in multiple numbers spaced apart at regular intervals along the X and Y directions. The via patterns (215) can be connected to the upper part of the second substrate (201) and can extend from the second substrate (201) in a vertical direction, for example, in the Z direction. Each of the via patterns (215) may have a lower width greater than the upper width. The via patterns (215) can be formed integrally with the second substrate (201). The via patterns (215) form a continuous structure with the second substrate (201), and the via patterns (215) and the second substrate (201) may be made of the same material, for example, a semiconductor material containing impurities of the same conductivity type. In an exemplary embodiment, the via patterns (215) may comprise at least one of a semiconductor material, for example, silicon (Si) and germanium (Ge). The via patterns (215) may be made of a doped semiconductor material containing impurities. For example, the via patterns (215) may comprise at least one of a P-type dopant, such as boron (B), aluminum (Al), gallium (Ga), and indium (In), or at least one of an N-type dopant, such as phosphorus (P), arsenic (As), and antimony (Sb). In an exemplary embodiment, the via patterns (215) and the second substrate (201) may each comprise polycrystalline silicon containing N-type impurities.

[0058] Each of the via patterns (215) may be a bypass via. The via patterns (215) may perform the function of grounding the second substrate (201) and the second horizontal conductive layer (204) during the manufacturing process of the semiconductor device (100) to prevent the occurrence of arcing.

[0059] The upper surface of each via pattern (215) can come into contact with the source connection pattern (260). The via patterns (215), together with the source connection pattern (260), can serve as a connection contact layer for electrically connecting the second substrate (201) to the source contact plug (253). That is, even if the source contact plug (253) is not directly connected to the second substrate (201), the via patterns (215) and the source connection pattern (260) provide an electrical connection path between the source contact plug (253) and the second substrate (201), so the source contact plug (253) and the second substrate (201) can be electrically connected to each other.

[0061] Gate electrodes (230) may be stacked vertically spaced apart from the second substrate (201) to form a stacked structure. Gate electrodes (230) may be placed between the second substrate (201) and the upper wiring structure (270). The gate electrodes (230) may include electrodes forming a ground select transistor, memory cells, and a string select transistor sequentially from the second substrate (201). The number of gate electrodes (230) forming the memory cells may be determined according to the storage capacity of the semiconductor device (100). According to an embodiment, the gate electrodes (230) forming the string select transistor and the ground select transistor may each be one or two or more, and may have the same or different structure as the gate electrodes (230) of the memory cells. Additionally, the gate electrodes (230) may further include a gate electrode (230) forming an erase transistor that is disposed at the bottom of the gate electrode (230) forming the string select transistor and at the top of the gate electrode (230) forming the ground select transistor and is used for an erase operation utilizing the Gate Induced Drain Leakage (GIDL) phenomenon.

[0062] Gate electrodes (230) are stacked spaced apart from each other along the vertical direction in the memory cell array region (MCA) and may extend from the memory cell array region (MCA) to the connection region (CA) at different lengths to form a stepped structure. The gate electrodes (230) may have a stepped structure along the X direction as shown in FIG. 2, and may also be arranged to have a stepped structure relative to each other in the Y direction. Due to the stepped structure, the gate electrodes (230) may form a stepped shape in which the upper gate electrode (230) extends longer than the lower gate electrode (230) and provide ends exposed from the interlayer insulating layers (220) toward the first substrate (101). In exemplary embodiments, at the ends, the gate electrodes (230) may have an upward thickness. Although not illustrated, some electrodes among the gate electrodes (230) that form the string select transistor may be separated by a separating insulating layer extending in the X direction.

[0063] The gate electrodes (230) may form a lower gate stacking group and an upper gate stacking group on the lower gate stacking group. The interlayer insulating layer (220) disposed between the lower gate stacking group and the upper gate stacking group may have a relatively thick thickness, but is not limited thereto. In FIG. 2, the stacking groups of the gate electrodes (230) are shown as being arranged in two vertically, but are not limited thereto, and the gate electrodes (230) may form a single stacking group or multiple stacking groups.

[0064] The gate electrodes (230) may comprise a metallic material, such as tungsten (W). According to an embodiment, the gate electrodes (230) may comprise polycrystalline silicon or a metal silicide material. In exemplary embodiments, the gate electrodes (230) may further comprise a diffusion barrier layer, for example, the diffusion barrier layer may comprise tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0066] Interlayer insulating layers (220) may be disposed between gate electrodes (230). The interlayer insulating layers (220), like the gate electrodes (230), may also be disposed spaced apart from each other in a direction perpendicular to the lower surface of the second substrate (201) and extended in the x-direction. The interlayer insulating layers (220) may include an insulating material such as silicon oxide or silicon nitride.

[0068] The separation region (MS) may be positioned to extend along the X direction through the gate electrodes (230) in the memory cell array region (MCA) and the connection region (CA). The separation region (MS) may be connected to the second substrate (201) by penetrating the entire gate electrodes (230) stacked beneath the second substrate (201). The separation region (MS) may have a shape in which the width decreases toward the second substrate (201) due to a high aspect ratio. The separation region (MS) may extend in the X direction to separate the gate electrodes (230) from each other in the Y direction. The separation region (MS) may include an insulating material such as silicon oxide or silicon nitride.

[0070] Channel structures (CH) each form a single memory cell string and can be spaced apart from each other in rows and columns in the memory cell array area (MCA). Channel structures (CH) can be arranged to form a grid pattern in the XY plane or arranged in a zigzag shape in one direction. Channel structures (CH) can extend in the Z direction, have a columnar shape, and have inclined sides that become narrower as they get closer to the second substrate (201) according to the aspect ratio.

[0071] Each of the channel structures (CH) may have a form in which lower and upper channel structures are connected, penetrating the lower gate stacking group and the upper gate stacking group of the gate electrodes (230), respectively, and may have a bending portion due to a difference or change in width in the connection area.

[0072] As illustrated in FIG. 4b, a channel layer (240) may be disposed within the channel structures (CH). The channel layer (240) of the lower channel structure and the channel layer (240) of the upper channel structure may be connected. Within the channel structures (CH), the channel layer (240) may be formed in an annular shape surrounding an internal core insulating layer (247), but according to the embodiment, it may have a columnar shape such as a cylinder or a prismatic column without a core insulating layer (247). The channel layer (240) may be connected to a first horizontal conductive layer (202) at the top. The channel layer (240) may include a semiconductor material such as polycrystalline silicon or single-crystal silicon.

[0073] Channel pads (249) may be disposed on the lower portion of the channel layer (240) in the channel structures (CH). The channel pads (249) may cover the lower portion of the core insulating layer (247) and come into contact with the channel layer (240). The channel pads (249) may include, for example, doped polycrystalline silicon.

[0074] A gate dielectric layer (245) may be disposed between the gate electrodes (230) and the channel layer (240). A gate dielectric layer (245) may be disposed between the second substrate (201) and the channel layer (240). As illustrated in FIG. 4b, the gate dielectric layer (245) may include a tunneling layer (241), an information storage layer (242), and a blocking layer (243) sequentially stacked from the channel layer (240). The tunneling layer (241) may tunnel charges to the information storage layer (242) and may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or a combination thereof. The information storage layer (242) may include silicon nitride (Si3N4) and may be a charge trap layer. The blocking layer (243) may comprise silicon oxide (SiO2), silicon oxynitride (SiON), high-dielectric constant (high-k) dielectric material, or a combination thereof. In exemplary embodiments, at least a portion of the gate dielectric layer (245) may extend horizontally along the gate electrodes (230).

[0076] The contact plugs (252, 253, 254) may each have a cylindrical or truncated cone shape and may become narrower toward the top depending on the aspect ratio. The contact plugs (252, 253, 254) may penetrate a portion of the upper capping layer (290). The contact plugs (252, 253, 254) may include a gate contact plug (252), a source contact plug (253), and a peripheral contact plug (254). Each of the gate contact plug (252), the source contact plug (253), and the peripheral contact plug (254) may be spaced apart from each other and arranged in multiple numbers. Each of the contact plugs (252, 253, 254) may include a conductive layer and a barrier layer surrounding the sides and one end of the conductive layer. For example, as illustrated in FIG. 4a, the source contact plug (253) may include a conductive layer (253a) and a barrier layer (253b), and the barrier layer (253b) may surround the top and sides of the conductive layer (253a). The conductive layer (253a) may include a conductive material, for example, a metallic material such as tungsten (W), copper (Cu), or aluminum (Al), and the barrier layer (253b) may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN).

[0077] Gate contact plugs (252) are positioned in a connection area (CA) and may extend in a vertical direction, for example, in the Z direction. The gate contact plugs (252) may be connected to the ends or contact pads of the gate electrodes (230) in a stepped form, respectively. The gate contact plugs (252) may be connected to the upper wiring structure (270) from the bottom.

[0078] The source contact plug (253) may be spaced apart from the second substrate (201) on the outside of the second substrate (201) and may extend in a vertical direction, for example, in the Z direction. With respect to the upper surface of the first substrate (101), the upper surface of the source contact plug (253) may be located at a higher level than the upper surface of the second substrate (201). With respect to the upper surface of the first substrate (101), the upper surface of the source contact plug (253) may be located at substantially the same level as the upper surface of at least one of the via patterns (215). The source contact plug (253) may be connected to the source connection pattern (260) by penetrating the outer insulating layer (205) and the first upper insulating layer (210). For example, the upper surface of the source contact plug (253) may contact the extended portion (EP) of the source connection pattern (260). With respect to the upper surface of the first substrate (101), the lower surface of the source contact plug (253) may be located at a lower level than the lowest gate electrode (230) among the gate electrodes (230). The lower surface of the source contact plug (253) may be connected to the upper wiring structure (270). The width of the upper surface of the source contact plug (253) may be smaller than the width of the lower surface. The source contact plug (253) may be formed in the same process step as the peripheral contact plug (254) and may have the same or similar shape as the peripheral contact plug (254).

[0079] The peripheral contact plug (254) may be spaced apart from the second substrate (201) and the source contact plug (253) on the outside of the second substrate (201) and may extend in a vertical direction, for example, in the Z direction. The peripheral contact plug (254) may be connected to the peripheral contact pad (265) below by penetrating the outer insulating layer (205) and the first upper insulating layer (210). The upper surface of the peripheral contact plug (254) may be in contact with the peripheral contact pad (265). The peripheral contact plug (254) may be connected to the upper wiring structure (270). With respect to the upper surface of the first substrate (101), the upper surface of the peripheral contact plug (254) and the upper surface of the source contact plug (253) may be located at substantially the same level.

[0081] A source connection pattern (260) may be placed on a second substrate (201). The source connection pattern (260) may be placed at a level higher than the upper surface of the second substrate (201) with respect to the upper surface of the first substrate (101). The source connection pattern (260) may electrically connect via patterns (215) and a source contact plug (253) to each other. As shown in FIG. 4a, the source connection pattern (260) may include a conductive layer (260a) and a barrier layer (260b), and the conductive layer (260a) may be placed on the barrier layer (260b). The via patterns (215) and the source contact plug (253) may come into contact with the barrier layer (260b). The conductive layer (260a) may include a conductive material, for example, a metallic material such as tungsten (W), copper (Cu), or aluminum (Al), and the barrier layer (260b) may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN).

[0082] As illustrated in FIG. 3, the source connection pattern (260) may include an area formed of a grid-shaped or mesh-type pattern on the upper surface of the second substrate (201). For example, the source connection pattern (260) may include first patterns (261) extending in the X direction and second patterns (262) extending in the Y direction in a plane parallel to the upper surface of the second substrate (201). The first patterns (261) and the second patterns (262) may intersect each other and may be formed integrally and connected to each other. By having such a shape, the source connection pattern (260) can disperse stress caused by the metal material layer of the source connection pattern (260) and control warpage of the semiconductor device. Via patterns (215) may be arranged to be connected to at least one of the first patterns (261) and the second patterns (262).

[0083] As illustrated in FIGS. 2 and 3, the source connection pattern (260) may include an extension portion (EP) extending onto an outer region (PA) of the second substrate (201). The extension portion (EP) may be a portion extending horizontally from an overlapping portion where the source connection pattern (260) overlaps with the second substrate (201) in the vertical direction (Z). The extension portion (EP) may overlap with a portion of the outer insulating layer (205) in the vertical direction (Z) and may not overlap with the second substrate (201) in the vertical direction (Z). At least one of the first patterns (261) and the second patterns (262) may include an extension portion (EP) extending in a direction away from the second substrate (201) than the outer end of the second substrate (201). In FIG. 3, extension portions (EP) may be arranged in multiple numbers on the outer region (PA) on both sides along the X direction of the first patterns (261) and in multiple numbers on the outer region (PA) on both sides along the Y direction of the second patterns (262). The extension portions (EP) of the source connection pattern (260) may be directly connected to the source contact plug (253).

[0084] When the source contact plug (253) is directly connected to the edge portion of the second substrate (201), the semiconductor material layer of the second substrate (201) may provide an electrical connection path from the edge portion of the second substrate (201) to the channel structure (CH) of the memory cell array region (MCA). The electrical connection path has a length approximately from the edge portion of the second substrate (201) to the channel structure (CH) of the memory cell array region (MCA). In this case, since the semiconductor material layer has a relatively higher electrical resistance than the metal material layer, noise generated by the resistance component of the second substrate (201) may interfere with the operation of the memory cell (e.g., a read operation). For example, when current is flowed through the common source line of the second substrate (201), the resistance component of the second substrate (201) may cause a voltage drop in the common source line, which may prevent the read operation of the memory cell from being performed properly. According to an exemplary embodiment of the present invention, a source contact plug (253) is directly connected to a source connection pattern (260) made of a metal material, and the source connection pattern (260) is widely arranged on the upper surface of a second substrate (201) so that the source contact plug (253) can be electrically connected to the second substrate (201). Accordingly, since the metal material layer of the source connection pattern (260), which has relatively low electrical resistance, can provide an electrical connection path from the source contact plug (253) in the outer region (PA) to the channel structure (CH) of the memory cell array region (MCA), the length of the electrical connection path caused by the semiconductor material layer of the second substrate (201), which has relatively high electrical resistance, can be reduced. Accordingly, since the resistance component of the common source line of the second substrate (201) can be reduced, noise generated by the common source line during the operation of the memory cell can be reduced, and the electrical characteristics and reliability of the semiconductor device can be improved.

[0086] Peripheral contact pads (265) and peripheral contact vias (267) may be placed on peripheral contact plugs (254). Peripheral contact pads (265) may be spaced apart from source connection patterns (260) in an outer region (PA). Peripheral contact pads (265) may be in contact with the upper surface of peripheral contact plugs (254). Peripheral contact vias (267) are placed on peripheral contact pads (265) and may be connected to a conductive pad (300). Peripheral contact vias (267) may have a lower region width that is smaller than the upper region width. Peripheral contact pads (265) and peripheral contact vias (267) may contain the same material as source connection patterns (260). In an exemplary embodiment, peripheral contact vias (267) may contain aluminum (Al).

[0088] The upper wiring structure (270) can electrically connect the gate electrodes (230), channel structures (CH), the second substrate (201), and the conductive pad (300) to the circuit elements (120). The upper wiring structure (270) may include a channel contact plug (271), a gate contact stud (272), a source contact stud (273), a peripheral contact stud (274), an upper contact plug (275), and an upper wiring line (277). The channel contact plug (271) can be connected to the channel pad (249) of the channel structure (CH). The channel contact plug (271) can be electrically connected to the channel layer (240) through the channel pad (249) of the channel structures (CH) in the memory cell array region (MCA). The gate contact stud (272) can be connected to the gate contact plug (252). The source contact stud (273) can be connected to the source contact plug (253). The peripheral contact stud (274) can be connected to the peripheral contact plug (254). The upper contact plug (275) can have a cylindrical or truncated cone shape, and the upper wiring line (277) can have at least one region in the shape of a line. The upper contact plugs (275) can be connected to the channel contact plug (271), the gate contact stud (272), the source contact stud (273), and the peripheral contact stud (274), respectively. The upper wiring line (277) can be connected to the upper contact plug (275). The upper wiring structure (270) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier layer comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN).In exemplary embodiments, the number of layers and arrangement of the upper contact plugs (275) and upper wiring lines (277) constituting the upper wiring structure (280) may be varied.

[0090] The upper bonding structure (280) can be connected to the upper wiring structure (270). The upper bonding structure (280) may include an upper bonding via (282), an upper bonding pad (284), and an upper bonding insulating layer (286). The upper bonding via (282) can be connected to the upper wiring structure (270). The upper bonding pad (284) can be connected to the upper bonding via (282). The upper bonding via (282) and the upper bonding pad (284) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier layer. The upper bonding insulating layer (286) may also function as a diffusion barrier layer for the upper bonding pad (284) and may include at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The upper bonding insulating layer (286) may have a thickness thinner than that of the upper bonding pad (284), but is not limited thereto.

[0092] The upper capping layer (290) is disposed below the second substrate (201) and can cover the second substrate (201), the outer insulating layer (205), and the gate electrodes (230). The upper capping layer (290) may include a plurality of insulating layers. The upper capping layer (290) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0094] Upper insulating layers (210, 295) may be disposed on the second substrate (201). The upper insulating layers (210, 295) may include a first upper insulating layer (210) covering the sides of via patterns (215) and a second upper insulating layer (295) on the first upper insulating layer (210). The second upper insulating layer (295) may cover the source connection pattern (260) and the peripheral contact pad (265). The upper insulating layers (210, 295) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0096] The conductive pad (300) is an input / output pad of the semiconductor device (100) and can be electrically connected to a controller. The conductive pad (300) can be in contact with a peripheral contact via (267). The conductive pad (300) can be electrically connected to circuit elements (120) of a peripheral circuit region (PERI). The conductive pad (300) may include the same material as the source connection pattern (260). In an exemplary embodiment, the conductive pad (300) may include aluminum (Al).

[0098] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. The area marked 'A' in FIG. 5 may correspond to a cross-section of the semiconductor device cut along the cutting line Ia-Ia' in FIG. 6.

[0099] FIG. 6 is a plan view illustrating some components of a semiconductor device according to exemplary embodiments. FIG. 6 illustrates a region corresponding to FIG. 3.

[0100] Referring to FIGS. 5 and 6, the arrangement of patterns in the semiconductor device (100A) may differ in some ways from the preceding embodiment. For example, in the semiconductor device (100A), via patterns (215) may be arranged so as to be directly connected to regions where the first patterns (261) and the second patterns (262) intersect each other. The via patterns (215) may be arranged on the same straight line as the first patterns (261) and may be arranged on the same straight line as the second patterns (262). However, such arrangement is exemplary, and the arrangement relationship and shape of the via patterns (215) and the source connection pattern (260) may vary depending on the embodiment, and will be further explained exemplarily with reference to FIGS. 8a to 8f below.

[0102] FIG. 7 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 7 illustrates an enlarged view of the region corresponding to region 'C' in FIG. 2.

[0103] Referring to FIG. 7, via patterns (215A) of the semiconductor device (100B) may comprise a material different from that of the second substrate (201). For example, the via patterns (215A) may comprise at least one of a metallic material such as aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo), and a metallic nitride such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The second substrate (201) may comprise a semiconductor material. Since the via patterns (215A) comprise a metallic material, the contact resistance can be lowered compared to the case where a semiconductor material is included. The via patterns (215A) are not formed integrally with the second substrate (201), and the via patterns (215A) can be formed first, a planarization process can be performed, and then the second substrate (201) can be formed. In this case, the boundary between the via patterns (215A) and the second substrate (201) can be distinguished.

[0105] FIGS. 8a through 8f are plan views illustrating some components of a semiconductor device according to exemplary embodiments. FIGS. 8a through 8f illustrate regions corresponding to FIG. 3.

[0106] Referring to FIG. 8a, the source connection pattern (260-A) may include first patterns (261) extending in the X direction, and the first patterns (261) may be electrically connected to the second substrate (201) through via patterns (215) placed underneath. The first patterns (261) may be line-shaped in a plane. The first patterns (261) may include extension portions (EP) extending to an outer region (PA) on both sides along the X direction, and each extension portion (EP) may be directly connected to a source contact plug (253).

[0107] Referring to FIG. 8b, the source connection pattern (260-B) may include second patterns (262) extending in the Y direction, and the second patterns (262) may be electrically connected to the second substrate (201) through via patterns (215) placed underneath. The second patterns (262) may be line-shaped in a plane. The second patterns (262) may include extension portions (EP) extending to an outer region (PA) on both sides along the Y direction, and each extension portion (EP) may be directly connected to a source contact plug (253).

[0108] Referring to FIG. 8c, the source connection pattern (260-C) may include extension portions (EP) in which the first patterns (261) extend to the outer region (PA) on both sides along the X direction, and the second patterns (262B) may not extend to the outer region (PA). The second patterns (262B) may be placed between the first patterns (261) to serve as a bridge connecting the first patterns (261) to each other.

[0109] Referring to FIG. 8d, a plurality of source contact plugs (253), for example, two, may be disposed in each extension portion (EP) of the source connection pattern (260-D). The first pattern (261a) and the second pattern (262a) of the source connection pattern (260-D) may each have a greater width than the first pattern (261) and the second pattern (262) of the preceding embodiment.

[0110] Referring to FIG. 8e, a plurality of source contact plugs (253), for example, two, may be disposed in the extension portion (EP) of each of the first patterns (261) or second patterns (262a) of the source connection pattern (260-E). For example, the second patterns (262a) may have a width greater than the width of each of the first patterns (261).

[0111] Referring to FIG. 8f, the source connection pattern (260-F) may include a plate portion (260P) and a plurality of extension portions (EP) extending from the plate portion (260P) to an outer region (PA). The plate portion (260P) is disposed on the second substrate (201) and may be directly connected to via patterns (215).

[0113] FIG. 9 is a partial enlarged cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 9 illustrates an enlarged view of the region corresponding to region 'D' of FIG. 2.

[0114] Referring to FIG. 9, in the semiconductor device (100C), the memory cell region (CELL) may not include the first and second horizontal conductive layers (202, 204) under the second substrate (201), unlike in the embodiment of FIG. 2. Additionally, the channel structure (CHa) may further include an epitaxial layer (207).

[0115] The epitaxial layer (207) is positioned to contact the second substrate (201) at the top of the channel structure (CHa) and may be positioned on the side of at least one gate electrode (230). The epitaxial layer (207) may be positioned in a recessed area of ​​the second substrate (201). The height of the lower surface of the epitaxial layer (207) may be lower than the lower surface of the top gate electrode (230) and higher than the upper surface of the gate electrode (230) below it, but is not limited to what is illustrated. The epitaxial layer (207) may be connected to the channel layer (240) through its lower surface. A gate insulating layer (208) may be further positioned between the epitaxial layer (207) and the gate electrode (230) adjacent to the epitaxial layer (207).

[0117] FIGS. 10 to 16 are schematic cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. In FIGS. 10 to 16, regions corresponding to the region shown in FIG. 2 are shown.

[0118] Referring to FIG. 10, circuit elements (120), a lower wiring structure (130), a lower bonding structure (180), and a lower capping layer (190) forming a peripheral circuit region (PERI) can be formed on a first substrate (101).

[0119] First, device isolation layers can be formed within the first substrate (101), and a circuit gate dielectric layer (122) and a circuit gate electrode (124) can be sequentially formed on the first substrate (101). The device isolation layers can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer (122) can be formed on the first substrate (101), and the circuit gate electrode (124) can be formed on the circuit gate dielectric layer (122). Next, spacer layers (126) can be formed on both sidewalls of the circuit gate dielectric layer (122) and the circuit gate electrode (124), and source / drain regions (128) can be formed by injecting impurities into the active region of the first substrate (101) on both sides of the circuit gate electrode (124).

[0120] The lower contact plugs (135) of the lower wiring structure (130) can be formed by forming a part of the lower capping layer (190), then etching and removing a part of it, and burying a conductive material. The lower wiring lines (137) can be formed, for example, by depositing a conductive material and then patterning it.

[0121] The lower bonding via (182) of the lower bonding structure (180) can be formed by forming a part of the lower capping layer (190), then etching and removing a part of it, and burying a conductive material. The lower bonding pad (184) can be formed, for example, by depositing a conductive material and then patterning it. The lower bonding structure (180) can be formed, for example, by a deposition process or a plating process. The lower bonding insulating layer (186) can be formed by covering a part of the upper surface and side of the lower bonding pad (184), and then performing a flattening process until the upper surface of the lower bonding pad (184) is exposed.

[0122] The lower capping layer (190) may be composed of a plurality of insulating layers. The lower capping layer (190) may be part of each step of forming the lower wiring structure (130) and the lower bonding structure (180). By doing so, a peripheral circuit region (PERI) may be formed.

[0124] Referring to FIG. 11, via patterns (215) can be formed on a base substrate (10) and a second substrate (201) can be formed. First to third horizontal sacrificial layers (211, 212, 213) and a second horizontal conductive layer (204) can be formed on the second substrate (201). A lower stacked structure can be formed by alternately stacking sacrificial insulating layers (218) and interlayer insulating layers (220), a vertical sacrificial structure (228) penetrating the lower stacked structure can be formed, and an upper stacked structure can be formed by alternately stacking sacrificial insulating layers (218) and interlayer insulating layers (220).

[0125] First, a first upper insulating layer (210) can be formed on a base substrate (10), and via patterns (215) penetrating therein can be formed. The base substrate (10) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The base substrate (10) may be provided for thickness control of the second substrate (201) in the process step of removing the base substrate (10) described below. The via patterns (215) can be formed by forming via holes penetrating a portion of the first upper insulating layer (210) and then filling them with a semiconductor material.

[0126] The second substrate (201) may be formed integrally with the via patterns (215) in the step of forming the via patterns (215), or it may be formed in a separate process step from the via patterns (215). For example, the via patterns (215) may be formed while a semiconductor material layer fills the via holes, and the semiconductor material layer may extend over the upper surface of the via holes and the upper surface of the first upper insulating layer (210) to form the second substrate (201). A portion of the second substrate (201) may be removed from the outer region (PA). An outer insulating layer (205) may be formed in the region where the second substrate (201) is removed from the outer region (PA). In an exemplary embodiment, the semiconductor device (100B) of FIG. 7 may be manufactured by filling the via holes with a metal material, performing a planarization process, forming the second substrate (201), and then performing subsequent processes.

[0127] Next, first to third horizontal sacrificial layers (211, 212, 213) and a second horizontal conductive layer (204) can be formed on the second substrate (201). The second substrate (201) can be formed spaced apart from the base substrate (10) by the first upper insulating layer (210). The first to third horizontal sacrificial layers (211, 212, 213) can be sequentially stacked on the second substrate (201). The first to third horizontal sacrificial layers (211, 212, 213) may be layers that are replaced by the first horizontal conductive layer (202) of FIG. 2, which is formed through a subsequent process in the memory cell array region (MCA). The second horizontal conductive layer (204) can be formed on the third horizontal sacrificial layer (213).

[0128] The sacrificial insulating layers (218) may be layers in which a portion is replaced by gate electrodes (230) (see FIG. 2) through a subsequent process. The sacrificial insulating layers (218) may be made of a material different from the interlayer insulating layers (220) and may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers (220) under specific etching conditions. For example, the interlayer insulating layer (220) may be made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers (218) may be made of a material different from the interlayer insulating layer (220) selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In the embodiments, the thickness of the interlayer insulating layers (220) may not all be the same. The thickness of the interlayer insulating layers (220) and the sacrificial insulating layers (218) and the number of constituent films may vary from what is illustrated.

[0129] In order for the upper sacrificial insulating layers (218) to extend shorter than the lower sacrificial insulating layers (218) in the connection region (CA), photolithography and etching processes can be repeatedly performed on the sacrificial insulating layers (218) using a mask layer. By doing so, the sacrificial insulating layers (218) can form a stepped structure in a predetermined unit.

[0130] A vertical sacrificial structure (228) can be formed by anisotropically etching the lower stacked structure of sacrificial insulating layers (218) and interlayer insulating layers (220) using a mask layer, and by forming lower channel holes in the shape of holes and then filling them. The vertical sacrificial structure (228) may include a semiconductor material such as polycrystalline silicon. In an exemplary embodiment, the vertical sacrificial structure (228) may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. After forming the vertical sacrificial structure (228), an upper stacked structure of sacrificial insulating layers (218) and interlayer insulating layers (220) may be formed on the lower stacked structure and the vertical sacrificial structure (228).

[0131] Next, an upper capping layer (290) covering the laminated structure of the sacrificial insulating layers (218) and the interlayer insulating layers (220) may be partially formed.

[0133] Referring to FIG. 12, channel structures (CH) can be formed penetrating the stacked structure of sacrificial insulating layers (218) and interlayer insulating layers (220). An opening (OP) penetrating the stacked structure of sacrificial insulating layers (218) and interlayer insulating layers (220) can be formed in the region corresponding to the separation region (MS) (see FIG. 2).

[0134] Channel structures (CH) can be formed by embedding hole-shaped channel holes into a plurality of layers. The plurality of layers may include a gate dielectric layer (245), a channel layer (240), a core insulating layer (247), and a channel pad (249). The upper channel holes of the channel holes can be formed by anisotropically etching the upper stacked structure of the sacrificial insulating layers (218) and interlayer insulating layers (220) using a separate mask layer. The lower channel holes of the channel holes can be formed by removing the vertical sacrificial structure (228) exposed through the upper channel holes. When a plasma dry etching process is used to form the channel holes, a potential difference may be generated between the upper and lower parts of the channel holes due to ions generated within the channel holes. However, the second horizontal conductive layer (204) and the second substrate (201) are connected to the base substrate (10) by via patterns (215), so that, for example, positive charges can flow to the base substrate (10) and negative charges that have moved through the mask layer can flow to the base substrate (10), thereby preventing the occurrence of arcing defects caused by the potential difference.

[0135] Due to the height of the stacked structure, the side walls of the channel structures (CH) may not be perpendicular to the upper surface of the second substrate (201). The channel structures (CH) may be formed to recess a portion of the second substrate (201).

[0136] The gate dielectric layer (245) may be formed to have a uniform thickness. In this step, the gate dielectric layer (245) may be formed in whole or in part, and a portion extending perpendicularly to the second substrate (201) along the channel structures (CH) may be formed in this step. The channel layer (240) may be formed on the gate dielectric layer (245) within the channel structures (CH). The core insulating layer (247) is formed to fill the channel structures (CH) and may be an insulating material. The channel pad (249) may be made of a conductive material, for example, polycrystalline silicon.

[0137] Next, the opening (OP) may be formed to penetrate the stacked structure of the sacrificial insulating layers (218) and the interlayer insulating layers (220), and to penetrate the second horizontal conductive layer (204) and the first to third horizontal sacrificial layers (211, 212, 213) from the bottom. The opening (OP) may be formed to partially recess the second substrate (201).

[0139] Referring to FIG. 13, the sacrificial insulating layers (218) can be removed through the opening (OP) and the gate electrodes (230) can be formed. A separation region (MS) can be formed in the opening (OP).

[0140] First, a second horizontal sacrificial layer (212) can be exposed by an etch-back process while forming separate sacrificial spacer layers within the opening (OP). The second horizontal sacrificial layer (212) can be selectively removed from the exposed area in the memory cell array area (MCA), and then the upper and lower first and third horizontal sacrificial layers (211, 213) can be removed.

[0141] The first to third horizontal sacrificial layers (211, 212, 213) can be removed by an etching process. During the removal process of the first and third horizontal sacrificial layers (211, 213), a portion of the gate dielectric layer (245) exposed in the area where the second horizontal sacrificial layer (212) was removed can also be removed. After forming a first horizontal conductive layer (202) by depositing a conductive material in the area where the first to third horizontal sacrificial layers (211, 212, 213) were removed, the sacrificial spacer layers can be removed within the opening (OP). By this process, the first horizontal conductive layer (202) can be formed in the memory cell array area (MCA), and the first to third horizontal sacrificial layers (211, 212, 213) can remain in the connection area (CA).

[0142] Next, the sacrificial insulating layers (218) can be removed through the opening (OP) to form tunnel sections, and the tunnel sections can be filled with a conductive material to form gate electrodes (230). The conductive material may include a metal, polycrystalline silicon, or metal silicide material. After forming the gate electrodes (230), the conductive material deposited within the opening (OP) can be removed through an additional process, and then an insulating material can be filled to form a separation region (MS).

[0144] Referring to FIG. 14, an upper wiring structure (270) including gate contact plugs (252), source contact plugs (253), peripheral contact plugs (254), and channel contact plugs (271) can be formed, and an upper bonding structure (280) can be formed.

[0145] Gate contact plugs (252) may be formed to be connected to gate electrodes (230) in a connection region (CA), and source contact plugs (253) and peripheral contact plugs (254) may be formed to be connected to a base substrate (10) in an outer region (PA). Channel contact plugs (271) may be formed to be connected to channel structures (CH) in a memory cell array region (MCA). The gate contact plugs (252), source contact plugs (253), and peripheral contact plugs (254) may be formed at different depths, but may be formed by simultaneously forming contact holes using an etch stop layer or the like, and then filling the contact holes with a conductive material. However, in exemplary embodiments, it may be possible for some of the gate contact plugs (252), source contact plugs (253), and peripheral contact plugs (254) to be formed in different process steps.

[0146] Contact studs (272, 273, 274) can be formed to be connected to gate contact plugs (252), source contact plugs (253), and peripheral contact plugs (254), respectively. Upper contact plugs (275) can be formed on the contact studs (272, 273, 274) and can connect upper wiring lines (277) to each other vertically.

[0147] Next, the upper bonding structure (280) can be formed in a manner similar to that of forming the lower bonding structure (180). By doing so, a memory cell region (CELL) can be formed. However, during the manufacturing process of the semiconductor device, the memory cell region (CELL) may further include a base substrate (10).

[0149] Referring to FIG. 15, the peripheral circuit region (PERI), which is the first substrate structure, and the memory cell region (CELL), which is the second substrate structure, can be joined.

[0150] The peripheral circuit region (PERI) and the memory cell region (CELL) can be connected by bonding the lower bonding pad (184) and the upper bonding pad (284) by applying pressure. The lower bonding insulating layer (186) and the upper bonding insulating layer (286) can be connected by bonding them by applying pressure. The memory cell region (CELL) on the peripheral circuit region (PERI) can be bonded upside down so that the upper bonding pad (284) faces downward. The peripheral circuit region (PERI) and the memory cell region (CELL) can be directly bonded without the interposition of an adhesive, such as a separate adhesive layer.

[0152] Referring to FIG. 16, the base substrate (10) can be removed to form a source connection pattern (260) and a peripheral contact pad (265).

[0153] First, the base substrate (10) can be removed by a polishing process, such as a grinding process, or a chemical mechanical polishing process. The base substrate (10) can be completely removed so that the surface of the via patterns (215) is exposed. The surface of the source contact plug (253) and the peripheral contact plug (254) can also be exposed.

[0154] Next, a metal layer may be formed on the first upper insulating layer (210), and the metal layer may be patterned to form a source connection pattern (260) and a peripheral contact pad (265). The source connection pattern (260) may be formed to include an extension portion (EP) in an outer region (PA) so as to be directly connected to the source contact plug (253) and may be directly connected to each via pattern (2150). The source connection pattern (260) may be formed to have various shapes as illustrated in FIGS. 3, FIGS. 6, and FIGS. 8a through 8f. For example, the source connection pattern (260) may include at least one region having a grid shape or a line shape in a plane. The peripheral contact pad (265) may be formed spaced apart from the source connection pattern (260). In an exemplary embodiment, the source connection pattern (260) and the peripheral contact pad (265) may be formed by first patterning the insulating layer and then filling it with a conductive material.

[0156] Next, a portion of the second upper insulating layer (295) can be formed, and peripheral contact vias (267) and conductive pads (300) can be formed. Peripheral contact vias (267) can be formed by forming via holes that penetrate a portion of the second upper insulating layer (295) and then filling them with a conductive material. Conductive pads (300) can also be formed by removing a portion of the second upper insulating layer (295) and then filling them with a conductive material. By doing so, the semiconductor device of FIGS. 1 to 4b can be manufactured.

[0158] FIG. 17 is a schematic diagram illustrating a data storage system including a semiconductor device according to exemplary embodiments.

[0159] Referring to FIG. 17, the data storage system (1000) may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The data storage system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the data storage system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100).

[0160] The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device described above with reference to FIGS. 1 through 8. The semiconductor device (1100) may include a first semiconductor structure (1100F) and a second semiconductor structure (1100S) on the first semiconductor structure (1100F). In exemplary embodiments, the first semiconductor structure (1100F) may be placed next to the second semiconductor structure (1100S). The first semiconductor structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second semiconductor structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0162] In the second semiconductor structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0163] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0164] In exemplary embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT1) may be used for an erase operation to delete data stored in memory cell transistors (MCTs) using the GIDL phenomenon.

[0165] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connection lines (1115) extending from the first semiconductor structure (1100F) to the second semiconductor structure (1100S). The bit lines (BL) can be electrically connected to the page buffer (1120) through second connection lines (1125) extending from the first semiconductor structure (1100F) to the second semiconductor structure (1100S).

[0166] In the first semiconductor structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCT). The decoder circuit (1110) and the page buffer (1120) can be controlled by a logic circuit (1130). The semiconductor device (1000) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first semiconductor structure (1100F) to the second semiconductor structure (1100S).

[0168] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the data storage system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1000).

[0169] The processor (1210) can control the overall operation of the data storage system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the data storage system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0171] FIG. 18 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment.

[0172] Referring to FIG. 18, a data storage system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0173] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the data storage system (2000) and the external host. In exemplary embodiments, the data storage system (2000) may communicate with the external host according to any one of the interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the data storage system (2000) may operate by power supplied from the external host through the connector (2006). The data storage system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0174] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the data storage system (2000).

[0175] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the data storage system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the DRAM (2004) is included in the data storage system (2000), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0177] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0178] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 17 and may be an area including the conductive pad (300) of FIG. 2. Each of the semiconductor chips (2200) may include gate stacking structures (3210) and channel structures (3220). Each of the semiconductor chips (2200) may include the semiconductor device described above with reference to FIGS. 1 to 9.

[0179] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to embodiments, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0180] In exemplary embodiments, the controller (2002) and the semiconductor chips (2200) may be included in a single package. In an exemplary embodiment, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0182] FIG. 19 is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 19 illustrates an exemplary embodiment of the semiconductor package (2003) of FIG. 18 and conceptually shows a region of the semiconductor package (2003) of FIG. 18 cut along the cutting line II-II'.

[0183] Referring to FIG. 19, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120) (see FIG. 18), lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body portion (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) can be connected to the wiring patterns (2005) of the main board (2010) of the data storage system (2000) through conductive connections (2800) as in FIG. 18.

[0185] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first semiconductor structure (3100) and a second semiconductor structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first semiconductor structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second semiconductor structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), channel structures (3220) penetrating the gate stacking structure (3210) and separation regions (3230), bit lines (3240) electrically connected to the memory channel structures (3220), and contact plugs (3235) electrically connected to the word lines (WL) (see FIG. 17) of the gate stacking structure (3210). As described above with reference to FIGS. 1 to 9, in each of the semiconductor chips (2200), the source contact plug (253) is directly connected to the source connection pattern (260), and the source connection pattern (260) can be arranged to be directly connected to via patterns (215) connected to the upper part of the second substrate (201).

[0186] Each of the semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first semiconductor structure (3100) and extends into the second semiconductor structure (3200). The through-wire (3245) may be positioned outside the gate stack structure (3210) and may be further positioned to penetrate the gate stack structure (3210). Each of the semiconductor chips (2200) may further include an input / output pad (2210) (see FIG. 18) that is electrically connected to the peripheral wiring (3110) of the first semiconductor structure (3100), and the input / output pad (2210) may be an area including a conductive pad (300).

[0188] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0190] CH: Channel structure MS: Separation area 101: First substrate 120: Circuit element 130: Lower wiring structure 180: Lower bonding structure 190: Lower capping layer 201: Second substrate 202, 204: Horizontal conductive layer 205: Outer insulating layer 215: Via pattern 211, 212, 213: Horizontal sacrificial layer 218: Sacrificial insulation layer 220: Interlayer insulation layer 230: Gate electrode 240: Channel layer 245: Gate dielectric layer 247: Core insulating layer 249: Channel Pad 252: Gate Contact Plug 253: Source contact plug 254: Peripheral contact plug 260: Source connection pattern 265: Peripheral contact pad 267: Peripheral contact via 270: Upper wiring structure 280: Upper bonding structure 290: Upper capping layer

Claims

Claim 1 A first semiconductor structure comprising a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure; and a second semiconductor structure comprising: a second substrate disposed on the first semiconductor structure and including an upper surface and a lower surface opposite to the upper surface and facing the first substrate; gate electrodes stacked spaced apart from each other along a vertical direction perpendicular to the lower surface of the second substrate; channel structures each including a channel layer that penetrates the gate electrodes and extends in the vertical direction; an upper wiring structure disposed below the gate electrodes and the channel structures; and an upper bonding structure connected to the upper wiring structure and bonded to the lower bonding structure. The second semiconductor structure further comprises via patterns on the upper surface of the second substrate, a source contact plug spaced apart from the second substrate, and a source connection pattern that contacts the upper surface of each of the via patterns and electrically connects the via patterns and the source contact plug to each other. The source connection pattern includes an overlapping portion that overlaps with the second substrate in the vertical direction and an extension portion that extends from the overlapping portion in a horizontal direction parallel to the lower surface of the second substrate. The source contact plug is connected to the extension portion of the source connection pattern and the vertical Semiconductor device overlapping in the direction. Claim 2 A semiconductor device according to claim 1, wherein, with respect to the upper surface of the first substrate, the upper surface of the source contact plug is located at a higher level than the upper surface of the second substrate, and the upper surface of the source contact plug is in contact with the extended portion of the source connection pattern. Claim 3 A semiconductor device according to claim 1, wherein, with respect to the upper surface of the first substrate, the upper surface of the source contact plug is located at the same level as the upper surface of at least one of the via patterns. Claim 4 A semiconductor device according to claim 1, wherein the source connection pattern comprises at least one region having a grid shape or a line shape on the upper surface of the second substrate. Claim 5 A semiconductor device according to claim 1, wherein the source connection pattern comprises a barrier layer and a conductive layer on the barrier layer, and the barrier layer contacts the via patterns and the source contact plug. Claim 6 In claim 1, each of the via patterns is a semiconductor device in which the width of the lower portion is greater than the width of the upper portion. Claim 7 A semiconductor device according to claim 1, wherein the via patterns and the second substrate are made of a semiconductor material containing impurities of the same conductivity type. Claim 8 A semiconductor device according to claim 1, wherein the second substrate is made of a semiconductor material and the via patterns are each made of a metal material. Claim 9 A semiconductor device according to claim 1, wherein the second semiconductor structure further comprises a peripheral contact plug extending in the vertical direction, spaced apart from the source contact plug on the outside of the second substrate. Claim 10 In claim 9, the semiconductor device further comprises a second semiconductor structure, a peripheral contact pad that contacts the upper surface of the peripheral contact plug and is spaced apart from the source connection pattern, a peripheral contact via on the peripheral contact pad, and a conductive pad on the peripheral contact via. Claim 11 A semiconductor device according to claim 9, wherein, with respect to the upper surface of the first substrate, the upper surface of the peripheral contact plug and the upper surface of the source contact plug are located at the same level. Claim 12 A semiconductor device comprising: a first substrate; circuit elements disposed on the first substrate; a lower wiring structure electrically connected to the circuit elements; a lower bonding structure connected to the lower wiring structure; an upper bonding structure joined to the lower bonding structure; an upper wiring structure connected to the upper bonding structure; a second substrate disposed on the upper wiring structure and comprising an upper surface and a lower surface opposite to the upper surface and facing the first substrate; gate electrodes disposed between the upper wiring structure and the second substrate and stacked spaced apart from each other; channel structures penetrating the gate electrodes and each comprising a channel layer; via patterns on the upper surface of the second substrate; a source contact plug spaced apart from the second substrate at the outside of the second substrate and having an upper surface at a level higher than the upper surface of the second substrate relative to the upper surface of the first substrate and a lower surface at a level lower than the lower surface of the lowest gate electrode among the gate electrodes; and a source connection pattern in contact with the upper surface of each of the via patterns and the upper surface of the source contact plug. Claim 13 In claim 12, the width of the upper surface of the source contact plug is smaller than the width of the lower surface, and each of the via patterns has an upper width smaller than the lower width, forming a semiconductor device. Claim 14 A semiconductor device according to claim 12, wherein, with respect to the upper surface of the first substrate, the upper surface of the source contact plug is located at the same level as the upper surface of at least one of the via patterns. Claim 15 In claim 12, the source connection pattern is a semiconductor device having a mesh-type pattern on the upper surface of the second substrate. Claim 16 A semiconductor device according to claim 12, wherein, in a plane parallel to the upper surface of the second substrate, the source connection pattern comprises first patterns extending in a first direction and second patterns extending in a second direction intersecting the first patterns. Claim 17 A semiconductor device according to claim 16, wherein in the above plane, at least one of the first patterns and the second patterns includes an extension portion extending in a direction further away from the second substrate than the outer end of the second substrate, and the upper surface of the source contact plug contacts the extension portion of the source connection pattern. Claim 18 In claim 16, the semiconductor device wherein the via patterns are connected to at least one of the first patterns and the second patterns. Claim 19 A first semiconductor structure comprising a first substrate and circuit elements on the first substrate; a second semiconductor structure comprising a second substrate having an upper surface and a lower surface opposite to the upper surface and facing the first semiconductor structure, gate electrodes stacked spaced apart from each other on the lower surface of the second substrate, and channel structures penetrating the gate electrodes; a semiconductor storage device comprising an input / output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device through the input / output pad and controlling the semiconductor storage device, wherein the first semiconductor structure further comprises a lower wiring structure electrically connected to the circuit elements; and a lower bonding structure connected to the lower wiring structure, and the second semiconductor structure comprises an upper bonding structure bonded to the lower bonding structure; an upper wiring structure connected to the upper bonding structure; and via patterns on the upper surface of the second substrate. A data storage system further comprising: a source connection pattern that contacts the upper surface of each of the above via patterns and includes an overlapping portion that overlaps with the second substrate in a vertical direction perpendicular to the lower surface of the second substrate and an extension portion that extends from the overlapping portion in a horizontal direction parallel to the lower surface of the second substrate; and a source contact plug that is connected to the upper wiring structure, is spaced apart from the second substrate at the outside of the second substrate, and extends in the vertical direction to contact the extension portion of the source connection pattern. Claim 20 A data storage system according to claim 19, wherein the source contact plug overlaps with the extended portion of the source connection pattern in the vertical direction, and the upper surface of the source contact plug in contact with the extended portion of the source connection pattern is located at a higher level than the upper surface of the second substrate.

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