Hybrid Thin Film Transistor And Organic Light Emitting Display Using The Same

Abstract

The present invention relates to a hybrid type thin-film transistor in which different types of thin-film transistors are disposed on the same flexible substrate, and an organic light-emitting display device using the same. The organic light-emitting display device according to the present invention comprises a flexible substrate having a display area and a non-display area, a first buffer layer disposed across the entire surface of the flexible substrate, a driving transistor disposed on the buffer layer in the display area and comprising a polycrystalline silicon (LTPS) layer, a first gate electrode, a first source electrode, and a first drain electrode, and a capacitor electrode located on the first source electrode of the driving transistor and constituting a storage capacitor together with the first source electrode. Additionally, the organic light-emitting display device comprises a switching transistor that is spaced apart from a driving transistor in a display area and includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, and a dummy electrode that is positioned above the switching transistor and is disposed on the same plane as the capacitor electrode using the same material, wherein the dummy electrode is the third gate electrode of the switching transistor. According to another feature of the present invention, an organic light-emitting display device comprises a flexible substrate having a display area and a non-display area, a driving transistor located in the display area in which a polycrystalline silicon (LTPS) layer is the active layer, and a switching transistor located in the display area and spaced apart from the driving transistor. Additionally, the switching transistor includes a first gate electrode, an oxide semiconductor layer overlapping with the gate electrode, a source electrode in contact with one side of the oxide semiconductor layer, a drain electrode in contact with the other side of the oxide semiconductor layer, and a second gate electrode connected to the first gate electrode.

Description

Technology Field

[0001] The present invention relates to a hybrid type thin-film transistor in which different types of thin-film transistors are arranged on the same flexible substrate, and an organic light-emitting display device using the same. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. The display device field has rapidly evolved into flat panel display devices (FPDs) that are thin, light, and capable of large areas, replacing bulky cathode ray tubes (CRTs).

[0003] Flat panel display devices include Liquid Crystal Display Devices (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Display Devices (OLEDs), and Electrophoretic Display Devices (EDs).

[0004] In the case of an active-type driven liquid crystal display, organic light-emitting display, and electrophoretic display, a thin-film transistor substrate is provided, wherein thin-film transistors allocated within pixel regions arranged in a matrix manner are disposed therein.

[0005] Liquid Crystal Display Devices (LCDs) display images by controlling the light transmittance of liquid crystals using an electric field. Organic Light Emitting Diodes display images by forming organic light-emitting elements on the pixels themselves, which are arranged in a matrix manner.

[0006] Organic light-emitting displays are self-luminous devices that emit light on their own, offering the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle.

[0007] In particular, organic light-emitting displays (OLEDs) that utilize the characteristics of organic light-emitting diodes with excellent energy efficiency are broadly classified into passive matrix type organic light-emitting displays (PMOLEDs) and active matrix type organic light-emitting displays (AMOLEDs).

[0008] An organic light-emitting display arranges pixels, each containing an organic light-emitting element and a pixel circuit, in a matrix form, and controls the brightness of the image by pixels driven according to the gradation of the video data.

[0009] In addition, the organic light-emitting display device comprises a plurality of gate electrode lines, a plurality of data lines, and a plurality of power lines, and a plurality of pixels connected to said lines and arranged in a matrix form. Each pixel comprises an organic light-emitting element composed of an organic light-emitting layer between an anode and a cathode, and a pixel circuit that independently drives the organic light-emitting element. The pixel circuit mainly consists of a switching transistor for transmitting a data signal, a driving transistor for driving the organic light-emitting element according to the data signal, and a capacitor for maintaining the data voltage. The switching transistor charges the data voltage into the capacitor in response to a scan pulse. The driving transistor controls the amount of current supplied to the organic light-emitting element according to the data voltage charged in the capacitor, thereby controlling the amount of light emitted by the organic light-emitting element. Furthermore, the turn-on time of the switching transistor can be made shorter than that of the driving transistor. Such turn-on time of the transistor is related to the power consumption of the organic light-emitting display device.

[0010] As the development of personal electronic devices becomes more active, display devices are also being developed into products with excellent portability and / or wearability. As such, display devices capable of low power consumption are required for application in portable or wearable devices. However, there are limitations in achieving low power consumption with the display technologies developed to date.

[0011] Consequently, in order to overcome these problems, there is a recent need for new pixel structures and organic light-emitting display devices capable of driving pixels with low power consumption. The problem to be solved

[0012] As described above, the inventors of the present invention have invented a new pixel structure and an organic light-emitting display device for driving pixels of an organic light-emitting display device with low power consumption.

[0013] Accordingly, the problem to be solved by the present invention is to provide a new pixel structure and an organic light-emitting display device in which a driving transistor having a polycrystalline silicon (LTPS) layer as the active layer and a switching transistor having an oxide semiconductor layer as the active layer are formed.

[0014] In addition, another problem that the present invention aims to solve is to provide a new structure and an organic light-emitting display device that improves bias temperature stress and shields external light incident on the upper and lower parts of the channel by forming a dummy metal pattern on a switching transistor including an oxide semiconductor layer so that the switching transistor has a dual gate electrode structure. means of solving the problem

[0015] To achieve the above objective, the organic light-emitting display device according to the present invention comprises a flexible substrate having a display area and a non-display area, a first buffer layer disposed across the entire surface of the flexible substrate, a driving transistor disposed on the buffer layer in the display area and comprising a polycrystalline silicon (LTPS) layer, a first gate electrode, a first source electrode and a first drain electrode, and a capacitor electrode located on the first source electrode of the driving transistor and constituting a storage capacitor together with the first source electrode.

[0016] Additionally, the device is characterized by comprising a switching transistor spaced apart from a driving transistor in a display area and including an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, and a dummy electrode positioned above the switching transistor and disposed on the same plane as the capacitor electrode using the same material, wherein the dummy electrode is the third gate electrode of the switching transistor.

[0017] According to another feature of the present invention, an organic light-emitting display device comprises a flexible substrate having a display area and a non-display area, a driving transistor located in the display area in which a polycrystalline silicon (LTPS) layer is the active layer, and a switching transistor located in the display area and spaced apart from the driving transistor.

[0018] Additionally, the switching transistor includes a first gate electrode, an oxide semiconductor layer overlapping with the gate electrode, a source electrode in contact with one side of the oxide semiconductor layer, a drain electrode in contact with the other side of the oxide semiconductor layer, and a second gate electrode connected to the first gate electrode. Effects of the invention

[0019] The organic light-emitting display device according to the present invention may have the characteristic of compensating for the disadvantages of one thin-film transistor by forming a driving transistor with a polycrystalline silicon (LTPS) layer as the active layer and a switching transistor with an oxide semiconductor layer as the active layer on the same substrate. In particular, by providing an oxide semiconductor thin-film transistor, low-speed driving can be achieved and power consumption reduced, thereby providing an organic light-emitting display device suitable for portable and / or wearable devices. In addition, by forming a storage capacitor (Cst) between the source electrode of the driving transistor and a portion of the electrode of the dummy metal pattern, the area of ​​the storage capacitor (Cst) of the high-resolution display device can be increased. Furthermore, by forming a dummy metal pattern on the switching transistor and utilizing a switching transistor having a double-gate electrode structure, bias temperature stress can be improved and external light incident on the upper and lower parts of the channel can be shielded. Brief explanation of the drawing

[0020] FIG. 1 is a configuration diagram of an organic light-emitting display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing the pixel structure illustrated in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a flowchart showing the pixel manufacturing process illustrated in FIG. 1 according to an embodiment of the present invention. FIGS. 4a to 4c are process cross-sectional views for explaining the pixel manufacturing process illustrated in FIG. 1 according to an embodiment of the present invention. Specific details for implementing the invention

[0021] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details.

[0023] Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the invention, such detailed description is omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0024] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit indication. In the case of descriptions regarding positional relationships, for example, where the positional relationship between two parts is described using expressions such as 'on,' 'above,' 'below,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0025] When an element or layer is referred to as being on another element or layer, it includes cases where another layer or element is placed directly on top of another element or in between.

[0026] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0027] Throughout the specification, the same reference numerals refer to the same components.

[0028] The size and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

[0029] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and as will be fully understood by those skilled in the art, various technical interlocking and operation are possible, and each embodiment may be implemented independently of one another or together in an interlocking relationship.

[0030] In the present invention, the transistor may be configured as a P-type or N-type, and for convenience of explanation, the transistor is configured as an N-type in the following embodiments.

[0031] Hereinafter, an organic light-emitting display device and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0032] FIG. 1 is a configuration diagram of an organic light-emitting display device according to an embodiment of the present invention.

[0033] The organic light-emitting display device (10) illustrated in FIG. 1 comprises a display panel (2) in which a plurality of gate lines (GL) and a plurality of data lines (DL) intersect to define each pixel (1), a gate driver (4) that transmits a pixel (1) driving signal to a plurality of gate lines (GL), a data driver (3) that transmits a pixel (1) driving voltage to a plurality of data lines (DL), and a timing controller (5) that aligns image data (RGB) input from the outside and supplies it to the data driver (3), and outputs a gate control signal (GCS) and a data control signal (DCS) to control the gate driver (4) and the data driver (3).

[0034] In an embodiment of the present invention, each pixel (1) is provided with an organic light-emitting diode (OLED) and a pixel driving circuit that independently drives the organic light-emitting diode (OLED), including a driving transistor that supplies a driving current to the organic light-emitting diode (OLED). The pixel driving circuit can compensate for deviations in electrical characteristics of the driving transistor, such as threshold voltage (Vth) and mobility, and can reduce deviations in brightness between each pixel (1) caused by differences in current supplied to the organic light-emitting diode (OLED). A pixel (1) according to such an embodiment of the present invention will be described in detail later with reference to FIGS. 2 to 4c.

[0035] The display panel (2) is provided with a plurality of intersecting gate lines (GL) and a plurality of data lines (DL), and a plurality of pixels (1) are arranged in the intersecting areas of these (GL, DL). Each pixel (1) is provided with an organic light-emitting diode (OLED) and a pixel driving circuit. Each pixel (1) is connected to a gate line (GL), a data line (DL), a first voltage (VDD) supply line (VDDL), and a second voltage (VSS) supply line (VSSL).

[0036] The gate driver (4) supplies a plurality of gate electrode signals to a plurality of gate lines (GL) according to a plurality of gate control signals (GCS) provided by the timing controller (5). The plurality of gate electrode signals include first and second scan signals (SCAN1, SCAN2), and these signals are supplied to each pixel (1) through the plurality of gate lines (GL). The first voltage (VDD) is a high potential voltage and has a voltage relatively higher than the second voltage (VSS), which is a low potential voltage. The second voltage (VSS) may be a ground voltage.

[0037] The data driver (3) converts digital image data (RGB) input from the timing controller (5) into a data voltage (Vdata) using a reference gamma voltage according to a plurality of data control signals (DCS) provided from the timing controller (5). Then, it supplies the converted data voltage (Vdata) to a plurality of data lines (DL). Meanwhile, the data driver (3) outputs the data voltage (Vdata) during the programming period of each pixel (1).

[0038] The timing controller (5) aligns the image data (RGB) input from the outside to the size and resolution of the display panel (2) and supplies it to the data driver (3). The timing controller (5) generates a plurality of gate control signals and data control signals (GCS, DCS) using synchronization signals (SYNC) input from the outside, such as a dot clock (DCLK), a data enable signal (DE), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync). Then, by supplying the generated plurality of gate control signals and data control signals (GCS, DCS) to the gate driver (4) and the data driver (3), respectively, the gate driver (4) and the data driver (3) are controlled.

[0039] Hereinafter, a pixel according to an embodiment of the present invention will be described in detail. FIG. 2 is a cross-sectional view schematically showing the pixel structure illustrated in FIG. 1.

[0040] With reference to FIG. 2, the structure of a pixel (1) of an organic light-emitting display device is described. As shown in FIG. 2, a pixel (1) according to an embodiment of the present invention includes a lower substrate (110), a buffer layer (111), a bottom shield metal (BSM, 120), an active buffer layer (112), an LTPS thin film transistor (130), an oxide semiconductor thin film transistor (140), a dummy metal layer (150), an organic light-emitting element (160), and a signal wiring (170).

[0041] In addition, a pixel (1) according to an embodiment of the present invention includes a gate insulating layer (113), an interlayer insulating layer (114), a passivation layer (115), a flattening layer (116), a bank (117), and an encapsulation portion (118).

[0042] The lower substrate (110) may be made of a plastic-based polymer material such as polyimide (PI). A plurality of switching transistors (ST) and driving transistors (DT) involved in driving an organic light-emitting diode (OLED) are formed on the lower substrate (110).

[0043] The lower substrate (110) may be attached to an auxiliary substrate (not shown). The auxiliary substrate may consist of a glass substrate and a sacrificial layer. The auxiliary substrate may be separated from the lower substrate (110) on which the organic light-emitting element is formed through a laser release process.

[0044] Additionally, the lower substrate (110) may include a display area and a non-display area. In the display area, a plurality of pixel areas are arranged in a matrix manner. Display elements for display functions are placed in the pixel areas. The non-display area is placed around the display area, and driving elements for driving the display elements formed in the pixel areas may be placed therein. Additionally, a portion of the non-display area of ​​the lower substrate (110) may be bent as needed.

[0045] The display area may be divided into a first area and a second area spaced apart from the first area. An organic light-emitting display device pixel (1) according to the present invention includes a first thin-film transistor disposed in the first area and a second thin-film transistor disposed in the second area on a lower substrate (110). The first thin-film transistor may be an LTPS thin-film transistor (130), and the second thin-film transistor may be an oxide semiconductor thin-film transistor (140). In particular, when a plurality of thin-film transistors are included within a single pixel area, the first thin-film transistor and the second thin-film transistor may be disposed adjacent to each other. In particular, the first thin-film transistor comprising a polycrystalline semiconductor material may be applied to a driving thin-film transistor, and the second thin-film transistor comprising an oxide semiconductor material may be applied to a switching thin-film transistor.

[0046] Additionally, the first thin-film transistor may be a thin-film transistor for a gate driving element formed in a non-display area, and the second thin-film transistor may be a thin-film transistor for a display element disposed within the pixel area of ​​the display area. Furthermore, when a gate driving element is formed in a non-display area, it can be implemented as a C-MOS type thin-film transistor including a polycrystalline silicon (LTPS) layer. That is, both P-MOS type and N-MOS type thin-film transistors including a polycrystalline silicon (LTPS) layer are formed in the gate driving portion within the non-display area. In this case, multiple mask processes are required for the N-MOS type to form a low-density doping region. Here, the N-MOS type thin-film transistor including the polycrystalline silicon (LTPS) layer can be replaced with a thin-film transistor including an oxide semiconductor layer to form a heterogeneous thin-film transistor. Then, since the low-density doping region can be excluded, there is an advantage in that the number of mask processes can be reduced.

[0047] A substrate equipped with such heterogeneous thin-film transistors can be applied to an organic light-emitting display device. For example, in the case of an organic light-emitting display device, the second thin-film transistor may be a switching thin-film transistor that selects a pixel, and the first thin-film transistor may be a driving thin-film transistor that drives the selected pixel. In some cases, the configuration may be reversed.

[0048] Next, a buffer layer (111) is formed over the entire surface of the lower substrate (110).

[0049] That is, the buffer layer (111) is formed across the entire display area and non-display area of ​​the lower substrate (110). The buffer layer (111) may have a structure in which multiple thin films are deposited. Here, for convenience, it is described as a single layer. It is more preferable to use silicon oxide (SiOx) for the buffer layer (111) so as not to have a special effect on the device.

[0050] Additionally, as shown in FIG. 2, a portion of the buffer layer (111) located in the non-display area may have a groove formed to minimize cracks that may occur during bending.

[0051] Next, the BSM (120) is selectively formed only in the necessary areas on the buffer layer (111). Additionally, the BSM (120) can be formed using a molybdenum (Mo) material. The BSM (120) is located on the buffer layer (111) and can be positioned to overlap with the LTPS thin-film transistor (130), which is the driving thin-film transistor of the pixel (1).

[0052] BSM (120) can fundamentally block potential generation on the surface of the lower substrate (110) and light entering from the outside.

[0053] Specifically, in the pixel (1) according to the embodiment of the present invention, the active layer of various transistors, including the driving transistor (DT), may be damaged by the laser release process. Additionally, a negative charge trap may be generated in the sacrificial layer by the laser and light introduced from the outside, and accordingly, positive charges may move from the polyimide (PI) forming the lower substrate (110) toward the sacrificial layer. Consequently, the potential of the surface of the lower substrate (110) may increase. As a result, the current flowing through the transistor may be reduced.

[0054] Additionally, the source electrode (133) of the LTPS thin-film transistor (130) connected to the organic light-emitting diode (OLED) remains in a floating state when the LTPS thin-film transistor (130) is turned off. In this case, as the potential of the surface of the lower substrate (110) increases, parasitic capacitance may occur between the lower substrate (110) and the source electrode (133) of the LTPS thin-film transistor (130), and the source electrode (133) may be continuously affected by the parasitic capacitance. Therefore, the current flowing through the source electrode of the LTPS thin-film transistor (130) may fluctuate due to the parasitic capacitance, and accordingly, afterimages may occur even upon restoration.

[0055] Additionally, after the laser release process, when a pixel (1) of an organic light-emitting display device (100) including a lower substrate (110) composed of a plastic-based polymer material such as polyimide (PI) is driven, heat may be generated in the lower substrate (110). As a result, charged particles generated in the lower substrate (110) move upward. The charged particles may affect the active layer of thin-film transistors and reduce the reliability of the organic light-emitting display device (100).

[0056] Accordingly, as shown in FIG. 2, the BSM (120) is electrically connected to the source electrode (133) of the LTPS thin-film transistor (130), thereby minimizing the effect on the charge flowing in the channel of the thin-film transistor driving the pixel (1), and as a result, the current drop phenomenon in which the driving current of the thin-film transistor is lowered, the restoration afterimage problem, and the reliability of the organic light-emitting display device (100) can be resolved.

[0057] Next, an active buffer layer (112) is positioned on the buffer layer (111) to surround the BSM (120) and protect the active layer of the LTPS thin-film transistor (130). The active buffer layer (112) is formed only in the display area of ​​the lower substrate (110). The active buffer layer (112) can be composed of the same material as the buffer layer (111).

[0058] Next, the LTPS thin film transistor (130) is positioned on the active buffer layer (112). The LTPS thin film transistor (130) may be composed of an active layer (131), a gate electrode (132), a source electrode (133), and a drain electrode (134).

[0059] The active layer (131) of the LTPS thin-film transistor (130) is composed of polycrystalline silicon (LTPS) material. Since LTPS material has high mobility (100 cm² / Vs or more), low power consumption, and excellent reliability, it can be applied to a gate driver and / or multiplexer (MUX) for driving devices that drive thin-film transistors for display devices. Alternatively, it is preferable to apply it as a driving thin-film transistor within a pixel in an organic light-emitting display device (100). When forming a semiconductor layer with LTPS material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when forming a semiconductor layer with an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is desirable to form the LTPS layer, which is processed under harsh conditions, first, and then form the oxide semiconductor layer later. In addition, to simplify the manufacturing process, it is desirable to form the components of the LTPS thin-film transistor (130) containing the LTPS layer and the oxide semiconductor thin-film transistor (140) containing the oxide semiconductor layer on the same layer. For example, it is preferable to form the gate electrode (132) of the LTPS thin film transistor (130) and the gate electrode (142) of the oxide semiconductor thin film transistor (140) on the same layer with the same metal material, and to also form the source-drain electrodes of each thin film transistor on the same layer with the same metal material. In particular, in order to secure the characteristics of the semiconductor device, it is preferable to form a top-gate structure that can accurately define the channel region.

[0060] The active layer (131) is formed on the upper surface of the active buffer layer (112). The active layer (131) includes the channel region (CA) of the LTPS thin-film transistor (130). The channel region (CA) is defined as the region where the gate electrode (132) and the active layer (131) overlap. Since the gate electrode (132) overlaps with the central part of the LTPS thin-film transistor (130), the central part of the LTPS thin-film transistor (130) becomes the channel region (CA). Both sides of the channel region (CA) are regions doped with impurities, and are defined as the source region (SA) and the drain region (DA).

[0061] A doping region including a source region (SA) and a drain region (DA) is defined by injecting impurities. The source region (SA) and the drain region (DA) may each include a high-density doping region (HDD) and a low-density doping region (LDD).

[0062] Additionally, the active layer (131) is formed by low-temperature crystallization of a polycrystalline semiconductor material such as polycrystalline silicon. When the LTPS thin film transistor (130) is a driving thin film transistor (DT), it is desirable that it has characteristics suitable for performing high-speed driving processing. For example, a thin film transistor of the P-MOS or N-MOS type may be used, or a thin film transistor of the C-MOS type that includes both may be provided. It is desirable that the thin film transistors of the P-MOS, N-MOS and / or C-MOS type include a polycrystalline semiconductor material such as polycrystalline silicon.

[0063] In addition, a gate electrode (132) is formed to overlap with the channel region (CA) of the active layer (131). As a result, the LTPS thin-film transistor (130) has a top-gate structure.

[0064] Additionally, as shown in FIG. 2, the source electrode (133) of the LTPS thin-film transistor (130) is in contact with the doping region of the active layer (131) and is electrically connected to the organic light-emitting diode (160). Additionally, the source electrode (133) may be electrically connected to the BSM (120). The drain electrode (134) of the LTPS thin-film transistor (130) is electrically connected to the source electrode of the oxide semiconductor thin-film transistor (140).

[0065] Next, the gate insulating layer (113) of the LTPS thin-film transistor (130) is formed on the active layer (131) of the LTPS thin-film transistor (130) in the display area of ​​the lower substrate (110). The gate insulating layer (113) may be formed of silicon nitride (SiNx) or silicon oxide (SiOx). In the case of the gate insulating layer (113), it is preferable to have a thickness of approximately 1,000 Å to 1,500 Å, considering the stability and characteristics of the device. If the gate insulating layer (113) is formed of silicon nitride (SiNx), a large amount of hydrogen may be contained within the gate insulating layer (113) during the manufacturing process. Since this hydrogen may diffuse to the outside of the gate insulating layer (113) during subsequent processes, it is preferable to form the gate insulating layer (113) with a silicon oxide (SiOx) material.

[0066] Next, the oxide semiconductor thin film transistor (140) is located on the gate insulating layer (113) in the display area of ​​the lower substrate (110). The oxide semiconductor thin film transistor (140) may be composed of an active layer (141), a gate electrode (142), a source electrode (143), and a drain electrode (144).

[0067] In addition, as shown in FIG. 2, a gate electrode (142) of an oxide semiconductor thin film transistor (140) is formed on the gate insulating layer (113).

[0068] The active layer (141) of the oxide semiconductor thin-film transistor (140) is composed of an oxide semiconductor material. For example, it is preferable to include oxide semiconductor materials such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO), and Indium Zinc Oxide (IZO). Oxide semiconductor materials have the characteristic of low off-current, which extends the voltage maintenance period of the pixel, making them suitable for display devices requiring low-speed operation and low power consumption. When including oxide semiconductor materials, it is preferable to have a bottom-gate structure that can more effectively secure the stability of the device when considering a structure that includes different types of thin-film transistors on a single substrate according to an embodiment of the present invention.

[0069] The active layer (141) of the oxide semiconductor thin film transistor (140) is located on the gate electrode (142), and the source electrode (143) and drain electrode (144) of the oxide semiconductor thin film transistor (140) are electrically contacted with the active layer (141). Additionally, the source electrode (143) is connected to the drain electrode (134) of the LTPS thin film transistor (130).

[0070] Additionally, signal wiring (170) can be formed in the non-display area of ​​the lower substrate (110) using the same material as the source electrode (143) and drain electrode (144) of the oxide semiconductor thin film transistor (140).

[0071] Additionally, the gate electrode (142) of the oxide semiconductor thin film transistor (140) is formed on the same plane with the same material as the gate electrode (132) of the LTPS thin film transistor (130). Additionally, the gate electrode (142) of the oxide semiconductor thin film transistor (140) may be formed with the same material as the BSM (120).

[0072] Subsequently, the interlayer insulating layer (114) is positioned over the gate electrode (132) of the LTPS thin-film transistor (130) and the gate electrode (142) of the oxide semiconductor thin-film transistor (140) in the display area of ​​the lower substrate (110). The interlayer insulating layer (114) preferably has a double-layer structure in which a nitride film (SIN) containing silicon nitride (SiNx) and an oxide film (SiO) containing silicon oxide (SiOx) are sequentially deposited. The interlayer insulating layer (114) is formed prior to the subsequent heat treatment process of the activation process and hydrogenation process for the active layer (131) of the LTPS thin-film transistor (130).

[0073] The nitride film (SIN) of the interlayer insulating layer (114) is deposited to perform hydrogenation treatment on the active layer (131) of the LTPS thin film transistor (130) containing polycrystalline silicon by diffusing hydrogen contained therein through a subsequent heat treatment process. The hydrogenation process refers to a process of filling less bonded spaces with hydrogen through an activation process for the active layer (131) of the LTPS thin film transistor (130).

[0074] On the other hand, the oxide film (SiO) of the interlayer insulating layer (114) is deposited to prevent hydrogen released from the nitride film (SIN) by a subsequent heat treatment process from diffusing too much into the semiconductor material of the oxide semiconductor thin film transistor (140), i.e., the active layer (141).

[0075] For example, hydrogen released from the nitride film (SIN) of the interlayer insulating layer (114) is preferably diffused into the active layer (131) of the LTPS thin-film transistor (130) positioned between the gate insulating layer (113) below it. Therefore, it is preferable that the nitride film (SIN) be deposited directly on the gate insulating layer (113). Accordingly, it is preferable to deposit an oxide film (SiO) on the nitride film (SIN). Considering the manufacturing process, it is preferable that the total thickness of the interlayer insulating layer (114) be 2,000 Å to 6,000 Å. Accordingly, it is preferable that the thickness of the nitride film (SIN) and the oxide film (SiO), respectively, be 1,000 Å to 3,000 Å. In addition, a large amount of hydrogen within the nitride film (SIN) of the interlayer insulating layer (114) can be diffused into the active layer (141) of the oxide semiconductor thin-film transistor (140). In particular, the oxide film (SiO) of the interlayer insulating layer (114) is intended to control the degree of diffusion of hydrogen released from the nitride film (SIN), and it is preferable that the thickness of the oxide film (SiO) be thicker than that of the gate insulating layer (113).

[0076] Additionally, the oxide film (SiO) of the interlayer insulating layer (114) inhibits the movement of hydrogen from the nitride film (SIN), which contains a relatively large amount of hydrogen, to the active layer (141) of the oxide semiconductor thin film transistor (141). When hydrogen moves from the nitride film (SIN) to the active layer (141) of the oxide semiconductor thin film transistor (140), reduction of the active layer (141) of the oxide semiconductor thin film transistor (140) proceeds, and a change occurs in the threshold voltage (Vth) of the oxide semiconductor thin film transistor (140).

[0077] Accordingly, an interlayer insulating layer (114) having a double-layer structure in which a nitride film (SIN) containing silicon nitride (SiNx) and an oxide film (SiO) containing silicon oxide (SiOx) are sequentially deposited is placed on the gate electrode (132) of an LTPS thin film transistor (130) and the gate electrode (132) of an oxide semiconductor thin film transistor (140).

[0078] Accordingly, during the subsequent heat treatment process, the movement of hydrogen from the interlayer insulating layer (114) to the active layer (141) of the oxide semiconductor thin film transistor (140) can be suppressed.

[0079] In addition, since the oxide film (SiO) of the interlayer insulating layer (114) that is in direct contact with the active layer (141) of the oxide semiconductor thin film transistor (140) is made of silicon oxide (SiOx) with a low hydrogen content, the effect of hydrogen can be reduced compared to when the insulating layer made of silicon nitride (SiNX) is in direct contact with the active layer (141) of the oxide semiconductor thin film transistor (140).

[0080] In particular, if the activation process and hydrogenation process for the active layer (131) of the LTPS thin film transistor (130) are not performed immediately after the interlayer insulating layer (114) is formed, but are performed after the active layer (141) of the oxide semiconductor thin film transistor (140) is formed, more hydrogen can move from the interlayer insulating layer (114) to the active layer (141) of the oxide semiconductor thin film transistor (140) due to the high temperature applied during the activation process and hydrogenation process.

[0081] Accordingly, in an organic light-emitting display device (100) according to one embodiment of the present invention, an interlayer insulating layer (114) having a double-layer structure in which a nitride film (SIN) containing silicon nitride (SiNx) and an oxide film (SiO) containing silicon oxide (SiOx) are sequentially deposited can be used to reduce the diffusion of hydrogen into the active layer (141) of an oxide semiconductor thin film transistor (140).

[0082] Therefore, the reduction of the active layer (141) of the oxide semiconductor thin film transistor (140) can be minimized, and the change in the threshold voltage (Vth) of the oxide semiconductor thin film transistor (140) can be minimized.

[0083] Additionally, contact holes are formed in the gate insulating layer (113) and the interlayer insulating layer (114) to expose the source region (SA) and drain region (DA) of the active layer (131) of the LTPS thin-film transistor (130).

[0084] Next, the passivation layer (115) is formed over the entire display area and non-display area of ​​the lower substrate (110).

[0085] Additionally, the passivation layer (115) is located on the upper surface of the interlayer insulating layer (114) and is formed to cover the LTPS thin film transistor (130) and the oxide semiconductor thin film transistor (140) to serve as a protective layer. The passivation layer (115) can cover the signal wiring (170) in a pattern shape so that cracks can be minimized when bending in the non-display area of ​​the lower substrate (110).

[0086] A dummy metal pattern (150) is located on the upper surface of the passivation layer (115). The dummy metal pattern (150) consists of a storage capacitor electrode (151) that forms a storage capacitor (Cst) together with the source electrode (133) of the LTPS thin film transistor (130), and a dummy electrode (152) that serves as the second gate electrode of the oxide semiconductor thin film transistor (140). The dummy metal pattern (150) may be composed of the same material as the source electrode (133) of the LTPS thin film transistor (130).

[0087] The storage capacitor electrode (151) overlaps with the source electrode (133) of the LTPS thin-film transistor (130) and is positioned with a large area. Additionally, the dummy metal pattern (150) forms a storage capacitor (Cst) together with the source electrode (133). The storage capacitor (Cst) can have a large capacitance by utilizing the storage capacitor electrode (151) with a large area, so it can be utilized in an organic light-emitting display device that requires high resolution.

[0088] A dummy electrode (152) is located on the upper part of an oxide semiconductor thin-film transistor (140). Additionally, the dummy electrode (152) can be connected to the gate electrode (142) of the oxide semiconductor thin-film transistor (140) through a contact metal pattern (not shown) and become the second gate electrode of the oxide semiconductor thin-film transistor (140). Thus, the dummy electrode (152) can serve to shield external light incident on the channel of the oxide semiconductor thin-film transistor (140) and has a feature that is advantageous against the Bias Temperature Stress (BTS) that the oxide semiconductor thin-film transistor (140) receives during the manufacturing process.

[0089] Next, the flattening layer (116) is placed on the passivation layer (115) on which the dummy metal pattern (150) is formed.

[0090] In the case of an organic light-emitting display device (100) according to an embodiment of the present invention, an organic light-emitting element (160) can be formed after completing an LTPS thin film transistor (130) and an oxide semiconductor thin film transistor (140). The organic light-emitting element (160) includes an organic light-emitting layer (162), and it is preferable that the organic light-emitting layer (162) be formed on a flat surface formed by a flattening layer (116). The flattening layer (116) is a layer disposed to flatten the upper surface of a lower substrate (110), and may include an organic insulating material, and it is preferable that the thickness be applied thickly to be 5,000 Å or more.

[0091] Next, the organic light-emitting element (160) is positioned on the upper surface of the flattening layer (116). The organic light-emitting element (160) consists of an anode electrode (161) which is a pixel electrode, an organic light-emitting layer (162), and a cathode electrode (163).

[0092] The anode electrode (161) is electrically connected to an LTPS thin film transistor (130) that acts as a driving thin film transistor (DT) using a contact metal pattern (not shown) among the dummy metal patterns (150).

[0093] A bank (117) is formed on a flattening layer (116) on which an anode electrode (161) is formed. The bank (117) has a structure that exposes a light-emitting region on the anode electrode (161) and covers the remaining portion. Therefore, when an organic light-emitting layer (162) is formed on the flattening layer (116) on which the bank (117) is formed, the organic light-emitting layer (162) can be stacked so as to make direct surface contact with the anode electrode (161) exposed within the light-emitting region. Subsequently, by stacking a cathode electrode (163) on the organic light-emitting layer (162), an organic light-emitting device (160) in which the anode electrode (161), the organic light-emitting layer (162), and the cathode electrode (163) are stacked in the light-emitting region can be completed.

[0094] Next, an encapsulation portion (118) is formed on the organic light-emitting element (160). Additionally, the encapsulation portion (118) is also located on the non-display area of ​​the lower substrate (110). The encapsulation portion (118) can serve to block foreign substances and moisture entering from the outside.

[0095] Finally, a signal wiring (170) is formed in the non-display area of ​​the lower substrate (110). The signal wiring (170) may be formed of the same material as the source and drain electrodes (143, 144) of the oxide semiconductor thin-film transistor (140). Additionally, the signal wiring (170) is electrically connected to a gate driver (4) that transmits a driving signal to the pixel (1).

[0096] FIG. 3 is a schematic flowchart for explaining a pixel illustrated in FIG. 1 according to an embodiment of the present invention. FIG. 4a to 4c are process cross-sectional views for explaining a method for manufacturing a pixel illustrated in FIG. 1 according to an embodiment of the present invention. FIG. 3 and FIG. 4a to 4c are a flowchart and process cross-sectional views for explaining a method for manufacturing a pixel (1) of an organic light-emitting display device (100) illustrated in FIG. 2, and redundant descriptions are omitted.

[0097] First, a buffer layer (111) is formed on the lower substrate (110) (S1000).

[0098] Referring to FIG. 4a, a buffer layer (111) is deposited on the surface of a lower substrate (110). Specifically, a single layer of buffer layer (111) may be formed by depositing either silicon nitride (SiNx) or silicon oxide (SiOx), or a multi-layer buffer layer (111) may be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx).

[0099] Next, a BSM (120) is formed on the surface of the buffer layer (111) (S1010).

[0100] Referring to FIG. 4a, a BSM (120) is deposited on a buffer layer (111). For example, a single layer of BMS (120) can be formed using the same material as the gate electrode (132) of an LTPS thin-film transistor (130).

[0101] Next, an active buffer layer (112) is formed on the buffer layer (111) (S1020).

[0102] Referring to FIG. 4b, an active buffer layer (112) is deposited to cover the BSM (120) on the surface of the buffer layer (111). Specifically, a single layer of active buffer layer (112) may be formed by depositing either silicon nitride (SiNx) or silicon oxide (SiOx), or a multi-layer active buffer layer (111) may be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx).

[0103] Next, an active layer (131) of an LTPS thin-film transistor (130) is formed on the active buffer layer (112) (S1030).

[0104] Referring to FIG. 4b, an amorphous silicon (a-Si) material is deposited on the surface of an active buffer layer (112) to form an a-Si layer (S1031), and a dehydrogenation process (S1032) is performed on the a-Si layer. If there is a large amount of hydrogen in the a-Si layer, the hydrogen in the a-Si layer may explode during the subsequent crystallization process (S1033), causing defects. Accordingly, the dehydrogenation process (S1032) is a process for removing hydrogen from the a-Si layer and is performed after the a-Si layer is formed and before the crystallization process (S1033) is performed.

[0105] Next, referring to FIG. 3, after the dehydrogenation process (S1032) is completed, a crystallization process for the a-Si layer is performed (S1033).

[0106] The crystallization process is a process of forming polysilicon by crystallizing amorphous silicon (a-Si) of an a-Si layer, and can be performed, for example, through an excimer laser annealing (ELA) process.

[0107] Next, to form the active layer (131) of the LTPS thin-film transistor (130), the crystallized p-Si layer is patterned (S1034).

[0108] Next, a gate insulating layer (113) of an LTPS thin film transistor (130) is formed (S1040), and a gate electrode (132) of an LTPS thin film transistor (130) and a gate electrode (142) of an oxide semiconductor thin film transistor (140) are formed (S1050).

[0109] Referring to FIG. 4b, a gate insulating layer (113) is formed on the active layer (131) of an LTPS thin-film transistor (130). Specifically, the gate insulating layer (113) can be formed from silicon nitride (SiNx) or silicon oxide (SiOx). In the case of the gate insulating layer (113), it is preferable to have a thickness of approximately 1,000 Å to 1,500 Å, considering the stability and characteristics of the device. If the gate insulating layer (113) is formed from silicon nitride (SiNx), a large amount of hydrogen may be contained within the gate insulating layer (113) during the manufacturing process. Since this hydrogen may diffuse to the outside of the gate insulating layer (113) during subsequent processes, it is preferable to form the gate insulating layer (113) from a silicon oxide (SiOx) material.

[0110] Next, a gate electrode material is deposited on the gate insulating layer (113), and the gate electrode material is patterned to form the gate electrode (132) of the LTPS thin film transistor (130) and the gate electrode (142) of the oxide semiconductor thin film transistor (140) (1050).

[0111] The material for the gate electrode can be various metallic materials such as molybdenum (Mo).

[0112] Next, a doping process is performed on the active layer (131) of the LTPS thin film transistor (130) using the gate electrode (132) of the LTPS thin film transistor (130) as a mask (S1060).

[0113] Referring to FIG. 4b, the source region (SA) and drain region (DA), i.e., the doping region, of the active layer (131) of the LTPS thin film transistor (130) can be defined by injecting impurities into the active layer (131) of the LTPS thin film transistor (130) placed below using the gate electrode (132) of the LTPS thin film transistor (130) as a mask. The process of defining the doping region may differ depending on whether it is a P-MOS thin film transistor, an N-MOS thin film transistor, or a C-MOS thin film transistor.

[0114] For example, in the case of an N-MOS thin-film transistor, a high-density doping region can be formed first, and then a low-density doping region can be formed later. Specifically, a high-density doping region can be defined using a photoresist having a size larger than the gate electrode (132) of the LTPS thin-film transistor (130), and then the photoresist can be removed and a low-density doping region (LDD) can be defined using the gate electrode (132) of the LTPS thin-film transistor (130) as a mask.

[0115] In some embodiments, a doping region including a source region (SA) and a drain region (DA) may be defined before forming the gate insulating layer (113). Immediately after forming the active layer (131) of the LTPS thin-film transistor (130), impurities may be doped using a photoresist.

[0116] Next, an interlayer insulating layer (114) is formed on the gate electrode (132) of the LTPS thin film transistor (130) and the gate electrode (142) of the oxide semiconductor thin film transistor (140) (S1070).

[0117] The interlayer insulating layer (114) is formed prior to the subsequent heat treatment process of the activation process and hydrogenation process for the active layer (131) of the LTPS thin-film transistor (130).

[0118] Referring to FIG. 4b, the interlayer insulating layer (114) can be formed as a double layer structure in which a nitride film (SIN) containing silicon nitride (SiNx) and an oxide film (SiO) containing silicon oxide (SiOx) are sequentially deposited.

[0119] The nitride film (SIN) of the interlayer insulating layer (114) is deposited to perform hydrogenation treatment on the active layer (131) of the thin-film transistor (130) containing polycrystalline silicon by diffusing hydrogen contained therein through a subsequent heat treatment process.

[0120] On the other hand, the oxide film (SiO) of the interlayer insulating layer (114) is deposited to prevent too much hydrogen released from the nitride film (SIN) by a subsequent heat treatment process from diffusing into the semiconductor material of the oxide semiconductor thin film transistor (140).

[0121] Next, an activation process is performed on the active layer (131) of the LTPS thin film transistor (130) (S1080), and a hydrogenation process is performed on the active layer (131) of the LTPS thin film transistor (130) (S1090).

[0122] First, regarding the activation process for the active layer (131) of the LTPS thin-film transistor (130), as a result of the doping process for the active layer (131) of the LTPS thin-film transistor (130) described above, the injected impurities (dopants) exist randomly. Accordingly, the activation process for the active layer (131) of the LTPS thin-film transistor (130) is a process of positioning the impurities in the silicon (Si) lattice. Furthermore, since the doping process for the active layer (131) of the LTPS thin-film transistor (130) is a process of artificially injecting impurities into the active layer, damage to the silicon (Si) may occur as a result of the doping process for the active layer (131) of the LTPS thin-film transistor (130). Accordingly, the damage to the silicon (Si) can be cured by performing an activation process for the active layer (131) of the LTPS thin-film transistor (130).

[0123] Next, regarding the hydrogenation process for the active layer (131) of the LTPS thin-film transistor (130), if vacancies exist in polysilicon, the characteristics deteriorate. Accordingly, the hydrogenation process for the active layer (131) of the LTPS thin-film transistor (130) is a process of filling the vacancies in the polysilicon with hydrogen. The hydrogenation process for the active layer (131) of the LTPS thin-film transistor (130) is performed by diffusing the hydrogen contained in the interlayer insulating layer (150) of the LTPS thin-film transistor (130) through a heat treatment process, and can be performed, for example, through a heat treatment process at approximately 350°C to 380°C. The active layer (131) of the LTPS thin-film transistor (130) can be stabilized by such a hydrogenation process for the active layer (131) of the LTPS thin-film transistor (130).

[0124] Next, an active layer (141) of an oxide semiconductor thin-film transistor (140) is formed on the interlayer insulating layer (114) (S1100).

[0125] Referring to FIG. 3, an IGZO layer is formed by depositing a metal oxide, for example, IGZO, on an interlayer insulating layer (114) (S1101). FIG. 3 describes the formation of an IGZO layer (1292) by assuming that the active layer (141) of the oxide semiconductor thin film transistor (140) is composed of IGZO among various metal oxides, but it is not limited thereto and other metal oxides other than IGZO may be used.

[0126] IGZO deposition is performed at a high temperature. Therefore, IGZO can crystallize during the IGZO deposition process. When IGZO is deposited at room temperature, the IGZO may be in an amorphous state, but when IGZO is deposited at a high temperature, it forms a network with an indium (In), gallium (Ga), and zinc (Zn) bilayer structure. Additionally, as crystallization proceeds at a high temperature, oxygen voids within the IGZO layer are reduced. If there are many oxygen voids within the IGZO layer, tunneling occurs, and consequently, the IGZO layer becomes conductive. Therefore, as crystallization proceeds at a high temperature during IGZO deposition, the BTS characteristics of the oxide semiconductor thin film transistor (140) can be improved and reliability can be increased.

[0127] Next, the IGZO layer is heat-treated (S1102) to stabilize the IGZO layer, and the IGZO layer is patterned (S1103) as shown in FIG. 4b to form the active layer (141) of the oxide semiconductor thin film transistor (140).

[0128] Next, the source electrode (133) and drain electrode (134) of the LTPS thin film transistor (130) and the source electrode (143) and drain electrode (144) of the oxide semiconductor thin film transistor (140) are formed (S1110).

[0129] As shown in FIG. 4b, the source electrode (133) of the LTPS thin film transistor (130) is electrically connected to the BSM (120) through contact holes of the interlayer insulating layer (114), the gate insulating layer (113), and the active buffer layer (112). Additionally, when the source electrode (133) and drain electrode (134) of the LTPS thin film transistor (130) and the source electrode (143) and drain electrode (144) of the oxide semiconductor thin film transistor (140) are formed, signal wiring (170) is formed in the non-display area of ​​the lower substrate (110) using the same material as the source electrode and drain electrode.

[0130] Referring to FIG. 4b, the source electrode (133) and drain electrode (134) of the LTPS thin film transistor (130) and the source electrode (143) and drain electrode (144) of the oxide semiconductor thin film transistor (140) can be formed by depositing and patterning a material for the source electrode and drain electrode on the gate insulating layer (114) and the active layer (141) of the oxide semiconductor thin film transistor (140). At this time, since the source electrode (133) and drain electrode (134) of the LTPS thin film transistor (130) and the source electrode (143) and drain electrode (144) of the oxide semiconductor thin film transistor (140) are formed with a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), the patterning process can be performed through dry etching. Additionally, the patterning process of the source electrode (143) and the drain electrode (144) simultaneously forms a groove in a portion of the buffer layer (111) formed in the non-display area of ​​the lower substrate (110) and removes the remaining insulating layers.

[0131] In some embodiments, to prevent damage to the active layer (141) of the oxide semiconductor thin film transistor (140), dry etching may be applied in two steps, by performing a first dry etching under high etching rate conditions and a second dry etching under low etching rate conditions, so that damage to the active layer (141) of the oxide semiconductor thin film transistor (140) may be reduced.

[0132] Next, a passivation layer (115) is formed to cover the LTPS thin film transistor (130) and the oxide semiconductor thin film transistor (140) (S1120).

[0133] The passivation layer (115) can be formed from silicon nitride (SiNx) or silicon oxide (SiOx). Additionally, the passivation layer (115) is formed over the entire display area and non-display area of ​​the lower substrate (110). Specifically, the passivation layer (115) formed in the non-display area surrounds the signal wiring (170). This can be seen as the passivation layer (115) serving to protect the signal wiring (170).

[0134] Next, a dummy metal pattern (150) is formed on the surface of the passivation layer (115) (S1130).

[0135] Referring to FIG. 4c, the dummy metal pattern (150) consists of a storage capacitor electrode (151) that forms a storage capacitor (Cst) together with the source electrode (133) of the LTPS thin-film transistor (130), and a dummy electrode (152) that serves as the second gate electrode of the oxide semiconductor thin-film transistor (140). The dummy metal pattern (150) may be composed of the same material as the source electrode (133) of the LTPS thin-film transistor (130).

[0136] Next, when forming a dummy metal pattern (150) by dry etching, a passivation layer (115) formed in an unmarked area of ​​the lower substrate (110) is also patterned together (S1140).

[0137] As a result, cracking can be minimized when a portion of the non-displayed area is bent.

[0138] Next, a planarization layer (116) is formed on the passivation layer (115) and the dummy metal pattern (150) (S1150), an anode electrode (161) of the organic light-emitting element (160) is formed on the planarization layer (116) (S1160), a bank (117) is formed on the planarization layer (116) and the anode electrode (161) (S1170), an organic light-emitting layer (162) is formed on the upper surface of the anode electrode (S1180), and a cathode electrode (163) is formed on the upper surface of the organic light-emitting layer (S1190).

[0139] Referring to FIG. 4c, the flattening layer (116) formed in the non-display area is also removed at the time of the process of patterning the organic light-emitting element (160).

[0140] Finally, an encapsulation portion (190) is formed on the organic light-emitting element (180) (S1200).

[0141] A dummy electrode of an organic light-emitting display device according to an embodiment of the present invention is characterized by being connected to a second gate electrode using a contact metal pattern located on the same plane as the second source electrode and made of the same material.

[0142] According to another feature of the present invention, the organic light-emitting display device further includes a lower protection metal pattern positioned on a first buffer layer and arranged to overlap with a driving transistor.

[0143] According to another feature of the present invention, the lower protection metal pattern of the organic light-emitting display device is electrically connected to the first source electrode to minimize the current drop of the driving transistor.

[0144] According to another feature of the present invention, the display area of ​​the organic light-emitting display device further includes a second buffer layer positioned on a lower protective metal pattern.

[0145] According to another feature of the present invention, the non-display area of ​​the organic light-emitting display device further includes a signal wiring portion formed on the same plane as the first source electrode using the same material.

[0146] According to another feature of the present invention, the organic light-emitting display device further includes a passivation layer formed to cover a driving transistor and a switching transistor.

[0147] According to another feature of the present invention, a capacitor electrode and a dummy electrode are positioned on the passivation layer of an organic light-emitting display device.

[0148] According to another feature of the present invention, the passivation layer of the organic light-emitting display device is formed across the display area and the non-display area.

[0149] According to another feature of the present invention, the passivation layer of an organic light-emitting display device has a pattern shape to minimize cracks occurring during bending in a non-display area.

[0150] According to another feature of the present invention, the first buffer layer of the organic light-emitting display device has a groove shape in a part of the non-display area.

[0151] According to another feature of the present invention, the flexible substrate of the organic light-emitting display device is characterized as being polyimide.

[0152] According to another feature of the present invention, the first gate electrode and the second gate electrode of the organic light-emitting display device are formed simultaneously on the same plane.

[0153] According to another feature of the present invention, the second gate electrode and the dummy electrode of the organic light-emitting display device are characterized by shielding external light incident on the upper and lower parts of the channel of the switching transistor.

[0154] According to another feature of the present invention, a dummy electrode of an organic light-emitting display device can minimize the bias temperature stress (BTS) of a switching transistor.

[0155] According to another feature of the present invention, the device further includes a gate-driven thin-film transistor located in a non-display area of ​​an organic light-emitting display and electrically connected to a part of a signal wiring section.

[0156] According to another feature of the present invention, the gate driving thin-film transistor of an organic light-emitting display device has a polycrystalline silicon (LTPS) layer as the active layer.

[0157] According to another feature of the present invention, the polycrystalline silicon (LTPS) layer of the driving transistor of the organic light-emitting display device and the first gate electrode are further included in a gate insulating layer.

[0158] According to another feature of the present invention, the organic light-emitting display device further includes an interlayer insulating layer located on the upper surface of a gate insulating layer and configured to cover a first gate electrode and a second gate electrode.

[0159] According to another feature of the present invention, the interlayer insulating layer of an organic light-emitting display device has a double-layer structure in which a nitride film (SIN) containing silicon nitride (SiNx) and an oxide film (SiO) containing silicon oxide (SiOx) are sequentially deposited.

[0160] Finally, according to another feature of the present invention, the oxide film (SiO) of the organic light-emitting display device can minimize the diffusion of hydrogen released from the nitride film (SIN) by a subsequent heat treatment process into the oxide semiconductor layer of the switching transistor.

[0161] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the technical configuration of the present invention described above may be implemented in other specific forms without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Furthermore, the scope of the present invention is defined by the claims set forth below rather than by the detailed description above. Additionally, all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0162] 110: Bottom substrate 120: BSM (Bottom Shield Metal) 130: LTPS thin-film transistor 140: Oxide semiconductor thin-film transistor 150: Dummy metal pattern 160: Organic light-emitting diode 111: Buffer layer 112: Active buffer layer 113: Gate insulation layer 114: Interlayer insulation layer 115: Passivation layer 116: Leveling layer 117: Bank 118: Bag Department

Claims

Claim 1 A flexible substrate comprising a display area and a non-display area; a plurality of pixels disposed in the display area; and a plurality of signal lines disposed in the non-display area, wherein each of the plurality of pixels comprises: a first transistor and a second transistor disposed on the flexible substrate; a passivation layer disposed on the first transistor and the second transistor; a dummy metal pattern disposed on the passivation layer; and a plurality of organic light-emitting diodes disposed on the dummy metal pattern. A display device comprising a plurality of organic light-emitting diodes and an encapsulation layer disposed thereon, wherein the first transistor comprises a first active layer made of polycrystalline silicon, a first gate electrode, a first source electrode, and a first drain electrode, and the second transistor comprises a second active layer made of an oxide semiconductor, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second active layer is disposed above the first gate electrode, and at least one of the first source electrode and the first drain electrode is electrically connected to at least one of the second source electrode and the second drain electrode, and the encapsulation layer is disposed to extend to the non-display area and cover the plurality of signal wires. Claim 2 A display device according to claim 1, further comprising a planarization layer disposed between the dummy metal pattern and the organic light-emitting element. Claim 3 A display device according to claim 1, wherein the dummy metal pattern is electrically connected to the organic light-emitting diode. Claim 4 A display device according to claim 1, wherein the first transistor is a driving thin-film transistor, and the dummy metal pattern electrically connects the driving thin-film transistor and the organic light-emitting element. Claim 5 A display device according to claim 1, further comprising a lower protective metal pattern positioned to overlap with the first transistor at the lower portion of the first transistor. Claim 6 In claim 5, the lower protective metal pattern is electrically connected to the first source electrode, the display device. Claim 7 A display device according to claim 1, wherein the dummy metal pattern comprises: a first dummy electrode overlapping with the first transistor; and a second dummy electrode overlapping with the second transistor. Claim 8 A display device according to claim 7, wherein the second dummy electrode overlaps with the second gate electrode. Claim 9 A display device according to claim 8, wherein the second dummy electrode is connected to the second gate electrode using a contact metal pattern located on the same plane as the second source electrode and made of the same material. Claim 10 In claim 7, the first dummy electrode overlaps with the first source electrode, a display device. Claim 11 A display device according to claim 1, wherein each of the plurality of organic light-emitting elements comprises an anode electrode, an organic light-emitting layer, and a cathode electrode, and the anode electrode overlaps with at least a part of the first transistor and the second transistor. Claim 12 A display device according to claim 1, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the same layer. Claim 13 A display device according to claim 1, wherein the plurality of signal wires are made of the same material as the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode. Claim 14 A display device according to claim 1, wherein the non-display area includes a bending portion, and the plurality of signal wires are disposed in the bending portion.

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