A method of manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided. The method for manufacturing the semiconductor device comprises forming a first lower overlay key including first and second patterns on a lower layer, forming a first upper overlay key including third and fourth patterns on an upper layer disposed perpendicular to the lower layer, detecting a first overlay error by irradiating a first measurement light onto a first measurement area spanning the first and second patterns, and detecting a second overlay error by irradiating a second measurement light onto a second measurement area spanning the first and second patterns and different from the first measurement area.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Technology

[0002] As semiconductor devices become more highly integrated, the linewidth of patterns contained within them is becoming finer, and as complex processes and materials are applied to the manufacturing process, the difficulty of the measurement process is also steadily increasing.

[0003] Due to the introduction of new materials or complex manufacturing processes, overlay key patterns for overlay measurement are subject to attack, or overlay keys are damaged by factors such as lower step heights, causing the difficulty of overlay measurement to increase; consequently, there are cases where overlay measurement becomes impossible for damaged overlay keys. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device that divides the entire overlay key into a plurality of measurement regions and performs overlay measurement for each measurement region.

[0005] The technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device that improves the accuracy of overlay measurement by optimizing an overlay recipe.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] A method for manufacturing a semiconductor device according to a few embodiments for achieving the above technical problem comprises forming a first lower overlay key including first and second patterns on a lower layer, forming a first upper overlay key including third and fourth patterns on an upper layer arranged perpendicularly to the lower layer, detecting a first overlay error by irradiating a first measurement light onto a first measurement area spanning the first and second patterns, and detecting a second overlay error by irradiating a second measurement light onto a second measurement area spanning the first and second patterns and different from the first measurement area.

[0008] A method for manufacturing a semiconductor device according to a few embodiments for achieving the above technical problem comprises forming a first lower overlay key including first and second patterns on a lower layer, forming a first upper overlay key including third and fourth patterns on an upper layer disposed perpendicular to the lower layer, detecting a first overlay error by irradiating a first measurement light over a first measurement area spanning the third and fourth patterns, and detecting a second overlay error by irradiating a second measurement light over a second measurement area spanning the third and fourth patterns and different from the first measurement area, wherein the third and fourth patterns are photoresist patterns.

[0009] A method for manufacturing a semiconductor device according to a few embodiments for achieving the above technical problem comprises forming a first lower overlay key including first and second patterns extending in a first direction and a second lower overlay key including third and fourth patterns extending in a second direction intersecting the first direction on a lower layer, wherein the second lower overlay key is arranged by rotating 90° around the origin with respect to the first lower overlay key, and forming a first upper overlay key including fifth and sixth patterns extending in a first direction and a second upper overlay key including seventh and eighth patterns extending in a second direction on an upper layer arranged perpendicularly to the lower layer, and irradiating a measurement light onto a first-1 measurement area spanning the first and second patterns and a second-1 measurement area spanning the third and fourth patterns to detect a first overlay error, wherein the first-1 measurement area is arranged by rotating 90° around the origin with respect to the second-1 measurement area, and a first-2 measurement area spanning the first and second patterns and different from the first-1 measurement area and spanning the third and fourth patterns A second overlay error is detected by irradiating a second-2 measurement area, which is different from the second-1 measurement area, with the first-2 measurement area being arranged rotated 90° around the origin with respect to the second-2 measurement area.

[0010] A method for manufacturing a semiconductor device according to a few embodiments for achieving the above technical problem comprises forming a first lower overlay key including first and second patterns on a lower layer, and forming a first upper overlay key including third and fourth patterns on an upper layer arranged perpendicularly to the lower layer, wherein the first and second patterns and the third and fourth patterns do not overlap each other in a planar view, and detecting a first overlay error by irradiating a first measurement light onto a first measurement area spanning the first and second patterns, detecting a second overlay error by irradiating a second measurement light onto a second measurement area spanning the first and second patterns and different from the first measurement area, and detecting an adjustment overlay error by irradiating a measurement light onto an adjustment measurement area spanning the first lower overlay key based on a first detection value of the first overlay error and a second detection value of the second overlay error. Brief explanation of the drawing

[0011] FIG. 1 is a schematic diagram illustrating an overlay error detection device used in a semiconductor device manufacturing method according to some embodiments of the present invention. FIG. 2 is a schematic diagram illustrating a spectroscopic image measuring instrument used in a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 4 is a drawing for explaining a semiconductor substrate according to some embodiments of the present invention. Figure 5 is a partial enlarged view of the semiconductor substrate of Figure 4. Figure 6 is an enlarged view of the overlay key area of ​​Figure 5. FIG. 7a is an exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5. FIG. 7b is another exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5. FIG. 7c is another exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5. Figure 8 is a diagram illustrating the measurement area for the overlay key area of ​​Figure 6. Figure 9 is a diagram illustrating another measurement area for the overlay key area of ​​Figure 6. FIGS. 10 to 12 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 13 is a diagram illustrating the adjustment measurement area for the overlay key area of ​​FIG. 6. FIG. 14 is a drawing for illustrating an overlay key of a semiconductor substrate according to some other embodiments of the present invention. Specific details for implementing the invention

[0012] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings. In the description of FIGS. 1 to 14, the same reference numerals are used for substantially identical components, and redundant descriptions of such components are omitted. Additionally, throughout the various drawings of the present invention, similar reference numerals are used for similar components.

[0013] FIG. 1 is a schematic diagram illustrating an overlay error detection device used in a semiconductor device manufacturing method according to some embodiments of the present invention.

[0014] Referring to FIG. 1, an overlay error detection device (1) according to some embodiments of the present invention includes a spectroscopic image measurement equipment (100) and a computing system (200).

[0015] The spectroscopic image measuring instrument (100) irradiates a semiconductor substrate with measurement light and measures characteristic values ​​of the semiconductor substrate from reflected light reflected from the semiconductor substrate. Specifically, the spectroscopic image measuring instrument (100) analyzes the semiconductor substrate by detecting the polarization state and diffraction reflected from the sample, i.e., the semiconductor substrate. These polarization states can be described as Ψ(psi) and Δ(delta), where Ψ(psi) is the ratio of the reflection coefficients of the p-wave and the s-wave, and Δ(delta) is the phase difference. Accordingly, the spectroscopic image measuring instrument (100) measures the complex refractive index of the material forming the semiconductor substrate according to the wavelength of the measurement light, and provides various information about the sample, i.e., the semiconductor substrate, including the thickness of the thin film including the semiconductor substrate, as well as the complex refractive index, shape, crystal state, chemical structure, and electrical conductivity, and detects the degree of alignment between the lower layer and the upper layer through this.

[0016] The spectroscopic image measuring instrument (100) uses an image sensor or a camera equipped with an image sensor as a detector for detecting reflected light. However, the scope of the present invention is not limited to using only the spectroscopic image measuring instrument (100). That is, various embodiments of the present invention may be implemented using an image measuring instrument that uses an image sensor or a camera equipped with an image sensor as a detector, but uses light of various wavelengths as measurement light. A detailed description of the spectroscopic image measuring instrument (100) will be provided later in relation to FIG. 2.

[0017] The computing system (200) receives data measured by the spectroscopic image measuring instrument (100), such as data regarding the polarization state of a sample expressed as Ψ (psi) and Δ (delta), and analyzes the data.

[0018] In some embodiments of the present invention, the computing system (200) includes a processor (210) and a memory (220), and the processor (210) and the memory (220) can exchange data through a bus (230). For example, data measured by a spectroscopic image measuring instrument (100) may be transmitted to the computing system (200) and then stored in the memory (220) of the computing system (200). The data measured in the memory (220) may be graphed or undergo various analysis processes through analysis software or an application running on the processor (210).

[0019] The memory (220) can store recipe information, which is setting information for overlay measurement such as the arrangement and size of the measurement area and the center wavelength / bandwidth / spectral structure of the measurement light, as well as kernel 3sigma, periodic ratio, contrast ratio, etc., which indicate the degree of overlay error between the upper and lower layers, as a single output file.

[0020] In some embodiments of the present invention, the computing system (200) may include portable computers such as desktop computers, servers, notebook computers, laptop computers, etc., as well as mobile computers such as smartphones, tablet computers, etc., but the scope of the present invention is not limited thereto. Meanwhile, in some embodiments of the present invention, the computing system (200) may be directly connected to the spectroscopic image measuring instrument (100) (e.g., via a cable) and may be connected to the wired network such as a LAN (Local Area Network), WAN (Wide Area Network), etc., or wireless network such as a WiFi network, cellular network, etc., to exchange data with each other.

[0021] FIG. 2 is a schematic diagram illustrating a spectroscopic image measuring instrument used in a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0022] Referring to FIG. 2, the spectroscopic image measuring instrument (100) may include a light source (110), a spectrometer (111), a filter (112), an image sensor (120), and a stage (500). As previously described in relation to FIG. 1, the spectroscopic image measuring instrument (100) uses light of mixed light including a continuous wavelength band as the measurement light (L), but is not limited thereto, and may use light of a short wavelength according to the embodiment.

[0023] In some embodiments of the present invention, the light source (110) may be a white light source, but the present invention is not limited thereto.

[0024] Meanwhile, a spectrometer (111) and a filter (112) may be used to convert light emitted from a light source (110) into light having a specific wavelength or light having a specific band of wavelength.

[0025] The spectrometer (111) disperses light emitted from the light source (110) according to wavelength and provides the dispersed light to the filter (112). The filter (112) receiving the dispersed light generates measurement light (L) that is irradiated onto the semiconductor substrate (30), can adjust the center wavelength and wavelength band of the measurement light (L), and can determine the spectral structure (e.g., single pass band, double pass band) of the measurement light (L) wavelength.

[0026] Although not shown, light generated from the filter (112) is polarized by a polarizer and irradiated onto a sample, i.e., a semiconductor substrate (30), at any angle of incidence through an illumination optical system. In some embodiments of the present invention, light generated from the filter (112) may be irradiated onto the semiconductor substrate (30) through a compensator in addition to the polarizer, or may be irradiated onto the semiconductor substrate (30) through a phase modulator instead of a compensator.

[0027] The image sensor (120) receives measurement light reflected from the semiconductor substrate (30), measures changes in polarization, diffraction, and energy magnitude as an image, and can detect overlay errors between upper and lower layers. Data collected in the form of an image can be transmitted to and processed by the computing system (200) shown in FIG. 1.

[0028] The spectroscopic image measuring instrument (100) can perform measurements on a semiconductor substrate (30) located on a stage (500).

[0029] Although not shown, the semiconductor substrate (30) may be transferred to the stage (500) after the photolithography process is performed externally. However, embodiments according to the technical concept of the present invention are not limited thereto. For example, after etching is performed in an etching device, the semiconductor substrate (30) may be transferred to the stage (500).

[0030] FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0031] Referring to FIG. 3, in a method for manufacturing a semiconductor device according to some embodiment, a plurality of lower overlay keys are formed on a lower layer (S110). A plurality of lower overlay keys are formed on an upper layer vertically arranged on the lower layer (S120).

[0032] FIG. 4 is a drawing for illustrating a semiconductor substrate according to some embodiment of the present invention. FIG. 5 is a partial enlarged view of the semiconductor substrate of FIG. 4. FIG. 6 is an enlarged view of the overlay key area of ​​FIG. 5. FIG. 7a is an exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5. FIG. 7b is another exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5. FIG. 7c is another exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5.

[0033] Referring further to FIGS. 4 to 7c, first to fourth lower overlay keys (310-340) can be formed using lower layers (LL1-LL3) on a substrate (300), and first to fourth upper overlay keys (410-440) can be formed using upper layers (HL1-HL3) arranged perpendicularly to the lower layers (LL1-LL3) in the third direction (x).

[0034] The semiconductor substrate (30) may correspond to the semiconductor substrate (30) placed on the stage (500) of FIG. 2.

[0035] Referring to FIGS. 4 and 5, a semiconductor substrate (10) may include a plurality of shot regions (SH). A shot region (SH) may be an area exposed by a single exposure process. A single shot region (SH) may include a single chip region (CA) or a plurality of chip regions (CA). A chip region (CA) may include a plurality of circuit regions.

[0036] A scribe lane region (SA) may be placed between a plurality of chip regions (CA). Here, a chip region (CA) may be defined by a scribe lane region (SA). For example, a scribe lane region (SA) may surround a chip region (CA).

[0037] In some embodiments, the overlay key region (OA) may be placed on the semiconductor substrate (10). For example, the overlay key region (OA) may be placed on the scribe lane region (SA). However, embodiments according to the technical concept of the present invention are not limited thereto. For example, the overlay key region (OA) may be placed on the chip region (CA). Here, the overlay key region (OA) is described as being placed on the scribe lane region (SA) between a plurality of chip regions (CA).

[0038] Referring to FIGS. 6 and FIGS. 7a, the semiconductor substrate (30) may include a chip region (CA) and an overlay key region (OA1). The chip region (CA) and the overlay key region (OA1) may be spaced apart from each other. For example, the semiconductor substrate (30) shown in FIG. 5 may be a semiconductor substrate (30) after an exposure process and an etching process have been performed on the upper layer (HL1).

[0039] FIG. 7a illustrates an embodiment in which the semiconductor device manufacturing method of the present invention may be applied to a memory device. The memory device may include a volatile memory device such as SRAM and / or DRAM, but may also include a non-volatile memory device such as flash memory, PRAM and / or RRAM.

[0040] For example, a substrate (300), a contact (302), a contact plug (304), a mold layer (401, 403), a support layer (402, 404), a first mask layer (405), a second mask layer (406), an anti-reflection layer (407), and a first chip pattern (P1) may be formed on a chip area (CA). For example, a substrate (300), first to fourth lower overlay keys (310-340), a mold layer (401, 403), a support layer (402, 404), a first mask layer (405), a second mask layer (406), an anti-reflection layer (407), and first to fourth upper overlay keys (410-440) may be formed on an overlay key area (OA1).

[0041] A contact (302) is disposed on a first surface (300a) of a substrate (300) and, specifically, may contact a source / drain region disposed on the substrate (300). The contact (302) may extend in a third direction (Z) and contact a contact plug (304) included in an insulating layer (303) and be electrically connected. Although the contact (302) is depicted as a single layer in the drawing, it may include a plurality of conductive layers and may include contacts, silicides, and landing pads, etc. An interlayer insulating film (302) is disposed between the above components disposed between the substrate (300) and the insulating layer (303), and the above components may be created based on patterns formed using a lower layer (LL1).

[0042] The contact plug (304) can be positioned to be aligned with the first hole pattern (HP1) formed by the first chip pattern (P1), and the alignment can be achieved through the placement of the first to fourth lower overlay keys (310-340) and the first to fourth upper overlay keys (410-440) described later.

[0043] The bit line (BL) may extend in a second direction (Y) between the contacts (302). A separate insulating material (IL) may be placed between the insulating layer (303) and the bit line (BL), and according to the embodiment, the insulating material (IL) may be a spacer. Some of the bit lines (BL) may be electrically insulated from the substrate (300) by the insulating material (IL), and some of the bit lines (BL) may be electrically connected to the substrate (300).

[0044] Mold layers (401, 403) and support layers (402, 404) may be alternately stacked on an insulating layer (303), and a first mask layer (405), a second mask layer (406), and an anti-reflection layer (407) may be sequentially stacked on a support layer (404).

[0045] The mold layer (401, 403) may include silicon oxide, for example, and the support layer (402, 404) may be made of silicon nitride, but is not limited thereto. The first mask layer (405) may include silicon oxide, and the second mask layer (406) may include SOH (Spin On Hardmask), but is not limited thereto. The anti-reflection layer (150) may include silicon nitride or silicon oxynitride. For example, the anti-reflection layer (407) may be silicon oxynitride.

[0046] A first chip pattern (P1) is disposed on a first surface (407a) of an anti-reflection layer (407) and can be formed by performing an exposure and etching process on an upper layer (HL1). The upper layer (HL1) may include a photoresist or a metal, and according to an embodiment, the upper layer (HL1) may include a carbon compound. Accordingly, the first chip pattern (P1) may be a photoresist pattern.

[0047] According to an embodiment, the first chip pattern (P1) may be a photoresist pattern on which EUV patterning is performed. The EUV is light having a wavelength in the range of 4 nm to 124 nm, and, exemplarily, in the present invention, a wavelength in the range of 4 nm to 20 nm may be used, and the EUV light may be generated by providing a laser to a plasma source material (e.g., TiN). The photoresist may be PMMA (polymethylmethacrylate), poly(4-hydroxystryrene), etc., but is not limited thereto.

[0048] The first hole pattern (HP1) can be formed by the first chip pattern (P1) so as to be aligned with the contact plug (304) in the third direction (Z), and a lower electrode can be formed along the first hole pattern (HP1), and the lower electrode can be in contact with the contact plug (304) to form a memory cell structure.

[0049] The first to fourth lower overlay keys (310-340) are disposed on the first surface (300a) of the substrate (300) and can be formed by patterning on the upper layer (HL1). The first to fourth lower overlay keys (310-340) can be formed by performing an exposure and etching process on the lower layer (LL1), and the lower layer (LL1) may include a photoresist or a metal, and according to the embodiment, the lower layer (LL1) may include a carbon compound. Accordingly, the first to fourth lower overlay keys (310-340) may be photoresist patterns.

[0050] The first lower overlay key (310) may include first_1 to first_6 lower patterns (311-316). Each of the first_1 to first_6 lower patterns (311-316) extends in a first direction (X), and the first_1 to first_6 lower patterns (311-316) may be arranged in a line in a second direction (Y). According to an embodiment, the first_1 to first_5 lower patterns (311-315) may be rectangular in shape in a planar manner, but the first_6 lower pattern (316) may be a defective pattern with some areas damaged compared to the first_1 to first_5 lower patterns (311-315). The damage, etc., may be influenced or attacked by a process, etc., on the chip area (CA).

[0051] The second lower overlay key (320) may be positioned rotated 90° clockwise with respect to the first lower overlay key (310) with respect to the origin (O) of the overlay area (OA1). For example, the second-third lower pattern (323) may be positioned rotated 90° clockwise with respect to the first-third lower pattern (313) with respect to the origin (O). However, depending on the embodiment, some patterns may be damaged and thus defective patterns, and the second_1 to second_3 lower patterns (321-323) may be rectangular in shape in a planar manner, while the second_4 to second_6 lower patterns (324-326) may be defective patterns with some areas damaged compared to the second_1 to second_3 lower patterns (321-323).

[0052] The third lower overlay key (330) may be positioned rotated 90° clockwise with respect to the second lower overlay key (320) with respect to the origin (O) of the overlay area (OA1), and the fourth lower overlay key (340) may be positioned rotated 90° clockwise with respect to the third lower overlay key (330) with respect to the origin (O) of the overlay area (OA1). However, the lower patterns included in the third lower overlay key (330) and the fourth lower overlay key (340) may be rectangular in shape in a planar manner.

[0053] An insulating layer (303), a mold layer (401, 403), and a support layer (402, 404) may be alternately laminated on the first to fourth lower overlay keys (310-340), and a first mask layer (405), a second mask layer (406), and an anti-reflection layer (407) may be sequentially laminated on the support layer (404). An interlayer insulating film (302) may be disposed between the first to fourth lower overlay keys (310-340) and between the first to fourth lower overlay keys (310-340) and the insulating layer (303).

[0054] The first to fourth upper overlay keys (410-440) are disposed on the first surface (407a) of the anti-reflection layer (407) and can be formed by patterning on the upper layer (HL1). The first to fourth upper overlay keys (410-440) can be formed by performing an exposure and etching process on the upper layer (HL1), and the upper layer (HL1) may include a photoresist or a metal, and according to the embodiment, the upper layer (HL1) may include a carbon compound. Accordingly, the first to fourth upper overlay keys (410-440) may be a photoresist pattern.

[0055] The first to fourth upper overlay keys (410-440) may be arranged so as not to overlap in a planar manner with the first to fourth lower overlay keys (310-340).

[0056] The first upper overlay key (410) may include first_1 to first_6 upper patterns (411-416). Each of the first_1 to first_6 upper patterns (411-416) extends in a first direction (X), and the first_1 to first_6 upper patterns (411-416) may be arranged in a line in a second direction (Y). According to an embodiment, the first_1 to first_6 upper patterns (411-416) may be rectangular in shape in a planar manner.

[0057] The second upper overlay key (420) may be positioned rotated 90° clockwise with respect to the first upper overlay key (410) with respect to the origin (O) of the overlay area (OA1). For example, the second_6 upper pattern (426) may be positioned rotated 90° clockwise with respect to the first_6 upper pattern (416) with respect to the origin (O). According to an embodiment, the second_1 to second_6 upper patterns (421-426) may be rectangular in shape in a planar manner.

[0058] The third upper overlay key (430) may be positioned rotated 90° clockwise with respect to the second upper overlay key (420) with respect to the origin (O) of the overlay area (OA1), and the fourth upper overlay key (440) may be positioned rotated 90° clockwise with respect to the third upper overlay key (430) with respect to the origin (O) of the overlay area (OA1). According to an embodiment, the patterns included in the third upper overlay key (430) and the fourth upper overlay key (440) may be rectangular in shape in a planar manner.

[0059] The first to fourth lower overlay keys (310-340) and the first to fourth upper overlay keys (410-440) do not overlap each other in a planar view and can be arranged in a square shape in a planar view. Through such first to fourth lower overlay keys (310-340) and first to fourth upper overlay keys (410-440), the first hole pattern (HP1) and the contact plug (304) can be aligned in a third direction (Z).

[0060] FIG. 7b is another exemplary cross-sectional view of a semiconductor substrate cut along AA of FIG. 5. Hereinafter, with reference to FIG. 7b, embodiments in which a semiconductor device manufacturing method according to several other embodiments of the present invention may be applied to a storage device are described. The description focuses on the differences from the memory devices shown in FIG. 7a.

[0061] The storage device may include non-volatile memory (NVM) for storing data. The non-volatile memory may include V-NAND flash memory with a 2D (2-dimensional) or 3D (3-dimensional) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0062] For example, a substrate (300), a plurality of conductive layers (306), an insulating layer (408), an anti-reflection layer (407), and a second chip pattern (HP2) may be formed on a chip area (CA). For example, a substrate (300), first to fourth lower overlay keys (310-340), an insulating layer (408), an anti-reflection layer (407), and first to fourth upper overlay keys (410-440) may be formed on an overlay key area (OA1).

[0063] It is obvious that the substrate (300), the anti-reflection layer (407), the second upper layer (HL2), the second lower layer (LL2), the second chip pattern (HP2), the first to fourth lower overlay keys (310-340) and the first to fourth upper overlay keys (410-440) correspond to the substrate (300), the anti-reflection layer (407), the first chip pattern (HP1), the first upper layer (HL1), the first lower layer (LL1), the first to fourth lower overlay keys (310-340), and the first to fourth upper overlay keys (410-440) of FIG. 7a, and thus the description is omitted.

[0064] A plurality of conductive layers (306) may be stacked in a third direction (Z) on a substrate (300). A conductive layer (306) adjacent to the substrate (300) may extend in a first direction (X) and protrude in part more than a conductive layer (306) adjacent to an insulating layer (408), so that the plurality of conductive layers (306) may form a step structure. The plurality of conductive layers (306) may include a plurality of word lines, string selection lines, and ground selection lines, etc., in a storage device.

[0065] The channel structure (CH) can extend in a third direction (Z) perpendicular to the upper surface of the substrate (300) and penetrate a plurality of conductive layers (306). The channel structure (CH) may include a data storage layer, a channel layer, and an embedded insulating layer, etc.

[0066] An insulating layer (408) may be formed on the channel structure (CH), and a bit line plug may be formed within the insulating layer (408) through a subsequent process. An anti-reflection layer (407) and a second chip pattern (P2) may be formed on the insulating layer (408).

[0067] Similar to FIG. 7a, the second hole pattern (HP2) and the channel structure (CH) can be aligned in the third direction (Z) through the arrangement of the first to fourth lower overlay keys (310-340) and the first to fourth upper overlay keys (410-440). A bitline plug can be formed along the second hole pattern (HP2), and the bitline plug can electrically connect the bitline and the channel structure (CH). An interlayer insulating film (302) can be disposed between the above configurations disposed between the substrate (300) and the insulating layer (408).

[0068] An insulating layer (408) and an anti-reflective layer (407) can be laminated in the order of the first to fourth lower overlay keys (310-340) in the third direction (z). An interlayer insulating film (302) can be disposed between the components disposed between the substrate (300) and the insulating layer (408) on the overlay key area (OA1).

[0069] FIG. 7c is another exemplary cross-sectional view of a semiconductor substrate cut along AA in FIG. 5. Hereinafter, with reference to FIG. 7c, embodiments in which a semiconductor device manufacturing method according to some other embodiments of the present invention may be applied to a logic device are described. The description focuses on the differences from the memory devices shown in FIG. 7a.

[0070] The above logic device may include a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit) and / or DPU (Data Processing Unit), etc., but the technical concept of the present invention is not limited to the examples of the above logic device.

[0071] For example, a substrate (300), a transistor (TR), an interlayer insulating film (302), an anti-reflection layer (407), and a third chip pattern (HP3) may be formed on a chip area (CA). For example, a substrate (300), first to fourth lower overlay keys (310-340), an interlayer insulating film (302), an anti-reflection layer (407), and first to fourth upper overlay keys (410-440) may be formed on an overlay key area (OA1).

[0072] It is obvious that the substrate (300), interlayer insulating film (302), anti-reflection layer (407), third upper layer (HL3), third lower layer (LL3), third chip pattern (HP3), first to fourth lower overlay keys (310-340) and first to fourth upper overlay keys (410-440) correspond to the substrate (300), interlayer insulating film (302), anti-reflection layer (407), third upper layer (HL3), third lower layer (LL3), third chip pattern (HP3), first to fourth lower overlay keys (310-340) and first to fourth upper overlay keys (410-440) of FIG. 7a, respectively, and thus the description is omitted.

[0073] A plurality of transistors (TR) may be disposed on a substrate (300), and each transistor (TR) may include a source / drain region (307). As in FIG. 7a, the third hole pattern (HP3) and the source / drain region (307) may be aligned in a third direction (Z) through the arrangement of the first to fourth lower overlay keys (310-340) and the first to fourth upper overlay keys (410-440). A contact may be formed penetrating the interlayer insulating film (302) along the third hole pattern (HP3), and the contact may electrically connect the plurality of transistors (TR) to external wiring.

[0074] Referring again to FIG. 3, in a method for manufacturing a semiconductor device according to some embodiments, a plurality of measurement regions (ROI, Region Of interest) are set for each overlay through an overlay error detection device (1) (S130).

[0075] FIG. 8 is a drawing for explaining the measurement area for the overlay key area of ​​FIG. 6. Referring further to FIG. 6 and FIG. 8, for the first lower overlay key (310), the first_1 lower measurement area (R310_1) is set across the first_4 to 1_6 lower patterns (314-316) and has a long side of a first width (Wa) and a short side of a second width (Wb). The first_2 lower measurement area (R310_2) is set across the first_4 to 1_6 lower patterns (314-316) while not overlapping planarly with the first_1 lower measurement area (R310_1) and has a long side of a first width (Wa) and a short side of a second width (Wb). The 1_3 lower measurement area (R310_3) is set across the 1_4 to 1_6 lower patterns (314-316) while not overlapping planarly with the 1_1 and 1_2 lower measurement areas (R310_1, R310_2), and has a long side of a first width (Wa) and a short side of a second width (Wb). The 1_4 lower measurement area (R310_4) is set across the 1_1 to 1_3 lower patterns (311-313) while not overlapping planarly with the 1_1 to 1_3 lower measurement areas (R310_1-R310_3), and has a long side of a first width (Wa) and a short side of a second width (Wb). The 1_5 lower measurement area (R310_5) is set across the 1_1 to 1_3 lower patterns (311-313) while not overlapping planarly with the 1_1 to 1_4 lower measurement areas (R310_1-R310_4), and has a long side with a length of 1 width (Wa) and a short side with a length of 2 width (Wb). The 1_6 lower measurement area (R310_6) is set across the 1_1 to 1_3 lower patterns (311-313) while not overlapping planarly with the 1_1 to 1_5 lower measurement areas (R310_1-R310_5), and has a long side with a length of 1 width (Wa) and a short side with a length of 2 width (Wb).

[0076] The arrangement relationship between the first lower overlay key (310) and the first to sixth lower measurement areas (R310_1-R310_6) is the arrangement between the second lower overlay key (320) and the second_1 to second_6 lower measurement areas (R320_1-R320_6), the arrangement between the third lower overlay key (330) and the third_1 to third_6 lower measurement areas (R330_1-R330_6), the arrangement between the fourth lower overlay key (340) and the fourth_1 to fourth_6 lower measurement areas (R340_1-R340_6), the arrangement between the first upper overlay key (410) and the first_1 to first_6 upper measurement areas (R410_1-R410_6), and the arrangement between the second upper overlay key (420) and the second_1 to second_6 upper measurement areas (R420_1-R420_6). It is obvious that the arrangement between the third upper overlay key (430) and the third_1 to third_6 upper measurement areas (R430_1-R430_6), and the arrangement between the fourth upper overlay key (440) and the fourth_1 to fourth_6 upper measurement areas (R440_1-R440_6) can also be applied, so the explanation is omitted.

[0077] The 2_1 lower measurement area (R320_1) may be positioned rotated 90° clockwise with respect to the origin (O) of the overlay area (OA1) with respect to the 1_1 lower measurement area (R310_1), the 3_1 lower measurement area (R330_1) may be positioned rotated 90° clockwise with respect to the origin (O) of the overlay area (OA1) with respect to the 2_1 lower measurement area (R320_1), and the 4_1 lower measurement area (R340_1) may be positioned rotated 90° clockwise with respect to the origin (O) of the overlay area (OA1) with respect to the 3_1 lower measurement area (R330_1).

[0078] Likewise, the arrangement relationship between the 1_1 to 4_1 lower measurement areas (R310_1-R340_1) is the arrangement between the 1_2 to 4_2 lower measurement areas (R310_2-R340_2), the arrangement between the 1_3 to 4_3 lower measurement areas (R310_3-R340_3), the arrangement between the 1_4 to 4_4 lower measurement areas (R310_4-R340_4), the arrangement between the 1_5 to 4_5 lower measurement areas (R310_5-R340_5), the arrangement between the 1_6 to 4_6 lower measurement areas (R310_6-R340_6), the arrangement between the 1_1 to 4_1 upper measurement areas (R410_1-R440_1), and the arrangement between the 1_2 to 4_2 upper measurement areas (R410_2-R440_2). It can also be applied to the arrangement between the upper measurement areas 1_3 to 4_3 (R410_3-R440_3), the arrangement between the upper measurement areas 1_4 to 4_4 (R410_4-R440_4), the arrangement between the upper measurement areas 1_5 to 4_5 (R410_5-R440_5), and the arrangement between the upper measurement areas 1_6 to 4_6 (R410_6-R440_6), so it is obvious that an explanation regarding this is omitted.

[0079] FIG. 9 is a diagram illustrating another measurement area for the overlay key area of ​​FIG. 6. Hereinafter, with reference to FIG. 9, a measurement area setting (S130, see FIG. 3) of a semiconductor device manufacturing method according to some other embodiments of the present invention will be described. The description will focus on the differences from the measurement area setting (S130) illustrated in FIG. 8.

[0080] Unlike the measurement area setting of FIG. 8, at least a portion of the first_1 lower measurement area (R310_1') may overlap planarly with the first_2 lower measurement area (R310_2'), the first_4 lower measurement area (R310_4'), and the first_5 lower measurement area (R310_5'). At least a portion of the first_2 lower measurement area (R310_2') may overlap planarly with the first_1 lower measurement area (R310_1'), the first_3 lower measurement area (R310_3'), the first_4 lower measurement area (R310_4'), the first_5 lower measurement area (R310_5'), and the first_6 lower measurement area (R310_6'). At least a portion of the 1_3 lower measurement area (R310_3') may overlap planarly with the 1_2 lower measurement area (R310_2'), the 1_5 lower measurement area (R310_5'), and the 1_6 lower measurement area (R310_6'). At least a portion of the 1_4 lower measurement area (R310_4') may overlap planarly with the 1_1 lower measurement area (R310_1'), the 1_2 lower measurement area (R310_2'), and the 1_5 lower measurement area (R310_5'). At least a portion of the 1_5 lower measurement area (R310_5') may overlap planarly with the 1_1 lower measurement area (R310_1'), the 1_2 lower measurement area (R310_2'), the 1_3 lower measurement area (R310_3'), the 1_4 lower measurement area (R310_4'), and the 1_6 lower measurement area (R310_6'). At least a portion of the 1_6 lower measurement area (R310_5') may overlap planarly with the 1_2 lower measurement area (R310_2'), the 1_3 lower measurement area (R310_3'), and the 1_5 lower measurement area (R310_5').

[0081] Likewise, the arrangement relationship between the first to sixth lower measurement areas (R310_1'-R310_6') is the arrangement between the second_1 to second_6 lower measurement areas (R320_1'-R320_6'), the arrangement between the third_1 to third_6 lower measurement areas (R330_1'-R330_6'), the arrangement between the fourth_1 to fourth_6 lower measurement areas (R340_1'-R340_6'), the arrangement between the first_1 to first_6 upper measurement areas (R410_1'-R410_6'), the arrangement between the second_1 to second_6 upper measurement areas (R420_1'-R420_6'), the arrangement between the third_1 to third_6 upper measurement areas (R430_1'-R430_6'), and the fourth_1 to fourth_6 upper measurement areas. It can also be applied to the placement relationship between regions (R440_1'-R440_6'), so it is self-evident that the explanation is omitted.

[0082] Referring again to FIG. 3, in a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) measures an overlay on a plurality of measurement regions (ROI) to measure the detection value of an overlay error (S140).

[0083] Referring to FIGS. 8 and FIGS. 10 to 12, the overlay error detection device (1) can determine the degree of alignment between the pattern of the upper layer (HL1, FIG. 7a) and the configurations on the substrate (300, FIG. 7a) by irradiating a measurement light (L, see FIG. 1) onto each measurement area and measuring the reflected light.

[0084] In a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) has a first center frequency (λ) in the first_1 to 4_1 lower measurement areas (R310_1-R340_1) and the first_1 to 4_1 upper measurement areas (R410_1-R440_1). C Each measurement can be performed by simultaneously irradiating a first measurement light having a first bandwidth (BW_R_1) and having _R_1).

[0085] The degree of alignment in the second direction (Y) can be determined by irradiating the first measurement light onto the lower measurement areas (R310_1, R330_1) of the first and third_1 and the upper measurement areas (R410_1, R430_1) of the first and third_1, and the degree of alignment in the first direction (X) can be determined by irradiating the first measurement light onto the lower measurement areas (R320_1, R340_1) of the second and fourth_1 and the upper measurement areas (R420_1, R440_1) of the second and fourth_1.

[0086] Through the reflected first measurement light, the overlay error detection device (1) can measure the first kernel 3 sigma (3σ_R_1), the first periodic ratio (Periodic_Ratio_R_1), and the first contrast ratio (CP_R_1), and can detect the first detection value (Residual_R_1) of the first overlay error through the measured values.

[0087] The memory (220) of the overlay error detection device (1) can store the arrangement information of the first_1 to fourth_1 lower measurement areas (R310_1-R340_1) and the first_1 to fourth_1 upper measurement areas (R410_1-R440_1) and the first measurement light and the detection value for the first overlay error in the first output file (OutputFile_R_1).

[0088] In a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) has a second center frequency (λ) in the first_2 to 4_2 lower measurement regions (R310_2-R340_2) and the first_2 to 4_2 upper measurement regions (R410_2-R440_2). C Each measurement can be performed by simultaneously irradiating a second measurement light having a second bandwidth (BW_R_2) and having _R_2).

[0089] The degree of alignment in the second direction (Y) can be determined by irradiating the lower measurement areas (R310_2, R330_2) of the first_2 and third_2 and the upper measurement areas (R410_2, R430_2) of the first_2 and third_2 with a second measurement light, and the degree of alignment in the first direction (X) can be determined by irradiating the lower measurement areas (R320_2, R340_2) of the second_2 and fourth_2 and the upper measurement areas (R420_2, R440_2) of the second_2 and fourth_2 with a second measurement light.

[0090] Through the reflected second measurement light, the overlay error detection device (1) can measure the second kernel 3 sigma (3σ_R_2), the second periodic ratio (Periodic_Ratio_R_2), and the second contrast ratio (CP_R_2), and can detect the second detection value (Residual_R_2) of the second overlay error through the measured values.

[0091] The memory (220) of the overlay error detection device (1) can store the arrangement information of the first_2 to fourth_2 lower measurement areas (R310_2-R340_2) and the first_2 to fourth_2 upper measurement areas (R410_2-R440_2), recipe information for the second measurement light, and detection values ​​for the second overlay error in the second output file (OutputFile_R_2).

[0092] In a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) has a third center frequency (λ) in the first_3 to 4_3 lower measurement area (R310_3-R340_3) and the first_3 to 4_3 upper measurement area (R410_3-R440_3). C Each measurement can be performed by simultaneously irradiating a third measurement light having a third bandwidth (BW_R_3) and having _R_3).

[0093] The degree of alignment in the second direction (Y) can be determined by irradiating the lower measurement areas (R310_3, R330_3) of the first_3 and third_3 and the upper measurement areas (R410_3, R430_3) with the third measurement light, and the degree of alignment in the first direction (X) can be determined by irradiating the lower measurement areas (R320_3, R340_3) of the second_3 and fourth_3 and the upper measurement areas (R420_3, R440_3) with the third measurement light.

[0094] Through the reflected third measurement light, the overlay error detection device (1) can measure the third kernel 3 sigma (3σ_R_3), the third periodic ratio (Periodic_Ratio_R_3), and the third contrast ratio (CP_R_3), and can detect the third detection value (Residual_R_3) of the third overlay error through the measured values.

[0095] The memory (220) of the overlay error detection device (1) can store the arrangement information of the first to fourth lower measurement areas (R310_3-R340_3) and the first to fourth upper measurement areas (R410_3-R440_3) and the third measurement light, as well as the detection value for the first overlay error, in the third output file (OutputFile_R_3).

[0096] In a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) has a fourth center frequency (λ) in the first_4 to 4_4 lower measurement area (R310_4-R340_4) and the first_4 to 4_4 upper measurement area (R410_4-R440_4). C Each measurement can be performed by simultaneously irradiating a fourth measurement light having a fourth bandwidth (BW_R_4) and having _R_4).

[0097] The degree of alignment in the second direction (Y) can be determined by irradiating the fourth measurement light onto the lower measurement areas (R310_4, R330_4) of the first_4 and third_4 and the upper measurement areas (R410_4, R430_4) of the first_4 and third_4, and the degree of alignment in the first direction (X) can be determined by irradiating the fourth measurement light onto the lower measurement areas (R320_4, R340_4) of the second_4 and fourth_4 and the upper measurement areas (R420_4, R440_4) of the second_4 and fourth_4.

[0098] Through the reflected fourth measurement light, the overlay error detection device (1) can measure the fourth kernel 3 sigma (3σ_R_4), the fourth periodic ratio (Periodic_Ratio_R_4), and the fourth contrast ratio (CP_R_4), and can detect the fourth detection value (Residual_R_1) of the fourth overlay error through the measured values.

[0099] The memory (220) of the overlay error detection device (1) can store the arrangement information of the first to fourth lower measurement areas (R310_4-R340_4) and the first to fourth upper measurement areas (R410_4-R440_4) and the fourth measurement light, as well as the detection value for the fourth overlay error, in the fourth output file (OutputFile_R_1).

[0100] In a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) has a fifth center frequency (λ) in the first_5 to 4_5 lower measurement area (R310_5-R340_5) and the first_5 to 4_5 upper measurement area (R410_5-R440_5). C Each measurement can be performed by simultaneously irradiating a fifth measurement light having a fifth bandwidth (BW_R_5) and having _R_5).

[0101] The degree of alignment in the second direction (Y) can be determined by irradiating the 5th measurement light onto the 1_5 and 3_5 lower measurement areas (R310_5, R330_5) and the 1_5 and 3_5 upper measurement areas (R410_5, R430_5), and the degree of alignment in the first direction (X) can be determined by irradiating the 5th measurement light onto the 2_5 and 4_5 lower measurement areas (R320_5, R340_5) and the 2_5 and 4_5 upper measurement areas (R420_5, R440_5).

[0102] Through the reflected fifth measurement light, the overlay error detection device (1) can measure the fifth kernel 3 sigma (3σ_R_5), the fifth period ratio (Periodic_Ratio_R_5), and the fifth contrast ratio (CP_R_5), and can detect the fifth detection value (Residual_R_5) of the fifth overlay error through the measured values.

[0103] The memory (220) of the overlay error detection device (1) can store the arrangement information of the first to fourth lower measurement areas (R310_5-R340_5) and the first to fourth upper measurement areas (R410_5-R440_5) and the recipe information for the fifth measurement light and the detection value for the fifth overlay error in the fifth output file (OutputFile_R_5).

[0104] In a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) has a 6th center frequency (λ) in the 1st_6 to 4th_6 lower measurement area (R310_6-R340_6) and the 1st_6 to 4th_6 upper measurement area (R410_6-R440_6). C Each measurement can be performed by simultaneously irradiating a sixth measurement light having a sixth bandwidth (BW_R_6) and having _R_6).

[0105] The degree of alignment in the second direction (Y) can be determined by irradiating the 6th measurement light onto the 1_6 and 3_6 lower measurement areas (R310_6, R330_6) and the 1_6 and 3_6 upper measurement areas (R410_6, R430_6), and the degree of alignment in the first direction (X) can be determined by irradiating the 2_6 and 4_6 lower measurement areas (R320_6, R340_6) and the 2_6 and 4_6 upper measurement areas (R420_6, R440_6).

[0106] Through the reflected sixth measurement light, the overlay error detection device (1) can measure the sixth kernel 3 sigma (3σ_R_6), the sixth period ratio (Periodic_Ratio_R_6), and the sixth contrast ratio (CP_R_6), and can detect the sixth detection value (Residual_R_6) of the sixth overlay error through the measured values.

[0107] The memory (220) of the overlay error detection device (1) can store the arrangement information of the 1st to 4th lower measurement areas (R310_6-R340_6) and the 1st to 4th upper measurement areas (R410_6-R440_6) and the 6th measurement light, as well as the detection value for the 6th overlay error, in the 6th output file (OutputFile_R_6).

[0108] Referring to FIGS. 6, 8, and 11, the kernel 3-sigma value for the third group (R_3), which corresponds to the first to fourth-third lower measurement areas (R310_3-R340_3) and the first to fourth-third upper measurement areas (R410_3-R440_3), is measured to be the lowest among the first to sixth groups (R_1-R_6). This indicates that the degree of overlay error is the lowest. This is because the first to fourth-third lower measurement areas (R310_3-R340_3) do not perform measurements on the first-first lower pattern (311) and the second-fourth to sixth lower patterns (324-326), which are defective patterns with some areas damaged.

[0109] A first group (R_1) including a second_1 sub-measurement area (R320_1) that performs measurements on the first_1 sub-pattern (311) and the second_4 to 2_6 sub-patterns (324-326) has the highest kernel 3-sigma value among the first to 6 groups (R_1-R_6).

[0110] An overlay error detection device (1) according to some embodiments can set a measurement area by avoiding first, fifth, and sixth groups (R_1, R_5, R_6) that exceed a predetermined threshold value (α).

[0111] In addition, referring to Fig. 12, variations in the detection value can also be observed in which the kernel 3-sigma value varies in the same measurement area depending on the variation in the center wavelength (λ) of the measurement light (L).

[0112] Referring to FIGS. 3 and 13, in a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) sets an adjustment measurement area for an overlay key based on the detection value of an overlay error in FIGS. 11 and FIGS. 12 (S150).

[0113] For the first lower overlay key (310), the first lower measurement area (R310) is set across the first_1 to 1_5 lower patterns (311-315), has a long side of a third width (Wa'), and a short side of a fourth width (Wb'). For the second lower overlay key (320), the second lower measurement area (R320) is set across the second_1 to 1_5 lower patterns (321-325) and is not set for the damaged area of ​​the second_4 to 2_6 lower patterns (324-326), and has a long side of a third width (Wa') and a short side of a fourth width (Wb'). The third lower measurement area (R330) is set across the third_1 to third_5 lower patterns (331-335) and has a long side of the third width (Wa') and a short side of the fourth width (Wb'). The fourth lower measurement area (R340) is set across the fourth_1 to fourth_5 lower patterns (341-345) and has a long side of the third width (Wa') and a short side of the fourth width (Wb'). The fifth lower measurement area (R350) is set across the fifth_1 to fifth_5 lower patterns (351-355) and has a long side of the third width (Wa') and a short side of the fourth width (Wb'). The 6th lower measurement area (R360) is set across the 6_1 to 6_5 lower patterns (361-365) and has a long side of a 3rd width (Wa') and a short side of a 4th width (Wb').

[0114] The length of the third width (Wa') is different from the first width (Wa) of FIG. 6, and the length of the fourth width (Wb') is different from the second width (Wb) of FIG. 6. Depending on the embodiment, the length of the third width (Wa') may be greater than the first width (Wa), and the length of the fourth width (Wb') may be greater than the second width (Wb).

[0115] Referring again to FIG. 3, in a method for manufacturing a semiconductor device according to some embodiments, an overlay error detection device (1) measures an overlay on an adjustment measurement area and measures the detection value of an overlay error (S160).

[0116] The overlay error detection device (1) can determine the degree of alignment between the pattern of the upper layer (HL1, FIG. 7a) and the configurations on the substrate (300, FIG. 7a) by irradiating a measurement light (L, see FIG. 1) onto each adjustment measurement area and measuring the reflected light.

[0117] A semiconductor device manufacturing method according to some embodiments involves an overlay error detection device (1) performing steps S130 and S140 to set an adjustment measurement area and perform an overlay measurement to measure the detection value of the overlay error. Accordingly, the adjustment measurement area performs overlay measurement by excluding the defective pattern, and furthermore, the recipe of the measurement light can also be optimized according to the recipe information of the measurement light, so the reliability of the overlay measurement can be improved.

[0118] FIG. 14 is a drawing for illustrating an overlay key of a semiconductor substrate according to some other embodiments of the present invention.

[0119] Hereinafter, an overlay key region (OA2) of a semiconductor substrate (30) according to another embodiment of the present invention will be described with reference to FIG. 14. The description will focus on the differences from the overlay key region (OA1) shown in FIG. 6.

[0120] Fifth and sixth lower overlay keys (350, 360) and fifth and sixth upper overlay keys (450, 460) may be placed on the overlay key area (OA2).

[0121] The fifth lower overlay key (350) may include the fifth_1 to fifth_6 lower patterns (351-356), the sixth lower overlay key (360) may include the sixth_1 to sixth_6 lower patterns (351-356), the fifth upper overlay key (450) may include the fifth_1 to fifth_6 upper patterns (451-456), and the sixth upper overlay key (460) may include the sixth_1 to sixth_6 upper patterns (451-456).

[0122] Each of the 5th and 6th lower overlay keys (350, 360) corresponds to the 1st and 2nd lower overlay keys (310, 320) of FIG. 6, and each of the 5th and 6th upper overlay keys (450, 460) may correspond to the 1st and 2nd upper overlay keys (410, 420) of FIG. 6.

[0123] The fifth lower overlay key (350) may overlap with the fifth upper overlay key (450) in a planar view, and the sixth lower overlay key (360) may overlap with the sixth upper overlay key (460) in a planar view, and the 5_1 to 5_6 lower patterns (351-356) included in the fifth lower overlay key (350) are not planarly overlapped with the 5_1 to 5_6 upper patterns (451-456) included in the fifth upper overlay key (450), but are arranged alternately with each other. That is, the 5_2 lower pattern (452) may be placed between the 5_1 and 5_2 upper patterns (451, 452), and the 5_1 upper pattern (451) may be placed between the 5_1 and 5_2 lower patterns (351, 352). This arrangement can also be applied to the 6th lower overlay key (360) and the 6th upper overlay key (460).

[0124] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0125] 1: Overlay error detection device 100: Spectroscopic imager 110: Light source 111: Spectrometer 112: Filter 210: Processor 220: Memory 230: Bus 500: Stage

Claims

Claim 1 A method for manufacturing a semiconductor device, comprising forming a first lower overlay key including first and second patterns on a lower layer, forming a first upper overlay key including third and fourth patterns on an upper layer arranged perpendicularly to the lower layer, detecting a first overlay error by irradiating a first measurement light onto a first measurement area spanning the first and second patterns, and detecting a second overlay error by irradiating a second measurement light onto a second measurement area spanning the first and second patterns and different from the first measurement area, wherein the first pattern and the second pattern are arranged along a first direction, and the first pattern and the second pattern are each extended in a second direction intersecting the first direction. Claim 2 A method for manufacturing a semiconductor device according to claim 1, further comprising irradiating a third measurement light to a third measurement area spanning the third and fourth patterns to detect the first overlay error, and irradiating a fourth measurement light to a fourth measurement area spanning the third and fourth patterns and different from the third measurement area to detect the second overlay error. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the first to fourth patterns are photoresist patterns. Claim 4 A method for manufacturing a semiconductor device according to claim 1, wherein at least a portion of the first measurement region overlaps with the second measurement region in a planar view. Claim 5 A method for manufacturing a semiconductor device according to claim 1, further comprising forming a second lower overlay key on the lower layer including fifth and sixth patterns different from the first and second patterns, wherein the second lower overlay key is arranged rotated 90° around the origin with respect to the first lower overlay key. Claim 6 A method for manufacturing a semiconductor device according to claim 5, further comprising irradiating a first measurement light to a fifth measurement area spanning the fifth and sixth patterns to detect the first overlay error, and irradiating a second measurement light to a sixth measurement area spanning the fifth and sixth patterns and different from the fifth measurement area to detect the second overlay error. Claim 7 A method for manufacturing a semiconductor device according to claim 6, wherein the fifth measurement area is arranged rotated 90° around the origin with respect to the first measurement area, and the sixth measurement area is arranged rotated 90° around the origin with respect to the second measurement area. Claim 8 A method for manufacturing a semiconductor device according to claim 6, wherein the first measurement light is simultaneously irradiated to the first measurement area and the fifth measurement area to detect the first overlay error, and the second measurement light is simultaneously irradiated to the second measurement area and the sixth measurement area to detect the second overlay error. Claim 9 A method for manufacturing a semiconductor device according to claim 1, further comprising detecting an adjustment overlay error by irradiating a measurement light onto an adjustment measurement area spanning the first lower overlay key based on a first detection value of the first overlay error and a second detection value of the second overlay error. Claim 10 A method for manufacturing a semiconductor device according to claim 9, wherein the length of the long side of the adjustment measurement area extending in the first direction is different from the length of the long side of the first measurement area extending in the first direction. Claim 11 A method for manufacturing a semiconductor device according to claim 1, wherein the first and second patterns and the third and fourth patterns do not overlap each other in a planar view. Claim 12 A method for manufacturing a semiconductor device, comprising forming a first lower overlay key including first and second patterns on a lower layer, forming a first upper overlay key including third and fourth patterns on an upper layer positioned perpendicular to the lower layer, detecting a first overlay error by irradiating a first measurement light onto a first measurement area spanning the third and fourth patterns, and detecting a second overlay error by irradiating a second measurement light onto a second measurement area spanning the third and fourth patterns and different from the first measurement area, wherein the third and fourth patterns are photoresist patterns, the third pattern and the fourth pattern are arranged along a first direction, and the third pattern and the fourth pattern are each extended in a second direction intersecting the first direction. Claim 13 A method for manufacturing a semiconductor device according to claim 12, further comprising irradiating a third measurement light to a third measurement area spanning the first and second patterns to detect the first overlay error, and irradiating a fourth measurement light to a fourth measurement area spanning the first and second patterns and different from the third measurement area to detect the second overlay error. Claim 14 A method for manufacturing a semiconductor device according to claim 12, wherein at least a portion of the first measurement region overlaps with the second measurement region in a planar view. Claim 15 A method for manufacturing a semiconductor device according to claim 12, further comprising detecting an adjustment overlay error by irradiating a measurement light onto an adjustment measurement area spanning the first lower overlay key based on a first detection value of the first overlay error and a second detection value of the second overlay error. Claim 16 A method for manufacturing a semiconductor device according to claim 15, wherein the length of the long side of the adjustment measurement area extending in the first direction is different from the length of the long side of the first measurement area extending in the first direction. Claim 17 A first lower overlay key including first and second patterns extending in a first direction and a second lower overlay key including third and fourth patterns extending in a second direction intersecting the first direction are formed on a lower layer, wherein the second lower overlay key is arranged rotated 90° around the origin with respect to the first lower overlay key, and a first upper overlay key including fifth and sixth patterns extending in the first direction and a second upper overlay key including seventh and eighth patterns extending in the second direction are formed on an upper layer arranged perpendicularly to the lower layer, and a first overlay error is detected by irradiating a first_1 measurement area spanning the first and second patterns and a second_1 measurement area spanning the third and fourth patterns, wherein the first_1 measurement area is arranged rotated 90° around the origin with respect to the second_1 measurement area, and a first_2 measurement area spanning the first and second patterns and different from the first_1 measurement area and the second_1 measurement area spanning the third and fourth patterns A method for manufacturing a semiconductor device comprising irradiating a measurement light to a second measurement area different from the first measurement area to detect a second overlay error, wherein the first measurement area is arranged rotated 90° around the origin with respect to the second measurement area. Claim 18 A method for manufacturing a semiconductor device according to claim 17, further comprising detecting an adjustment overlay error by irradiating a measurement light onto an adjustment measurement area spanning the first lower overlay key based on a first detection value of the first overlay error and a second detection value of the second overlay error. Claim 19 A method for manufacturing a semiconductor device according to claim 18, wherein the length of the long side of the adjustment measurement area extending in the first direction is different from the length of the long side of the first_1 measurement area extending in the first direction. Claim 20 A method for manufacturing a semiconductor device according to claim 17, wherein the second upper overlay key is positioned rotated 90° around the origin with respect to the first upper overlay key, and the first overlay error is detected by irradiating a measurement light to a third_1 measurement area spanning the fifth and sixth patterns and a fourth_1 measurement area spanning the seventh and eighth patterns, wherein the third_1 measurement area is positioned rotated 90° around the origin with respect to the fourth_1 measurement area, and the second overlay error is detected by irradiating a measurement light to a third_2 measurement area spanning the fifth and sixth patterns and different from the third_1 measurement area, and a fourth_2 measurement area spanning the seventh and eighth patterns and different from the fourth_1 measurement area, wherein the third_2 measurement area is positioned rotated 90° around the origin with respect to the fourth_2 measurement area.

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