Asymmetric switch element and dicke-radiometer comprising the same

Abstract

An asymmetric switch circuit and a Dike radiation system equipped with the same are disclosed. An asymmetric switch circuit according to one embodiment of the present invention may include a first circuit section configured to connect a first port and a second port and forming a signal transmission path corresponding to the ON state of the asymmetric switch circuit, and a second circuit section configured to connect a reference load and the second port and forming a noise ingress path corresponding to the OFF state of the asymmetric switch circuit.

Description

Technology Field

[0001] The present invention relates to an asymmetric switch circuit and a Dicke radiometer equipped with the same. For example, the present invention relates to an asymmetric CMOS switch for implementing a millimeter-wave Dicke radiometer. Background Technology

[0002] Millimeter waves are a unique frequency band capable of acquiring internal transmission and reflection images without stimulating or damaging objects. In this regard, years of research and development have demonstrated the potential of millimeter waves in various fields, such as non-destructive inspection, security inspection, and radio astronomy. In particular, millimeter wave imaging systems have garnered attention due to their low ionization energy and see-through imaging capabilities, but several challenges remain for commercialization.

[0003] One of these is that imaging systems rely heavily on the sensitivity of the receiver, and receiver sensitivity is an important specification for millimeter-wave imaging systems to achieve high-resolution images. Dicke radiometer systems, which minimize the influence of noise on the input signal, are used for millimeter-wave passive imaging and can provide a level of high sensitivity capable of producing effective imaging results even for very small inputs, such as black-body radiation.

[0004] Specifically, a Decay switch inserted between the antenna and the low-noise amplifier operates by modulating the received signal to reduce the impact of noise introduced from the antenna on the receiver, and the reduced noise characteristics can significantly improve the signal-to-noise ratio (SNR) at the detector output.

[0005] In addition, in the case of the Dike switch, the operating frequency is high enough to ignore the flicker noise effect around the DC level so as to minimize noise generated by the device, and the switch component used in the Dike radiometer is required to have an insertion loss of about 3 dB in the ON state and an isolation characteristic of about 20 dB or more in the OFF state to achieve a sufficient resolution image and prevent bottlenecks.

[0006] Conventional Dike switches were designed using high-performance, high-cost compound semiconductor and SiGe BiCMOS technologies, or based on symmetric topologies. However, switch performance depends on the manufacturing process of the Dike switch, and conventional Dike switches faced limitations in simultaneously improving insertion loss and separation characteristics due to the adoption of a symmetric structure.

[0007] In this regard, Figure 1 is a diagram exemplifying the structure of a conventional symmetrical single-pole double-throw (SPDT) type Dike switch.

[0008] Referring to Fig. 1, since it is difficult to overcome the aforementioned trade-off relationship with a symmetrical single-pole double-throw type Dike switch, it is necessary to implement a Dike switch with low loss characteristics and high separation characteristics that is highly integrated, mass-producible, and reliable for the commercialization of millimeter-wave imaging systems.

[0009] The technology forming the background of this invention is disclosed in Korean Registered Patent Publication No. 10-1947905. The problem to be solved

[0010] The present invention aims to solve the problems of the aforementioned conventional technology by providing an asymmetric switch circuit that can minimize insertion loss and enhance separation characteristics by being implemented in an asymmetric form, and a Dike radiometer equipped with the same.

[0011] The present invention aims to solve the problems of the aforementioned conventional technology by providing an asymmetric switch circuit capable of effectively canceling out antenna noise ingress by implementing the same switch impedance observed at the output terminal, and a Dicke radiometer equipped with the same.

[0012] However, the technical problems that the embodiments of the present invention aim to solve are not limited to the technical problems described above, and other technical problems may exist. means of solving the problem

[0013] As a technical means for achieving the above-mentioned technical problem, an asymmetric switch circuit according to one embodiment of the present invention may include a first circuit section configured to connect a first port and a second port and forming a signal transmission path corresponding to the ON state of the asymmetric switch circuit, and a second circuit section configured to connect a reference load and the second port and forming a noise ingress path corresponding to the OFF state of the asymmetric switch circuit.

[0014] In addition, an asymmetric switch circuit according to one embodiment of the present invention can be designed such that the signal transmission path and the noise ingress path have an asymmetric structure by applying preset design parameters to each of the first circuit section and the second circuit section in a mutually distinct manner.

[0015] In addition, in an asymmetric switch circuit according to one embodiment of the present invention, the design parameters may be determined such that the first switch impedance viewed from the output terminal of the asymmetric switch circuit and the second switch impedance viewed from the output terminal of the second circuit correspond to each other.

[0016] In addition, the design parameters may include specification information of a switching element included in each of the first circuit section and the second circuit section, and length information of a transmission line formed in each of the first circuit section and the second circuit section.

[0017] In addition, if the switching element is a CMOS-based element, the specification information may include the channel width of the switching element.

[0018] In addition, the channel width of the switching element included in the first circuit may be set to be smaller than the channel width of the switching element included in the second circuit.

[0019] In addition, the first circuit section may be provided in a two-stage structure including a first switching element and a second switching element, and the second circuit section may be provided in a two-stage structure including a third switching element and a fourth switching element.

[0020] In addition, the specification information of at least some of the first to fourth switching elements may be set differently from one another.

[0021] Additionally, the transmission line may include a first transmission line connecting the first port and the first switching element in the first circuit section, and a second transmission line connecting the reference load and the third switching element in the second circuit section.

[0022] In addition, the length of the first transmission line may be set differently from the length of the second transmission line.

[0023] Additionally, the transmission line may include a third transmission line connecting the first switching element and the second switching element in the first circuit section, and a fourth transmission line connecting the third switching element and the fourth switching element in the second circuit section.

[0024] In addition, the length of the third transmission line and the length of the fourth transmission line can be set to be the same.

[0025] In addition, the first port can be connected to an antenna.

[0026] In addition, the above reference load can be designed considering the impedance characteristics of the antenna.

[0027] In addition, a resistor element may be connected to each body of the switching element.

[0028] Meanwhile, a Dike radiometer having an asymmetric switch circuit according to one embodiment of the present invention may include the asymmetric switch circuit, a detection module connected to the asymmetric switch circuit that alternately amplifies and detects a sum signal including a target signal and a noise signal and the noise signal, and an amplification module that generates an output signal including the target signal according to the difference between the amplified and detected sum signal and the amplified and detected noise signal using a single-pole double-throw (SPDT) switch.

[0029] The means for solving the problem described above are merely exemplary and should not be interpreted as intended to limit the present invention. In addition to the exemplary embodiments described above, additional embodiments may exist in the drawings and the detailed description of the invention. Effects of the invention

[0030] According to the means for solving the problem of the present invention described above, an asymmetric switch circuit that can minimize insertion loss and increase separation characteristics by being implemented in an asymmetric form, and a Dike radiation system equipped with the same can be provided.

[0031] According to the means for solving the problem of the present invention described above, an asymmetric switch circuit capable of effectively canceling out antenna noise ingress by equally implementing the switch impedance seen at the output terminal, and a Dike radiation system equipped with the same can be provided.

[0032] However, the effects obtainable from this invention are not limited to those described above, and other effects may exist. Brief explanation of the drawing

[0033] Figure 1 is a diagram illustrating the structure of a conventional symmetrical single-pole double-throw (SPDT) type Dike switch. FIG. 2 is a schematic diagram of a Dike radiation system having an asymmetric switch circuit according to one embodiment of the present invention. FIG. 3 is a schematic diagram of an asymmetric switch circuit according to one embodiment of the present invention. FIG. 4 is a diagram showing a signal transmission path provided by an asymmetric switch circuit according to one embodiment of the present invention. FIG. 5 is a diagram showing a noise incident path provided by an asymmetric switch circuit according to one embodiment of the present invention. Figure 6 is a conceptual diagram showing the difference in length between the transmission lines of the first circuit and the second circuit. Figure 7 is a conceptual diagram showing equivalent circuits corresponding to the signal transmission path and the noise incidence path, respectively. Figure 8 is a graph showing the simulation results for the output reflection coefficient corresponding to the signal transmission path and the noise incident path. FIG. 9 is a graph showing the measurement and simulation results of insertion loss in the ON state and separation characteristics in the OFF state, as an experimental example associated with an asymmetric switch circuit according to one embodiment of the present invention. FIG. 10 is a graph showing the measurement and simulation results of input and output reflection coefficients as an experimental example associated with an asymmetric switch circuit according to one embodiment of the present invention. FIG. 11 is a graph showing a comparison of performance with a conventional Dike switch as an experimental example associated with an asymmetric switch circuit according to one embodiment of the present invention. Specific details for implementing the invention

[0034] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0035] Throughout this specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "electrically connected" or "indirectly connected" with other elements interposed between them.

[0036] Throughout the entire specification, when a component is described as being located "on," "on top," "on top," "under," "on bottom," or "on bottom" of another component, this includes not only cases where the component is in contact with the other component but also cases where another component exists between the two components.

[0037] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0038] The present invention relates to an asymmetric switch circuit and a Dicke radiometer equipped with the same. For example, the present invention relates to an asymmetric CMOS switch for implementing a millimeter-wave Dicke radiometer.

[0039] FIG. 2 is a schematic diagram of a Dike radiation system having an asymmetric switch circuit according to one embodiment of the present invention.

[0040] Referring to FIG. 2, a Dicke radiometer (10) (hereinafter referred to as 'Dicke radiometer (10)') having an asymmetric switch circuit according to one embodiment of the present invention may include an asymmetric switch circuit (100) (hereinafter referred to as 'asymmetric switch circuit (100)') according to one embodiment of the present invention, a detection module (200), an amplification module (300), and a synchronization control module (400). For example, the amplification module (300) may be a chopper module as shown in FIG. 2, but is not limited thereto.

[0041] Additionally, referring to FIG. 2, the Dicke radiometer (10) disclosed herein may optionally include components such as a low noise amplifier (LNA; 201) and a variable gain amplifier (VGA; 203), but is not limited thereto.

[0042] Specifically, the detection module (200) may be connected to an asymmetric switch circuit (100) and may be equipped with a detector (202) for alternately detecting a sum signal ('Signal + Noise' in FIG. 2) and a noise signal including a target signal ('Signal' in FIG. 2) and a noise signal ('Noise' in FIG. 2).

[0043] Additionally, the amplification module (300) can generate an output signal ('Output' in FIG. 2) that selectively includes a target signal (Signal) based on the difference between the amplified and detected sum signal and the amplified and detected noise signal using a single-pole double-throw (SPDT) switch (301).

[0044] Additionally, the synchronization control module (400) can control the synchronization (synchronization) of the operation timing of the asymmetric switch circuit (100) and the amplification module (300).

[0045] Below, the specific structure and function of the asymmetric switch circuit (100) will be described in detail.

[0046] FIG. 3 is a schematic diagram of an asymmetric switch circuit according to one embodiment of the present invention.

[0047] Referring to FIG. 3, the asymmetric switch circuit (100) may include a first circuit section (110) and a second circuit section (120).

[0048] Specifically, the first circuit section (110) is configured to connect the first port (Port 1), which is an input port, and the second port (Port 2), which is an output port, and can form a signal transmission path in response to the on-state of the asymmetric switch circuit (100).

[0049] In addition, the second circuit section (120) has a reference load (R ref ; 12) is configured to connect the second port (Port 2) and can form a noise incident path corresponding to the off state of the asymmetric switch circuit (100).

[0050] Referring to FIG. 2 described above, the first port (Port 1) is a port connected to an antenna (11) that receives a summation signal including a target signal and a noise signal, and the reference load (12) may be designed (e.g., a resistance value is determined) considering the impedance characteristics of the antenna (11). For example, the reference load (12) may be a resistor element having a resistance value of 50Ω, but is not limited thereto.

[0051] In this regard, in the description of the embodiments of the present invention, the 'On state' may refer to a switching state in which the asymmetric switch circuit (100) operates to receive a summation signal including a target signal and a noise signal from the antenna (11) through the first port, and the 'Off state' may refer to a switching state in which the summation signal from the antenna (11) is not applied, and the noise signal is received through the reference load (12). For example, the asymmetric switch circuit (100) illustrated in FIG. 2 as a single-pole double-throw (SPDT) switch may be understood as having an operating state in which it forms a signal path to the antenna (11) through the terminal illustrated on the relatively upper side (12 o'clock direction), and an operating state in which it forms a signal path to the reference load (12) through the terminal illustrated on the relatively lower side (6 o'clock direction), which is understood as the 'Off state'.

[0052] In addition, referring to FIG. 3, the asymmetric switch circuit (100) disclosed herein, unlike a conventional Dike switch, is characterized by the fact that predetermined design parameters are applied separately to each of the first circuit section (110) and the second circuit section (120), thereby designing the signal transmission path and the noise incidence path to have an asymmetric structure.

[0053] Meanwhile, in the description of the embodiment of the present invention, the fact that the asymmetric switch circuit (100) applies a design method having an 'asymmetric structure' means that, unlike conventional Dike switches which had limitations in simultaneously improving insertion loss and separation characteristics because the circuit part forming the signal transmission path and the circuit part forming the noise incident path were designed symmetrically (symmetric structure) to match and mutually cancel out the noise signal applied along with the target signal through the signal transmission path and the noise signal applied through the noise incident path, the asymmetric switch circuit (100) disclosed in the present invention operates to generate an output signal in which the noise signal is canceled out by maintaining the noise signal introduced through the signal transmission path and the noise signal applied through the noise incident path equally, while the circuit part involved in the signal transmission path (in other words, the first circuit part (110)) is designed to minimize insertion loss, and the part involved in the noise incident path The circuit part (in other words, the second circuit part (120)) may refer to a design method in which design parameters applied to each circuit part of the first circuit part (110) and the second circuit part (120) are applied asymmetrically rather than identically in order to design the circuit part so as to maximize isolation characteristics.

[0054] In this regard, the design parameters applied for the asymmetric structure design of the asymmetric switch circuit (100) may include specification information of the switching element included in each of the first circuit section (110) and the second circuit section (120), and length information of the transmission line formed in each of the first circuit section (110) and the second circuit section (120).

[0055] FIG. 4 is a diagram showing a signal transmission path provided by an asymmetric switch circuit according to one embodiment of the present invention.

[0056] Referring to FIG. 4, the asymmetric switch circuit (100) disclosed herein may be provided with a first circuit section (110) having a two-stage structure including a first switching element (M1) and a second switching element (M2).

[0057] FIG. 5 is a diagram showing a noise incident path provided by an asymmetric switch circuit according to one embodiment of the present invention.

[0058] Referring to FIG. 5, the asymmetric switch circuit (100) disclosed herein may be provided with a two-stage structure in which the second circuit section (120) includes a third switching element (M3) and a fourth switching element (M4).

[0059] In addition, in the description of the embodiments of the present invention, the specification information of the switching element applied as a design parameter may specifically refer to the channel width of each of the first switching element (M1) to the fourth switching element (M4) when the switching element is a CMOS-based element (e.g., a transistor element manufactured through a CMOS process). However, it is not limited to this, and the 'specification information,' which is a design parameter applied separately to the first circuit section (110) and the second circuit section (120), may include various design elements such as the base area depending on the type of the switching element. For reference, in the case of an asymmetric switch circuit (100) equipped with a CMOS-based switching element, there may be an advantage in that mass production through a CMOS process is easy.

[0060] Meanwhile, in the description of the embodiment of the present invention, the switching element provided in the first circuit section (110) and the switching element provided in the second circuit section (120) may have different specification information. For example, when a plurality of switching elements are provided in the first circuit section (110) and a plurality of switching elements are provided in the second circuit section (120), the specification information of at least some of the switching elements of the first circuit section (110) and the second circuit section (120) may be set differently from each other. In this regard, according to one embodiment of the present invention, in the case of an asymmetric switch circuit (100) having a CMOS-based transistor as a switching element, the channel width of the switching element (e.g., first switching element (M1), second switching element (M2), etc.) included in the first circuit section (110) may be set to be smaller than the channel width of the switching element (e.g., third switching element (M3), fourth switching element (M4), etc.) included in the second circuit section (120).

[0061] Specifically, according to one embodiment of the present invention, the larger value between the channel width of the first switching element (M1) on the side of the first circuit section (110) and the channel width of the second switching element (M2) can be set to be smaller than the smaller value between the channel width of the third switching element (M3) on the side of the second circuit section (120) and the channel width of the fourth switching element (M4).

[0062] To help with a more specific understanding, for example, the channel width of the first switching element (M1) may be set to 30 μm, the channel width of the second switching element (M2) may be set to 40 μm, the channel width of the third switching element (M3) may be set to 100 μm, and the channel width of the fourth switching element (M4) may be set to 80 μm, but is not limited thereto.

[0063] Meanwhile, regarding the trend of design parameters concerning the specification information of the switching elements provided in the first circuit section (110) and the second circuit section (120), in the millimeter wave switch design, in the case of devices connected in series, the on-state resistance (R on Losses are added due to ), and off-state capacitance (C off Because of the difficulties caused by the capacitive feed, the shunt-connected transistor topology is mainly applied.

[0064] However, shunt-connected transistors have a trade-off element in terms of designing a relatively large number of shunt stages; specifically, while increasing the number of shunt stages can result in relatively superior separation characteristics, it can conversely reduce insertion loss.

[0065] With this in mind, the asymmetric switch circuit (100) disclosed herein may adopt a two-stage topology using a quarter-wave transformer at the common node to effectively perform impedance conversion for switching operation.

[0066] Meanwhile, each switching element (shunt transistor) of the asymmetric switch circuit (100) has a gate control voltage (V C It is turned on or off by ), and when this gate control voltage is set to High, the low impedance appearing at the drain terminal is converted to a high impedance through a quarter-wave transformer so that the signal is isolated, and in another adjacent path, the gate control voltage is set to Low so that the shunt transistor and the transmission line form an LC-distributed network so that the signal is transmitted.

[0067] The specifications (size) of such switching elements have a significant impact on the trade-off relationship between the two performance parameters mentioned above, and accordingly, different design parameters must be applied to the signal transmission path and the noise ingress path of the asymmetric switch circuit (100).

[0068] Specifically, the signal transmission path and the noise incident path each require different design parameters. Specifically, the signal transmission path corresponding to the on-state of the asymmetric switch circuit (100) (see FIG. 4) must be designed to minimize insertion loss, and the noise incident path corresponding to the off-state of the asymmetric switch circuit (100) (see FIG. 5) must be designed to maximize isolation.

[0069] In other words, the insertion loss of a shunt switch in the millimeter-wave band is C in the on-state. off It is governed by leakage through, and the smaller the size of the shunt transistor in the signal transmission path, the lower C off As it also becomes smaller, a shunt switching element relatively small compared to the noise entry path can be used in the signal transmission path to reduce insertion loss for the signal transmission path, and by placing a relatively large shunt transistor in the noise entry path, a relatively small transistor R in the noise entry path can be used. on High separation characteristics can be achieved by achieving this.

[0070] In other words, in the case of the asymmetric switch circuit disclosed herein, by designing the specifications (size) of the switching element separately for the first circuit section (110) and the second circuit section (120), there is an advantage of being able to achieve both low insertion loss in the On-state and high separation characteristics in the Off-state.

[0071] In addition, regarding the length information of the transmission line formed and applied as a design parameter in the description of the embodiment of the present invention, the transmission line is a first transmission line connecting the first port (Port 1) and the first switching element (M1) in the first circuit section (110), and a reference load (R) in the second circuit section (120). ref It may include a second transmission line connecting the ) and the third switching element (M3).

[0072] Figure 6 is a conceptual diagram showing the difference in length between the transmission lines of the first circuit and the second circuit.

[0073] Referring to FIG. 6, the length (L1) of the first transmission line of the first circuit section (110) may be set to be larger than the length (L2) of the second transmission line of the second circuit section (120). For the sake of understanding, design parameters of the asymmetric switch circuit (100) disclosed herein may be applied such that the length (L1) of the first transmission line is 225 µm and the length (L2) of the second transmission line is 30 µm, but are not limited thereto.

[0074] Additionally, the transmission line forming the asymmetric switch circuit (100) may include a third transmission line connecting a first switching element (M1) and a second switching element (M2) in the first circuit section (110), and a fourth transmission line connecting a third switching element (M3) and a fourth switching element (M4) in the second circuit section (120).

[0075] In this regard, the length of the third transmission line on the first circuit section (110) side and the length of the fourth transmission line on the second circuit section (120) side may be set to be the same according to an embodiment of the present invention. For example, the lengths of the third transmission line and the fourth transmission line may have a common length (L3) of 180 μm, and the design parameters of the asymmetric switch circuit (100) disclosed herein may be applied, but are not limited thereto.

[0076] Additionally, referring to FIGS. 3 to 6, in the case of the asymmetric switch circuit (100) disclosed herein, a body floating technique may be applied in which a resistor element is connected to the body of each switching element. For example, referring to FIGS. 3 to 6, a resistor element R1 may be connected to the body of the first switching element (M1), a resistor element R3 may be connected to the body of the second switching element (M2), a resistor element R5 may be connected to the body of the third switching element (M3), and a resistor element R7 may be connected to the body of the fourth switching element (M4), and each resistor element may have the same resistance value (e.g., 5kΩ).

[0077] In this regard, the body of the switching element is generally connected to the power node and the ground node for a stable threshold voltage, and in particular, when applying a body bias control method using negative bias, the insertion loss and insulation performance can be improved by controlling the threshold voltage of the switching element. However, since negative bias is difficult to implement and complicates the circuit, in the case of the asymmetric switch circuit (100) disclosed herein, a body floating technique connecting a resistor element can be adopted instead of using negative body bias to improve leakage between the drain and the body of the shunt transistor.

[0078] Figure 7 is a conceptual diagram showing equivalent circuits corresponding to the signal transmission path and the noise incident path, respectively, and Figure 8 is a graph showing the simulation results for the output reflection coefficient corresponding to the signal transmission path and the noise incident path.

[0079] Referring to FIGS. 7 and 8, in the case of the asymmetric switch circuit (100) disclosed herein, design parameters can be determined such that the first switch impedance viewed from the output terminal of the asymmetric switch circuit (e.g., the second port (Port 2) side) and the second switch impedance viewed from the output terminal of the second circuit (120) correspond to each other.

[0080] This can be understood as being intended to ensure that, despite the asymmetric structure between the first circuit section (110) and the second circuit section (120) of the asymmetric switch circuit (100), the impedance characteristics at the output terminal are similar to the noise signals introduced into the inputs of the first circuit section (110) and the second circuit section (120), respectively, so that they have similar characteristics at the output, regardless of the switching operation of the asymmetric switch circuit (100). That is, if the reflection coefficient of the output signal appears the same in each switching state (in other words, the on-state and the off-state) of the asymmetric switch circuit (100), the noise signals introduced from the two paths of the signal transmission path and the noise incidentence path are similarly applied, so that the noise introduced from the input of the antenna (11) is canceled out by the operation of the Dicke radiation system (10).

[0081] Hereinafter, an experimental example associated with the asymmetric switch circuit (100) disclosed herein will be described with reference to FIGS. 9 to 11.

[0082] FIG. 9 is a graph showing the measurement and simulation results of insertion loss in the ON state and separation characteristics in the OFF state, as an experimental example associated with an asymmetric switch circuit according to one embodiment of the present invention.

[0083] Referring to Fig. 9, the measured insertion loss and separation characteristics showed results in good agreement with the simulation; in particular, the insertion loss in the D-band was less than 2.8 dB, and the separation characteristic was greater than 22 dB. Additionally, the minimum insertion loss and maximum separation characteristic were measured at 1.7 dB at 155 GHz and 29 dB at 122 GHz, respectively. The performance improvement shown in the measurement results around 155 GHz is due to additional C off This may be caused by, and this can be explained by the fact that the small parasitic capacitance of the transistor is not included in the simulation model.

[0084] FIG. 10 is a graph showing the measurement and simulation results of input and output reflection coefficients as an experimental example associated with an asymmetric switch circuit according to one embodiment of the present invention.

[0085] Referring to Fig. 10, the measured input and output reflection losses were greater than 10 dB in the frequency range of 85 to 150 GHz.

[0086] FIG. 11 is a graph showing a comparison of performance with a conventional Dicke switch as an experimental example associated with an asymmetric switch circuit according to one embodiment of the present invention. Specifically, in the graph of FIG. 11, 'A' represents the performance of a switch circuit disclosed in prior research [SB Reyaz et al., "W-Band RF-Mems Dicke Switch Networks in a GaAs MMIC Process," Microw. Opt. Technol. Lett., vol. 55, pp. 2849-2853, Dec. 2013.], 'B' represents the performance of a switch circuit disclosed in prior research [R. Ben Yishay and D. Elad, "D-band Dicke-radiometer in 90 nm SiGe BiCMOS technology," Proc. IEEE MTT-S Int. Microw. Symp. (IMS), pp. 1957-1960, Jun. 2017.], and 'C' represents the performance of a switch circuit disclosed in prior research [F. This shows the performance of the switch circuit disclosed in Meng, K. Ma, KS Yeo and S. Xu, "Monolithic Sub-Terahertz SPDT Switches With Low Insertion Loss and Enhanced Isolation," IEEE Trans. Terahertz Sci. Technol., vol. 8, no. 2, pp. 192-200, Mar. 2018.

[0087] Referring to FIG. 11, the asymmetric switch circuit (100) disclosed herein showed results of optimal performance compared to switch circuits in prior research that were manufactured using a relatively high-performance process, even though it was manufactured using bulk CMOS technology.

[0088] A driving method for a Dike radiometer equipped with an asymmetric switch circuit according to one embodiment of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the present invention, or may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The above-described hardware device may be configured to operate as one or more software modules to perform the operation of the present invention, and vice versa.

[0089] In addition, the driving method of the Dike radiometer equipped with the aforementioned asymmetric switch circuit can also be implemented in the form of a computer program or application executed by a computer stored on a recording medium.

[0090] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0091] The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and the concept of equivalents thereof should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0092] 10: Dicke radiosystem having an asymmetric switch circuit 100: Asymmetrical switch circuit 110: From the 1st circuit 120: 2nd circuit 200: Detection module 201: Low Noise Amplifier (LNA) 202: Detector 203: Variable Gain Amplifier (VGA) 300: Amplification Module 301: Single-pole double-throw switch 400: Synchronous control module

Claims

Claim 1 In an asymmetric switch circuit, a first circuit part is configured to connect a first port and a second port and forms a signal transmission path in response to the ON state of the asymmetric switch circuit; An asymmetric switch circuit comprising: a second circuit section configured to connect a reference load and the second port and forming a noise ingress path corresponding to the off-state of the asymmetric switch circuit; wherein a pre-set design parameter is applied to each of the first circuit section and the second circuit section separately in order to design the first circuit section to reduce insertion loss and the second circuit section to increase separation characteristics, so that the signal transmission path and the noise ingress path are designed to have an asymmetric structure; wherein the design parameter includes specification information of a switching element included in each of the first circuit section and the second circuit section, and if the switching element is a CMOS-based element, the specification information includes the channel width of the switching element, and wherein the channel width of the switching element included in the first circuit section is set to be smaller than the channel width of the switching element included in the second circuit section. Claim 2 An asymmetric switch circuit according to claim 1, wherein the design parameters are determined such that the first switch impedance viewed from the output terminal of the asymmetric switch circuit and the second switch impedance viewed from the output terminal of the second circuit correspond to each other. Claim 3 An asymmetric switch circuit according to claim 1, wherein the design parameter further includes length information of a transmission line formed in each of the first circuit section and the second circuit section. Claim 4 delete Claim 5 An asymmetric switch circuit according to claim 3, wherein the first circuit part is provided in a two-stage structure including a first switching element and a second switching element, and the second circuit part is provided in a two-stage structure including a third switching element and a fourth switching element, wherein the specification information of at least some of the first to fourth switching elements is set differently from each other. Claim 6 In claim 5, the transmission line comprises a first transmission line connecting the first port and the first switching element in the first circuit section and a second transmission line connecting the reference load and the third switching element in the second circuit section, wherein the length of the first transmission line is set differently from the length of the second transmission line, an asymmetric switch circuit. Claim 7 In claim 5, the transmission line comprises a third transmission line connecting the first switching element and the second switching element in the first circuit section and a fourth transmission line connecting the third switching element and the fourth switching element in the second circuit section, wherein the length of the third transmission line and the length of the fourth transmission line are set to be the same, an asymmetric switch circuit. Claim 8 An asymmetric switch circuit according to claim 1, wherein the first port is connected to an antenna, and the reference load is designed considering the impedance characteristics of the antenna. Claim 9 An asymmetric switch circuit according to paragraph 3, characterized in that a resistor element is connected to each body of the switching element. Claim 10 A Dike radiometer comprising an asymmetric switch circuit, the Dike radiometer comprising: an asymmetric switch circuit according to claim 1; a detection module connected to the asymmetric switch circuit, which alternately amplifies and detects a sum signal including a target signal and a noise signal input through a first circuit and the noise signal input through a second circuit; and an amplification module that alternately receives the amplified and detected sum signal and the amplified and detected noise signal using a single-pole double-throw (SPDT) switch connected to the output of the detection module, and generates an output signal including the target signal according to the difference between the amplified and detected sum signal and the amplified and detected noise signal.

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