Semiconductor devices and a method of the same

Abstract

A semiconductor device may include a substrate comprising a peripheral region and a cell region; and an active pattern protruding from the substrate. The active pattern may include a first active pattern on the peripheral region and a second active pattern on the cell region, and a first corner on the upper part of the first active pattern and a second corner on the upper part of the second active pattern may have a rounded shape, and the curvature of the first corner may be greater than the curvature of the second corner.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a rounded upper corner of an active pattern and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increase in speed and lower power consumption of electronic devices, semiconductor devices embedded in them are also required to have fast operating speeds and / or low operating voltages, and to meet these requirements, more highly integrated semiconductor devices are necessary. However, as the high integration of semiconductor devices intensifies, the reliability of the semiconductor devices may deteriorate and the production yield may decrease. Accordingly, much research is being conducted to improve the reliability and production yield of semiconductor devices. Relevant prior art includes U.S. Patent Application Publication US2007 / 0114633 (May 24, 2007), Registered Patent Publication No. 10-0672120 (January 19, 2007), and Registered Patent Publication No. 10-2014-0137222 (December 2, 2014). The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved reliability.

[0005] Another technical objective of the present invention is to provide a method for manufacturing a semiconductor device with improved yield.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to the present invention may include a substrate comprising a peripheral region and a cell region; and an active pattern protruding from the substrate. The active pattern may include a first active pattern on the peripheral region and a second active pattern on the cell region, and a first corner on the upper part of the first active pattern and a second corner on the upper part of the second active pattern may have a rounded shape, and the curvature of the first corner may be greater than the curvature of the second corner.

[0008] A semiconductor device according to the present invention may include a substrate including a peripheral region; an active pattern protruding from the substrate on the peripheral region; a device isolation pattern between the active pattern and an adjacent active pattern; and a gate dielectric pattern extending along the upper surface of the active pattern and the upper surface of the device isolation pattern. The upper corner of the active pattern may have a rounded shape, the upper surface of the device isolation pattern may be located at substantially the same height as the upper surface of the active pattern or at a lower height than the upper surface of the active pattern, and the bottom surface of the gate dielectric pattern may have a rounded shape along the profile of the upper corner of the active pattern.

[0009] A method for manufacturing a semiconductor device according to the present invention may include: sequentially forming a lower mask film and an upper mask film on a substrate including a peripheral region and a cell region; forming a first mask pattern on the peripheral region and a second mask pattern on the cell region on the upper mask film; removing a portion of the upper mask film exposed by the second mask pattern on the cell region; removing the first mask pattern on the peripheral region after the portion of the upper mask film is removed; and using the second mask pattern as an etching mask to etch the remainder of the upper mask film on the cell region and the peripheral region to form an upper mask pattern. The upper mask pattern may cover the lower mask film on the peripheral region and expose a portion of the lower mask film on the cell region. Effects of the invention

[0010] According to the concept of the present invention, the upper corner of an active pattern on a surrounding area may have a rounded shape, and accordingly, the bottom surface of a gate dielectric pattern on the active pattern may also have a rounded shape along the profile of the corner. As a result, the concentration of the electric field on the gate dielectric pattern in the area adjacent to the corner may be alleviated, and the degradation of the gate dielectric pattern may be prevented. Through this, the reliability of the semiconductor device may be improved.

[0011] Furthermore, a seam inside a device isolation pattern adjacent to the active pattern may be formed at the bottom of the device isolation pattern, and accordingly, the seam may not be exposed to the outside. As a result, process defects such as residue that may form inside the exposed seam during subsequent processes can be improved, and production yield can be improved. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram of a semiconductor device according to embodiments of the present invention. FIGS. 2 to 12 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, FIGS. 2 and FIGS. 8 are enlarged views corresponding to PR and CR of FIGS. 1, FIGS. 3 to 7 are cross-sectional views corresponding to AA' and B-B' of FIGS. 2, and FIGS. 9 to 12 are cross-sectional views corresponding to AA' and B-B' of FIGS. 8. Figures 13 and 14 are enlarged views corresponding to P1 and P2 in Figure 12. Fig. 15 is an enlarged view corresponding to P3 and P4 of Fig. 12. FIG. 16 is a plan view showing a semiconductor device according to some embodiments of the present invention. FIG. 17 is a cross-sectional view corresponding to AA' and B-B' in FIG. 16. Figures 18 and 19 are enlarged views corresponding to P5 in Figure 17. Specific details for implementing the invention

[0013] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0015] FIG. 1 is a block diagram of a semiconductor device according to embodiments of the present invention.

[0016] Referring to FIG. 1, the semiconductor device may include cell blocks (CB) and a surrounding block (PB) that surrounds each of the cell blocks (CB). The semiconductor device may be a memory device, and each of the cell blocks (CB) may include a cell circuit such as a memory integrated circuit. The cell blocks (CB) may be spaced apart from each other in a first direction (D1) and a second direction (D2) that intersects (e.g., orthogonally) the first direction (D1).

[0017] The peripheral block (PB) may include various peripheral circuits necessary for the operation of the cell circuit, and the peripheral circuits may be electrically connected to the cell circuit. The peripheral block (PB) may include sense amplifier circuits (SA) and sub-wordline driver circuits (SWD). For example, the sense amplifier circuits (SA) may face each other with the cell blocks (CB) in between, and the sub-wordline driver circuits (SWD) may face each other with the cell blocks (CB) in between. The peripheral block (PB) may further include power supply and ground driver circuits for driving the sense amplifier, but the concept of the present invention is not limited thereto.

[0019] FIGS. 2 to 12 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, FIGS. 2 and FIG. 8 are enlarged views corresponding to PR and CR of FIG. 1, FIGS. 3 to 7 are cross-sectional views corresponding to AA' and B-B' of FIG. 2, and FIGS. 9 to 12 are cross-sectional views corresponding to AA' and B-B' of FIG. 8. FIGS. 13 and 14 are enlarged views corresponding to P1 and P2 of FIG. 12. FIG. 15 is an enlarged view corresponding to P3 and P4 of FIG. 12.

[0020] Referring to FIGS. 2 and 3, a substrate (10) including a peripheral region (PR) and a cell region (CR) may be provided. The substrate (10) may be a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The peripheral region (PR) may be one region of the substrate (10) provided with the peripheral block (PB) of FIG. 1, and the cell region (CR) may be another region of the substrate (10) provided with each cell block (CB) of FIG. 1. The lower surface of the substrate (10) may be parallel to the first direction (D1) and the second direction (D2).

[0021] A lower mask film (12) and an upper mask film (14) may be formed sequentially on the substrate (10). The lower mask film (12) and the upper mask film (14) may be formed to cover the upper surface of the substrate (10) on the peripheral region (PR) and the cell region (CR). The lower mask film (12) may include a material having a high etching selectivity ratio with respect to the upper mask film (14). For example, the lower mask film (12) may include silicon oxide, and the upper mask film (14) may include polysilicon.

[0022] A first mask pattern (20) may be formed on the surrounding area (PR), and a second mask pattern (22) may be formed on the cell area (CR). The first and second mask patterns (20, 22) may be formed, for example, by Quadruple Patterning Technology (QPT). The first mask pattern (20) may be a multilayer film comprising at least one of a carbon-based material (e.g., an amorphous carbon layer (ACL), a Spin-On Hardmask (SOH)), or a silicon oxynitride film. For example, the first mask pattern (20) may be a multilayer film in which a carbon-based material and a silicon oxynitride film are stacked in sequence. The second mask pattern (22) may have a line shape that intersects the first direction (D1) and the second direction (D2) and extends in a third direction (D3) parallel to the lower surface of the substrate (10). The second mask pattern (22) may be spaced apart from adjacent second mask patterns (22) in the first direction (D1). The second mask pattern (22) may, for example, include silicon oxide.

[0023] The upper mask (14) may include a first part (14a), a second part (14b), and a third part (14c). The first part (14a) may be an area of ​​the upper mask (14) that overlaps vertically with the first mask pattern (20) and the second mask pattern (22). The upper surface of the first part (14a) may be in contact with the bottom surface of the first mask pattern (20) or the bottom surface of the second mask pattern (22), and the bottom surface of the first part (14a) may be in contact with the upper surface of the lower mask (12). The second part (14b) may be another area of ​​the upper mask (14) that does not overlap vertically with the second mask pattern (22). The upper surface of the second part (14b) may be exposed by the second mask pattern (22). The third portion (14c) may be another area of ​​the upper mask film (14) that does not vertically overlap with the second mask pattern (22) and may be provided below the second portion (14b). The bottom surface of the third portion (14c) may be in contact with the upper surface of the lower mask film (12). The second portion (14b) may be a portion that is removed through a removal process described later with reference to FIG. 4, and the third portion (14c) may be a portion that is not removed below the second portion (14b). That is, through a subsequent removal process, the area where the second portion (14b) and the third portion (14c) are provided may be adjusted, and furthermore, the curvature of the active pattern (AP), described finally with reference to FIG. 12 to FIG. 14, may be adjusted.

[0024] Referring to FIG. 4, the second portion (14b) of the upper mask film (14) on the cell region (CR) can be removed. The removal process may include an anisotropic etching process using the second mask pattern (22) as an etching mask.

[0025] The first part (14a) and the third part (14c) may not be removed through the removal process. The first part (14a) may remain on the surrounding area (PR) and the cell area (CR), and the third part (14c) may remain on the cell area (CR). The upper surface of the third part (14c) may be exposed and may be located at a lower height than the upper surface of the first part (14a). The upper surface of the lower mask film (12) may be covered by the first part (14a) and the third part (14c) and may not be exposed. Through the removal process, the upper part of the first mask pattern (20) and the upper part of the second mask pattern (22) may be removed.

[0026] Referring to FIG. 5, the first mask pattern (20) on the surrounding area (PR) can be removed. The removal process may include performing an ashing process. Through the removal process, the upper surface of the first portion (14a) on the surrounding area (PR) may be exposed. The upper surface of the first portion (14a) on the cell area (CR) may be covered by the second mask pattern (22) and may not be exposed. The removal process of the first mask pattern (20) may be performed as an in-situ process with the removal process of the second portion (14b) of the upper mask film (14).

[0027] Referring to FIG. 6, an etching process can be performed on the upper mask film (14), and an upper mask pattern (15) can be formed through the etching process. The etching process may include an anisotropic etching process using the second mask pattern (22) as an etching mask. Through the etching process, the upper portion of the second mask pattern (22) can be etched.

[0028] In detail, the third portion (14c) may be etched on the cell region (CR). Accordingly, a portion of the lower mask film (12) may be exposed. The portion of the lower mask film (12) may be a region of the lower mask film (12) that does not vertically overlap with the second mask pattern (22). On the cell region (CR), the first portion (14a) of the upper mask film (14) may not be etched by the etching process and may form the upper mask pattern (15).

[0029] The upper portion of the first portion (14a) of the upper mask film (14) on the surrounding area (PR) may be etched by the etching process. Accordingly, the thickness of the first portion (14a) along the fourth direction (D4) on the surrounding area (PR) may be reduced. The fourth direction (D4) may be a direction perpendicular to the lower surface of the substrate (10). The remainder of the first portion (14a) on the surrounding area (PR) may remain on the lower mask film (12) without being etched by the etching process, and the upper mask pattern (15) on the surrounding area (PR) may be formed.

[0030] The height of the upper surface of the upper mask pattern (15) on the surrounding area (PR) may be located at a height substantially equal to or lower than the height of the upper surface of the upper mask pattern (15) on the cell area (CR). For the fourth direction (D4), the thickness of the upper mask pattern (15) on the surrounding area (PR) may be substantially equal to or thinner than the thickness of the upper mask pattern (15) on the cell area (CR). The difference in thickness between the upper mask patterns (15) on the surrounding area (PR) and the cell area (CR) can be controlled through the removal process described with reference to FIG. 4. Through the removal process of FIG. 4, the thickness of the second part (14b) and the third part (14c) can be defined. The thicker the thickness of the third part (14c) (i.e., the less the amount of upper mask film (14) removed through the removal process of FIG. 4), the greater the difference in thickness between the upper mask patterns (15).

[0031] Referring to FIG. 7, the second mask pattern (22) may be removed. A portion of the lower mask film (12) on the cell region (CR) may be removed together with the second mask pattern (22). The portion of the lower mask film (12) may be the upper part of an area that does not vertically overlap with the upper mask pattern (15) and may be an area exposed by the upper mask pattern (15). The upper surface of the substrate (10) may be covered by the lower mask film (12) and may not be exposed by the lower mask film (12). The lower mask film (12) on the surrounding region (CR) may not be removed.

[0032] Referring to FIGS. 8 and 9, a third mask film (30) and a photoresist pattern (32) can be formed in sequence. First, the third mask film (30) can cover the upper mask pattern (15) on the peripheral region (PR) and the cell region (CR). Subsequently, a photoresist film (not shown) can cover the third mask film (30), and the photoresist film can be patterned into the photoresist pattern (32) through an exposure and development process.

[0033] On the surrounding area (PR), the photoresist pattern (32) may be spaced apart from neighboring photoresist patterns (32) in the first direction (D1). On the cell area (CR), the photoresist pattern (32) may include holes (H). The holes (H) may be spaced apart from each other in the first direction (D1) and the second direction (D2). Each of the holes (H) may overlap vertically with a part of the upper mask pattern (15).

[0034] Referring to FIG. 10, the third mask film (30) can be etched along the photoresist pattern (32), thereby forming a third mask pattern (not shown). Subsequently, a fourth mask pattern (16) can be formed by etching the upper mask pattern (15) using the third mask pattern as an etching mask. Although not shown, from a planar perspective, the upper mask pattern (15), having a line shape extending in the third direction (D3) on the cell region (CR), can be separated into a plurality of fourth mask patterns (16) that are spaced apart from each other in the third direction (D3) and have bar shapes extending in the third direction (D3). The fourth mask pattern (16) on the peripheral region (PR) can have substantially the same shape as the photoresist pattern (32) from a planar perspective.

[0035] For example, the etching process using the photoresist pattern (32) and the third mask pattern may be performed only once. For another example, the etching process may be performed multiple times. In this case, each time the etching process is performed, the holes (H) of FIG. 8 may be provided at different locations.

[0036] The height of the upper surface of the fourth mask pattern (16) on the surrounding area (PR) may be located at a height substantially equal to or lower than the height of the upper surface of the fourth mask pattern (16) on the cell area (CR). With respect to the fourth direction (D4), the thickness of the fourth mask pattern (16) on the surrounding area (PR) may be substantially equal to or thinner than the thickness of the fourth mask pattern (16) on the cell area (CR). The thickness difference between the fourth mask patterns (16) on the surrounding area (PR) and the cell area (CR) may be proportional to the thickness difference between the upper mask patterns (15) on the surrounding area (PR) and the cell area (CR) described with reference to FIG. 6. Consequently, the thickness difference between the fourth mask patterns (16) can be controlled through the removal process described with reference to FIG. 4. The width of the bottom surface of the fourth mask pattern (16) on the surrounding area (PR) may be greater than the width of the bottom surface of the fourth mask pattern (16) on the cell area (CR).

[0037] Referring to FIG. 11, the lower mask film (12) and the upper part of the substrate (10) can be etched using the fourth mask pattern (16) as an etching mask, thereby forming the lower mask pattern (13) and the active pattern (AP).

[0038] The above active pattern (AP) may include a first active pattern (AP1) on the surrounding area (PR) and a second active pattern (AP2) on the cell area (CR). The active pattern (AP) may be an unetched portion of the upper part of the substrate (10). For convenience of explanation, the remainder of the substrate (10) excluding the active pattern (AP) will be referred to as the substrate (10) from now on. Accordingly, the active pattern (AP) may protrude from the substrate (10), and the bottom surface of the active pattern (AP) may be in contact with the upper surface of the substrate (10). Specifically, the bottom surface (52) of the first active pattern (AP1) may be in contact with the upper surface (56) of the substrate (10) on the surrounding area (PR), and the bottom surface (62) of the second active pattern (AP2) may be in contact with the upper surface (66) of the substrate (10) on the cell area (CR). With respect to the first direction (D1) above, the width of the first active pattern (AP1) at the same height may be greater than the width of the second active pattern (AP2). For example, the width of the upper surface (54) of the first active pattern (AP1) may be greater than the width of the upper surface of the second active pattern (AP2).

[0039] A recess may be formed between the above active pattern (AP) and an adjacent active pattern (AP). A first recess (RE1) may be formed between the first active pattern (AP1) and an adjacent first active pattern (AP1), and a second recess (RE2) may be formed between the second active pattern (AP2) and an adjacent second active pattern (AP2). At the same height, the width of the first recess (RE1) may be greater than the width of the second recess (RE2). The depth of the first recess (RE1) may differ from the depth of the second recess (RE2). For example, the depth of the first recess (RE1), which has a greater width, may be deeper than the depth of the second recess (RE2) due to an etching loading effect. As another example, the area to be etched of the first recess (RE1) having a larger width may be relatively wider than that of the second recess (RE2), and as a result, the depth of the first recess (RE1) may be shallower than the depth of the second recess (RE2). Accordingly, the length (L1) of the first active pattern (AP1) with respect to the fourth direction (D4) may differ from the length (L2) of the second active pattern (AP2).

[0040] The lower mask pattern (13) may be formed on the active pattern (AP). The height of the upper surface of the lower mask pattern (13) on the peripheral region (PR) may be located at a height substantially equal to or lower than the height of the upper surface of the lower mask pattern (13) on the cell region (CR). For the fourth direction (D4), the thickness of the lower mask pattern (13) on the peripheral region (PR) may be substantially equal to or thinner than the thickness of the lower mask pattern (13) on the cell region (CR). The thickness difference between the lower mask patterns (13) on the peripheral region (PR) and the cell region (CR) may be controlled by the thickness difference between the fourth mask patterns (16) on the peripheral region (PR) and the cell region (CR) described with reference to FIG. 10. Consequently, the thickness difference between the lower mask patterns (13) may be controlled through the removal process described with reference to FIG. 4.

[0041] Referring to FIG. 12, the lower mask pattern (13) can be removed. Subsequently, the recess can be filled with a device isolation pattern (STI). Specifically, the first recess (RE1) can be filled with the first device isolation pattern (STI1) among the device isolation patterns (STI), and the second recess (RE2) can be filled with the second device isolation pattern (STI2) among the device isolation patterns (STI). The device isolation pattern (STI) may include silicon oxide, silicon nitride, or a combination thereof.

[0042] The first device isolation pattern (STI1) may include a seam (SM) inside. The seam (SM) may be a type of empty space. The upper portion of the seam (SM) may be located at a height lower than the upper surface (58) of the first device isolation pattern (STI1). That is, the seam (SM) may not be exposed to the outside of the first device isolation pattern (STI1).

[0043] Referring to FIGS. 12 to 14, the upper surface of the device isolation pattern (STI) may be located at a height substantially equal to or lower than the upper surface of an adjacent active pattern (AP). Specifically, the upper surface (58) of the first device isolation pattern (STI1) may be located at a height substantially equal to or lower than the upper surface (54) of the first active pattern (AP1), and the upper surface (68) of the second device isolation pattern (STI2) may be located at a height substantially equal to or lower than the upper surface (64) of the second active pattern (AP2). For example, as shown in FIG. 13, the upper surface (58) of the first device isolation pattern (STI1) may be located at a height substantially equal to the upper surface (54) of the first active pattern (AP1). As another example, as shown in FIG. 14, the upper surface (58) of the first device isolation pattern (STI1) may be located at a lower height than the upper surface (54) of the first active pattern (AP1).

[0044] The upper corner of the above active pattern (AP) may have a rounded shape. For example, the upper corner of the above active pattern (AP) may have a convexly rounded shape. The first corner (EG1) of the upper part of the first active pattern (AP1) may have a more rounded shape than the second corner (EG2) of the upper part of the second active pattern (AP2). That is, the curvature of the first corner (EG1) may be greater than the curvature of the second corner (EG2).

[0045] The difference in curvature between the first edge (EG1) and the second edge (EG2) can be controlled by the difference in thickness between the fourth mask patterns (16) on the surrounding area (PR) and the cell area (CR) described with reference to FIG. 10. The greater the difference in thickness between the fourth mask patterns (16) (i.e., the thinner the thickness of the fourth mask pattern (16) on the surrounding area (PR) is than the thickness of the fourth mask pattern (16) on the cell area (PR)), the greater the difference in curvature may be. This is because the fourth mask pattern (16) is used as an etching mask for forming the active pattern (AP). For example, when forming the first active pattern (AP1), the thinner the thickness of the fourth mask pattern (16) on the surrounding area (PR), the greater the curvature may be due to the first edge (EG1) being etched further. The difference in curvature between the first edge (EG1) and the second edge (EG2) can be increased. Consequently, the difference in curvature between the first edge (EG1) and the second edge (EG2) can be controlled through the removal process described with reference to FIG. 4.

[0046] The first active pattern (AP1) may have a first width (w1), a second width (w2), and a third width (w3). The first width (w1) may be the width of the bottom surface (52) of the first active pattern (AP1). The second width (w2) may be the width of the top surface (54) of the first active pattern (AP1). The third width (w3) may be the width at a height that is half the height from the bottom surface (52) of the first active pattern (AP1) to the top surface (54) of the first active pattern (AP1). The third width (w3) may be smaller than the first width (w1) and larger than the second width (w2). The difference between the third width (w3) and the first width (w1) may be smaller than the difference between the third width (w3) and the second width (w2).

[0047] Referring to FIGS. 12 and 15, the first active pattern (AP1) and the second active pattern (AP2) may each have a first side (S1) and a second side (S2). The first side (S1) and the second side (S2) may each be in contact with the first device isolation pattern (STI1) and the second device isolation pattern (STI2). The first side (S1) may form a first angle (A1) with the upper surface (56) of the substrate (10) on the peripheral region (PR) at the bottom of the first active pattern (AP1). The second side (S2) may form a second angle (A2) with the upper surface (66) of the substrate (10) on the cell region (CR) at the bottom of the second active pattern (AP2). The first angle (A1) and the second angle (A2) may each be greater than 90 degrees. The first angle (A1) may be substantially the same as the second angle (A2) or larger than the second angle (A2).

[0049] According to the present invention, the second portion (14b) of the upper mask film (14) on the cell region (CR) may be removed first before the first mask pattern (20) on the peripheral region (PR) is removed. After the first mask pattern (20) is removed, the third portion (14c) of the upper mask film (14) may be removed. That is, while the removal process of the third portion (14c) is in progress, the upper mask film (14) on the peripheral region (PR) may not be covered by the first mask pattern (20). As a result, the upper portion of the upper mask film (14) on the peripheral region (PR) may be removed together. Accordingly, the thickness of the fourth mask pattern (16) formed thereafter in the fourth direction (D4) may be relatively smaller in the peripheral region (PR). That is, the fourth mask pattern (16), which is an etching mask for forming the first active pattern (AP1) on the surrounding region (PR), can be thinned. Accordingly, during the etching process for forming the active pattern (AP), the first active pattern (AP1) can be relatively more affected by etching compared to the case where the fourth mask pattern (16) on the surrounding region (PR) is not thinned. As a result, the first corner (EG1) of the first active pattern (AP1) can have a rounded shape, and subsequently, as shown in FIG. 19, the bottom surface of the gate dielectric pattern (305) can also have a rounded shape along the profile of the first corner (EG1). Due to this, the concentration of the electric field on the gate dielectric pattern (305) in the region adjacent to the first corner (EG1) can be relieved, and the degradation of the gate dielectric pattern (305) can be prevented. Through this, the reliability of the semiconductor device can be improved.

[0050] Furthermore, due to the relatively large etching effect, the first side (S1) of the first active pattern (AP1) may form a first angle (A1) greater than 90 degrees with the upper surface (56) of the substrate (10) on the surrounding area (PR). Accordingly, the shim (SM) within the first device isolation pattern (STI1) may be formed below the first device isolation pattern (STI1) and not exposed to the outside. As a result, process defects such as residue that may form within the exposed shim (SM) during subsequent processes can be improved, and production yield can be enhanced.

[0052] FIG. 16 is a plan view showing a semiconductor device according to some embodiments of the present invention. FIG. 17 is a cross-sectional view corresponding to AA' and B-B' in FIG. 16. FIG. 18 and FIG. 19 are enlarged views corresponding to P5 in FIG. 17.

[0053] Referring to FIGS. 16 to 19, a substrate (10) including a peripheral region (PR) and a cell region (CR) may be provided. The substrate (10) may be a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0054] An active pattern (AP) may be disposed on the substrate (10). The active pattern (AP) may protrude from the substrate (10). The active pattern (AP) may include a first active pattern (AP1) disposed on the peripheral region (PR) and a second active pattern (AP2) disposed on the cell region (CR). In a planar view, the second active pattern (AP2) may have a bar shape extending in the third direction (D3).

[0055] The first active pattern (AP1) may have a first edge (EG1) on its upper surface, and the second active pattern (AP2) may have a second edge (EG2) on its upper surface. The first edge (EG1) and the second edge (EG2) may have a rounded shape. The curvature of the first edge (EG1) may be greater than the curvature of the second edge (EG2).

[0056] A device isolation pattern (STI) may be disposed between the active pattern (AP) and an adjacent active pattern (AP). The device isolation pattern (STI) may include a first device isolation pattern (STI1) interposed between the first active patterns (AP1) and a second device isolation pattern (STI2) interposed between the second active patterns (AP2). The device isolation pattern (STI) may include silicon oxide, silicon nitride, or a combination thereof. Among the device isolation patterns (STI), the first device isolation pattern (STI1) may include a seam (SM) inside.

[0057] The upper surface of the above-mentioned device isolation pattern (STI) may be located at a height substantially equal to or lower than the upper surface of an adjacent active pattern (AP). The upper surface (58) of the above-mentioned device isolation pattern (STI1) may be located at a height substantially equal to or lower than the upper surface (54) of the above-mentioned active pattern (AP1). For example, as shown in FIG. 18, the upper surface (58) of the above-mentioned device isolation pattern (STI1) may be located at a height substantially equal to the upper surface (54) of the above-mentioned active pattern (AP1). For another example, as shown in FIG. 19, the upper surface (58) of the above-mentioned device isolation pattern (STI1) may be located at a height lower than the upper surface (54) of the above-mentioned active pattern (AP1).

[0058] Impurity regions may be provided within the active pattern (AP). The impurity regions may include a first impurity region (111), a second impurity region (112), and a third impurity region (113). The first impurity region (111) may be provided on the upper side of the first active pattern (AP1). The second impurity region (112) may be provided on the upper side of the second active pattern (AP2) and may be provided adjacent to the center of the second active pattern (AP2) in a planar view. The third impurity region (113) may be provided on the upper side of the second active pattern (AP2) and may be provided adjacent to both ends of the second active pattern (AP2) in a planar view. The second impurity region (112) may contain impurities of the same conductivity type (e.g., N-type) as the third impurity region.

[0059] A pair of word lines (WL) may cross the second active pattern (AP2) in the first direction (D1) on the cell region (CR). The pair of word lines (WL) may be spaced apart from each other in the second direction (D2). The second impurity region (112) may be interposed between the pair of word lines (WL), and the third impurity region (113) may be provided adjacent to the end of the second active pattern (AP2) that is not interposed between the pair of word lines (WL). The pair of word lines (WL) may be embedded within the substrate (10).

[0060] On the surrounding region (PR), a gate dielectric pattern (305) and a gate structure (GS) may be disposed on the first active pattern (AP1). The gate dielectric pattern (305) and the gate structure (GS) may be stacked sequentially on the first active pattern (AP1). The gate dielectric pattern (305) may extend along the upper surface (54) of the first active pattern (AP1) and the upper surface (58) of the first device isolation pattern (STI1). The gate dielectric pattern (305) may, for example, include silicon oxide.

[0061] The upper surface of the gate dielectric pattern (305) on the first device isolation pattern (STI1) may be located at a height substantially equal to or lower than the upper surface of the gate dielectric pattern (305) on the first active pattern (AP1). For example, as shown in FIG. 18, the upper surface of the gate dielectric pattern (305) on the first device isolation pattern (STI1) may be located at a height substantially equal to the upper surface of the gate dielectric pattern (305) on the first active pattern (AP1). For another example, as shown in FIG. 19, the upper surface of the gate dielectric pattern (305) on the first device isolation pattern (STI1) may be located at a height lower than the upper surface of the gate dielectric pattern (305) on the first active pattern (AP1).

[0062] The bottom surface of the gate dielectric pattern (305) may have a rounded shape along the profile of the first corner (EG1). That is, the gate dielectric pattern (305) may have a curvature greater than 0 in the region adjacent to the first corner (EG1) on the upper side of the first active pattern (AP1).

[0063] When the first corner (EG1) has an angular shape, the bottom surface of the gate dielectric pattern (305) may have an angular shape along the profile of the first corner (EG1). In this case, when the semiconductor device is driven, an electric field may be concentrated on the angular region, and as a result, the gate dielectric pattern (305) may be stressed and degraded. Therefore, when the bottom surface of the gate dielectric pattern (305) has a rounded shape rather than an angular shape, the concentration of the electric field transmitted to the gate dielectric pattern (305) can be mitigated, and as a result, the degradation of the gate dielectric pattern (305) can be prevented.

[0064] The gate structure (GS) may traverse the first active pattern (AP1). The gate structure (GS) may include a peripheral polysilicon pattern (310a), a first peripheral ohmic pattern (331a), a peripheral metal-containing pattern (330a), a first peripheral capping pattern (351a), and a spacer (355). The peripheral polysilicon pattern (310a), the first peripheral ohmic pattern (331a), the peripheral metal-containing pattern (330a), and the first peripheral capping pattern (351a) may be stacked sequentially on the gate dielectric pattern (305). The spacer (355) may be provided on the side of the surrounding polysilicon pattern (310a), the side of the first surrounding ohmic pattern (331a), the side of the surrounding metal-containing pattern (330a), and the side of the first surrounding capping pattern (351a). A second surrounding capping pattern (352a) may cover the upper surface of the first lower capping pattern (351a) and extend with a substantially uniform thickness along the side of the spacer (355) and the upper surface of the gate dielectric pattern (305). A lower insulating pattern (370) may wrap the gate structure (GS) and the second surrounding capping pattern (352a).

[0065] For example, the surrounding polysilicon pattern (310a) may include polysilicon that is doped with impurities or not doped. For example, the first surrounding ohmic pattern (331a) may include a metal silicide. For example, the surrounding metal-containing pattern (330a) may include a metal (tungsten, titanium, tantalum, etc.). For example, the first and second surrounding capping patterns (351a, 352a) may include silicon nitride. For example, the spacer (355) may include silicon oxide.

[0066] A third peripheral capping pattern (353a), a peripheral diffusion prevention pattern (342a), and a contact plug (CPLG) may be provided, which are stacked sequentially on the lower insulation pattern (370). A peripheral filling pattern (400a) may be interposed between the contact plug (CPLG) and an adjacent contact plug (CPLG). The peripheral filling pattern (400a) may penetrate the peripheral diffusion prevention pattern (342a) and extend into the third peripheral capping pattern (353a).

[0067] For example, the third peripheral capping pattern (353a) may include silicon nitride. For example, the peripheral diffusion prevention pattern (342a) may include a metal nitride such as titanium nitride or tantalum nitride. For example, the contact plug (CPLG) may include a metal-containing material such as tungsten.

[0068] A peripheral etch-stop pattern (420a) and an upper insulating pattern (500) may be provided, which are sequentially stacked on the contact plug (CPLG) and the peripheral filling pattern (400a). For example, the peripheral etch-stop pattern (420) may include SiBN. The etch-stop pattern (420) may include a single film or multiple films. For example, the upper insulating pattern (500) may include silicon oxide.

[0069] On the cell region (CR), a buffer pattern (306) may cover the second active pattern (AP2), the second device isolation pattern (STI2), and the pair of word lines (WL). The buffer pattern (306) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0070] Bitlines (BL) may be placed on the buffer pattern (306). The bitlines (BL) may extend along the second direction (D2) and may be spaced apart from each other along the first direction (D1). Each of the bitlines (BL) may include a first cell ohmic pattern (331b) and a cell metal-containing pattern (330b) stacked in sequence. The first cell ohmic pattern (331b) and the cell metal-containing pattern (330b) may each include the same material as the first peripheral ohmic pattern (331a) and the peripheral metal-containing pattern (330a).

[0071] Cell polysilicon patterns (310b) may be interposed between the bit lines (BL) and the buffer pattern (306). The cell polysilicon patterns (310b) may contain the same material as the surrounding polysilicon pattern (310a).

[0072] Bitline contacts (DC) may be interposed between the bitlines (BL) and the second impurity regions (112), respectively. The bitlines (BL) may be electrically connected to the second impurity regions (112) by the bitline contacts (DC). The bitline contacts (DC) may comprise polysilicon that is doped with or undoped with impurities.

[0073] The bitline contacts (DC) may be placed within a third recess region (RE3). The third recess region (RE3) may be provided above the second impurity regions (112) and above the adjacent second device isolation pattern (STI2). The first buried insulation pattern (314) and the second buried insulation pattern (315) may fill the remainder within the third recess region (RE3).

[0074] A cell capping pattern (350) may extend in the second direction (D2) on each of the bit lines (BL). The cell capping pattern (350) may include a first cell capping pattern (351b), a second cell capping pattern (352b), and a third cell capping pattern (353b) that are stacked in sequence and extend in the second direction (D2). The first to third cell capping patterns (351b, 352b, 353b) may each include the same material as the first to third peripheral capping patterns (351a, 352a, 353a).

[0075] Each side of the cell polysilicon patterns (310b), each upper side of the bitline contacts (DC), each side of the bitlines (BL), and the side of the capping pattern (350) may be covered by a bitline spacer (SP). The bitline spacer (SP) may extend along the second direction (D2) on each of the bitlines (BL).

[0076] The bitline spacer (SP) may include a first sub-spacer (321) and a second sub-spacer (325) spaced apart from each other. For example, the first sub-spacer (321) and the second sub-spacer (325) may be spaced apart by an air gap (AG). The first sub-spacer (321) may be in contact with each side of the bitlines (BL) and may extend along the side of the capping pattern (350). The second sub-spacer (325) may be provided along the side of the first sub-spacer (321). The first and second sub-spacers (321, 325) may include silicon nitride.

[0077] The upper spacer (360) may cover the side of the first sub-spacer (321) and may extend to the upper surface of the second sub-spacer (325). The upper spacer (360) may further cover the air gap (AG).

[0078] Storage node contacts (BC) may be interposed between adjacent bit lines (BL) among the bit lines (BL). The storage node contacts (BC) may be spaced apart from each other in the first direction (D1) and the second direction (D2). The storage node contacts (BC) may comprise polysilicon that is doped with impurities or not doped.

[0079] A second cell ohmic pattern (341b) may be placed on each of the storage node contacts (BC). A cell diffusion prevention pattern (342b) may conformally cover the second cell ohmic pattern (341b), the bitline spacer (SP), and the cell capping pattern (350). The cell diffusion prevention pattern (342b) may contain the same material as the surrounding diffusion prevention pattern (342a). The second cell ohmic pattern (341b) may be interposed between the cell diffusion prevention pattern (342b) and each of the storage node contacts (BC).

[0080] Landing pads (LP) may be placed on the storage node contacts (BC) respectively. The landing pads (LP) may be spaced apart from each other in the first direction (D1) and the second direction (D2). The landing pads (LP) may include a metal-containing material such as tungsten.

[0081] A cell filling pattern (400b) may wrap around each of the landing pads (LP). The cell filling pattern (400b) may be interposed between adjacent landing pads (LP). The cell filling pattern (400b) may contain the same material as the surrounding filling pattern (400a).

[0082] Lower electrodes (BE) may each be disposed on the landing pads (LP). The lower electrodes (BE) may comprise at least one of impurity-doped polysilicon, a metal nitride such as titanium nitride, and a metal film such as tungsten, aluminum, and copper. Each of the lower electrodes (BE) may have a cylindrical shape, a hollow cylinder, or a cup shape. An upper support pattern (SS1) may support the upper sidewalls of the lower electrodes (BE), and a lower support pattern (SS2) may support the lower sidewalls of the lower electrodes (BE). The upper and lower support patterns (SS1, SS2) may comprise an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0083] A cell etch-stopping pattern (420b) may be provided on the cell filling pattern (400b) between the lower electrodes (BE). A dielectric film (DL) may cover the surface of the lower electrodes (BE) and the surface of the upper and lower support patterns (SS1, SS2). The dielectric film (DL) may comprise, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric film (for example, hafnium oxide). An upper electrode (TE) may be placed on the dielectric film (DL) and may fill the space between the lower electrodes (BE). The upper electrode (TE) may comprise at least one of an impurity-doped polysilicon film, an impurity-doped silicon germanium film, a metal nitride such as titanium nitride, and a metal film such as tungsten, aluminum, and copper. The lower electrodes (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA).

[0085] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art. Explanation of the symbols

[0086] AP: Active pattern STI: Device isolation pattern EG1, EG2: 1st and 2nd corners SM: Seam 10: Substrate 12, 14: Lower and upper mask films 13, 15: Lower and upper mask patterns

Claims

Claim 1 A semiconductor device comprising: a substrate including a peripheral region including peripheral circuits and a cell region including a memory integrated circuit; a first active pattern on the peripheral region; a second active pattern on the cell region; and a device isolation pattern between the first active pattern and an adjacent first active pattern on the peripheral region, wherein a first corner on the upper part of the first active pattern and a second corner on the upper part of the second active pattern have a rounded shape, the curvature of the first corner is greater than the curvature of the second corner, and on the peripheral region, the uppermost surface of the device isolation pattern is located at a lower height than the uppermost surface of the first active pattern. Claim 2 A semiconductor device according to claim 1, wherein the angle formed by the upper surface of the substrate and the side of the first active pattern at the bottom of the first active pattern is greater than 90 degrees. Claim 3 In claim 1, the device isolation pattern is a semiconductor device including a seam inside. Claim 4 In claim 3, the upper portion of the seam is a semiconductor device located at a height lower than the upper surface of the device isolation pattern. Claim 5 delete Claim 6 A semiconductor device according to claim 1, further comprising a gate dielectric pattern extending along the uppermost surface of the first active pattern and the uppermost surface of the device isolation pattern, wherein the bottom surface of the gate dielectric pattern has a rounded shape along the profile of the first corner of the upper part of the first active pattern. Claim 7 A semiconductor device comprising: a substrate including a cell region including a memory integrated circuit and a peripheral region including peripheral circuits; an active pattern protruding from the substrate on the peripheral region; a device isolation pattern between the active pattern and an adjacent active pattern; and a gate dielectric pattern extending along the upper surface of the active pattern and the upper surface of the device isolation pattern, wherein the upper corner of the active pattern has a rounded shape, and on the peripheral region, the uppermost surface of the device isolation pattern is located at a height lower than the uppermost surface of the active pattern, and the bottom surface of the gate dielectric pattern has a rounded shape along the profile of the upper corner of the active pattern. Claim 8 A method for manufacturing a semiconductor device comprising: sequentially forming a lower mask film and an upper mask film on a substrate including a peripheral region and a cell region; forming a first mask pattern on the peripheral region and a second mask pattern on the cell region on the upper mask film; removing a portion of the upper mask film exposed by the second mask pattern on the cell region; removing the first mask pattern on the peripheral region after the portion of the upper mask film is removed; and using the second mask pattern as an etching mask to etch the remainder of the upper mask film on the cell region and the peripheral region to form an upper mask pattern, wherein the upper mask pattern covers the lower mask film on the peripheral region and exposes a portion of the lower mask film on the cell region. Claim 9 A method for manufacturing a semiconductor device according to claim 8, further comprising: forming a third mask pattern on the upper mask pattern; etching the upper mask pattern using the third mask pattern as an etching mask to form a fourth mask pattern; and etching the lower mask film and the upper surface of the substrate using the fourth mask pattern as an etching mask to form a lower mask pattern and an active pattern, wherein the height of the upper surface of the fourth mask pattern on the peripheral region is located at a height substantially equal to or lower than the height of the upper surface of the fourth mask pattern on the cell region. Claim 10 A method for manufacturing a semiconductor device according to claim 9, wherein the height of the upper surface of the lower mask pattern on the surrounding region is located at a height substantially equal to or lower than the height of the upper surface of the lower mask pattern on the cell region.

Images