Method for semiconductor etching in micro LED fabrication

Abstract

The present invention relates to a semiconductor etching method for manufacturing a micro LED, comprising: a film deposition step of forming a mask layer on a semiconductor layer grown on a substrate; The present invention comprises an etching step of etching the semiconductor layer in a vertical direction using the deposited mask layer, wherein the mask layer comprises a hard mask layer, and the deposition step comprises a first deposition step of depositing a first hard mask layer on the semiconductor layer, a second deposition step of depositing a second hard mask layer on the first hard mask layer, and a third deposition step of depositing a third hard mask layer on the second hard mask layer, wherein the thickness of the second hard mask layer is formed to be thinner than the first hard mask layer and the third hard mask layer, and the thickness of the third hard mask layer is formed to be thinner than the first hard mask layer, but is formed having a flat upper surface so as not to cause over-etching. According to the present invention, by etching the semiconductor layer using a hard mask, problems such as sidewall damage and over-etching occurring in an etching process for manufacturing a micro LED of size of 10㎛ or less having a wavelength of 630 nm or more can be effectively improved, and the selectivity can be significantly improved. It is possible.

Description

Technology Field

[0001] The present invention relates to a semiconductor etching method for manufacturing micro LEDs, and more specifically, to a semiconductor etching method for manufacturing micro LEDs that etches a semiconductor layer using a hard mask. Background Technology

[0002] Micro-LED is attracting attention as a next-generation display technology that offers advantages such as ultra-high definition, high brightness, low power consumption, and a long lifespan. In particular, compared to conventional OLEDs (organic light-emitting diodes) and LCDs (liquid crystal displays), it offers high energy efficiency and a wider color gamut, making it a subject of interest in various application fields such as smartphones, TVs, wearable devices, augmented reality (AR), and virtual reality (VR).

[0003] As the size of these micro LEDs shrinks to the order of a few micrometers, the precision of chip manufacturing and etching processes is often insufficient with existing technologies. Specifically, conventional etching techniques make it difficult to maintain uniformity between the upper and lower structures during the process, which can consequently lead to degradation of device performance and weakened stability.

[0004] These problems are particularly pronounced in the manufacturing process of ultra-fine micro LEDs of 10㎛ or less, where sidewall damage during the etching process has a fatal impact, such as deterioration of the device's electrical characteristics, reduced luminous efficiency, and shortened lifespan. In particular, such damage increases current leakage and impairs the quality of the active layer, which not only reduces the reliability of the device but also poses a risk of significantly lowering the yield of the manufacturing process.

[0005] Accordingly, there is a need for a solution to overcome the limitations of existing etching processes and to manufacture high-quality micro LEDs. Prior art literature

[0006] Republic of Korea Registered Patent No. 10-0838394 The problem to be solved

[0007] The objective of the present invention is to provide a semiconductor etching method for manufacturing micro LEDs using a hard mask to etch a semiconductor layer, so as to solve the aforementioned conventional problems and to improve problems such as sidewall damage and over-etching that occur during an etching process for manufacturing micro LEDs with a size of 10 μm or less and a wavelength of 630 nm or more. means of solving the problem

[0008] The above objective is achieved, according to the present invention, by a film formation step of forming a mask layer on a semiconductor layer grown on a substrate; The semiconductor etching method for manufacturing a micro LED comprises an etching step of etching the semiconductor layer in a vertical direction using the deposited mask layer, wherein the mask layer comprises a hard mask layer, and the deposition step comprises a first deposition step of depositing a first hard mask layer on the semiconductor layer, a second deposition step of depositing a second hard mask layer on the first hard mask layer, and a third deposition step of depositing a third hard mask layer on the second hard mask layer, wherein the thickness of the second hard mask layer is formed to be thinner than the first hard mask layer and the third hard mask layer, and the thickness of the third hard mask layer is formed to be thinner than the first hard mask layer, but is formed to have a flat upper surface so as not to cause over-etching. Additionally, the deposition step may further include a fourth deposition step of depositing a PR (photoresist) mask layer of a preset pattern on the third hard mask layer. Additionally, the first hard mask layer and the third The hard mask layer is SiOx or SiN x It is formed as such, and the second hard mask layer can be formed of Cr.

[0009] delete

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[0012] delete Effects of the invention

[0013] According to the present invention, by etching a semiconductor layer using a hard mask, problems such as sidewall damage and over-etching that occur in the etching process for manufacturing micro LEDs with a size of 10 μm or less and a wavelength of 630 nm or more can be effectively improved, and the selectivity can be significantly improved.

[0014] Meanwhile, the effects of the present invention are not limited to those mentioned above, and various effects may be included within the scope obvious to a person skilled in the art from the contents described below. Brief explanation of the drawing

[0015] FIG. 1 is a flowchart of a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention, and FIG. 2 illustrates detailed steps of the film deposition step of a semiconductor etching method for manufacturing a micro LED according to one embodiment of the present invention, and FIG. 3 illustrates the etching process of a semiconductor layer according to a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention, and FIG. 4 illustrates in detail a semiconductor layer of a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention, and FIG. 5 illustrates the etching results when a conventional mask layer is introduced and when the hard mask layer of the present invention is introduced, respectively. FIG. 6 illustrates the etching results when Cr, Al, or Ni is introduced as the material of the second hard mask layer of the present invention, respectively. Figure 7 illustrates experimental results showing normal etching and over-etching occurring according to the thickness of the first hard mask layer of the present invention. Specific details for implementing the invention

[0016] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings.

[0017] In addition, when describing embodiments of the present invention, if it is determined that a detailed description of related known configurations or functions would hinder understanding of the embodiments of the present invention, such detailed description is omitted.

[0018] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by such terms.

[0020] Now, with reference to the attached drawings, a semiconductor etching method (S100) for manufacturing a micro LED according to one embodiment of the present invention will be described in detail.

[0021] FIG. 1 is a flowchart of a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention, FIG. 2 illustrates a detailed step of a film deposition step (S120) of a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention, FIG. 3 illustrates an etching process of a semiconductor layer (120) according to a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention, and FIG. 4 illustrates in detail a semiconductor layer (120) of a semiconductor etching method for manufacturing a micro LED according to an embodiment of the present invention.

[0022] As illustrated in FIGS. 1 to 4, a semiconductor etching method (S100) for manufacturing a micro LED according to one embodiment of the present invention includes a preparation step (S110), a film deposition step (S120), and an etching step (S130).

[0023] The preparation step (S110) is a step of preparing a substrate (110) on which a semiconductor layer (120) has been grown on the upper surface.

[0024] In the present invention, the semiconductor layer (120) refers to an epi-layer, epitaxial layer, or epitaxial stack including an n-type semiconductor region, an active layer, and a p-type semiconductor region, and such a semiconductor layer (120) can be prepared by epitaxial growth through a metal organic chemical vapor deposition (MOCVD) device or the like on a GaAs substrate (110).

[0025] Furthermore, after the semiconductor layer (120) of the present invention is epitaxially grown, a transparent electrode layer (E) may be deposited on top, and in addition, various layers required in the micro LED manufacturing process may be additionally included.

[0026] The semiconductor layer (120) is capable of emitting light having a wavelength of 630 nm or more, and specifically includes a template layer, an n-type contact layer, an n-type engineering layer, an n-type clad layer, an active layer, a p-type clad layer, a TSBR layer, a window layer, and a p-type contact layer, and a transparent electrode layer (E) is formed on the upper surface of the semiconductor layer (120).

[0027] A template layer is grown on the substrate (110) as a base layer to alleviate irregularities on the surface of the GaAs substrate (110) and to improve the quality of the upper epitaxial growth, thereby reducing the defect density between the substrate (110) and the epitaxial layer. This template layer can be grown with the same GaAs material as the substrate (110) and can be doped as n-type using Si (silicon), etc. as a dopant.

[0028] The n-contact layer is a layer connected to the cathode to transmit current, optimizes electron transport to the active layer, and is grown on a template layer. This n-contact layer can be grown with GaInP material and can be doped to n-type using Si or the like as a dopant.

[0029] An n-engineering layer is a layer that enables uniform luminescence by controlling electrical properties to optimize the electron movement path and improving current diffusion, and is grown on an n-type contact layer. This n-engineering layer can be grown from AlGaInP material and can be doped into n-type using Si or the like as a dopant.

[0030] The n-clad layer is a layer that transfers electrons to the active layer. It has a high bandgap and serves to confine electrons and holes so that they can recombine in the active layer, and it is grown on an n-clad engineering layer. This n-clad layer can be grown from AlInP material and can be doped into the n-type using Si or the like as a dopant.

[0031] The active layer is a layer that generates light through the recombination of electrons and holes, and is grown by undoping on an n-type clad layer.

[0032] This active layer includes a quantum well layer and a barrier layer, and the quantum well layer is a layer in which electrons and holes recombine to generate light with a wavelength of 630 nm or more, which can be grown from GaInP material, and the quantum well structure can be formed by repeating it 15 times to maximize luminescence efficiency.

[0033] In addition, the barrier layer is a layer that confines electrons and holes by being located at the top and bottom of the quantum well layer, respectively, to maximize the recombination efficiency of the quantum well layer, and can be grown from AlGaInP material, and the upper barrier layer can be formed by repeating the barrier structure 15 times to prevent leakage of electrons and holes.

[0034] The p-clad layer is a layer that transports holes to the active layer. It has a high bandgap and serves to confine electrons and holes so that they can recombine in the active layer, and it is grown on the active layer. This p-clad layer can be grown from AlInP material and can be doped to p-type using carbon (C) as a dopant.

[0035] A tensile strain barrier reducing layer (TSBR) is a layer grown on a p-type clad layer to increase the stability of the device by reducing interlayer lattice strain (tensile strain). This TSBR layer can be grown from GaInP material and plays a role in reducing the reflection of light emitted from the active layer and improving emission efficiency.

[0036] A window layer is a layer that provides a light emission path and is grown on a TSBR layer. This window layer has high light transmittance and low absorption, and can be grown from GaP material to maximize luminescence efficiency.

[0037] A p-contact layer is a layer that is connected to the anode and transmits current, and is grown on the window layer. This p-contact layer can be grown from GaP material and can be doped to p-type using C or the like as a dopant.

[0038] The transparent electrode layer (E) is an optically transparent and electrically conductive layer that can be deposited through a physical vapor deposition (PVD) such as sputtering. It is preferable that this transparent electrode layer (E) be formed from an indium tin oxide (ITO) material, but it is not limited thereto, and it may be formed from any one material selected from the group consisting of NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, and IGZO.

[0039] Meanwhile, the semiconductor layer (120) of the present invention is not limited to the stacking order described above or to the layers described above, and may include various layers required in the micro LED manufacturing process in addition to these.

[0040] The film formation step (S120) is a step of forming a mask layer (130) for vertical etching on a semiconductor layer (120) and a transparent electrode layer (E) grown on a substrate (110).

[0041] At this time, the mask layer (130) in the membrane stage (S120) includes a hard mask layer (130), and this membrane stage (S120) more specifically includes a first membrane stage (S121), a second membrane stage (S122), a third membrane stage (S123), and a fourth membrane stage (S124).

[0042] The first membrane formation step (S121) is a step of forming a first hard mask layer (131) on a semiconductor layer (120).

[0043] Specifically, in the first film deposition step (S121), a first hard mask layer (131) is deposited to prevent damage to the lower semiconductor layer (120) during vertical etching and to improve the adhesion of the second hard mask layer (132), and this first hard mask layer (131) is silicon oxide (SiO x ) or silicon nitride (SiN x It can be formed by ) and can be deposited through methods such as PECVD (plasma enhanced chemical vapor deposition), sputtering, or ALD (atomic layer deposition), but is not limited thereto.

[0044] When a metal hard mask is directly deposited on a semiconductor layer (120), there is a disadvantage that it is difficult to remove, and there is a problem that the surface of the semiconductor layer (120) may be damaged during the process of removing the metal hard mask. Accordingly, in the present invention, a first hard mask layer (131) is deposited first, and then a second hard mask layer (132) of metal is deposited thereon to protect the surface of the semiconductor layer (120) and improve adhesion. In addition, the first hard mask layer (131) allows the second hard mask layer (132) to be easily removed. For example, when the first hard mask layer (131) is etched and removed, the upper second hard mask layer (132) and the third hard mask layer (133), which will be described later, can also be easily removed together. At this time, the etching method may be chemical wet etching using a strong acid or strong base, dry etching using plasma, etc., but is not limited thereto.

[0045] The second tabernacle step (S122) is the step of tabernacle-forming the second hard mask layer (132) on the first hard mask layer (131).

[0046] Specifically, in the second film deposition step (S122), a second hard mask layer (132) is deposited to have high mechanical strength and corrosion resistance despite its thin thickness, and to serve as a robust protective layer in the vertical etching process. This second hard mask layer (132) serves to enable deeper etching of a certain size during vertical etching of the semiconductor layer (120). The second hard mask layer (132) can be formed of metal, and preferably can be formed of chromium (Cr). Meanwhile, the second hard mask layer (132) can be deposited through methods such as sputtering or electron beam evaporation, but is not limited thereto.

[0047] The third tabernacle step (S123) is the step of tabernacle-forming the third hard mask layer (133) on the second hard mask layer (132).

[0048] Specifically, in the third film formation step (S123), a third hard mask layer (133) is deposited to provide a surface for the stable formation of the PR mask layer (130) formed on the upper side, to protect the lower layer during pattern transfer, and to provide additional chemical and mechanical stability. This third hard mask layer (133) is made of silicon oxide (SiO₂) in the same way as the first hard mask layer (131). x ) or silicon nitride (SiN x It can be formed by ) and can be deposited through methods such as PECVD (plasma enhanced chemical vapor deposition), sputtering, or ALD (atomic layer deposition), but is not limited thereto.

[0049] Meanwhile, in the present invention, the thickness of the third hard mask layer (133) may be formed to be thinner than the first hard mask layer (131) and thicker than the second hard mask layer (132), and when the total thickness of the semiconductor layer (120) is formed to be 3.8㎛ to 4.6㎛, the thickness of the first hard mask layer (131) may be formed to be 0.8㎛ to 1.6㎛, the thickness of the second hard mask layer (132) may be formed to be 0.04㎛ to 0.12㎛, and the thickness of the third hard mask may be formed to be 0.24㎛ to 0.32㎛. For example, when the thickness of the semiconductor layer (120) is 3.9 μm, the thickness of the first hard mask layer (131) can be formed to be 1.2 μm, the thickness of the second hard mask layer (132) to be 0.08 μm, and the thickness of the third hard mask layer (133) to be 0.28 μm.

[0050] Meanwhile, the ratio of the thicknesses of the first hard mask layer (131), the second hard mask layer (132), and the third hard mask layer (133) based on the third hard mask layer (133) can be set to 4.29 : 0.29 : 1. Furthermore, the ratio of the thicknesses of the semiconductor layer (120), the first hard mask layer (131), the second hard mask layer (132), and the third hard mask layer (133) based on the third hard mask layer (133) can be set to 13.93 : 4.29 : 0.29 : 1.

[0051] That is, in the present invention, the thickness of the first hard mask layer (131) can be formed to be the thickest as described above, because the second hard mask layer (132) on the first hard mask layer (131) is a metal layer and has a lower etching ratio compared to the first hard mask layer (131), and because the thickness of the lower first hard mask layer (131) must be formed thickly in order to determine the size and shape of the second hard mask layer (132).

[0052] Specifically, if the thickness of the first hard mask layer (131) is formed to be thicker than the above ratio, the etching time increases, which may slow down the process speed and consequently increase the manufacturing cost. On the other hand, if the thickness of the first hard mask layer (131) is formed to be thinner than the above ratio, there is a higher possibility that the lower semiconductor layer (120) will be damaged by plasma or the like during the etching process, and there is a problem that it may be difficult to maintain uniformity between the upper and lower parts of the semiconductor layer (120) as the first hard mask layer (131) is easily eroded and lost during the etching process.

[0053] Additionally, the thickness of the second hard mask layer (132) can be formed to be as thin as possible according to the above ratio, because if the metal Cr layer is formed thickly, etching becomes difficult and hinders uniform etching of the semiconductor layer (120).

[0054] Specifically, if the thickness of the second hard mask layer (132) is formed thicker than the above ratio, there is a disadvantage that more deposition time is required to deposit the thick Cr layer, and material consumption increases, leading to higher manufacturing costs. Additionally, since the thick Cr layer has high corrosion resistance, the removal time increases, and consequently, there is a problem that it is difficult to maintain uniformity in the etching process. Furthermore, there is a disadvantage that interlayer defects may be caused by differences in the coefficient of thermal expansion in the multilayer structure. On the other hand, if the thickness of the second hard mask layer (132) is formed thinly, falling short of the above ratio, there is a problem that it may be difficult to maintain uniformity between the upper and lower parts of the semiconductor layer (120) as it is rapidly lost during the plasma etching process.

[0055] In addition, the thickness of the third hard mask layer (133) can be formed to be thinner than the first hard mask layer (131) and thicker than the second hard mask layer (132) as in the above ratio, because a flat surface must be formed on the upper surface of the third hard mask layer (133) during the initial etching so that etching can be performed normally without over-etching.

[0056] Specifically, if the thickness of the third hard mask layer (133) is formed thicker than the above ratio, there is a problem in that the upper surface of the third hard mask layer (133) cannot be formed flatly due to the accumulation of thickness non-uniformity during the deposition process. Accordingly, in anisotropic etching where etching proceeds only in a specific direction, if the upper surface is not flat, the difference in height of the upper surface distorts the plasma density or the distribution of the reaction gas, causing the etching direction to change abnormally, and consequently, over-etching occurs. On the other hand, if the thickness of the third hard mask layer (133) is formed thinly, falling short of the above ratio, the non-uniformity occurring in the initial stage of the deposition process is directly reflected on the surface, which may result in the upper surface not being formed flatly, and there is a problem in that the flatness may be reduced due to easy damage during the pattern transfer of the subsequent PR mask layer (130). Furthermore, there is a problem in that the thin third hard mask layer (133) is likely to be consumed quickly during the etching process, causing the lower second hard mask layer (132) to be exposed early, which can lead to damage to the lower first mask layer (130) or semiconductor layer (120).

[0057] The fourth film deposition step (S124) is a process of forming an etching pattern through a photolithography process, and is a step of forming a PR (photoresist) mask layer (134) of a pre-set pattern on the third hard mask layer (133).

[0058] Specifically, in the fourth film formation step (S124), a uniform PR mask layer (134) is formed on the third hard mask layer (133) through spin coating, etc., and then a preset etching pattern is formed using UV lithography, etc., and then unnecessary parts can be removed using a developer. At this time, a positive PR or negative PR solution may be used as the PR solution.

[0059] The etching step (S130) is a step of etching the semiconductor layer (120) in a vertical direction using the deposited mask layer (130).

[0060] Specifically, in the etching step (S130), the semiconductor layer (120) is etched in a vertical direction up to approximately a part of the n-type contact layer using an anisotropic etching method such as plasma etching. At this time, in order to prevent over-etching during the etching step (S130), the etching is performed so that the third hard mask layer (133) maintains a flat upper surface during the initial etching.

[0061] Meanwhile, after the etching is completed, the hard mask layer (130) can be removed using chemical wet etching with a strong acid or strong base, or dry etching with plasma, as described above. For example, the first hard mask layer (131) or the third hard mask layer (133) can be removed using an HF (hydrofluoric acid) solution, and in the present invention, the second hard mask layer (132) formed of Cr can be removed together as the first hard mask layer (131) is removed, and the PR mask layer (130) can also be removed together as the first hard mask layer (131) or the third hard mask layer (133) is removed. Furthermore, a part of the first hard mask layer (131) may function as a passivation layer.

[0062] According to the semiconductor etching method for manufacturing a micro LED of the present invention, which includes the preparation step (S110), the film formation step (S120), and the etching step (S130) as described above, by etching the semiconductor layer (120) using a hard mask, problems such as sidewall damage and over-etching that occur in the etching process for manufacturing a micro LED of 10 μm or less with a wavelength of 630 nm or more can be effectively improved, and the selectivity ratio can be significantly improved.

[0064] The present invention will be explained in more detail below through specific experiments. However, the following experimental examples are intended only to explain the present invention, and the content of the present invention is not limited to the following experimental examples.

[0066] Experimental Example 1 - Hard Mask Layer Introduction Experiment

[0067] FIG. 5 illustrates the etching results when a conventional mask layer (130) is introduced and when the hard mask layer (130) of the present invention is introduced, respectively. The experimental conditions are as shown in Table 1 below, the experimental results are as shown in Table 2 below, and other conditions were set identically.

[0069] Conventional mask layer (130) application Application of the hard mask layer (130) of the present invention Mask layer (130) material SiO2 First mask layer (130): SiO2 Second mask layer (130): Cr Third mask layer (130): SiO2 Mask layer (130) thickness (㎛) 1.2 First mask layer (130): 1.2 Second mask layer (130): 0.08 Third mask layer (130): 0.28

[0071] Conventional mask layer (130) application Application of the hard mask layer (130) of the present invention Upper width (㎛) of the semiconductor layer (120) 1.033 1.033 Semiconductor layer (120) intermediate width (㎛) 1.186 1.132 Lower width (㎛) of the semiconductor layer (120) 1.725 1.348

[0073] As shown in Table 2 and Figure 5 above, when the hard mask layer (130) of the present invention is applied compared to the conventional mask layer (130), it was confirmed that the uniformity of the upper and lower parts of the semiconductor layer (120) is greatly increased.

[0075] Experimental Example 2 - Experiment on the second hard mask layer material

[0076] FIG. 6 illustrates the etching results when Cr, Al, or Ni is introduced as the material of the second hard mask layer (132) of the present invention.

[0077] As shown in FIG. 6, when Al or Ni was introduced as the material of the second hard mask layer (132), it was confirmed that the etching of the semiconductor layer (120) was not performed normally and that separation by die unit was not performed properly.

[0078] Specifically, when Al was introduced as the material of the second hard mask layer (132), Al redeposition and poly phenomena occurred on the wafer surface during etching after PR removal, causing contamination on the wafer surface and confirming that the etched shape was inappropriate. In addition, when Ni was introduced as the material of the second hard mask layer (132), the etching selectivity ratio between Ni and the first hard mask layer (131) did not match, and likewise, confirming that the etched shape was inappropriate.

[0079] Meanwhile, when Cr was introduced as the material of the second hard mask layer (132), it was confirmed that the etching of the semiconductor layer (120) was performed normally and separated well into die units.

[0081] Experimental Example 3 - Over-etching Induction Experiment

[0082] FIG. 7 illustrates experimental results showing normal etching and over-etching occurring depending on the thickness of the first hard mask layer (131) of the present invention.

[0083] FIG. 7(a) and FIG. 7(b) show that the thickness of the first hard mask layer (131) is 1.2 μm, the thickness of the second hard mask layer (132) is 0.08 μm, and the thickness of the third hard mask layer (133) is 0.28 μm, respectively, and etching is performed. In FIG. 7(a), it can be seen that the upper surface of the third hard mask layer (133) is easily flattened during the initial etching, and accordingly, it can be seen that etching is performed normally without over-etching as in FIG. 7(b).

[0084] Meanwhile, Fig. 7 (c) shows that the thickness of the first hard mask layer (131) and the second hard mask layer (132) are maintained at the same level, while the thickness of the third hard mask layer (133) is formed to be 0.5 μm thick. As the upper surface is not flat due to the thick third hard mask layer (133), it was confirmed that over-etching occurred after the etching process.

[0086] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate.

[0087] Furthermore, terms such as "include," "compose," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; therefore, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0088] Furthermore, the above description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention.

[0089] Accordingly, the embodiments disclosed in this invention are intended to illustrate, not limit, the technical concept of the invention, and the scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of this invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of this invention. Explanation of the symbols

[0090] S100: Semiconductor etching method for micro LED manufacturing S110: Preparation stage S120: Tabernacle Stage S121: The First Tabernacle Stage S122: The Second Tabernacle Stage S123: The Third Tabernacle Stage S124: The Fourth Tabernacle Stage S130: Etching step 110 : Substrate 120 : Semiconductor layer E : Transparent electrode layer 130 : Mask layer 131 : First hard mask layer 132 : Second hard mask layer 133 : Third hard mask layer 134 : PR mask layer

Claims

Claim 1 A semiconductor etching method for manufacturing a micro LED, comprising: a deposition step of depositing a mask layer on a semiconductor layer grown on a substrate; and an etching step of etching the semiconductor layer in a vertical direction using the deposited mask layer, wherein the mask layer comprises a hard mask layer, and the deposition step comprises a first deposition step of depositing a first hard mask layer on the semiconductor layer, a second deposition step of depositing a second hard mask layer on the first hard mask layer, and a third deposition step of depositing a third hard mask layer on the second hard mask layer, wherein the thickness of the second hard mask layer is formed to be thinner than the first hard mask layer and the third hard mask layer, and the thickness of the third hard mask layer is formed to be thinner than the first hard mask layer, but has a flat upper surface so as not to cause over-etching. Claim 2 delete Claim 3 A semiconductor etching method for manufacturing a micro LED according to claim 1, wherein the film deposition step further comprises a fourth film deposition step of depositing a PR (photoresist) mask layer having a preset pattern on the third hard mask layer. Claim 4 In claim 3, the first hard mask layer and the third hard mask layer are SiO x or SiN x A semiconductor etching method for manufacturing a micro LED, wherein the second hard mask layer is formed of Cr. Claim 5 delete

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