Thin film transistor substrate and display apparatus comprising the same

Abstract

One embodiment of the present invention provides a thin film transistor comprising: an oxide semiconductor layer on a substrate; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer that overlaps at least partially with the oxide semiconductor layer; a separation insulating layer on the gate electrode; a source electrode and a drain electrode on the separation insulating layer; the oxide semiconductor layer comprises a channel portion that overlaps with the gate electrode and a connection portion that does not overlap at least partially with the gate electrode, and the source electrode and the drain electrode are in contact with the connection portion of the oxide semiconductor layer; the separation insulating layer is in contact with the connection portion of the oxide semiconductor layer, wherein the hydrogen concentration of the connection portion is higher than the hydrogen concentration of the channel portion, and the separation insulating layer and the source electrode and the drain electrode are in contact with the connection portion together.

Description

Technology Field

[0001] The present invention relates to a thin-film transistor substrate and a display device including the same. Background Technology

[0002] Since thin film transistors can be manufactured on glass or plastic substrates, they are widely used as switching or driving elements in display devices such as liquid crystal display devices or organic light-emitting devices.

[0003] Thin film transistors can be classified based on the material constituting the active layer into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which oxide semiconductor is used as the active layer.

[0004] Since amorphous silicon can be deposited to form an active layer in a short time, amorphous silicon thin-film transistors (a-Si TFTs) have the advantages of short manufacturing process times and low production costs. On the other hand, amorphous silicon thin-film transistors have the disadvantage of limited use in applications such as active matrix organic light-emitting diodes (AMOLEDs) due to their low mobility resulting in poor current driving capability and the occurrence of threshold voltage fluctuations.

[0005] Polycrystalline silicon thin-film transistors (poly-Si TFTs) are fabricated by crystallizing amorphous silicon after it has been deposited. Since the manufacturing process requires a crystallization step, the number of process steps increases, leading to higher manufacturing costs. Furthermore, because the crystallization process is performed at high temperatures, polycrystalline silicon TFTs face difficulties in being applied to large-area devices. Additionally, due to their polycrystalline nature, it is challenging to ensure the uniformity of polycrystalline silicon TFTs.

[0006] Oxide semiconductor thin-film transistors (Oxide TFTs) have recently attracted significant attention for their applications as thin-film transistors because they can achieve high mobility even when the oxide semiconductor layer is deposited at low temperatures, and they exhibit a large variation in resistance depending on oxygen content, making it very easy to obtain desired properties. In particular, examples of oxide semiconductors that can be used for the active layer include zinc oxide (ZnO), indium zinc oxide (InZnO), or indium gallium zinc oxide (InGaZnO4). While thin-film transistors containing an oxide semiconductor active layer can be constructed in various structures, coplanar or back-channel etch (BCE) structures are frequently used due to their device characteristics.

[0007] However, the oxide semiconductor layer may be damaged during the patterning process, including etching and heat treatment, in the manufacturing process of oxide semiconductor thin-film transistors, which can reduce the driving stability and reliability of the thin-film transistors. The problem to be solved

[0008] The present invention aims to provide a thin-film transistor comprising an oxide semiconductor layer having a hydrogen-containing insulating layer as a connecting portion.

[0009] The present invention aims to provide a thin-film transistor and a method for manufacturing the same, wherein the operating characteristics are improved and the degradation of reliability is prevented by including a connection portion that is conductive through hydrogen diffusion from a connection portion of an insulating layer containing hydrogen.

[0010] The present invention aims to provide a thin-film transistor and a method for manufacturing the same, wherein insulation failure between a gate electrode and an oxide semiconductor layer is prevented by including an insulating layer that covers the entire surface of a gate electrode. means of solving the problem

[0011] One embodiment of the present invention for achieving the above-mentioned objective provides a thin film transistor comprising: an oxide semiconductor layer on a substrate; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer that overlaps at least partially with the oxide semiconductor layer; a separation insulating layer on the gate electrode; a source electrode and a drain electrode on the separation insulating layer; the oxide semiconductor layer comprises a channel portion that overlaps with the gate electrode and a connection portion that does not overlap at least partially with the gate electrode; a source electrode and a drain electrode in contact with the connection portion of the oxide semiconductor layer; a separation insulating layer in contact with the connection portion of the oxide semiconductor layer; the hydrogen concentration of the connection portion is higher than the hydrogen concentration of the channel portion; and the separation insulating layer and the source electrode and the drain electrode are in contact with the connection portion together.

[0012] The gate insulating layer is placed on the entire surface of the oxide semiconductor layer opposite the substrate.

[0013] The separation insulating layer contains more hydrogen than the gate insulating layer.

[0014] The connection portion simultaneously includes a surface in contact with the separated insulating layer and a surface in contact with the source electrode and the drain electrode.

[0015] The isolation insulation layer may consist of a single or double or more layers.

[0016] The gate insulating layer and the separation insulating layer cover the entire surface of the gate electrode.

[0017] Another embodiment of the present invention provides a method for manufacturing a thin-film transistor, comprising the steps of: forming an oxide semiconductor layer on a substrate; forming a gate insulating layer on the oxide semiconductor layer; forming a gate electrode on the gate insulating layer that overlaps at least partially with the oxide semiconductor layer; forming a first separating insulating layer on the gate electrode; forming a second separating insulating layer on the first separating insulating layer connected to the oxide semiconductor layer; diffusion of hydrogen (H) atoms from the second separating insulating layer into the oxide semiconductor layer; and forming a source electrode and a drain electrode on the second separating insulating layer connected to the oxide semiconductor.

[0018] The gate insulating layer is formed on the entire surface of the oxide semiconductor layer.

[0019] The step of forming a second separating insulating layer includes the step of depositing the second separating insulating layer on the entire surface of the first separating insulating layer, the step of heat treating (annealing) the second separating insulating layer, and the step of forming a contact hole.

[0020] In the heat treatment step of the second separation insulating layer, a connection portion of the oxide semiconductor layer is formed by hydrogen (H) diffusion in the oxide semiconductor layer, and the connection portion is doped to have a higher carrier density than the region excluding the connection portion.

[0021] The first isolation insulating layer is formed to cover at least two sides of the gate. Effects of the invention

[0022] The present invention can improve the operating characteristics of a thin-film transistor and prevent a decrease in reliability by configuring an insulating layer containing hydrogen in an oxide semiconductor layer as a connection part and making it conductive therefrom.

[0023] In addition, the present invention can prevent insulation failure between the gate electrode and the oxide semiconductor layer in a thin-film transistor as the insulating layer covers the entire surface of the gate electrode.

[0024] In addition, the present invention can provide a display device having excellent reliability and driving stability by including a thin-film transistor as described above.

[0025] In addition to the effects mentioned above, other features and advantages of the present invention are described below. Through such description and explanation, the features and effects of the present invention will be clearly understood by those skilled in the art to which the present invention pertains. Brief explanation of the drawing

[0026] FIG. 1 is a cross-sectional view showing a thin-film transistor according to one embodiment of the present invention. Figure 2 is a flowchart illustrating a method for manufacturing a thin-film transistor shown in Figure 1. FIGS. 3a to 3f are cross-sectional views illustrating a method for manufacturing a thin-film transistor shown in FIG. 1. Specific details for implementing the invention

[0027] The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of the present invention is complete and to inform those skilled in the art of the scope of the invention. The present invention is defined only by the scope of the claims.

[0028] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, identical components may be referred to by the same reference numerals. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0029] Where terms such as “comprising,” “having,” or “consisting of” are used in this specification, other parts may be added unless the expression “only” is used. Where a component is expressed in the singular, it includes the plural unless specifically stated otherwise.

[0030] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0031] For example, when the positional relationship between two parts is described using expressions such as “on,” “upper,” “lower,” or “next to,” one or more other parts may be located between the two parts unless expressions such as “immediately” or “directly” are used.

[0032] Spatially relative terms such as “below” or “beneath,” “lower,” “above,” and “upper” may be used to facilitate the description of the relationship between one element or component and another, as illustrated in the drawings. Spatially relative terms should be understood as terms that include different orientations of the element during use or operation, in addition to the orientations illustrated in the drawings. For example, if an element illustrated in the drawings is flipped, an element described as being “below” or “beneath” of another element may be placed “above” of that other element. Therefore, the exemplary term “below” may include both the lower and upper directions. Similarly, the exemplary terms “above” or “upper” may include both the upper and lower directions.

[0033] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using expressions such as “after,” “following,” “next to,” or “before,” it may include cases where the sequence is not continuous unless expressions such as “immediately” or “directly” are used.

[0034] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0035] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0036] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0037] In assigning reference numerals to the components of each drawing describing an embodiment of the present invention, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings.

[0038] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished merely for convenience of explanation, and the source electrode and the drain electrode may be interchangeable. The source electrode may become the drain electrode, and the drain electrode may become the source electrode. Furthermore, the source electrode of one embodiment may become the drain electrode in another embodiment, and the drain electrode of one embodiment may become the source electrode in another embodiment.

[0039] In some embodiments of the present invention, for convenience of explanation, the source region and the source electrode are distinguished and the drain region and the drain electrode are distinguished, but the embodiments of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Additionally, the source region may be the drain electrode, and the drain region may be the source electrode.

[0040] FIG. 1 is a cross-sectional view showing a thin-film transistor according to one embodiment of the present invention.

[0041] The thin-film transistor illustrated in FIG. 1 includes a substrate (100), an active layer (110), a gate insulating layer (120), a gate electrode (130), a first interlayer insulating layer (140), a second interlayer insulating layer (150), a source electrode (160), and a drain electrode (170).

[0042] The substrate (100) may include at least one of glass and a polymer resin. For example, a glass substrate or a polymer resin substrate may be used as the substrate (100). As a polymer resin substrate, there is a plastic substrate. The plastic substrate may include at least one of polyimide (PI), polycarbonate (PC), polyethylene (PE), polyester, polyethylene terephthalate (PET), and polystyrene (PS), which are transparent polymer resins having flexible properties.

[0043] The active layer (110) is disposed on the substrate (100) and includes an oxide semiconductor material. According to one embodiment of the present invention, the active layer (110) is, for example, an oxide semiconductor layer made of an oxide semiconductor material.

[0044] The active layer (110) may include at least one of the following oxide semiconductor materials: ZO (ZnO)-based, IZO (InZnO)-based, IGZO (InGaZnO)-based, TO (SnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, GO (GaO)-based, IO (InO)-based, and ITZO (InSnZnO). More specifically, the active layer (110) may include at least one of the following oxide semiconductor materials: ZO (ZnO)-based, IZO (InZnO)-based, IGZO (InGaZnO)-based, and TO (SnO)-based.

[0045] The active layer (110) includes a channel portion (110C), a first connection portion (110S), and a second connection portion (110D). The first connection portion (110S) and the second connection portion (110D) may be formed by selectively conductive the active layer (110). The first connection portion (110S) and the second connection portion (110D) are generally positioned on both sides of the channel portion (110C).

[0046] A gate insulating layer (120) is disposed on the active layer (110). The gate insulating layer (120) may include at least one of silicon oxide and silicon nitride. The gate insulating layer (120) may have a single film structure or a multilayer film structure.

[0047] The gate insulating layer (120) comprises an insulating material, for example, at least one of silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium silicate (Hf-SiOx), and zirconium silicate (Zr-SiOx).

[0048] A gate electrode (130) is disposed on a gate insulating layer (120). The gate electrode (130) is spaced apart from the active layer (110) and overlaps at least partially with the active layer (110). The gate electrode (130) overlaps with the channel portion (110C) of the active layer (110).

[0049] The gate electrode (130) may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode (130) may have a multilayer structure comprising at least two conductive films having different physical properties.

[0050] A first interlayer insulating layer (140) is disposed on the gate electrode (130). The first interlayer insulating layer (140) is an insulating layer made of an insulating material. Specifically, the first interlayer insulating layer (140) may be made of an organic material, may be made of an inorganic material, or may be made of a laminate of an organic layer and an inorganic layer.

[0051] A second interlayer insulating layer (150) is disposed on the first interlayer insulating layer (140). The second interlayer insulating layer (150) is connected to the active layer (110) through at least two contact holes formed in the first interlayer insulating layer (140) and the gate insulating layer (120).

[0052] A source electrode (160) and a drain electrode (170) are disposed on the second interlayer insulating layer (150). The source electrode (160) and the drain electrode (170) are spaced apart from each other and are each connected to the active layer (110). The source electrode (160) and the drain electrode (170) are each connected to the active layer (110) through at least two contact holes formed in the second interlayer insulating layer (150).

[0053] The source electrode (160) and the drain electrode (170) may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The source electrode (160) and the drain electrode (170) may each be made of a single layer of metal or an alloy of metal, or may be made of two or more layers.

[0054] FIG. 2 is a flowchart illustrating a method for manufacturing a thin-film transistor according to one embodiment of the present invention.

[0055] FIGS. 3a to 3f are cross-sectional views illustrating a method for manufacturing a thin-film transistor according to one embodiment of the present invention.

[0056] As shown in FIGS. 2 and FIGS. 3a, an active layer (110) is formed on a substrate (100) (step S100).

[0057] Specifically, a metal oxide semiconductor material is deposited on a substrate (100) through processes such as sputtering and metal-organic chemical vapor deposition (MOCVD), and then the metal oxide semiconductor material is patterned through photolithography and etching processes to form an active layer (110).

[0058] As shown in FIGS. 2 and FIGS. 3b, a gate insulating layer (120) and a gate electrode (130) are formed on a substrate (100) on which an active layer (110) is formed (step S200).

[0059] Specifically, a gate insulating material is formed on the active layer (110) by a CVD deposition method, and a gate metal layer is formed thereon by a deposition method such as sputtering. Inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx) are used as the gate insulating material. As the gate metal layer, a metal material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum and neodymium alloy (AlNd), aluminum (Al), chromium (Cr), or an alloy thereof is used as a single layer, or is used in a multilayer structure using these materials. Then, a gate electrode (130) is formed by patterning the gate metal layer through a photolithography process and an etching process.

[0060] As shown in FIGS. 2 and FIGS. 3c, a first interlayer insulating layer (140) having at least two contact holes is formed on a substrate (100) on which a gate electrode (130) is formed (step S300).

[0061] Specifically, a first interlayer insulating layer (140) is formed on a substrate (100) on which a gate electrode (130) is formed by a method such as PECVD. An inorganic insulating material, such as silicon oxide (SiOx), is used as the first interlayer insulating material. Then, a contact hole is formed by patterning the gate insulating layer (120) and the first interlayer insulating layer (140) through a photolithography process and an etching process. Here, the contact hole penetrates the gate insulating layer (120) and the interlayer insulating layer (140) to expose the active layer (110). Additionally, the entire surface of the gate electrode (130) can be covered by the gate insulating layer (120) and the first interlayer insulating layer (140). When the gate insulating layer (120) and the first interlayer insulating layer (140) completely cover the gate electrode (130), insulation failure between the gate electrode (130) and the active layer (110) can be prevented.

[0062] On the other hand, there are cases where the gate insulating layer is patterned and formed in the same way as the gate electrode. In this case, leakage current may occur between the gate electrode and the active layer due to residues or other impurities from the gate electrode forming material, or a short circuit may occur between the gate electrode and the active layer. If such leakage current or short circuit occurs, the thin-film transistor cannot perform its function properly.

[0063] In one embodiment of the present invention, since the gate insulating layer (120) and the first interlayer insulating layer (140) completely cover the gate electrode (130), leakage current or short circuit between the gate electrode (130) and the active layer (110) is prevented, thereby ensuring the reliability of the thin-film transistor. In particular, even if the thickness of the gate insulating layer (120) is reduced, leakage current or short circuit between the gate electrode (130) and the active layer (110) does not occur, so the thin-film transistor can be made thinner and the switching characteristics are improved.

[0064] As shown in FIGS. 2 and 3d, a second interlayer insulating layer (150) is formed on a substrate (100) on which a first interlayer insulating layer (140) is formed, and a heat treatment process is carried out (step S400).

[0065] Specifically, a second interlayer insulating layer (150) is formed on a substrate (100) on which a first interlayer insulating layer (140) is formed by a method such as PECVD. As the second interlayer insulating material, an inorganic insulating material containing hydrogen, such as silicon nitride (SiNx), is used. The second interlayer insulating layer (150) is connected to an active layer (110) through at least two contact holes formed in the gate insulating layer (120) and the first interlayer insulating layer (140).

[0066] The active layer (110) of FIG. 3D will be described in more detail below.

[0067] The active layer (110) includes a channel portion (110C) that overlaps with the gate electrode (130), and first and second connection portions (110S, 110D) in which at least a portion does not overlap with the gate electrode (130). The first and second connection portions (110S, 110D) include a first connection portion (110S) and a second connection portion (110D) that are connected to the second interlayer insulating layer (150).

[0068] The channel portion (110C) is an area that overlaps with the gate electrode (130) of the active layer (110).

[0069] At least a portion of the first and second connecting portions (110S, 110D) does not overlap with the gate electrode (130). The entire first and second connecting portions (110S, 110D) may not overlap with the gate electrode (130), or a portion of the first and second connecting portions (110S, 110D) may overlap with the gate electrode (130).

[0070] The first and second connecting portions (110S, 110D) can be formed by selectively conductive the active layer (110). For conductive purposes, after forming the second interlayer insulating layer (150), a heat treatment process may be performed at a temperature of 370°C or lower, and through the heat treatment process, hydrogen atoms present in the second interlayer insulating layer (150) diffuse into the first and second connecting portions (110S, 110D) of the active layer (110). These first and second connecting portions (110S, 110D) have excellent conductivity and high mobility. Through the first and second connecting portions (110S, 110D), the active layer (110) can make excellent electrical contact with the source electrode (160) and the drain electrode (170). The first and second connecting parts (110S, 110D) are also called "conducting parts".

[0071] The first and second connecting portions (110S, 110D) contain hydrogen (H). For example, the first and second connecting portions (110S, 110D) may be formed by doping a portion of the active layer (110) with hydrogen (H). Here, the doping is due to the diffusion of hydrogen (H) present in the second interlayer insulating layer (150). Accordingly, the hydrogen (H) concentration of the first and second connecting portions (110S, 110D) is higher than the hydrogen concentration of the channel portion (110C).

[0072] When hydrogen is doped into the active layer (110), hydrogen (H) atoms combine with oxygen (O) to form OH, generating free electrons, which increases the carrier density of the active layer (110) and thus increases conductivity. For example, referring to the chemical formula below, if the physical properties of the active layer are IGZO (InGaZnO), hydrogen (H) in the ZnO bond combines with oxygen (O) to form OH and generates free electrons. Also, in the InO3 bond, hydrogen (H) combines with oxygen (O) to form OH and generates free electrons. Therefore, the first and second connecting portions (110S, 110D) doped with hydrogen can become conductive.

[0073]

[0074]

[0075] As shown in FIGS. 2 and FIGS. 3e, at least two contact holes are formed in the second interlayer insulating layer (150) (step S500).

[0076] Specifically, a contact hole is formed by patterning the second interlayer insulating layer (150) on a substrate having the second interlayer insulating layer (150) formed thereon through a photolithography process and an etching process. Here, the contact hole penetrates the second interlayer insulating layer (150) to expose the active layer (110).

[0077] As shown in FIGS. 2 and FIGS. 3f, a source electrode (160) and a drain electrode (170) are formed on the second interlayer insulating layer (150) (step S600).

[0078] Specifically, source and drain metal layers are formed on a second interlayer insulating layer (150) having at least two contact holes by a deposition method such as sputtering. As source and drain metal layers, a metal material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum and neodymium alloy (AlNd), aluminum (Al), chromium (Cr), or an alloy thereof is used as a single layer, or is used in a multilayer structure using these. Then, a source electrode (160) and a drain electrode (170) are formed on the second interlayer insulating layer (150) by patterning the source and drain metal layers through a photolithography process and an etching process.

[0079] The conductive first and second connection portions (110S, 110D) processed in step S400 above can have excellent electrical connection with the source electrode (160) and drain electrode (170) processed in step S600 above. On the other hand, the channel portion (110C) is hardly affected by hydrogen doping (or diffusion) and can maintain excellent semiconductor characteristics.

[0080] As such, according to one embodiment of the present invention, the thin-film transistor has excellent reliability and stable operating characteristics.

[0081] The foregoing description and the attached drawings are merely illustrative of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations, such as combining, separating, substituting, and changing the components, within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0082] 100: Substrate 110: Active layer 120: Gate insulation layer 130: Gate electrode 140: First interlayer insulation layer 150: Second interlayer insulation layer 160: Source electrode 170: Drain electrode

Claims

Claim 1 A thin film transistor comprising: an oxide semiconductor layer on a substrate; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer that overlaps at least partially with the oxide semiconductor layer; a separation insulating layer on the gate electrode; and a source electrode and a drain electrode on the separation insulating layer, wherein the oxide semiconductor layer comprises a channel portion that overlaps with the gate electrode and a connection portion that does not overlap at least partially with the gate electrode, wherein the source electrode and the drain electrode are in contact with the connection portion of the oxide semiconductor layer, the separation insulating layer is in contact with the connection portion of the oxide semiconductor layer, the hydrogen concentration of the connection portion is higher than the hydrogen concentration of the channel portion, the separation insulating layer and the source electrode and the drain electrode are in contact with the connection portion together, and the separation insulating layer comprises a first separation insulating layer disposed on the gate electrode and a second separation insulating layer disposed on the first separation insulating layer, wherein the second separation insulating layer is in direct contact with the connection portion for the conduction of the oxide semiconductor layer and contains more hydrogen than the first separation insulating layer. Claim 2 In claim 1, the thin film transistor, wherein the gate insulating layer is disposed in the remaining area excluding the region that overlaps with a part of the connection portion of the oxide semiconductor layer. Claim 3 A thin film transistor according to claim 1, wherein the gate insulating layer and the first separating insulating layer are made of the same material, and the second separating insulating layer is made of a material different from the gate insulating layer and the first separating insulating layer. Claim 4 A thin-film transistor according to claim 1, wherein the surface of the connection portion contacting the connection portion and the separating insulating layer contacts the source electrode and the drain electrode. Claim 5 delete Claim 6 A thin-film transistor according to claim 1, wherein the gate insulating layer and the separation insulating layer cover the entire surface of the gate electrode Claim 7 A method for manufacturing a thin-film transistor comprising: forming an oxide semiconductor layer on a substrate; forming a gate insulating layer on the oxide semiconductor layer; forming a gate electrode on the gate insulating layer that overlaps at least partially with the oxide semiconductor layer; forming a first isolation insulating layer on the gate electrode; patterning the gate insulating layer and the first isolation insulating layer to have at least two contact holes that expose a portion of the upper surface of the oxide semiconductor layer; forming a second isolation insulating layer on the first isolation insulating layer connected to the oxide semiconductor layer; diffusion of hydrogen (H) atoms from the second isolation insulating layer into the oxide semiconductor layer; patterning the second isolation insulating layer to have contact holes that overlap with the at least two contact holes of the gate insulating layer and the first isolation insulating layer; and forming a source electrode and a drain electrode on the second isolation insulating layer connected to the oxide semiconductor layer; wherein the second isolation insulating layer is in direct contact with a connection portion of the oxide semiconductor layer for conductive formation of the oxide semiconductor layer and contains more hydrogen than the first isolation insulating layer. Claim 8 A method for manufacturing a thin-film transistor, wherein, in claim 7, the step of forming the gate insulating layer is the step of forming the gate insulating layer on the entire surface of the oxide semiconductor layer. Claim 9 A method for manufacturing a thin-film transistor according to claim 7, wherein the step of forming the second separating insulating layer comprises: depositing the second separating insulating layer on the entire surface of the first separating insulating layer; heat treating (annealing) the second separating insulating layer; and forming a contact hole in the second separating insulating layer. Claim 10 A method for manufacturing a thin-film transistor according to claim 9, wherein, in the step of heat-treating the second separating insulating layer, a connection portion of the oxide semiconductor layer is formed by hydrogen (H) diffusion in the oxide semiconductor layer, and the connection portion is doped to have a higher carrier density than the region excluding the connection portion. Claim 11 A method for manufacturing a thin-film transistor according to claim 7, wherein the step of forming the first separating insulating layer is the step of forming the first separating insulating layer such that the first separating insulating layer covers at least two faces of the gate insulating layer. Claim 12 A method for manufacturing a thin-film transistor according to claim 7, wherein the gate insulating layer and the first separating insulating layer are made of the same material, and the second separating insulating layer is made of a material different from the gate insulating layer and the first separating insulating layer.

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