Test Element Group and Semiconductor Device incluindg the same

Abstract

A test device group according to an embodiment of the present invention may include: an active region extending in a first direction on a substrate; gate structures extending in a second direction intersecting the active region on the substrate; a first gate contact plug disposed on the gate structures and in contact with the gate electrode layers of each of the gate structures; source / drain regions disposed on the active region at least on one side of the gate structures; and source / drain contact plugs disposed on each of the source / drain regions and electrically connected to each of the source / drain regions. The first gate contact plug may be spaced apart from the source / drain contact plugs in the second direction and extend in the first direction.

Description

Technology Field

[0001] The present invention relates to a group of test elements and a semiconductor device including the same. Background Technology

[0003] In a process for manufacturing semiconductor devices using semiconductor wafers, a Test Element Group (TEG) for verifying the process may be provided on the wafer. By detecting defects in the Test Element Group, actual chip defects are prevented from passing to the next process, thereby preventing reliability failures in advance and improving yield. Various layout designs for Test Element Groups are being studied to accurately and quickly verify the causes of defects. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a group of test elements for detecting defects such as open or short circuits, and a semiconductor device including the same. means of solving the problem

[0007] A test device group according to exemplary embodiments may include: an active region extending in a first direction on a substrate; gate structures extending in a second direction intersecting the active region on the substrate; a first gate contact plug disposed on the gate structures and in contact with the gate electrode layers of each of the gate structures; source / drain regions disposed on the active region at least on one side of the gate structures; and source / drain contact plugs disposed on each of the source / drain regions and electrically connected to each of the source / drain regions. The first gate contact plug may extend in the first direction spaced apart from the source / drain contact plugs in the second direction.

[0008] A test device group according to exemplary embodiments may include: an active region extending in a first direction on a substrate; gate structures each comprising a first portion extending in a second direction intersecting the active region on the substrate, and a second portion extending in the second direction, spaced apart from the first portion and in the second direction on the substrate and facing the first portion; a source / drain region disposed on the active region between the first portions of adjacent gate structures; a source / drain contact plug disposed on the source / drain region and electrically connected to the source / drain region, and comprising a portion extending in the second direction and disposed between the second portions of adjacent gate structures; and a gate contact plug disposed on the source / drain contact plug and the second portions of the gate structures and in contact with the gate electrode layers of the second portions of each gate structure.

[0009] A semiconductor device according to exemplary embodiments may include an integrated circuit region in which a transistor is disposed; and a dummy region adjacent to the integrated circuit region in which a plurality of test element groups are disposed. Each of the plurality of test element groups may include gate structures extending in a second direction intersecting an active region extending in a first direction on a substrate; and a pad region disposed on the gate structures, in contact with the gate electrode layers of each of the gate structures, and including a gate contact plug extending in the first direction, to which an electrical signal is applied. Effects of the invention

[0011] By forming a detection pad of a test device group for detecting open or short circuits in semiconductor devices at the gate contact plug level, defects in the underlying structure can be accurately detected while reducing the Test Around Time.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a layout diagram illustrating a wafer including a group of test elements according to an exemplary embodiment. FIG. 2 is a layout diagram illustrating a group of test elements according to an exemplary embodiment. FIGS. 3a and FIGS. 3b are cross-sectional views illustrating a group of test elements according to exemplary embodiments. FIG. 4 is a layout diagram illustrating a group of test elements according to exemplary embodiments. FIGS. 5A and FIGS. 5B are cross-sectional views illustrating a group of test elements according to exemplary embodiments. FIG. 6 is a layout diagram illustrating a group of test elements according to exemplary embodiments. FIGS. 7a and FIGS. 7b are cross-sectional views illustrating a group of test elements according to exemplary embodiments. FIG. 8 is a layout diagram illustrating a group of test elements according to exemplary embodiments. FIGS. 9a and FIGS. 9b are cross-sectional views illustrating a group of test elements according to exemplary embodiments. FIG. 10 is a layout diagram illustrating a group of test elements according to exemplary embodiments. FIGS. 11a to 13b are cross-sectional views illustrating the manufacturing process of a test element group according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0016] In the following, terms such as "upper," "middle," and "lower" may be replaced with other terms, such as "first," "second," and "third," to describe the components of the specification. While terms such as "first," "second," and "third" may be used to describe various components, they are not limited by these terms, and "first component" may be named "second component."

[0018] FIG. 1 is a layout diagram illustrating a wafer including a group of test elements according to exemplary embodiments.

[0019] Referring to FIG. 1, a semiconductor device (10) according to exemplary embodiments may include a plurality of chip regions (11) where an integrated circuit chip is formed, and a partition region (12) defined between the plurality of chip regions (11). The plurality of chip regions (11) may be arranged along a plurality of rows and columns on a wafer.

[0021] Each of the plurality of chip regions (11) may include an integrated circuit region and a dummy region.

[0022] Semiconductor devices may be provided in the integrated circuit region, and various circuit elements such as resistors, capacitors, transistors, diodes, etc., may be formed. The semiconductor device may be, for example, a memory cell device. In exemplary examples, the semiconductor device may be a flash memory device, a Phase-Change Random Access Memory (PRAM) device, a Resistive RAM (RRAM) device, a Ferroelectric RAM (FeRAM) device, a Magnetic RAM (MRAM) device, a Dynamic RAM (DRAM) device, a Static RAM (SRAM) device, a Synchronous Dynamic RAM (SDRAM) device, etc., but is not limited thereto. In other embodiments, the semiconductor device may be a logic device.

[0023] Multiple semiconductor processes may be performed to form semiconductor devices in the integrated circuit regions of multiple chip regions (11). If any of the multiple semiconductor processes are not properly performed, defects such as open circuits or short circuits may occur, which can be a major factor in significantly degrading the performance of the semiconductor device. For example, if a contact plug lands with misalignment in the source / drain region, a contact failure may occur between the contact plug and the source / drain region, resulting in an open circuit failure between the contact plug and the source / drain region. Such defects can be a major factor in significantly degrading the performance of the semiconductor chip. Therefore, during the manufacturing of semiconductor devices in the integrated circuit region, detection may be required to determine whether each of the multiple semiconductor processes has been properly performed.

[0024] To determine the suitability of the semiconductor process in the integrated circuit region, a Test Element Group (TEG) (e.g., 100 in FIG. 2) may be provided on a wafer. Multiple Test Element Groups may be placed on the wafer. In an exemplary embodiment, the Test Element Group may be placed in a dummy region where semiconductor elements are not formed. The dummy region may be defined as an area outside the integrated circuit region. In another embodiment, the Test Element Group may be placed in a partitioned region (12), or in both the dummy region and the partitioned region (12). The Test Element Group placed in the dummy region may remain in the final produced chip, whereas the Test Element Group placed in the partitioned region (12) may not remain in the final produced chip.

[0025] A test element group can be formed simultaneously with a semiconductor device in an integrated circuit area. By inspecting the electrical characteristics of the test element group during the manufacturing of the semiconductor device, it is possible to verify whether the semiconductor device has been formed normally. The structure of the test element group (TEG), defect detection methods, etc., will be described in detail in the following figures: Figs. 2, 3a, and 3b.

[0027] The partitioned region (12) may be an area for separating multiple chip regions (11) from one another by a scribing process, for example, a scribe lane. Semiconductor devices formed in the integrated circuit region may not be placed in the partitioned region (12). Considering the efficiency and reliability of the scribing process, the partitioned region (12) may be defined by multiple straight lines defined between multiple chip regions (11) arranged along multiple rows and columns.

[0029] Below, with reference to FIGS. 2, FIGS. 3a and FIGS. 3b, a test element group (100) according to exemplary embodiments will be described.

[0030] FIG. 2 is a layout diagram of a test element group according to exemplary embodiments, and FIG. 3a and FIG. 3b are cross-sectional views of a test element group (100) along I-I', II-II', III-III' and IV-IV' of FIG. 2.

[0032] Referring to FIGS. 2, FIGS. 3a and FIGS. 3b, a test device group (100) may include a substrate (101), an active region (105) on the substrate, a device isolation layer (110) defining the active region (105), a plurality of channel layers (140) spaced perpendicularly apart from each other on the active region (105), source / drain regions (150) in contact with the plurality of channel layers (140), gate structures (160) extending across the active region (105), source / drain contact plugs (191) in contact with the source / drain regions (150), and a gate contact plug (192) in contact with the gate structures (160).

[0034] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group 4 semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc.

[0036] The device isolation layer (110) may define an active region (105) on a substrate (101). The device isolation layer (110) may be formed, for example, by a shallow trench isolation (STI) process. According to embodiments, the device isolation layer (110) may further include a region that extends deeper with a step downwards from the substrate (101). The device isolation layer (110) may expose a portion of the upper part of the active region (105). According to embodiments, the device isolation layer (110) may have a curved upper surface having a higher level as it is adjacent to the active region (105). The device isolation layer (110) may be made of an insulating material. The device isolation layer (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0038] The active region (105) is defined by the device isolation layer (110) within the substrate (101) and may be positioned to extend in the x-direction. The active region (105) may have a structure protruding from the substrate (101). The top of the active region (105) may be positioned to protrude to a predetermined height from the upper surface of the device isolation layer (110). The active region (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). The active region (105) on the substrate (101) may be partially recessed on both sides of the gate structure (160), and a source / drain region (150) may be positioned on the recessed active region (105). The active region (105) may include impurities or doping regions containing impurities.

[0040] The channel layers (140) may include two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active region (105), for example, in the z-direction, on the active region (105). The channel layers (140) may be spaced apart from the upper surface of the active region (105) while being connected to the source / drain region (150). The channel layers (140) may have a width equal to or similar to that of the active region (105) in the y-direction and a width equal to or similar to that of the gate structure (160) in the x-direction. However, according to embodiments, the channel layers (140) may have a reduced width such that their sides are located below the gate structure (160) in the x-direction.

[0041] The channel layers (140) may be made of a semiconductor material and may include, for example, silicon (Si). The channel layers (140) may be made of, for example, the same material as the substrate (101). The number and shape of the channel layers (140) may vary in the embodiments. For example, according to the embodiments, the channel layers (140) may further include a channel layer disposed on the upper surface of the active region (105).

[0043] Source / drain regions (150) may be disposed on an active region (105) at least on one side of a gate structure (160). Source / drain regions (150) may be disposed in a recessed area recessed from the upper surface of the active region (105). As shown in FIG. 3a, the source / drain regions (150) have an upper surface with a cross-section along the x-direction that is generally flat, and may have a curved shape with a circular part, an elliptical part, or a similar shape below the upper surface, but are not limited thereto. The shape of the source / drain regions (150) may be varied in the embodiments depending on the distance between adjacent gate structures (160), the height of the active region (105), etc.

[0044] As illustrated in FIG. 3b, the source / drain regions (150) may have cross-sections along the y-direction that are pentagonal or similar in shape and may be partially recessed by the source / drain contact plug (191). However, the shape of the source / drain region (150) is not limited thereto. Depending on the embodiments, the source / drain region (150) may have various shapes, for example, any one of polygonal, circular, and rectangular shapes.

[0046] A plurality of gate structures (160) may be arranged to extend in one direction, e.g., in the y-direction, intersecting the active region (105) and channel layers (140) above the active region (105) and channel layers (140). A channel region of a transistor may be formed in the active region (105) and channel layers (140) intersecting each gate structure (160). Each gate structure (160) may include a gate electrode layer (163), a gate dielectric layer (162) between the gate electrode layer (163) and the channel layers (140), spacer layers (161) on the sides of the gate electrode layer (163), and a gate capping layer (164) on the upper surface of the gate electrode layer (163).

[0047] The gate dielectric layer (162) may be positioned between the active region (105) and the gate electrode layer (163) and between the channel layers (140) and the gate electrode layer (163), and may be positioned to cover at least some of the faces of the gate electrode layer (163). For example, the gate dielectric layer (162) may be positioned to surround all faces except the top face of the gate electrode layer (163). The gate dielectric layer (162) may extend between the gate electrode layer (163) and the spacer layers (161), but is not limited thereto. The gate dielectric layer (162) may comprise an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The above high dielectric constant material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It can be any one of ), and praseodymium oxide (Pr2O3).

[0048] The gate electrode layer (163) may be disposed to extend above the channel layers (140) and fill between the channel layers (140) above the active region (105). The gate electrode layer (163) may be spaced apart from the channel layers (140) by a gate dielectric layer (162). The gate electrode layer (163) may include a conductive material. For example, it may include at least one of a metal nitride (e.g., titanium nitride film (TiN), tantalum nitride film (TaN), and tungsten nitride film (WN)), a metal material (e.g., at least one of aluminum (Al), tungsten (W), and molybdenum (Mo)), and silicon (e.g., doped polysilicon).

[0049] The gate electrode layer (163) may be composed of two or more multilayers. Spacer layers (161) may be disposed on both sides of the gate electrode layer (163). The spacer layers (161) may insulate the source / drain region (150) from the gate electrode layer (163). The spacer layers (161) may be formed into a multilayer structure according to the embodiments. The spacer layers (161) may include at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0050] The gate capping layer (164) may be disposed on top of the gate electrode layer (163) and may be surrounded by the gate electrode layer (163) and spacer layers (161). The gate capping layer (164) may include, for example, silicon nitride.

[0052] Interlayer insulating layers may be arranged to cover source / drain regions (150), gate structures (160), and device isolation layers (110). Interlayer insulating layers may be formed in multiple numbers and may include, for example, first to third interlayer insulating layers (181, 182, 183). In an exemplary embodiment, the first interlayer insulating layer (181) may be arranged to cover source / drain regions (150), gate structures (160), and device isolation layers (110), the second interlayer insulating layer (182) may be arranged on the first interlayer insulating layer (181), and the third interlayer insulating layer (183) may be arranged on the second interlayer insulating layer (182). The first to third interlayer insulating layers (181, 182, 183) may include, for example, at least one of oxide, nitride, oxynitride, and low-k dielectric. Defect detection by the test element group (100) can be performed by irradiating a gate contact plug (192) with a charged particle beam after the formation of the first and second interlayer insulating layers (181, 182) and before the formation of the third interlayer insulating layers (183). A specific method for detecting defects using the test element group (100) will be described later.

[0054] Source / drain contact plugs (191) can penetrate the first and second interlayer insulating layers (181, 182) to come into contact with source / drain regions (150) and can apply an electrical signal to the source / drain regions (150).

[0055] Source / drain contact plugs (191) may be placed on a source / drain region (150) and may have a longer length along the y-direction than the source / drain region (150), as shown in the III-III' cross-sectional view of FIG. 3B. Source / drain contact plugs (191) may be placed between adjacent gate structures (160) and may have a shorter length along the y-direction than the gate structures (160). The upper surface of the source / drain contact plug (191) may be placed at a higher level than the lower surface of the gate contact plug (192), as shown in FIG. 3A.

[0056] The source / drain contact plug (191) may have a slanted side such that the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but is not limited thereto. The source / drain contact plug (191) may be positioned to recess the source / drain region (150) to a predetermined depth. The source / drain contact plug (191) may include, for example, at least one of a metal nitride (e.g., at least one of titanium nitride film (TiN), tantalum nitride film (TaN) and tungsten nitride film (WN)) and at least one of a metallic material (at least one of aluminum (Al), tungsten (W) and molybdenum (Mo).

[0058] The test element group (100) may further include dummy contact plugs (191'). The dummy contact plugs (191') may not intersect the active region (105) and may not come into contact with the source / drain region (150). The dummy contact plugs (191') may be placed at the same location as the source / drain contact plugs formed in the actual chip regions and may be formed simultaneously with the source / drain contact plug (191). The dummy contact plugs (191') are not used for defect detection but may be configured to minimize changes from the actual chip. The dummy contact plugs (191') may not come into contact with the gate contact plug (192), which is the detection pad, and depending on the embodiments, the dummy contact plugs (191') may be omitted.

[0060] A gate contact plug (192) may be disposed on a plurality of gate structures (160) on top of a device isolation layer (110). The gate contact plug (192) may be spaced apart in the y-direction from the active region (105) and spaced apart in the y-direction from a source / drain contact plug (191). The gate contact plug (192) may recess the gate capping layers (164) of the plurality of gate structures (160) to make contact with the gate electrode layers (163). The gate contact plug (192) may apply an electrical signal to the gate electrode layers (163). At least a portion of the gate capping layers (164) may remain without being recessed. For example, as shown in the IV-IV' cross-sectional view of FIG. 3B, the portions on both sides of the gate capping layers (164) that are in contact with the spacer layers (161) may remain.

[0061] The gate contact plug (192) may be positioned to recess at least a portion of the first and second interlayer insulating layers (181, 182) covering the source / drain regions (150) and gate structures (160) to a predetermined depth. As shown in the IV-IV′ cross-sectional view of FIG. 3b, the first interlayer insulating layer (181) may be recessed to a greater depth than the gate capping layers (164). This is due to the difference in selectivity between the first interlayer insulating layer (181) and the gate capping layer (164). For example, if the first interlayer insulating layer (181) contains silicon oxide and the gate capping layers (164) contain silicon nitride, the oxide has a higher selectivity than the nitride, so the etching rate of the first interlayer insulating layer (181) may be faster than the etching rate of the gate capping layer (164). As a result, the gate contact plug (192) can be recessed to a greater depth in the first interlayer insulating layer (181) than in the gate capping layers (164). However, the shape of the gate contact plug (192) is not limited thereto, and the recessed shape may vary depending on the type of material of the gate capping layers (164) and the first interlayer insulating layer (181).

[0062] Referring to FIG. 2, the gate contact plug (192) may have an approximate H shape when viewed from above. For example, the gate contact plug (192) may include a first extension extending in the x-direction, a second extension extending in the x-direction and spaced apart from the first extension in the y-direction, and a connecting portion positioned between the first extension and the second extension to connect the first extension and the second extension, wherein the length in the x-direction of each of the first extension and the second extension may be greater than the length in the x-direction of the connecting portion. Accordingly, the gate contact plug (192) may have an approximate horizontal H shape when viewed from above. The gate contact plug (192) may have a shape that extends in the x-direction intersecting a plurality of gate structures (160) and has a predetermined thickness in the z-direction. By having such a shape, the gate contact plug (192) can easily apply an electrical signal and easily identify differences in brightness of the SEM image depending on whether there is a defect. That is, the gate contact plug (192) can function as a pad for detecting defects. The shape of the gate contact plug (192) can be varied within the range in which it can perform the function as a detection pad. For example, the shape of the upper surface of the gate contact plug (192) can be rectangular, elliptical, ladder-shaped, etc.

[0063] The gate contact plug (192) may comprise, for example, at least one of a metal nitride (e.g., at least one of titanium nitride (TiN), tantalum nitride (TaN) and tungsten nitride (WN)) and at least one of a metal material (at least one of aluminum (Al), tungsten (W) and molybdenum (Mo). In an exemplary embodiment, the gate contact plug (192) may comprise the same material as the source / drain contact plug (191).

[0065] The test element group (100) illustrated in FIGS. 2 to 3b can detect defects in the substructure of a semiconductor device. The test element group (100) can detect short circuits between gate structures (160) and adjacent source / drain contact plugs (191), and short circuits between gate structures (160) and adjacent source / drain regions (150).

[0066] Defect detection by the test element group (100) can be performed by irradiating a charged particle beam, such as an electron beam, onto a gate contact plug (192) to induce a voltage difference, and analyzing the brightness of the gate contact plug (192) in a scanning electron microscope (SEM) image of the test element group (100).

[0067] As illustrated in FIGS. 2 and 3a, the gate contact plug (192) can contact the gate electrode layers (163) of each of the plurality of gate structures (160) and can apply an electrical signal to the gate electrode layers (163). Charge is also accumulated on the gate electrode layers (163) in contact with the gate contact plug (192) by a beam of charged particles irradiated onto the gate contact plug (192).

[0068] When the test element group (100) is formed normally, the charge from the charged particle beam can be accumulated on the gate contact plug (192) and the gate electrode layers (163). The gate contact plug (192) on the SEM image may appear bright due to the accumulated charge.

[0069] In contrast, if a defect occurs in the substructure of the test device group (100), the gate contact plug (192) in the SEM image may appear dark. For example, if a short circuit defect occurs between the gate structure (160) and the adjacent source / drain contact plug (191), the charge accumulated in the gate electrode layer (163) through the gate contact plug (192) may move to the source / drain region (150) through the source / drain contact plug (191) and leak out. As a result, since charge does not accumulate in the gate contact plug (192), the gate contact plug (192) in the SEM image may appear dark.

[0070] In a similar manner, even when a short circuit occurs between the gate structure (160) and the source / drain region (150), the gate contact plug (192) on the SEM image appears dark, so the defect in the lower structure of the test device group (100) can be detected.

[0072] As described above, defect detection by the test device group (100) can be performed by forming a gate contact plug (192) and then irradiating the gate contact plug (192) with a charged particle beam. That is, the test device group according to the present embodiment can detect defects in the device by using the gate contact plug (192) as a detection pad before forming the BEOL (Back End Of Line). Since the test device group according to the present embodiment conducts defect inspection before forming the BEOL, the test around time of the semiconductor device is reduced, and only defects in the underlying structure can be selectively detected by excluding the influence of BEOL defects. As a result, the efficiency and accuracy of the inspection can be improved.

[0073] In an exemplary embodiment, the test element group (100) may not include wiring in the BEOL level layer (e.g., M1 Layer). As illustrated in FIGS. 3a and 3b, the test element group (100) may further include a third interlayer insulating layer (183) covering the upper surface.

[0075] Next, FIG. 4 is a layout drawing illustrating a test element group (100A) according to exemplary embodiments, and FIG. 5a and FIG. 5b are cross-sectional views illustrating a test element group (100A) according to exemplary embodiments.

[0076] FIGS. 5A and 5B illustrate cross-sectional views of test element groups (100) along I-I', II-II', III-III' and IV-IV' of FIG. 4.

[0077] In the embodiments of FIGS. 4 to 5b, if the same drawing numbers as FIGS. 2 to 3b are used but the alphabet is different, it is intended to describe embodiments different from FIGS. 2 to 3b, and the features described in the same drawing numbers described above may be the same or similar.

[0079] The test element group (100A) of FIGS. 4 to 5b differs from the test element group (100) of FIGS. 2 to 3b in that some of the gate structures are separated in the y-direction and further include an upper contact plug (193).

[0081] Referring to FIGS. 4 to 5b, the test element group (100A) may include a first gate structure (160A_1) and second gate structures (160A_2).

[0082] The first gate structure (160A_1) may extend in the y direction to intersect the active region (105) on the substrate (101) and to contact the gate contact plug (192A). The second gate structures (160A_2) may each include a first part (P1) and a second part (P2). The first part (P1) extends in the y direction intersecting the active region (105) on the substrate (101) and may overlap with a part of the first gate structure (160A_1) in the x direction. The second part (P2) is spaced apart from the first part (P1) in the y direction and faces the first part (P1), and may extend in the y direction and overlap with a part of the first gate structure (160A_1) in the x direction. The first gate structure (160A_1) may have a longer length in the y direction than the first part (P1) and the second part (P2) of the second gate structure (160A_2).

[0083] Although an embodiment including one first gate structure (160A_1) and a plurality of second gate structures (160A_2) is illustrated in FIGS. 4 to 5b, the number and location of the first and second gate structures (160A_1, 160A_2) are not limited thereto and may be changed depending on the connection structure of the elements, defect detection targets, etc.

[0085] The test element group (100A) may further include an upper contact plug (193) in addition to the source / drain contact plug (191A) and the gate contact plug (192A).

[0086] Source / drain contact plugs (191A) may be placed on source / drain regions (150) and electrically connected to the source / drain regions (150). The source / drain regions (150) and the source / drain contact plugs (191A) may be placed between the first gate structure (160A_1) and the first portion (P1) of the adjacent second gate structure (160A_2), and between the first portions (P1) of the adjacent second gate structures (160A_2).

[0088] An upper contact plug (193) may be placed on a source / drain contact plug (191A) and a first gate structure (160A_1). The upper contact plug (193) may be electrically connected by contacting the source / drain contact plug (191A). The upper contact plug (193) may be positioned to recess the second interlayer insulating layer (182) and the gate capping layer (164) of the first gate structure (160A_1) so as to be in contact with the gate electrode layer (163). The source / drain contact plug (191A) and a first portion (P1) of the second gate structure (160A_2) may be electrically connected by the upper contact plug (193).

[0089] The upper contact plug (193) can be formed in the same process as the gate contact plug (192A). The upper contact plug (193) may have an upper surface positioned at the same level as the upper surface of the gate contact plug (192A) and may contain the same material as the gate contact plug (192A).

[0091] A gate contact plug (192A) may be placed on a first gate structure (160A_1) and a second part (P2) of a second gate structure (160A_2). The gate contact plug (192A) may be electrically connected by contacting the gate electrode layer (163) of the first gate structure (160A_1) and the gate electrode layers (163) of the second part (P2) of the second gate structure (160A_2).

[0093] The test element group (100A) illustrated in FIGS. 4 to 5b can detect an open fault between the source / drain contact plug (191A) and the upper contact plug (193).

[0094] The gate contact plug (192A) can come into contact with the gate electrode layers (163) of each of the second parts (P2) of the first gate structure (160A_1) and the second gate structures (160A_2). Charge is accumulated on the gate electrode layers (163) in contact with the gate contact plug (192A) by a beam of charged particles irradiated onto the gate contact plug (192A).

[0095] When the test element group (100A) is formed normally, the charge accumulated in the gate contact plug (192A) by the charged particle beam can move to the source / drain region (150) through the gate electrode layer (163) of the first gate structure (160A_1), the upper contact plug (193), and the source / drain contact plug (191A). That is, since no charge is accumulated in the gate contact plug (192A), the gate contact plug (192A) may appear dark in the SEM image.

[0096] In contrast, if a defect occurs in the lower structure of the test element group (100A), for example, if an open defect occurs between the source / drain contact plug (191A) and the upper contact plug (193), the charge from the charged particle beam cannot move to the source / drain region (150) and accumulates in the gate contact plug (192A), the first gate structure (160A_1), and the upper contact plug (193), so the gate contact plug (192A) may appear bright in the SEM image.

[0098] The test element group (100A) of FIGS. 4 to 5b is configured with a gate contact plug (192A) as a detection pad, as in the embodiment of FIGS. 2 to 3b, so that the inspection time is reduced and the accuracy of detecting lower defects can be improved.

[0100] Next, FIG. 6 is a layout drawing illustrating a test element group (100B) according to exemplary embodiments, and FIG. 7a and FIG. 7b are cross-sectional views illustrating a test element group (100A) according to exemplary embodiments.

[0101] FIGS. 7a and 7b illustrate cross-sectional views of test element groups (100B) along I-I', II-II', III-III' and IV-IV' of FIG. 6.

[0102] In the embodiments of FIGS. 6 to 7b, if the same drawing numbers as FIGS. 2 to 3b are used but the alphabet is different, it is intended to describe embodiments different from FIGS. 2 to 3b, and the features described in the same drawing numbers described above may be the same or similar.

[0104] The test element group (100B) of FIGS. 6 to 7b differs from the test element group (100) of FIGS. 2 to 3b in that the gate structures (160B) are separated in the y-direction and the gate contact plug (192B) contacts the source / drain contact plug (191B_2).

[0106] Referring to FIGS. 6 to 7b, the gate structures (160B) of the test device group (100B) may include a first portion (P1) and a second portion (P2). The first portion (P1) may extend in the y-direction intersecting the active region (105) on the substrate (101). The second portion (P2) may extend in the y-direction spaced apart from the first portion (P1) in the y-direction and facing the first portion (P1). The second portion (P2) may be disposed on the device isolation layer (110) and may not intersect the active region (105).

[0108] The test element group (100B) may include a first source / drain contact plug (191B_1) and a second source / drain contact plug (191B_2). The first and second source / drain contact plugs (191B_1, 191B_2) may each be placed on source / drain regions (150) and electrically connected to the source / drain regions (150).

[0109] The first source / drain contact plugs (191B_1) may be placed between the first parts (P1) of adjacent gate structures (160B). The first source / drain contact plugs (191B_1) may have a similar length along the y-direction as the first parts (P1) of the gate structures (160B).

[0110] The second source / drain contact plug (191B_2) is positioned on the source / drain region (150) between the first portions (P1) of the gate structures (160B) and extends in the y direction, and may include a portion positioned between the second portions (P2) of the gate structures (160B). The second source / drain contact plug (191B_2) may have a longer length along the y direction than the first source / drain contact plug (191B_1).

[0112] A gate contact plug (192B) may be placed on the second portion (P2) of the gate structure (160B) and the second source / drain contact plug (191B_2). The gate contact plug (192B) may be placed on top of the device isolation layer (110). The gate contact plug (192B) may be placed to recess the second interlayer insulation layer (182) and the gate capping layers (164) of the second portion (P2) of the gate structures (160B). The gate contact plug (192B) may be electrically connected by contacting the gate electrode layers (163) of the second portion (P2) of the gate structures (160B). The gate contact plug (192B) may be electrically connected by contacting the second source / drain contact plug (191B_2).

[0113] The number and placement locations of the first and second source / drain contact plugs (191B_1, 191B_2) are not limited to those depicted and may be changed depending on the structure of the semiconductor device, etc.

[0115] The test element group (100B) illustrated in FIGS. 6 to 7b can detect an open failure caused by a break in the second source / drain contact plug (191B_2).

[0116] The gate contact plug (192B) can come into contact with the second part (P2) of the gate structures (160B) and the second source / drain contact plug (191B_2). Charge is accumulated in the second part (P2) of the gate structures (160B) and the second source / drain contact plug (191B_2) that are in contact with the gate contact plug (192B) by a beam of charged particles irradiated onto the gate contact plug (192B).

[0117] When the test element group (100B) is formed normally, the charge accumulated in the second source / drain contact plug (191B_2) by the charged particle beam can move to the source / drain region (150) and leak out. That is, since no charge is accumulated in the gate contact plug (192B), the gate contact plug (192B) may appear dark in the SEM image.

[0118] In contrast, if a defect occurs in the substructure of the test element group (100B), for example, if a break occurs in the second source / drain contact plug (191B_2), the charge from the charged particle beam cannot move to the source / drain region (150) through the second source / drain contact plug (191B_2). Therefore, since the charge accumulates in the gate contact structure (192B), the gate contact plug (192B) may appear bright in the SEM image.

[0120] The test element group (100B) of FIGS. 6 to 7b is configured with a gate contact plug (192B) at the MOL level as a detection pad, as in the embodiment of FIGS. 2 to 3b, so the inspection time is reduced and the influence of BEOL defects is eliminated, thereby improving the accuracy of defect detection.

[0122] Next, FIG. 8 is a layout drawing illustrating a test element group (100C) according to exemplary embodiments, and FIG. 9a and FIG. 9b are cross-sectional views illustrating a test element group (100C) according to exemplary embodiments.

[0123] FIGS. 9A and 9B illustrate cross-sectional views of test element groups (100) along I-I', II-II', III-III' and IV-IV' of FIG. 8.

[0124] In the embodiments of FIGS. 8 to 9b, if the same drawing numbers as FIGS. 2 to 3b are used but the alphabet is different, it is intended to describe embodiments different from FIGS. 2 to 3b, and the features described in the previously described same drawing numbers may be the same or similar.

[0126] The test element group (100C) of FIGS. 8 to 9b differs from the test element group (100) of FIGS. 2 to 3b in that it further includes second gate contact plugs (193C) in addition to the first gate contact plug (192C).

[0127] Second gate contact plugs (193C) may be disposed on gate structures (160C). The second gate contact plugs (193C) may be disposed to recess the gate capping layers (164) of the gate structures (160C) so as to make contact with the gate electrode layers (163). The second gate contact plugs (193C) may be disposed between the source / drain contact plugs (191C).

[0128] In FIGS. 8 to 9b, one second gate contact plug (193C) is provided on each gate structure (191C), but the number of gate contact plugs (193C) disposed on each gate structure (191C) is not limited thereto. According to embodiments, a plurality of gate contact plugs may be disposed on each gate structure. For example, as shown in FIG. 10, three second gate contact plugs (193D) may be disposed on each gate structure (160D).

[0130] The test element group (100C) illustrated in FIGS. 8 to 9b can detect a short between the gate structures (160C) and the adjacent source / drain contact plugs (191C), a short between the gate structures (160C) and the adjacent source / drain regions (150), and a short between the second gate contact plugs (193C) and the adjacent source / drain contact plugs (191C).

[0131] The first gate contact plug (192C) can be electrically connected to the gate structures (160C) and the second gate contact plug (193C). Charge is accumulated in the first gate contact plug (192C), the gate electrode layers (163) of the gate structures (160C), and the second gate contact plugs (193C) by a beam of charged particles irradiated onto the first gate contact plug (192C).

[0132] When the test element group (100C) is formed normally, the charge from the charged particle beam can be accumulated on the first gate contact plug (192C), the gate electrode layers (163), and the second gate contact plugs (193C). As a result, the first gate contact plug (192C) on the SEM image may appear bright due to the accumulated charge.

[0133] In contrast, if a defect occurs in the substructure of the test device group (100C), the first gate contact plug (192C) in the SEM image may appear dark. For example, if a short circuit defect occurs between the source / drain contact plug (191C) and the second gate contact plug (193C), the charge from the charged particle beam may leak from the second gate contact plug (193C) to the source / drain region (150) through the adjacent source / drain contact plug (191C). That is, since charge does not accumulate in the first gate contact plug (192C), the first gate contact plug (192C) in the SEM image may appear dark.

[0135] The test element groups (100, 100A, 100B, 100C) of FIGS. 2 to 10 described above may be placed in a plurality of chip regions (11) of the semiconductor device (10) shown in FIG. 1 and used to detect defects occurring in the substructure of the semiconductor device.

[0136] In an exemplary embodiment, a plurality of chip regions (11 in FIG. 1) include a plurality of test element groups of different types, and the cause of defect detection can be identified by comparing the test results of each test element group.

[0137] For example, the test element group (100) illustrated in FIGS. 2 to 3b can detect short circuits between gate structures and adjacent source / drain contact plugs, and short circuits between gate structures and adjacent source / drain regions. The test element group (100C) illustrated in FIGS. 8 to 9b can additionally detect short circuit defects between gate contact plugs and adjacent source / drain contact plugs in addition to defects detectable by the test element group (100) of FIGS. 2 to 3b.

[0138] When a defect is detected by test element groups (100, 100C), and the test element group (100) of FIGS. 2 to 3b is determined to be normal (pad bright in SEM image) and the test element group (100C) of FIGS. 8 to 9b is determined to be defective (pad dark in SEM image), it can be determined that the cause of the defect is a short circuit between the gate contact plugs and the adjacent source / drain contact plugs.

[0140] In the test element groups according to the present embodiment, since the detection pad that irradiates the charged particle beam is a gate contact plug formed at the MOL level, unlike the case where the pad is formed at the BEOL level, defects at the MOL level can be selectively detected without detecting defects at the BEOL level (e.g., defects between the contact plug and the M1 Layer pad). This increases the accuracy of defect detection, and since detection is possible before the BEOL level is formed, the inspection time can be shortened.

[0142] In the embodiments of FIGS. 2 to 10, the semiconductor device is an MBCFET TM Although test device groups for the case of a Multi-Bridge Channel FET have been described, they are not limited thereto. In other embodiments, test device groups according to the present invention may also be applied when the semiconductor device is a finFET device, which is a transistor having a fin structure in the active region.

[0144] Next, FIGS. 11a to 13b are cross-sections illustrated in the order of process to explain a method for manufacturing a test element group (100) according to exemplary embodiments. FIGS. 11a to 13b illustrate an example of a method for manufacturing a semiconductor device of FIGS. 2 to 3b and illustrates cross-sections corresponding to FIGS. 3a and 3b.

[0146] First, we will briefly describe the steps up to the formation of the source / drain region (150) in the manufacturing method of the test element group.

[0147] A stacked structure can be formed by alternately stacking sacrificial layers (120) and channel layers (140) on a substrate (101). An active structure can be formed by removing a portion of the stacked structure and the substrate (101). The active structure may include sacrificial layers (120) and channel layers (140) that are alternately stacked with each other, and may further include an active region (105) formed to protrude from the upper surface of the substrate (101) by removing a portion of the substrate (101). In the region where a portion of the substrate (101) is removed, an insulating material may be buried, and then a recess may be formed so that the active region (105) protrudes.

[0149] Referring to FIGS. 11a and 11b, sacrificial gate structures (170) and spacer layers (161) can be formed on an active structure. By using the sacrificial gate structures (170) and spacer layers (161) as a mask, exposed sacrificial layers (120) and channel layers (140) between the sacrificial gate structures (170) can be removed to form a recess region.

[0150] A source / drain region (150) may be formed within a recess region. The source / drain region (150) may be formed by performing an epitaxial growth process within the recess region. The source / drain region (150) may be in contact with the side of the channel layers (140). The source / drain region (150) may contain impurities by in-situ doping and may include multiple layers having different doping elements and / or doping concentrations.

[0152] Referring to FIG. 12a and FIG. 12b, a first interlayer insulating layer (181) is formed between the sacrificial gate structures (170), and the sacrificial layers (120) and the sacrificial gate structures (170) can be removed.

[0153] The first interlayer insulating layer (181) can be formed by forming an insulating film covering the sacrificial gate structures (170) and the source / drain region (150) and performing a flattening process.

[0154] The sacrificial layers (120) and sacrificial gate structures (170) can be selectively removed with respect to the spacer layers (161), the first interlayer insulating layer (181), and the channel layers (140). After removing the sacrificial gate structures (170) to form upper gap regions (UR), the sacrificial layers (120) exposed through the upper gap regions (UR) can be removed to form lower gap regions (LR). For example, if the sacrificial layers (120) contain silicon germanium (SiGe) and the channel layers (140) contain silicon (Si), the sacrificial layers (120) can be selectively removed by performing a wet etching process using peracetic acid as an etchant.

[0156] Referring to FIGS. 13a and 13b, a gate structure (160) can be formed within the upper gap regions (UR) and lower gap regions (LR).

[0157] The gate dielectric layer (162) can be formed to conformally cover the inner surfaces of the upper gap regions (UR) and lower gap regions (LR). The gate electrode layer (163) can be formed to completely fill the upper gap regions (UR) and lower gap regions (LR). The gate electrode layer (163) and the spacer layers (161) can be removed from the upper gap regions (UR) to a predetermined depth from the top. A gate capping layer (164) can be formed in the area where the gate electrode layer (163) and the spacer layers (161) have been removed from the upper gap regions (UR). By this, a gate structure (160) comprising the gate dielectric layer (162), the gate electrode layer (163), the spacer layers (161), and the gate capping layer (164) can be formed.

[0158] Subsequently, the second interlayer insulating layer (182) can be formed by forming an insulating film covering the gate structure (160) and the first interlayer insulating layer (181) and performing a flattening process.

[0160] Next, referring to FIG. 2, FIG. 3a and FIG. 3b together, a source / drain contact plug (191) and a gate contact plug (192) can be formed.

[0161] The source / drain contact plug (191) can be formed by patterning the first and second interlayer insulating layers (181, 182) to form a contact hole and embedding a conductive material within the contact hole. The lower surface of the contact hole can be recessed into the source / drain region (150). The contact hole can be formed in a shape that extends along the y-direction between adjacent gate structures (160).

[0162] The gate contact plug (192) can be formed by patterning the first and second interlayer insulating layers (181, 182) and the gate capping layer (164) of the gate structure (160) to form a contact hole, and by embedding a conductive material within the contact hole. As shown in the layout diagram of FIG. 2, the gate contact plug (192) can be formed so that its upper surface has an approximately H-shape, but is not limited thereto and can be modified in various ways.

[0163] After performing a selective defect inspection of the semiconductor device (10 in FIG. 1), a subsequent BEOL process may be performed on the integrated circuit regions of the plurality of chip regions (11 in FIG. 1). At the same time, a third interlayer insulating layer (183) covering the entire upper surface may be formed on the test device group (100).

[0165] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0167] 10: Semiconductor device 11: Chip regions 12: Partitioned area 100: Test element group (TEG) 101: Substrate 105: Active region 110: Device isolation layer 140: Channel layer 150: Source / Drain Area 160: Gate Structure 181: 1st interlayer insulation layer 182: 2nd interlayer insulation layer 183: Third interlayer insulation 191: Source / drain contact plug 192: Gate contact plug 193: Upper contact plug

Claims

Claim 1 An active region extending in a first direction on a substrate; gate structures extending in a second direction intersecting the active region on the substrate; a first gate contact plug disposed on the gate structures and in contact with the gate electrode layers of each of the gate structures; source / drain regions disposed on the active region on at least one side of the gate structures; source / drain contact plugs disposed on each of the source / drain regions, electrically connected to each of the source / drain regions, and extending in the second direction; and dummy contact plugs spaced apart from at least one of the source / drain contact plugs in the second direction and extending in the second direction, and disposed on the same layer as the source / drain contact plugs; wherein the first gate contact plug extends in the first direction spaced apart from the source / drain contact plugs in the second direction, and the first gate contact plug is disposed between the dummy contact plugs and spaced apart from the dummy contact plugs in the first direction. Claim 2 A test element group according to claim 1, further comprising second gate contact plugs, wherein the second gate contact plugs are spaced apart from the first gate contact plug in the second direction and are disposed on the gate structures to contact the gate electrode layers of the gate structures. Claim 3 In paragraph 2, the second gate contact plugs are a group of test elements disposed between adjacent source / drain contact plugs. Claim 4 In claim 1, the first gate contact plug comprises a first extension portion extending in the first direction, a second extension portion extending in the first direction and spaced apart from the first extension portion in the second direction, and a connecting portion disposed between the first extension portion and the second extension portion and connecting the first extension portion and the second extension portion, wherein the length in the first direction of each of the first extension portion and the second extension portion is greater than the length in the first direction of the connecting portion, thereby forming a test element group. Claim 5 A test element group according to claim 1, wherein the upper surface of the source / drain contact plug is positioned at a higher level than the lower surface of the first gate contact plug. Claim 6 Gate structures each comprising: an active region extending in a first direction on a substrate; a first portion extending in a second direction intersecting the active region on the substrate; and a second portion extending in the second direction, spaced apart from the first portion and in the second direction on the substrate and facing the first portion; a source / drain region disposed on the active region between the first portions of adjacent gate structures; first source / drain contact plugs disposed on the source / drain region and electrically connected to the source / drain region, extending in the second direction and disposed between the first portions of adjacent gate structures; and a second source / drain contact plug, at least a portion of which is disposed on the source / drain region and electrically connected to the source / drain region, extending in the second direction and disposed between the first portions and the second portions of adjacent gate structures, respectively. A group of test elements comprising a second source / drain contact plug and a gate contact plug disposed on the second portions of the gate structures, and in contact with the gate electrode layers of the second portions of each of the gate structures and the second source / drain contact plug. Claim 7 In claim 6, the active region is defined by a device isolation layer, and the gate contact plug is disposed on top of the device isolation layer, a test device group. Claim 8 A test element group according to claim 6, further comprising an insulating layer covering the upper surface of the gate contact plug and the upper surface of the first source / drain contact plug. Claim 9 A semiconductor device comprising: an integrated circuit region on which a transistor is disposed; and a dummy region adjacent to the integrated circuit region on which a plurality of test element groups are disposed, wherein each of the plurality of test element groups comprises gate structures each including a first portion extending in a second direction intersecting an active region extending in a first direction on a substrate, and a second portion extending in the second direction, spaced apart from the first portion and in the second direction on the substrate and facing the first portion; source / drain contact plugs disposed between the first portions of the gate structures; a gate contact plug disposed on the second portions of the gate structures, contacting the gate electrode layers of each of the gate structures and extending in the first direction; and an upper contact plug disposed on the first portions of the gate structures and the source / drain contact plugs, contacting the gate electrode layers of the gate structures and the source / drain contact plugs, and comprising a pad region to which an electrical signal is applied. Claim 10 A semiconductor device according to claim 9, wherein each of the plurality of test element groups further comprises an insulating layer covering the upper surface of the gate structures and the pad region.

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