Semiconductor device including oxide channel layer and method of fabricating the same

Abstract

A semiconductor device according to one embodiment comprises a substrate, a source electrode layer and a drain electrode layer spaced apart from each other in a direction substantially perpendicular to the surface of the substrate on top of the substrate, a first and a second oxide channel layer each extended between the source electrode layer and the drain electrode layer in the direction substantially perpendicular to the surface of the substrate, a ferroelectric layer disposed adjacent to the first and second oxide channel layers, and a gate electrode layer disposed on the ferroelectric layer. The first and second oxide channel layers have different band gap energies.

Description

Technology Field

[0001] The present disclosure generally relates to a semiconductor device, and more specifically to a semiconductor device comprising an oxide channel layer and a ferroelectric layer and a method for manufacturing the same. Background Technology

[0002] With the trend of decreasing design rules and increasing integration density, research is continuing on semiconductor devices capable of ensuring structural stability and operational reliability within a reduced space. For example, in the case of memory devices, research is being conducted on technologies that increase memory cell integration density by reducing the memory cell area, while simultaneously improving the endurance of signal information stored within the memory cell.

[0003] A ferroelectric field-effect transistor is proposed as a candidate for a memory device capable of achieving the above objective. The ferroelectric field-effect transistor may be a memory device that stores signal information by utilizing remnants of polarization stored in different orientations within a ferroelectric layer, which is a gate dielectric layer. The problem to be solved

[0004] One embodiment of the present disclosure provides a semiconductor device capable of ensuring structural stability and operational reliability. means of solving the problem

[0005] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a source electrode layer and a drain electrode layer spaced apart from each other in a direction substantially perpendicular to the surface of the substrate on top of the substrate, a first and a second oxide channel layer each spaced apart in the direction substantially perpendicular to the surface of the substrate between the source electrode layer and the drain electrode layer, a ferroelectric layer disposed adjacent to the first and second oxide channel layers, and a gate electrode layer disposed on the ferroelectric layer. The first and second oxide channel layers have different band gap energies.

[0006] In a method for manufacturing a semiconductor device according to another aspect of the present disclosure, a stacked structure comprising a source electrode material layer, a first protective material layer, a gate electrode material layer, a second protective material layer, and a drain electrode material layer is formed sequentially stacked on the upper surface of a substrate. A hole pattern penetrating the stacked structure is formed on the upper surface of the substrate. The first and second protective material layers are selectively recessed within the hole pattern to form a first recessed space. The gate electrode material layer is selectively recessed within the hole pattern to form a second recessed space. The edge of the second recessed space extends from the edge of the first and second protective material layers in the first recessed space toward the interior of the gate material electrode layer. A ferroelectric layer is formed within the second recessed space. A first channel material layer and a second channel material layer are sequentially formed within the first recessed space. The band gap energy of the first channel material layer is smaller than the band gap energy of the second channel material layer. A third protective material layer covering at least the second channel material layer is formed inside the hole pattern. Effects of the invention

[0007] A semiconductor device according to the embodiments of the present disclosure described above can provide improved operating characteristics related to operating endurance, channel conductivity, chemical resistance, etc. Brief explanation of the drawing

[0008] FIG. 1 is a perspective view schematically showing a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view of the semiconductor device of Figure 1 taken along I-I'. Figure 3 is a schematic circuit diagram corresponding to the semiconductor device of Figure 1. FIG. 4a is a diagram schematically illustrating a first write operation of a semiconductor device according to one embodiment of the present disclosure. Figure 4b is an energy band diagram of the first and second oxide channel layers corresponding to Figure 4a. FIG. 5a is a diagram schematically illustrating a second write operation of a semiconductor device according to one embodiment of the present disclosure. Figure 5b is an energy band diagram of the first and second oxide channel layers corresponding to Figure 5a. FIGS. 6 to 12 are cross-sectional views schematically illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 13 and 14 are cross-sectional views schematically illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the present application will be described in more detail with reference to the attached drawings. In the drawings, the dimensions, such as the width or thickness of the components, have been slightly enlarged to clearly represent the components of each device. The drawings are described from the perspective of an observer, and when one element is mentioned as being positioned above another element, this implies both that the one element is positioned directly above the other element and that an additional element may be interposed between them. In multiple drawings, the same reference numerals refer to substantially identical elements.

[0010] Furthermore, singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as 'include' or 'have' are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should not be understood as precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0011] In carrying out the method, each process constituting the method may occur differently from the specified order unless a specific order is clearly indicated in the context. That is, each process may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

[0012] In this specification, the source electrode layer and the drain electrode layer may be relative concepts to each other. That is, depending on the circuit configuration of the ferroelectric field-effect transistor, the source electrode layer and the drain electrode layer may be functionally interchangeable. As an example, depending on the circuit configuration, the source electrode layer may function as a drain electrode, and the drain electrode layer may function as a source electrode.

[0013] FIG. 1 is a perspective view schematically showing a semiconductor device according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along I-I' of the semiconductor device of FIG. 1. FIG. 3 is a schematic circuit diagram corresponding to the semiconductor device of FIG. 1.

[0014] Referring to FIG. 2, the semiconductor device (1) may include first to fourth memory cells (MC1, MC2, MC3, MC4) on the upper surface of a substrate (101). The first to fourth memory cells (MC1, MC2, MC3, MC4) may include non-volatile memory elements. As an example, the first to fourth memory cells (MC1, MC2, MC3, MC4) may include a ferroelectric field effect transistor.

[0015] Referring to FIG. 3, the first memory cell (MC1) may include a first ferroelectric layer (FD1) and a first gate electrode (G1) between a first source electrode (S1) and a first drain electrode (D1). Through a write voltage applied to the first gate electrode (G1), a residual polarization of a predetermined orientation may be recorded as signal information in the first ferroelectric layer (FD1). The second memory cell (MC2) may include a second ferroelectric layer (FD2) and a second gate electrode (G2) for storing signal information between a second source electrode (S2) and a second drain electrode (D2). In this case, the first and second memory cells (MC1, MC2) may share drain electrodes (D1, D2). That is, the first drain electrode (D1) of the first memory cell (MC1) and the second drain electrode (D2) of the second memory cell (MC2) may be the same electrode.

[0016] Likewise, in FIG. 3, the third memory cell (MC3) may include a third ferroelectric layer (FD3) and a third gate electrode (G3) for storing signal information between the third source electrode (S3) and the third drain electrode (D3). The fourth memory cell (MC4) may include a fourth ferroelectric layer (FD4) and a fourth gate electrode (G4) for storing signal information between the fourth source electrode (S4) and the fourth drain electrode (D4). In this case, the third and fourth memory cells (MC3, MC4) may share the drain electrode (D3, D4). That is, the third drain electrode (D3) of the third memory cell (MC3) and the fourth drain electrode (D4) of the fourth memory cell (MC4) may be the same electrode.

[0017] Referring again to FIG. 2, the second memory cell (MC2) and the fourth memory cell (MC4) may be placed on top of the first memory cell (MC1) and the third memory cell (MC3), respectively. The first memory cell (MC1) and the third memory cell (MC3), which are placed adjacent to each other on a plane substantially parallel to the surface (101S) of the substrate (101), may be electrically separated from each other by a cell separation structure (180). Likewise, the second memory cell (MC2) and the fourth memory cell (MC4), which are placed adjacent to each other on a plane substantially parallel to the surface (101S) of the substrate (101), may be electrically separated from each other by a cell separation structure (180). Referring to FIG. 1 and FIG. 2 together, the cell separation structure (180) may be an insulating barrier structure extending in a direction substantially perpendicular to the surface (101S) of the substrate (101) (e.g., z-direction) and in a direction substantially parallel to the surface (101S) of the substrate (101) (e.g., y-direction), respectively. The cell separation structure (180) may comprise, for example, an oxide, a nitride, an oxynitride, or a combination thereof. In one embodiment, the cell separation structure (180) may comprise a silicon nitride layer or a metal nitride layer.

[0018] Referring to FIGS. 1 and FIGS. 2 together, the first to fourth memory cells (MC1, MC2, MC3, MC4) may have substantially the same configuration in terms of structure, but may operate independently of each other in terms of electricality based on the circuit diagram of FIGS. 3. In one embodiment, the first and second memory cells (MC1, MC2) are arranged to share the drain electrode layer (130) in terms of structure, but may operate independently of each other in terms of electricality based on the circuit diagram of FIGS. 3. Likewise, the third and fourth memory cells (MC3, MC4) are arranged to share the drain electrode layer (130) in terms of structure, but may operate independently of each other in terms of electricality based on the circuit diagram of FIGS. 3.

[0019] Meanwhile, FIG. 2 discloses four memory cells (MC1, M2, MC3, MC4) disposed on the upper surface of the substrate (101), but the inventive concept disclosed herein is not necessarily limited thereto. In some other embodiments, the semiconductor device (1) may include various other numbers of memory cells disposed on the upper surface of the substrate (101).

[0020] Referring to FIG. 1 and FIG. 2 together, each of the first to fourth memory cells (MC1, MC2, MC3, MC4) includes a source electrode layer (110) and a drain electrode layer (130) spaced apart from each other on the upper surface of a substrate (101), first and second oxide channel layers (122, 124) disposed between the source electrode layer (110) and the drain electrode layer (130), a ferroelectric layer (140) disposed adjacent to the first and second oxide channel layers (122, 124), and a gate electrode layer (150) disposed on the ferroelectric layer (140). Additionally, each of the first to fourth memory cells (MC1, MC2, MC3, MC4) may include first and second channel protection layers (160, 170) disposed to cover the first and second oxide channel layers (122, 124) on the upper surface of the substrate (101).

[0021] Referring to FIGS. 1 and 2, a substrate (101) is provided. The substrate (101) may include a semiconductor material. Specifically, the semiconductor material may include silicon, germanium, gallium arsenide, etc. The substrate (101) may be doped with n-type or p-type to have a predetermined conductivity.

[0022] Although not shown in FIGS. 1 and 2, the substrate (101) may include an integrated circuit. The integrated circuit may include a cell driving circuit that drives and controls the first to fourth memory cells (MC1, MC2, MC3, MC4). The integrated circuit may include, as an example, electrical components such as diodes and transistors.

[0023] A base insulating layer (105) may be disposed on a substrate (101). The base insulating layer (110) may, as an example, include an oxide, a nitride, an oxynitride, or two or more of these. Although not shown in FIGS. 1 and 2, at least one conductive layer may be disposed within the base insulating layer (105). The at least one conductive layer may function as wiring connecting different integrated circuits of the substrate (101), or as wiring connecting the integrated circuit to the first to fourth memory cells (MC1, MC2, MC3, MC4).

[0024] A source electrode layer (110) may be disposed on a base insulating layer (105). The source electrode layer (110) may include a conductive material. The conductive material may include, as an example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, as an example, n-type doped silicon, platinum, gold, palladium, molybdenum, nickel, tungsten, titanium, copper, aluminum, ruthenium, iridium, iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these.

[0025] Referring to FIGS. 1 and 2, a drain electrode layer (130) may be disposed spaced apart from the source electrode layer (110) with respect to a direction substantially perpendicular to the surface (101S) of the substrate (101) (e.g., the z-direction). The drain electrode layer (130) may be made of substantially the same material as the source electrode layer (110).

[0026] Referring to FIG. 2, a first oxide channel layer (122) may be disposed between the source electrode layer (110) and the drain electrode layer (130). The first oxide channel layer (122) may be disposed to extend in the direction (e.g., the z-direction) which is substantially perpendicular to the surface (101S) of the substrate (101). Accordingly, the first oxide channel layer (122) may be disposed to be in contact with the source electrode layer (110) and the drain electrode layer (130). The first oxide channel layer (122) may include electrons that move with a predetermined electron mobility along the applied electric field when an electric field is applied between the source electrode layer (110) and the drain electrode layer (130).

[0027] The first oxide channel layer (122) may include a metal oxide. The metal oxide may include, as an example, gallium oxide, indium gallium oxide, indium selenium oxide, indium magnesium oxide, indium gallium zinc oxide, indium tin gallium zinc oxide, indium silver oxide, or a combination of two or more of these.

[0028] Referring to FIG. 2, a second oxide channel layer (124) may be disposed adjacent to the first oxide channel layer (122). In one embodiment, the second oxide channel layer (124) may be disposed in contact with the first oxide channel layer (122). The second oxide channel layer (124) may be disposed to extend in the direction (e.g., z-direction) that is substantially perpendicular to the surface (101S) of the substrate (101) between the source electrode layer (110) and the drain electrode layer (130).

[0029] The second oxide channel layer (124) may be positioned to be in contact with the source electrode layer (110) and the drain electrode layer (130). The second oxide channel layer (124) may include electrons that move with a predetermined electron mobility along the applied electric field when an electric field is applied between the source electrode layer (110) and the drain electrode layer (130).

[0030] The second oxide channel layer (124) may include a metal oxide. The metal oxide may include, as an example, gallium oxide, indium gallium oxide, indium selenium oxide, indium magnesium oxide, indium gallium zinc oxide, indium tin gallium zinc oxide, indium silver oxide, or a combination of two or more of these. The second oxide channel layer (124) may have a different band gap energy from the first oxide channel layer (122). As an example, the second oxide channel layer (124) may have a smaller band gap energy than the first oxide channel layer (122).

[0031] Referring to FIG. 2, a ferroelectric layer (140) may be disposed between the source electrode layer (110) and the drain electrode layer (130), adjacent to the first and second oxide channel layers (124). Specifically, the ferroelectric layer (140) may be disposed on the second oxide channel layer (124). The ferroelectric layer (140) may have a pair of remanent polarizations having different orientations. The ferroelectric layer (140) may be disposed in contact with the second oxide channel layer (124). The ferroelectric layer (140) may be disposed spaced apart from the source electrode layer (110) and the drain electrode layer (130). The ferroelectric layer (140) may include a metal oxide. As an example, the metal oxide may include hafnium oxide, zirconium oxide, hafnium-zirconium oxide, or a combination of two or more of these.

[0032] A gate electrode layer (150) may be disposed on the ferroelectric layer (140). The gate electrode layer (150) may be disposed spaced apart from the source electrode layer (110) and the drain electrode layer (130). The gate electrode layer (150) may include a conductive material. The conductive material may include, as an example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, as an example, n-type doped silicon, platinum, gold, palladium, molybdenum, nickel, tungsten, titanium, copper, aluminum, ruthenium, iridium, iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these.

[0033] Depending on the polarity of the write voltage applied between the gate electrode layer (150) and the first and second oxide channel layers (122, 124), a pair of remanent polarizations having different orientations can be recorded within the ferroelectric layer (140). The remanent polarizations can be stored as signal information within the ferroelectric layer (140).

[0034] Referring again to FIGS. 1 and 2, a first channel protection layer (160) may be disposed to cover a first oxide channel layer (122) on top of a substrate (101). The first channel protection layer (160) may extend in a direction substantially perpendicular to the surface (101S) of the substrate (101). The first channel protection layer (160) may be a pillar-shaped structure. The first channel protection layer (160) may be disposed to passivate the sides of the source electrode layer (110), the first oxide channel layer (122), and the drain electrode layer (130).

[0035] Additionally, a second channel protection layer (170) may be disposed to cover the second oxide channel layer (124) on the upper surface of the substrate (101). The second channel protection layer (170) may be disposed to seal the second oxide channel layer (124) between the source electrode layer (110) and the drain electrode layer (130). The second channel protection layer (170) may be disposed to be in contact with the second oxide channel layer (124) in a direction substantially parallel to the surface (101S) of the substrate (101) (for example, the y-direction).

[0036] Each of the first and second channel protection layers (160, 170) may include an insulating material. In one embodiment, each of the first and second channel protection layers (160, 170) may include a nitride. The nitride may be, for example, silicon nitride or metal nitride. The nitride may inhibit the diffusion of chemicals containing hydrogen (H) or fluorine (F). Accordingly, the first and second channel protection layers (160, 170) may block the inflow of said chemicals from the outside of the first and second oxide channel layers (122, 124) into the inside of the first and second oxide channel layers (122, 124). As a result, said chemicals may be prevented from degrading the electrical properties of the first and second oxide channel layers (122, 124).

[0037] Referring again to FIGS. 1 and 2, the first channel protection layer (160) may be a structure extending in a direction substantially perpendicular to the surface (101S) of the substrate (101) on the base insulating layer (105) (e.g., z-direction). The first channel protection layer (160) may be formed to fill holes (11, 12) formed in a direction substantially perpendicular to the surface (101S) of the substrate (101) (e.g., z-direction) through the first to fourth memory cells (MC1, MC2, MC3, MC4).

[0038] The first oxide channel layer (122), the source electrode layer (110), and the drain electrode layer (130) may be arranged to surround the outer surface of the first channel protection layer (160) on the upper surface of the substrate (101). The second oxide channel layer (124) may be arranged to surround the first channel protection layer (160) on the first oxide channel layer (122). FIG. 4a is a schematic diagram illustrating a first write operation of a semiconductor device according to one embodiment of the present disclosure. FIG. 4b is an energy band diagram of the first and second oxide channel layers corresponding to FIG. 4a. FIG. 5a is a schematic diagram illustrating a second write operation of a semiconductor device according to one embodiment of the present disclosure. FIG. 5b is an energy band diagram of the first and second oxide channel layers corresponding to FIG. 5a. FIG. 4a and FIG. 5a are partial enlarged views of region 'A' of FIG. 2. The first and second write operations of the semiconductor device (1) can be described using a first memory cell (MC1) as an example.

[0039] Referring to FIG. 4a, the first write operation for the first memory cell (MC1) may be performed. The first write operation may proceed by grounding the first and second oxide channel layers (122, 124) and applying a first write voltage having negative polarity to the gate electrode layer (150). The first write voltage may align the polarization of the ferroelectric layer (140) in a first direction. The first direction may be a direction from the second oxide channel layer (124) to the gate electrode layer (150).

[0040] After the first writing voltage is removed, a first residual polarization (P1) aligned in the first direction is formed inside the ferroelectric layer (140), so that the ferroelectric layer (140) can store the first residual polarization (P1) as first signal information. The first residual polarization (P1) can place a negative charge (n) in the internal region of the ferroelectric layer (140) adjacent to the second oxide channel layer (124) and place a positive charge (p) in the internal region of the ferroelectric layer (140) adjacent to the gate electrode layer (150).

[0041] Referring to FIG. 4b, the energy states of the first and second oxide channel layers (122, 124) can be illustrated after the first writing operation has been performed. That is, FIG. 4b may be an energy band diagram of the first and second oxide channel layers (122, 124) after a remanent polarization (P1) has been formed inside the ferroelectric layer (140). Since the band gap energies (Eg-122, Eg-124) of the first and second oxide channel layers (122, 124) are different from each other, band banding may occur at the interface of the first and second oxide channel layers (122, 124). At this time, the Fermi energy level (E) of each of the first and second oxide channel layers (122, 124) F -122, E F -124) may be located between the conduction band and the valence band of the first and second oxide channels (122, 124). In FIG. 4b, 'Ec-122' and 'Ev-122' refer to the conduction band energy and the valence band energy of the first oxide channel layer (122), respectively, and 'Ec-124' and 'Ev-124' refer to the conduction band energy and the valence band energy of the second oxide channel layer (124), respectively.

[0042] Referring to FIG. 5a, the second write operation for the first memory cell (MC1) may be performed. The second write operation may proceed by grounding the first and second oxide channel layers (122, 124) and applying a second write voltage having positive polarity to the gate electrode layer (150). The second write voltage may align the polarization of the ferroelectric layer (140) in a second direction. The second direction may be a direction from the gate electrode layer (150) to the second oxide channel layer (124).

[0043] After the second writing voltage is removed, a second residual polarization (P2) aligned in the second direction is formed inside the ferroelectric layer (140), so that the ferroelectric layer (140) can store the second residual polarization (P2) as second signal information. The second residual polarization (P2) can place a positive charge (p) in the internal region of the ferroelectric layer (140) adjacent to the second oxide channel layer (124) and place a negative charge (n) in the internal region of the ferroelectric layer (140) adjacent to the gate electrode layer (150). Additionally, after the second writing operation, electrons (c) can be accumulated at the interface of the first and second oxide channel layers (122, 124).

[0044] Referring to FIG. 5b, the energy states of the first and second oxide channel layers (122, 124) can be illustrated after the second writing operation is performed. That is, FIG. 5b may be an energy band diagram of the first and second oxide channel layers (122, 124) after a remanent polarization (P2) is formed inside the ferroelectric layer (140). The Fermi energy level (E) of each of the first and second oxide channel layers (122, 124) F -122, E F-124) may be higher than the conduction band energy of the second oxide channel layer (124) at the interface of the first and second oxide channels (122, 124). Accordingly, electrons (c), which are conductive carriers, may be accumulated at the interface of the first and second oxide channels (122, 124).

[0045] Meanwhile, the read operation for the first memory cell (MC1) may proceed by applying a read voltage having positive polarity to the gate electrode layer (150) and applying an operating voltage between the source electrode layer (110) and the drain electrode layer (130) to determine the current flowing between the source electrode layer (110) and the drain electrode layer (130). At this time, the absolute value of the read voltage may be sufficiently small so as not to alter the first and second signal information. In some embodiments, the read voltage may be 0 V.

[0046] When the ferroelectric layer (140) of the first memory cell (MC1) stores the second signal information as described in relation to FIGS. 5a and 5b, electrons accumulated at the interface of the first and second oxide channel layers (122, 124) during the read operation can increase the density of the channel current by conducting between the source electrode layer (110) and the drain electrode layer (130). On the other hand, when the ferroelectric layer (140) of the first memory cell (MC1) stores the first signal information as described in relation to FIGS. 4a and 4b, the channel current conducting between the source electrode layer (110) and the drain electrode layer (130) can be sufficiently low. As an example, the sufficiently low channel current can correspond to the magnitude of the leakage current.

[0047] Accordingly, when performing a read operation on the first memory cell (MC1), the density of the channel current increases due to electrons accumulated at the interface of the first and second oxide channel layers (122, 124), thereby making it easier to identify the second signal information in comparison with the first signal information.

[0048] Meanwhile, according to one embodiment of the present disclosure, a ferroelectric layer (140) may be formed on a second oxide channel layer (124). By forming an interface between the ferroelectric layer (140) containing a metal oxide and the second oxide channel layer (124), an unwanted insulating layer may be prevented from being formed at the interface. In the conventional case, when a ferroelectric layer containing a metal oxide is formed directly on a semiconductor substrate, an interface insulating layer with a low dielectric constant may be formed at the interface between the semiconductor substrate and the ferroelectric layer due to oxidation of the semiconductor substrate. The interface insulating layer may be connected in series with the ferroelectric layer to form a low dielectric layer that is thinner than the ferroelectric layer. Accordingly, when a gate voltage is applied between the semiconductor substrate and the ferroelectric layer for the operation of the transistor, the electric field is concentrated on the interface insulating layer rather than the ferroelectric layer, and a phenomenon may occur in which the endurance of the transistor deteriorates. On the other hand, according to one embodiment of the present disclosure, the formation of an interface insulating layer at the interface between the ferroelectric layer (140) and the second oxide channel layer (124) is prevented, thereby mitigating the deterioration of the durability of the semiconductor device.

[0049] FIGS. 6 to 12 are cross-sectional views schematically illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The method for manufacturing a semiconductor device described in relation to FIGS. 6 to 12 can be applied to the method for manufacturing a semiconductor device (1) described above in relation to FIGS. 1 and 2.

[0050] Referring to FIG. 6, a substrate (1010) is provided. The substrate (1010) may include a semiconductor material. Specifically, the semiconductor material may include silicon, germanium, gallium arsenide, etc. The substrate (101) may be doped with n-type or p-type to have a predetermined conductivity.

[0051] Although not shown in FIG. 6, an integrated circuit may be formed within the substrate (1010). The integrated circuit may include a cell driving circuit that drives and controls a memory cell formed on the upper part of the substrate (1010). As an example, the integrated circuit may include electrical components such as diodes and transistors.

[0052] A base insulating layer (1050) may be formed on a substrate (1010). The base insulating layer (1050) may, as an example, include an oxide, a nitride, an oxynitride, or two or more of these. Although not shown in FIG. 6, at least one conductive layer may be disposed within the base insulating layer (1050). The conductive layer may function as wiring connecting different integrated circuits of the substrate (1010), or as wiring connecting the integrated circuit and the memory cell.

[0053] A stacked structure (1000) can be formed on a base insulating layer (1050). The stacked structure (1000) may include a source electrode material layer (1100), a first protective material layer (1120), a gate electrode material layer (1200), a second protective material layer (1140), a drain electrode material layer (1300), a second protective material layer (1140), a gate electrode material layer (1200), a first protective material layer (1120), and a source electrode material layer (1100) that are stacked sequentially.

[0054] The source electrode material layer (1100), the gate electrode material layer (1200), and the drain electrode material layer (1300) may include a conductive material. The conductive material may include, as an example, n-type doped silicon, platinum, gold, palladium, molybdenum, nickel, tungsten, titanium, copper, aluminum, ruthenium, iridium, iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these. The source electrode material layer (1100), the gate electrode material layer (1200), and the drain electrode material layer (1300) may be formed, as an example, using chemical vapor deposition, atomic layer deposition, or sputtering.

[0055] Each of the first and second protective material layers (1120, 1140) may include a nitride. The nitride may be, for example, silicon nitride or metal nitride. The first and second protective material layers (1120, 1140) may be formed using, for example, chemical vapor deposition, atomic layer deposition, or sputtering. The first and second protective material layers (1120, 1140) may have an etching selectivity with respect to the source electrode material layer (1100), the gate electrode material layer (1200), and the drain electrode material layer (1300).

[0056] Referring to FIG. 7, a hole pattern (H) is formed that penetrates the stacked structure (1000) on the upper surface of the substrate (1010). The hole pattern (H) can be formed by selectively etching the stacked structure (1000). The hole pattern (H) is formed in a direction substantially perpendicular to the surface (1010S) of the substrate (1010) and can expose the base insulating layer (1050).

[0057] Referring to FIG. 8, the first and second protective material layers (1120, 1140) are selectively recessed within the hole pattern (H) to form a first recessed space (R1). Additionally, the gate electrode material layer (1200) is selectively recessed within the hole pattern (H) to form a second recessed space (R2).

[0058] In one embodiment, the process of forming the first recessed space (R1) may include etching the first and second protective material layers (1120, 1140) in a direction substantially parallel to the surface (1010S) of the substrate (1010). Additionally, the process of forming the second recessed space (R2) may include etching the gate electrode material layer (1200) in a direction substantially parallel to the surface (1010S) of the substrate (1010). At this time, the edge (1200E) of the etched gate electrode material layer (1200) may be located further from the hole pattern (H) than the edges (1120E, 1140E) of the etched first and second protective material layers (1120, 1140).

[0059] Referring to FIG. 8, the second recessed space (R2) may be extended further in the lateral direction (e.g., x-direction) than the first recessed space (R1). That is, the gate electrode material layer (1200) may be recessed further in the lateral direction (e.g., x-direction) than the first and second protective material layers (1120, 1140). In this case, the first and second protective material layers (1120, 1140) may be recessed by substantially the same amount. Accordingly, the edges (1120E, 1140E) of the first and second protective material layers (1120, 1140) may be positioned to overlap in a direction substantially perpendicular to the surface (1010S) of the substrate (1010) (e.g., z-direction).

[0060] In one embodiment, the method of forming the first and second recessed spaces (R1, R2) may proceed to a process of selectively etching the first and second protective material layers (1120, 1140) and the gate electrode material layer (1200) by injecting an etching solution having an etching selectivity into the hole pattern (H).

[0061] Referring to FIG. 9, a ferroelectric layer (1400) is formed within a second recess space (R2). In one embodiment, the ferroelectric layer (1400) may be formed to fill the second recess space (R2). The ferroelectric layer (1400) may include a metal oxide. As an example, the metal oxide may include hafnium oxide, zirconium oxide, hafnium-zirconium oxide, or a combination of two or more of these. As an example, the ferroelectric layer (1400) may be formed using chemical vapor deposition or atomic layer deposition, etc.

[0062] Referring to FIG. 10, a first channel material layer (1500) may be formed within a first recess space (R1), and a second channel material layer (1600) may be formed on the first channel material layer (1500). The first channel material layer (1500) may be formed to be in contact with the first and second protective material layers (1120, 1140) and the ferroelectric layer (1400) in a direction substantially parallel to the surface (1010S) of the substrate (1010) (for example, the x-direction). The second channel material layer (1600) may be formed to be in contact with the first channel material layer (1500). In one embodiment, the first recess space (R1) may be filled by the first and second channel material layers (1400, 1500).

[0063] Each of the first and second channel material layers (1400, 1500) may include a metal oxide. As an example, the metal oxide may include gallium oxide, indium gallium oxide, indium selenium oxide, indium magnesium oxide, indium gallium zinc oxide, indium tin gallium zinc oxide, indium silver oxide, or a combination of two or more of these. As an example, the first and second channel material layers (1400, 1500) may be formed using chemical vapor deposition or atomic layer deposition.

[0064] The size of the band gap energy of the first channel material layer (1500) may differ from the size of the band gap energy of the second channel material layer (1600). In one embodiment, the band gap energy of the first channel material layer (1500) may be smaller than the band gap energy of the second channel material layer (1600).

[0065] Referring to FIG. 11, a third protective material layer (1700) can be formed inside a hole pattern (H) on a base insulating layer (1050). The third protective material layer (1700) can be formed to cover at least a second channel material layer (1600). Specifically, it can be formed to cover the sides of the source electrode material layer (1100), the drain electrode material layer (1300), and the second channel material layer (1600). The third protective material layer (1700) may include a nitride. The nitride may be, as an example, silicon nitride or metal nitride.

[0066] In one embodiment, the process of forming the third protective material layer (1700) may proceed to a process of forming a nitride structure that fills the interior of the hole pattern (H1). The third protective material layer (1700) may be formed using, for example, chemical vapor deposition, atomic layer deposition, or sputtering.

[0067] Referring to FIG. 12, a trench pattern (T) is formed between different third protective material layers (1700). The trench pattern (T) may extend in a direction substantially perpendicular to the surface (1010S) of the substrate (1010) (e.g., z-direction) and in a direction substantially parallel to the surface (1010S) of the substrate (1010) (e.g., y-direction), respectively. Subsequently, the interior of the trench pattern (T) may be filled with a conductive material to form a cell separation structure (1800).

[0068] The cell separation structure (1800) may include an insulating material. As an example, the insulating material may include an oxide, a nitride, an oxynitride, or a combination of two or more of these. As an example, the cell separation structure (1800) may include a silicon nitride layer or a metal nitride layer. Through the process described above, a semiconductor device according to one embodiment of the present disclosure can be manufactured.

[0069] FIGS. 13 and FIGS. 14 are cross-sectional views schematically illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Referring to FIG. 13, a cell wafer (2a) and a driving circuit wafer (2b) can each be manufactured.

[0070] The cell wafer (2a) may include a substrate (101a), a base insulating layer (105a), a cell structure (21), a cell wiring structure (22), and a cell capping insulating layer (230). The configuration of the substrate (101a), the base insulating layer (105a), and the cell structure (21) is substantially the same as the configuration of the semiconductor device (1) described in relation to FIGS. 1 and 2. However, the substrate (101a) may not have a cell driving circuit for driving and controlling the cell structure (21). The cell driving circuit may be formed inside the driving circuit wafer (2b).

[0071] A cell wiring structure (22) may be formed on the upper part of a cell structure (21). The cell wiring structure (22) may include at least one cell circuit pattern layer (210) electrically connected to a source electrode layer (110a) and a drain electrode layer (130a). Additionally, the cell wiring structure (22) may include a source contact layer (210C1) and a drain contact layer (210C2) that electrically connect the at least one cell circuit pattern layer (210) to the source electrode layer (110a) and the drain electrode layer (130a). Although not illustrated, the at least one cell circuit pattern layer (210) may be electrically connected to the gate electrode layer of the cell structure (21) through a gate contact layer.

[0072] Additionally, the cell wiring structure (22) may have a cell junction pad (220) electrically connected to at least one cell circuit pattern layer (210). The cell junction pad (220) may be electrically connected to at least one cell circuit pattern layer (210) through a cell pad contact layer (220C). A cell capping insulating layer (230) may be formed to cover the memory cell structure (21) and the cell wiring structure (22) on the upper surface of the substrate (101a).

[0073] Referring again to FIG. 13, the driving circuit wafer (2b) may include a substrate (301), a cell driving circuit (31), a driving circuit wiring structure (32), and a driving circuit capping insulating layer (360). The cell driving circuit (31) may include at least one driving transistor disposed on the substrate (301). The at least one driving transistor may include a gate dielectric layer (311) and a gate electrode layer (312) disposed on the substrate (301), and a well region (313) disposed within the substrate (301).

[0074] A driving circuit wiring structure (32) may be formed on the upper part of a cell driving circuit (31). The driving circuit wiring structure (32) may include a lower driving circuit pattern layer (320) that is electrically connected to a gate electrode layer (312) and a well region (313) through a lower contact layer (320C). Additionally, the driving circuit wiring structure (32) may include at least one upper driving circuit pattern layer (330, 340) that is electrically connected to the lower driving circuit pattern layer (320) through at least one interlayer contact layer (330C, 340C). The driving circuit wiring structure (32) may have a driving circuit junction pad (350) that is electrically connected to at least one upper driving circuit pattern layer (330, 340). The driving circuit junction pad (350) may be electrically connected to at least one upper driving circuit pattern layer (330, 340) through a pad contact layer (350C). The driving circuit capping insulating layer (360) can be formed to cover the cell driving circuit (31) and the driving circuit wiring structure (32) on the upper part of the substrate (301).

[0075] Referring to FIG. 14, a cell wafer (2a) and a driving circuit wafer (2b) are bonded so that the cell bonding pad (220) of the cell wafer (21) and the driving circuit bonding pad (350) of the driving circuit wafer (2b) are electrically connected. Accordingly, the cell bonding pad (220) and the driving circuit bonding pad (350) come into contact with each other, and the cell capping insulating layer (230) and the driving circuit capping insulating layer (360) can come into contact with each other.

[0076] Through the process described above, a semiconductor device (2) according to one embodiment of the present disclosure can be manufactured. The semiconductor device (2) can be manufactured by forming a cell structure (21) and a cell driving circuit (31) on separate substrates and joining the separate substrates. Accordingly, in the semiconductor device (2), the cell driving circuit (31) can be positioned on the upper part of the cell structure (21) with respect to the substrate (101a) of the cell wafer (2a).

[0077] According to the method for manufacturing a semiconductor device according to FIGS. 13 and 14, the difficulty of the process can be reduced compared to the case where a cell driving circuit (31) is formed on a single substrate and then a cell structure (21) is formed on top of the cell driving circuit (31). As an example, the thermal process during the process of forming the cell structure (21) can prevent the cell driving circuit (31) formed on the bottom from being thermally damaged.

[0078] Although the foregoing has been described with reference to the drawings and embodiments, those skilled in the art will understand that various modifications and changes can be made to the embodiments disclosed in this application without departing from the technical spirit of the application as described in the following claims. Explanation of the symbols

[0080] 1, 2: Semiconductor device, 2a: Cell wafer, 2b: Driving circuit wafer, 21: Cell structure, 22: Cell wiring structure, 31: Cell driving circuit, 32: Driving circuit wiring structure, 101, 101a: Substrate, 105, 105a: Base insulating layer, 110, 110a: Source electrode layer, 122: First oxide channel layer, 124: Second oxide channel layer, 130, 130a: Drain electrode layer, 140: Ferroelectric layer, 150: Gate electrode layer, 160: First channel protective layer, 170: Second channel protective layer, 180: Cell separation structure, 210: Cell circuit pattern layer, 210C1: Source contact layer, 210C2: Drain contact layer, 220: Cell junction pad, 230: Cell capping insulating layer, 301: Substrate, 311: Gate dielectric layer, 312: Gate electrode layer, 313: Well region, 320: Lower driving circuit pattern layer, 320C1, 320C2: Lower contact layer, 330, 340: Upper driving circuit pattern layer, 330C, 340C: Interlayer contact layer, 350: Driving circuit junction pad, 350C: Pad contact layer, 360: Driving circuit capping insulation layer, 1000: Laminated structure, 1010: Substrate, 1050: Base insulating layer, 1100: Source electrode material layer, 1120: First protective material layer, 1140: Second protective material layer, 1200: Gate electrode material layer, 1300: Drain electrode material layer, 1400: Ferroelectric layer, 1500: First channel material layer, 1600: Second channel material layer, 1700: Third protective material layer, 1800: Cell separation structure.

Claims

Claim 1 A semiconductor device comprising: a substrate; a source electrode layer and a drain electrode layer spaced apart from each other in a direction perpendicular to the surface of the substrate on the upper portion of the substrate; first and second oxide channel layers having different band gap energies, each arranged to extend in the direction perpendicular to the surface of the substrate between the source electrode layer and the drain electrode layer; a ferroelectric layer arranged adjacent to the first and second oxide channel layers; and a gate electrode layer arranged on the ferroelectric layer, wherein the first and second oxide channel layers are in contact with each other in a lateral direction parallel to the surface of the substrate. Claim 2 A semiconductor device according to claim 1, wherein each of the first and second oxide channel layers is arranged to be in contact with the source electrode layer and the drain electrode layer. Claim 3 A semiconductor device according to claim 1, further comprising first and second channel protection layers disposed to be in contact with the first and second oxide channel layers on the upper surface of the substrate. Claim 4 In claim 3, each of the first and second channel protection layers comprises a nitride semiconductor device. Claim 5 A semiconductor device according to claim 3, wherein the first channel protection layer extends in the direction perpendicular to the surface of the substrate and is arranged to passivate the sides of the source electrode layer, the first oxide channel layer, and the drain electrode layer. Claim 6 A semiconductor device according to claim 3, wherein the second channel protection layer is disposed to seal the second oxide channel layer between the source electrode layer and the drain electrode layer. Claim 7 A semiconductor device according to claim 1, wherein the second oxide channel layer has a smaller band gap energy than the first oxide channel layer. Claim 8 A semiconductor device according to claim 7, wherein each of the first and second oxide channel layers comprises at least one selected from the group consisting of gallium oxide, indium gallium oxide, indium selenium oxide, indium magnesium oxide, indium gallium zinc oxide, indium tin gallium zinc oxide, and indium silver oxide. Claim 9 A semiconductor device according to claim 1, wherein the first oxide channel layer and the second oxide channel layer are arranged to be in contact with each other, and the ferroelectric layer is arranged to be in contact with either of the first and second oxide channel layers. Claim 10 A semiconductor device according to claim 1, further comprising electrons accumulated at the interface of the first and second oxide channel layers when a recording voltage having a positive bias is applied to the gate electrode layer. Claim 11 A semiconductor device according to claim 1, further comprising a cell driving circuit disposed on the substrate above the source electrode layer and the drain electrode. Claim 12 A method for manufacturing a semiconductor device comprising: forming a stacked structure including a source electrode material layer, a first protective material layer, a gate electrode material layer, a second protective material layer, and a drain electrode material layer sequentially stacked on the upper surface of a substrate; forming a hole pattern penetrating the stacked structure on the upper surface of the substrate; selectively recessing the first and second protective material layers within the hole pattern to form a first recessed space; selectively recessing the gate electrode material layer within the hole pattern to form a second recessed space, wherein the second recessed space extends further inwardly than the first recessed space of the gate electrode material layer; forming a ferroelectric layer within the second recessed space; sequentially forming a first channel material layer and a second channel material layer having a band gap energy different from that of the first channel material layer within the first recessed space; and forming a third protective material layer covering at least the second channel material layer within the hole pattern. Claim 13 A method for manufacturing a semiconductor device according to claim 12, wherein the substrate comprises a cell driving circuit disposed on the lower part of the stacked structure. Claim 14 In claim 12, the method for manufacturing a semiconductor device wherein the first to third protective material layers comprise a nitride. Claim 15 A method for manufacturing a semiconductor device according to claim 12, wherein the step of forming the first recessed space includes the step of etching the first and second protective material layers in a direction parallel to the surface of the substrate, and the step of forming the second recessed space includes the step of etching the gate electrode material layer in a direction parallel to the surface of the substrate, and the edge of the etched gate electrode material layer is formed to be located further from the hole pattern than the edge of the etched first and second protective material layers. Claim 16 A method for manufacturing a semiconductor device according to claim 12, wherein each of the first and second channel material layers comprises at least one selected from the group consisting of gallium oxide, indium gallium oxide, indium selenium oxide, indium magnesium oxide, indium gallium zinc oxide, indium tin gallium zinc oxide, and indium silver oxide. Claim 17 A method for manufacturing a semiconductor device according to claim 12, wherein the first channel material layer is formed to be in contact with the first and second protective material layers and the ferroelectric layer in a direction parallel to the surface of the substrate. Claim 18 A method for manufacturing a semiconductor device according to claim 12, wherein the second channel material layer is formed to be in contact with the first channel material layer. Claim 19 A method for manufacturing a semiconductor device according to claim 12, wherein the band gap energy of the first channel material layer is smaller than the band gap energy of the second channel material layer. Claim 20 A method for manufacturing a semiconductor device according to claim 12, wherein the step of forming the third protective material layer comprises a process of forming a nitride structure that fills the interior of the hole pattern. Claim 21 A method for manufacturing a semiconductor device according to claim 12, further comprising the steps of: providing a cell wafer by forming a cell circuit pattern layer electrically connected to the source electrode material layer, the gate electrode material layer, and the drain electrode material layer, respectively, and a cell junction pad electrically connected to the cell circuit pattern layer on the upper surface of the substrate; providing a driving circuit wafer having a cell driving circuit, a driving circuit pattern layer electrically connected to the cell driving circuit, and a driving circuit junction pad electrically connected to the driving circuit pattern layer; and joining the cell wafer and the driving circuit wafer to electrically connect the cell junction pad of the cell wafer and the driving circuit junction pad of the driving circuit wafer.

Images