Display panel and display apparatus including the same

Abstract

The present invention provides a display panel having an extended display area so that an image can be displayed in a corner area, and a display device having the same, comprising: a substrate including a main display area and a first strip portion extending in a first direction from the main display area; a plurality of main pixel circuits arranged in a matrix in the main display area; a plurality of first auxiliary pixel circuits arranged in a row along the first direction in the first strip portion; a first data line connected to a first main pixel circuit in a first column among the plurality of main pixel circuits and a first-1 auxiliary pixel circuit which is part of the plurality of first auxiliary pixel circuits; a second data line connected to a second main pixel circuit in a second column among the plurality of main pixel circuits and a first-2 auxiliary pixel circuit which is part of the plurality of first auxiliary pixel circuits; and a first scan line connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display panel and a display device equipped with the same, and more specifically, to a display panel with an expanded display area so that an image can be displayed even in side and corner areas, and a display device equipped with the same. Background Technology

[0002] Recently, the designs of display devices have become increasingly diverse. For example, curved displays, foldable displays, and rollable displays are being developed. Furthermore, there is a trend toward expanding the display area and shrinking the non-display area. Consequently, various methods are being developed for designing the shapes of display devices. The problem to be solved

[0003] Embodiments of the present invention aim to provide a display panel with an extended display area so that an image can be displayed even in corner areas, and a display device equipped with the same. However, this objective is exemplary and does not limit the scope of the present invention. means of solving the problem

[0004] According to one aspect of the present invention, a display panel is provided comprising: a substrate including a main display area and a first strip portion extending in a first direction from the main display area; a plurality of main pixel circuits arranged in a matrix in the main display area; a plurality of first auxiliary pixel circuits arranged in a row along the first direction in the first strip portion; a first data line connected to a first main pixel circuit in a first column among the plurality of main pixel circuits and a first-1 auxiliary pixel circuit which is part of the plurality of first auxiliary pixel circuits; a second data line connected to a second main pixel circuit in a second column among the plurality of main pixel circuits and a first-2 auxiliary pixel circuit which is part of the plurality of first auxiliary pixel circuits; and a first scan line connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits.

[0005] According to one example, the substrate further includes a second strip portion extending in a second direction intersecting the first direction from the main display area, and the display panel may further include: a plurality of second auxiliary pixel circuits arranged in a row along the second direction in the second strip portion; a third data line connected to a third main pixel circuit in a third column among the plurality of main pixel circuits and a second-1 auxiliary pixel circuit which is part of the plurality of second auxiliary pixel circuits; a fourth data line connected to a fourth main pixel circuit in a fourth column among the plurality of main pixel circuits and a second-2 auxiliary pixel circuit which is part of the plurality of second auxiliary pixel circuits; and a second scan line connected to one of the second-1 auxiliary pixel circuits and one of the second-2 auxiliary pixel circuits.

[0006] According to one example, the first scan line can transmit a first scan signal, and the second scan line can transmit a second scan signal that is substantially synchronized with the first scan signal.

[0007] According to one example, the first scan line transmits a first scan signal, and the second scan line transmits a second scan signal which is a signal that is delayed by n horizontal scan periods compared to the first scan signal. (Here, n is a natural number.)

[0008] According to one example, the substrate further includes a corner display area adjacent to the corner of the main display area, and the first strip portion may be disposed in the corner display area and extend in the first direction from the corner of the main display area.

[0009] According to one example, the display panel may further include a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits; and a light emission control line connected to the one of the first-1 auxiliary pixel circuits and the other, and the one of the first-2 auxiliary pixel circuits and the other.

[0010] According to one example, the first-1 auxiliary pixel circuits and the first-2 auxiliary pixel circuits may be arranged alternately along the first direction.

[0011] According to one example, the display panel further includes a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits, wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal that is delayed by one horizontal scan period compared to the first scan signal.

[0012] According to one example, the display panel may further include a plurality of first auxiliary display elements that are electrically connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits, respectively, and emit light of a first color; and a plurality of second auxiliary display elements that are electrically connected to the other of the first-1 auxiliary pixel circuits and the other of the first-2 auxiliary pixel circuits, respectively, and emit light of a second color different from the first color.

[0013] According to one example, the display panel may further include a plurality of first auxiliary display elements that are electrically connected to one of the first-1 auxiliary pixel circuits and the other of the first-2 auxiliary pixel circuits, respectively, and emit light of a first color; and a plurality of second auxiliary display elements that are electrically connected to the other of the first-1 auxiliary pixel circuits and the one of the first-2 auxiliary pixel circuits, respectively, and emit light of a second color different from the first color.

[0014] According to one example, the display panel further includes a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits, wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal that is delayed by two horizontal scanning periods from the first scan signal.

[0015] According to one example, the display panel may further include a plurality of auxiliary display elements that are electrically connected to one of the first-1 auxiliary pixel circuits and the other, and one of the first-2 auxiliary pixel circuits and emit light of a first color.

[0016] According to one example, the display panel may further include a first auxiliary display element electrically connected to one of the first-1 auxiliary pixel circuits and emitting light of a first color; and a second auxiliary display element electrically connected to one of the first-2 auxiliary pixel circuits and emitting light of a second color different from the first color.

[0017] According to one example, the display panel further includes a third data line connected to the third main pixel circuits of the third column among the plurality of main pixel circuits, and the first-third auxiliary pixel circuits which are another part of the plurality of first auxiliary pixel circuits, and the first scan line may be connected to one of the first-third auxiliary pixel circuits.

[0018] According to another aspect of the present invention, a display device is provided comprising: a display panel including a main display area and a first strip portion extending in a first direction from a corner of the main display area and bent at a predetermined first radius of curvature; and a cover window covering the display panel having a shape corresponding to the shape of the display panel, wherein the display panel comprises: a plurality of main pixel circuits arranged in a matrix in the main display area; a plurality of first auxiliary pixel circuits arranged in a row along the first direction in the first strip portion; a first data line connected to a first main pixel circuit in a first column among the plurality of main pixel circuits and a first-1 auxiliary pixel circuit which is part of the plurality of first auxiliary pixel circuits; a second data line connected to a second main pixel circuit in a second column among the plurality of main pixel circuits and a first-2 auxiliary pixel circuit which is part of the plurality of first auxiliary pixel circuits; and a first scan line connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits.

[0019] According to one example, the display panel may further include: a second strip portion extending from the corner of the main display area in a second direction intersecting the first direction and bent at a preset second radius of curvature; a plurality of second auxiliary pixel circuits arranged in a row along the second direction in the second strip portion; a third data line connected to third main pixel circuits in a third column among the plurality of main pixel circuits and second-1 auxiliary pixel circuits which are part of the plurality of second auxiliary pixel circuits; a fourth data line connected to fourth main pixel circuits in a fourth column among the plurality of main pixel circuits and second-2 auxiliary pixel circuits which are part of the plurality of second auxiliary pixel circuits; and a second scan line connected to one of the second-1 auxiliary pixel circuits and one of the second-2 auxiliary pixel circuits.

[0020] According to one example, the first scan line can transmit a first scan signal, and the second scan line can transmit a second scan signal that is substantially synchronized with the first scan signal.

[0021] According to one example, the first scan line transmits a first scan signal, and the second scan line transmits a second scan signal which is a signal that is delayed by n horizontal scan periods compared to the first scan signal. (Here, n is a natural number.)

[0022] According to one example, the display panel may further include a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits; and a light emission control line connected to the one of the first-1 auxiliary pixel circuits and the other, and the one of the first-2 auxiliary pixel circuits and the other.

[0023] According to one example, the first-1 auxiliary pixel circuits and the first-2 auxiliary pixel circuits may be arranged alternately along the first direction.

[0024] According to one example, the display panel further includes a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits, wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal that is delayed by one horizontal scan period or two horizontal scan periods compared to the first scan signal.

[0025] According to one example, the display panel may further include: a first auxiliary display element electrically connected to one of the first-1 auxiliary pixel circuits and emitting light of a first color; and a second auxiliary display element electrically connected to one of the first-2 auxiliary pixel circuits and emitting light of a second color different from the first color.

[0026] According to one example, the display panel further includes a third data line connected to a third main pixel circuit of a third column among the plurality of main pixel circuits, and a first-to-third auxiliary pixel circuit which is another part of the plurality of first auxiliary pixel circuits, and the first scan line may be connected to one of the first-to-third auxiliary pixel circuits.

[0027] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0028] These general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0029] As described above, the display panel and display device according to the embodiments may have a corner display area so that the area where an image is displayed can be expanded.

[0030] In addition, the display panel and display device according to the present embodiments may be advantageous for saving space as pixel circuits placed in the corner display area share scan lines with each other, thereby reducing the number of wires placed in the corner display area.

[0031] Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0032] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment of the present invention. FIG. 2 is an exemplary cross-sectional view of the display device of FIG. 1 taken along I-I'. FIG. 3 is a schematic plan view showing a display panel that may be included in the display device of FIG. 1 in an unfolded state according to one embodiment. FIG. 4 is an exemplary cross-sectional view of a portion of the display panel of FIG. 3 cut along II-II'. FIG. 5 is an exemplary cross-sectional view of a portion of the display panel of FIG. 3 taken along III-III'. FIG. 6 is a schematic diagram illustrating a pixel arrangement structure that can be applied to the main display area of ​​a display device according to one embodiment of the present invention. FIG. 7 is a schematic diagram illustrating a pixel arrangement structure that can be applied to a corner display area of ​​a display device according to one embodiment of the present invention. FIG. 8 is an equivalent circuit diagram schematically showing a pixel circuit for driving a pixel according to one embodiment of the present invention. FIG. 9 is an equivalent circuit diagram schematically showing a pixel circuit for driving a pixel according to one embodiment of the present invention. FIG. 10 is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention. FIG. 11 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention. FIG. 12 illustrates a timing diagram of control signals for operating the pixel circuits illustrated in FIG. 11. FIG. 13 is a layout diagram showing the arrangement relationship of display elements and pixel circuits arranged in a corner display area of ​​a display panel according to one embodiment of the present invention. FIG. 14 is a layout diagram showing the arrangement relationship of display elements and pixel circuits arranged in a corner display area of ​​a display panel according to one embodiment of the present invention. FIG. 15 is an exemplary cross-sectional view of the auxiliary pixel circuits and auxiliary display elements of FIG. 14 taken along IV-IV'. FIG. 16 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention. FIG. 17 illustrates a timing diagram of control signals for operating the pixel circuits illustrated in FIG. 16. FIG. 18 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention. FIG. 19 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention. FIG. 20 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention. Specific details for implementing the invention

[0033] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0035] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0036] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0037] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0038] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of the other part, but also cases where another film, region, or component is interposed therein.

[0039] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0040] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0041] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0042] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0043] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0044] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment of the present invention.

[0045] Referring to FIG. 1, a display device (1) according to one embodiment is a device for displaying video or still images, and may include various devices that provide a display screen such as a mobile phone, smartphone, tablet PC, smart watch, watch phone, mobile communication terminal, electronic notebook, e-book, PMP (portable multimedia player), navigation, UMPC (Ultra Mobile PC), as well as a television, laptop, monitor, billboard, Internet of Things (IOT).

[0046] The display device (1) may include a main display area (MDA) including a front display area (FDA) and a side display area (SDA), and a corner display area (CDA).

[0047] The front display area (FDA) is an area placed on the front of the display device (1) and may be an area formed flat without being bent. The front display area (FDA) may have a rectangular shape including a short side in the x direction and a long side in the y direction. However, it is not limited thereto. The front display area (FDA) may have various polygonal shapes other than a rectangle, and may have a polygonal shape with rounded corners where the short side and the long side meet.

[0048] The side display area (SDA) may include a first side display area (SDA1), a second side display area (SDA2), a third side display area (SDA3), and a fourth side display area (SDA4).

[0049] The first side display area (SDA1) may be an area that extends from the first side of the front display area (FDA) and is bent at a predetermined curvature. The first side display area (SDA1) may extend from the lower side of the front display area (FDA). The first side display area (SDA1) may be an area positioned on the lower side of the display device (1).

[0050] The second side display area (SDA2) may be an area that extends from the second side of the front display area (FDA) and is bent at a predetermined curvature. The second side display area (SDA2) may extend from the right side of the front display area (FDA). The second side display area (SDA2) may be an area positioned on the right side of the display device (1).

[0051] The third side display area (SDA3) may be an area that extends from the third side of the front display area (FDA) and is bent at a predetermined curvature. The third side display area (SDA3) may extend from the left side of the front display area (FDA). The third side display area (SDA3) may be an area positioned on the left side of the display device (1).

[0052] The fourth side display area (SDA4) may be an area that extends from the fourth side of the front display area (FDA) and is bent at a predetermined curvature. The fourth side display area (SDA4) may extend from the upper side of the front display area (FDA). The fourth side display area (SDA4) may be an area positioned on the upper side of the display device (1).

[0053] The corner display area (CDA) may be a curved area extending from the corner of the main display area (MDA) and having a predetermined curvature. The corner display area (CDA) may be positioned between the first to fourth side display areas (SDA1 to 4). For example, the corner display area (CDA) may be positioned between the first side display area (SDA1) and the second side display area (SDA2), between the first side display area (SDA1) and the third side display area (SDA3), between the second side display area (SDA2) and the fourth side display area (SDA4), and between the third side display area (SDA3) and the fourth side display area (SDA4).

[0054] The display device (1) can provide an image using front pixels (PXf) placed in a front display area (FDA), side pixels (PXs) placed in a side display area (SDA), and corner pixels (or auxiliary pixels) (PXc) placed in a corner display area (CDA).

[0055] In some embodiments, the image displayed in the corner display area (CDA) and / or the side display area (SDA) is an auxiliary image and may have a lower resolution than the image displayed in the front display area (FDA). That is, the number of corner pixels (PXc) per unit area in the corner display area (CDA) may be smaller than the number of front pixels (PXf) per unit area in the front display area (FDA). In some embodiments, the resolution of the side display area (SDA) may be equal to or lower than the resolution of the front display area (FDA).

[0056] FIG. 2 is an exemplary cross-sectional view of the display device of FIG. 1 taken along I-I'.

[0057] Referring to FIG. 2, the display device (1) may include a display panel (10) and a cover window (20) placed on the display panel (10).

[0058] The cover window (20) can serve to cover and protect the display panel (10). The cover window (20) may be made of a transparent material. The cover window (20) may be made of, for example, glass or plastic. If the cover window (20) is made of plastic, the cover window (20) may have flexible properties.

[0059] The shape of the cover window (20) corresponds to the shape of the applied display device (1). For example, as shown in FIG. 1 above, if the display device (1) includes a side display area (SDA) and a corner display area (CDA), the cover window (20) may include a side portion corresponding to the side display area (SDA) and a corner portion corresponding to the corner display area (CDA). The side portion and the corner portion of the cover window (20) may be formed as curved surfaces, and in this case, may have a constant curvature or a changing curvature.

[0060] The display panel (10) may be positioned below the cover window (20). The cover window (20) and the display panel (10) may be joined through an adhesive member (30). The adhesive member (30) may be an optically cleared adhesive film (OCA) or an optically cleared resin (OCR).

[0061] FIG. 3 is a schematic plan view showing a display panel that may be included in the display device of FIG. 1 in an unfolded state according to one embodiment.

[0062] Referring to FIG. 3, various components forming a display panel (10) are arranged on a substrate (100). The substrate (100) includes a front display area (FDA), a side display area (SDA), a corner display area (CDA), and a peripheral area (PA).

[0063] Multiple front pixels (PXf) are arranged in the front display area (FDA), and a main image can be displayed by them. Each front pixel (PXf) can emit red, green, or blue light.

[0064] Side display areas (SDA) can be positioned at the top, bottom, left, and right of the front display area (FDA). Multiple side pixels (PXs) are arranged in the side display areas (SDA), and side images can be displayed through them. The side images may form a single overall image together with the main image, or the side images may be images independent from the main image.

[0065] A corner display area (CDA) may be placed in an area extending from the corner of a main display area (MDA). A corner display area (CDA) may be placed between two side display areas (SDA). Multiple corner pixels (PXc) are placed in the corner display area (CDA), and a corner image may be displayed by them. The corner image may form a single overall image together with the main image and the side image, or the corner image may be an image independent of the main image.

[0066] The corner display area (CDA) may include a first corner display area (CDA1) and a second corner display area (CDA2). The first corner display area (CDA1) is positioned at the edge of the substrate (100) rather than the second corner display area (CDA2), and the second corner display area (CDA2) may be positioned between the first corner display area (CDA1) and the front display area (FDA).

[0067] In addition to the corner pixels (PXc), a first scan driving circuit (SDRV1) may be disposed in the second corner display area (CDA2). The first scan driving circuit (SDRV1) may provide a scan signal for driving the corner pixels (PXc) disposed in the corner display area (CDA). Additionally, the first scan driving circuit (SDRV1) may provide a scan signal for driving the front pixels (PXf) or side pixels (PXs) disposed in the front display area (FDA) or the side display area (SDA). In some embodiments, the first scan driving circuit (SDRV1) may be simultaneously connected to the pixel circuit driving the corner pixels (PXc) and the pixel circuit driving the front pixels (PXf) to provide the same scan signal. In this case, a scan line (SL) connected to the first scan driving circuit (SDRV1) may extend from both sides of the first scan driving circuit (SDRV1) to the front display area (FDA) and the corner display area (CDA).

[0068] The peripheral area (PA) may be positioned outside the side display area (SDA). The peripheral area (PA) may be equipped with a second scan driving circuit (SDRV2) and a terminal portion (PAD).

[0069] The second scan driving circuit (SDRV2) can provide a scan signal for driving front pixels (PXf) and side pixels (PXs). The second scan driving circuit (SDRV2) is positioned to the right of the second side display area (SDA2) and / or to the left of the third side display area (SDA3) and can be connected to a scan line (SL) extended in the x-direction.

[0070] The terminal portion (PAD) may be positioned on the lower side of the first side display area (SDA1). The terminal portion (PAD) is exposed without being covered by an insulating layer and is connected to the display circuit board (FPCB). A display driving portion (32) may be positioned on the display circuit board (FPCB).

[0071] The display driving unit (32) can generate a control signal to be transmitted to the first scan driving circuit (SDRV1) and the second scan driving circuit (SDRV2). Additionally, the display driving unit (32) can generate a data signal. The generated data signal can be transmitted to pixels (PXf, PXs, PXc) through the fan-out wiring (FW) and the data line (DL) connected to the fan-out wiring (FW). The data lines (DL) can each extend in the y-direction and be connected to pixel circuits that drive the front pixels (PXf). The data lines (DL) can each extend in the y-direction and be connected to pixel circuits that drive the side pixels (PXs). The data lines (DL) can extend from the corners of the main display area (MDA, see FIG. 1) and be connected to pixel circuits that drive the corner pixels (PXc). In some embodiments, some data lines (DL) can be simultaneously connected to the pixel circuits that drive the front pixels (PXf) and the pixel circuits that drive the corner pixels (PXc). Some other data lines (DL) can be simultaneously connected to pixel circuits driving side pixels (PXs) and pixel circuits driving corner pixels (PXc).

[0072] FIG. 4 is an exemplary cross-sectional view of a portion of the display panel of FIG. 3 cut along II-II'.

[0073] Referring to FIG. 4, the display panel (10) includes a corner display area (CDA) and a main display area (MDA), and the corner display area (CDA) may include a first corner display area (CDA1) and a second corner display area (CDA2). The display panel (10) may include a substrate (100), a display layer (DISL) on the substrate (100), a touch screen layer (TSL), and an optical function layer (OFL).

[0074] The display layer (DISL) may include a circuit layer (PCL) containing thin-film transistors (TFTm, TFTc, TFTd), a display element layer containing display elements (DEm, DEc), and a thin-film encapsulation layer (TFEL). Insulating layers (IL, IL') may be disposed between the substrate (100) and the display layer (DISL), and within the display layer (DISL).

[0075] The substrate (100) may be made of an insulating material such as glass, quartz, or polymer resin. The substrate (100) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc.

[0076] A main pixel circuit (PCm) and a main display element (DEm) connected thereto may be disposed in the main display area (MDA) of the display panel (10). The main pixel circuit (PCm) includes at least one thin-film transistor (TFTm) and can control the light emission of the main display element (DEm). Meanwhile, since the main display area (MDA) includes a front display area (FDA) and a side display area (SDA) as described above in FIG. 1, the main pixel circuit (PCm) may correspond to the front pixel circuit and / or the side pixel circuit, and the main display element (DEm) may correspond to the front display element and / or the side display element.

[0077] A corner pixel circuit (PCc) and a corner display element (DEc) connected thereto may be disposed in the first corner display area (CDA1) and the second corner display area (CDA2) of the display panel (10). The corner pixel circuit (PCc) includes at least one thin-film transistor (TFTc) and can control the light emission of the corner display element (DEc).

[0078] Meanwhile, a first scan driving circuit (SDRV1) may be disposed in the second corner display area (CDA2) as described above in FIG. 3. The first scan driving circuit (SDRV1) includes at least one thin-film transistor (TFTd) and can provide a scan signal to corner pixel circuits (PCc) disposed in the corner display area (CDA). Corner display elements (DEc) disposed in the first corner display area (CDA1) and the second corner display area (CDA2) may be disposed in the same pixel arrangement. Due to the uniform pixel arrangement of the corner display elements (DEc), the corner display elements (DEc) in the second corner display area (CDA2) may be disposed overlapping with the first scan driving circuit (SDRV1).

[0079] The corner display area (CDA) is a secondary display area, and the resolution of the corner display area (CDA) may be smaller than the resolution of the main display area (MDA). That is, the number of corner display elements (DEc) placed in the corner display area (CDA) per unit area may be smaller than the number of main display elements (DEm) placed in the main display area (MDA) per unit area.

[0080] The corner display element (DEc) placed in the corner display area (CDA) may be provided to be larger than the main display element (DEm) placed in the main display area (MDA). For example, the light-emitting area of ​​the corner display element (DEc) may be provided to be larger than the light-emitting area of ​​the main display element (DEm) placed in the main display area (MDA). This may be intended to provide the same or similar brightness as the main display area (MDA) even with the small resolution of the corner display area (CDA).

[0081] The main display element (DEm) and corner display element (DEc), which are display elements, can be covered by a thin film encapsulation layer (TFEL). In some embodiments, the thin film encapsulation layer (TFEL) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer as shown in FIG. 4. In one embodiment, the thin film encapsulation layer (TFEL) may include first and second inorganic encapsulation layers (131, 133) and an organic encapsulation layer (132) between them.

[0082] The first inorganic encapsulation layer (131) and the second inorganic encapsulation layer (133) are silicon oxide (SiO2) and silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y It may include one or more inorganic insulating materials such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and may be formed by chemical vapor deposition (CVD), etc. The organic encapsulation layer (132) may include a polymer-based material. Polymer-based materials may include silicone resin, acrylic resin, epoxy resin, polyimide, and polyethylene.

[0083] The touch screen layer (TSL) can acquire coordinate information based on external input, such as a touch event. The touch screen layer (TSL) may include touch electrodes and touch wiring connected to the touch electrodes. The touch screen layer (TSL) can detect external input using a magnetic capacitance method or a mutual capacitance method.

[0084] A touch screen layer (TSL) may be formed on a thin film encapsulation layer (TFEL). Alternatively, the touch screen layer (TSL) may be formed separately on a touch substrate and then bonded onto the thin film encapsulation layer (TFEL) through an adhesive layer such as an optically clear adhesive (OCA). In one embodiment, the touch screen layer (TSL) may be formed directly on the thin film encapsulation layer (TFEL), in which case the adhesive layer may not be interposed between the touch screen layer (TSL) and the thin film encapsulation layer (TFEL).

[0085] The optical functional layer (OFL) may include an anti-reflective layer. The anti-reflective layer may reduce the reflectivity of light (external light) incident from the outside toward the display device (1, see FIG. 1). In some embodiments, the optical functional layer (OFL) may be a polarizing film. In some embodiments, the optical functional layer (OFL) may be provided as a filter plate comprising a black matrix and color filters.

[0086] The display panel (10) may be a light-emitting display panel including a light-emitting element. For example, the display panel (10) may be an organic light-emitting display panel using an organic light-emitting diode (OLED) as a light-emitting element, a micro light-emitting diode display panel using a micro LED as a light-emitting element, a quantum dot organic light-emitting display panel using a quantum dot and an organic light-emitting diode, or an inorganic light-emitting display panel using an inorganic semiconductor as a light-emitting element. Below, the description will focus on the case where the display panel (10) is an organic light-emitting display panel.

[0087] FIG. 5 is an exemplary cross-sectional view of a portion of the display panel of FIG. 3 taken along III-III'.

[0088] Referring to FIG. 5, a main pixel circuit (PCm) comprising at least one thin-film transistor (TFT) and a storage capacitor (Cst) and a main display element (DEm) connected to the main pixel circuit (PCm) may be disposed in the main display area (MDA). A main pixel (PXm) may be implemented as a light-emitting area of ​​the main display element (DEm). Meanwhile, since the main display area (MDA) includes a front display area (FDA) and a side display area (SDA) as described above in FIG. 1, the main pixel (PXm) may correspond to a front pixel (PXf) and / or a side pixel (PXs).

[0089] Below, a stacked structure of the components included in the display panel (10) will be described.

[0090] The substrate (100) may be made of an insulating material such as glass, quartz, or polymer resin. The substrate (100) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. In some embodiments, the substrate (100) may have a structure in which an organic layer / an inorganic layer / an organic layer are stacked.

[0091] A buffer layer (111) is positioned on a substrate (100) to reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100) and to provide a flat surface on the substrate (100). The buffer layer (111) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials. A barrier layer (not shown) that blocks the penetration of outside air may be further included between the substrate (100) and the buffer layer (111). In some embodiments, the buffer layer (111) is silicon oxide (SiO2) or silicon nitride (SiN X It can be provided as )

[0092] A thin-film transistor (TFTm) may be disposed on the upper part of the buffer layer (111). The thin-film transistor (TFTm) includes a semiconductor layer (A), a gate electrode (G), a source electrode (S), and a drain electrode (D). The thin-film transistor (TFTm) is connected to a main display element (DEm) to drive the main display element (DEm).

[0093] The semiconductor layer (A) is disposed on the buffer layer (111) and may include polysilicon. In another embodiment, the semiconductor layer (A) may include amorphous silicon. In another embodiment, the semiconductor layer (A) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer (A) may include a channel region, an impurity-doped source region, and a drain region.

[0094] A first gate insulating layer (112) may be provided to cover the semiconductor layer (A). The first gate insulating layer (112) may be silicon oxide (SiO2) or silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y It may include inorganic insulating materials such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The first gate insulating layer (112) may be a single layer or a multilayer containing the aforementioned inorganic insulating material.

[0095] A gate electrode (G) is disposed on the upper portion of the first gate insulating layer (112) so as to overlap with the semiconductor layer (A). The gate electrode (G) may be composed of a single layer or multiple layers, including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. As an example, the gate electrode (G) may be a single layer of Mo.

[0096] The second gate insulating layer (113) may be provided to cover the gate electrode (G). The second gate insulating layer (113) may be silicon oxide (SiO2) or silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y It may include inorganic insulating materials such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second gate insulating layer (113) may be a single layer or a multilayer containing the aforementioned inorganic insulating material.

[0097] An upper electrode (CE2) of a storage capacitor (Cst) may be disposed on the upper portion of the second gate insulating layer (113). The upper electrode (CE2) of the storage capacitor (Cst) may overlap with the gate electrode (G) below it. The gate electrode (G) and the upper electrode (CE2) that overlap with the second gate insulating layer (113) in between may form a storage capacitor (Cst). The gate electrode (G) may function as the lower electrode (CE1) of the storage capacitor (Cst).

[0098] The upper electrode (CE2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or a multilayer of the aforementioned materials.

[0099] The interlayer insulating layer (115) can be formed to cover the upper electrode (CE2). The interlayer insulating layer (115) may be silicon oxide (SiO2) or silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N yIt may include aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. The interlayer insulating layer (115) may be a single layer or a multilayer containing the aforementioned inorganic insulating material.

[0100] The source electrode (S) and the drain electrode (D) may be disposed on an interlayer insulating layer (115). The source electrode (S) and the drain electrode (D) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the source electrode (S) and the drain electrode (D) may be formed as a multilayer structure of Ti / Al / Ti.

[0101] The first organic insulating layer (116) may be disposed on the source electrode (S) and the drain electrode (D). The first organic insulating layer (116) may include photosensitive polyimide, polyimide, polystyrene (PS), polycarbonate (PC), BCB (Benzocyclobutene), HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), general-purpose polymers such as polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, or vinyl alcohol polymers.

[0102] Alternatively, the first organic insulating layer (116) may be provided with a siloxane-based organic material. The siloxane-based organic material may include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, and polydimethylsiloxanes.

[0103] A connecting electrode (CM) and various wiring (WL), such as a driving voltage line or a data line, can be arranged on the upper part of the first organic insulating layer (116), which can be advantageous for high integration.

[0104] The second organic insulating layer (117) may be disposed to cover the connecting electrode (CM) and wiring (WL) on the first organic insulating layer (116). The second organic insulating layer (117) may have a flat upper surface so that the pixel electrode (121) disposed thereon can be formed flatly. The second organic insulating layer (117) may be provided with a siloxane-based organic material having high light transmittance and flatness. The siloxane-based organic material may include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, and polydimethylsiloxanes.

[0105] Alternatively, the second organic insulating layer (117) may include a photosensitive polyimide, a general-purpose polymer such as BCB (Benzocyclobutene), HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, or a vinyl alcohol polymer.

[0106] A main display element (DEm) may be disposed on the second organic insulating layer (117). The pixel electrode (121) of the main display element (DEm) may be connected to the main pixel circuit (PCm) through a connecting electrode (CM) disposed on the first organic insulating layer (116).

[0107] The pixel electrode (121) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode (121) may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the pixel electrode (121) may have a structure having films formed of ITO, IZO, ZnO, or In2O3 above and below the aforementioned reflective film. In this case, the pixel electrode (121) may have a stacked structure of ITO / Ag / ITO.

[0108] The pixel defining film (118) may have an opening (OP) on the second organic insulating layer (117) that covers the edge of the pixel electrode (121) and exposes the central part of the pixel electrode (121). The size and shape of the light-emitting area of ​​the main display element (DEm), that is, the main pixel (PXm), are defined by the opening (OP).

[0109] The pixel defining film (118) can serve to prevent an arc, etc. from occurring at the edge of the pixel electrode (121) by increasing the distance between the edge of the pixel electrode (121) and the opposing electrode (123) above the pixel electrode (121). The pixel defining film (118) can be formed by a method such as spin coating using an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO (hexamethyldisiloxane), and phenolic resin.

[0110] A light-emitting layer (122b) formed to correspond to a pixel electrode (121) is disposed inside the opening (OP) of the pixel defining film (118). The light-emitting layer (122b) may include a high-molecular-weight material or a low-molecular-weight material and may emit red, green, blue, or white light.

[0111] An organic functional layer (122o) may be disposed on the upper and / or lower portion of the light-emitting layer (122b). The organic functional layer (122o) may include a first functional layer (122a) and / or a second functional layer (122c). At least one of the first functional layer (122a) and the second functional layer (122c) may be omitted.

[0112] The first functional layer (122a) may be disposed below the light-emitting layer (122b). The first functional layer (122a) may be a single layer or a multilayer made of organic material. The first functional layer (122a) may be a hole transport layer (HTL) having a single-layer structure. Alternatively, the first functional layer (122a) may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer (122a) may be integrally formed to correspond to the main display elements (DEm) included in the main display area (MDA).

[0113] The second functional layer (122c) may be disposed on top of the light-emitting layer (122b). The second functional layer (122c) may be a single layer or a multilayer made of organic material. The second functional layer (122c) may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer (122c) may be integrally formed to correspond to the main display elements (DEm) included in the main display area (MDA).

[0114] A counter electrode (123) is disposed on the upper portion of the second functional layer (122c). The counter electrode (123) may include a conductive material with a low work function. For example, the counter electrode (123) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode (123) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer comprising the aforementioned materials. The counter electrode (123) may be integrally formed to correspond to the main display elements (DEm) included in the main display area (MDA).

[0115] The layers from the pixel electrode (121) formed in the main display area (MDA) to the counter electrode (123) can form an organic light-emitting diode (OLED).

[0116] An upper layer (150) containing an organic material may be formed on the counter electrode (123). The upper layer (150) may be a layer provided to protect the counter electrode (123) while simultaneously increasing light extraction efficiency. The upper layer (150) may contain an organic material with a higher refractive index than the counter electrode (123). Alternatively, the upper layer (150) may be provided by stacking layers with different refractive indices. For example, the upper layer (150) may be provided by stacking a high refractive index layer, a low refractive index layer, and a high refractive index layer. In this case, the refractive index of the high refractive index layer may be 1.7 or higher, and the refractive index of the low refractive index layer may be 1.3 or lower.

[0117] The upper layer (150) may additionally include LiF. Alternatively, the upper layer (150) may additionally include an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx).

[0118] A thin film encapsulation layer (TFEL) may be disposed on the upper layer (150). The thin film encapsulation layer (TFEL) can prevent external moisture or foreign substances from penetrating into the organic light-emitting diode (OLED).

[0119] The thin film encapsulation layer (TFEL) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, FIG. 5 illustrates a structure in which the thin film encapsulation layer (TFEL) is stacked with a first inorganic encapsulation layer (131), an organic encapsulation layer (132), and a second inorganic encapsulation layer (133). In other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be changed.

[0120] The first inorganic encapsulation layer (131) and the second inorganic encapsulation layer (133) are silicon oxide (SiO2) and silicon nitride (SiN xIt may include one or more inorganic insulating materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and may be formed by chemical vapor deposition (CVD), etc. The organic encapsulation layer (132) may include a polymer-based material. Polymer-based materials may include silicone resin, acrylic resin, epoxy resin, polyimide, and polyethylene. The first inorganic encapsulation layer (131), the organic encapsulation layer (132), and the second inorganic encapsulation layer (133) may be formed integrally to cover the main display area (MDA).

[0121] Meanwhile, although the stacking structure of the main display area (MDA) was explained as an example in Fig. 5, this stacking structure can be applied in the same way to the corner display area (CDA).

[0122] FIG. 6 is a schematic diagram illustrating a pixel arrangement structure that can be applied to the main display area of ​​a display device according to one embodiment of the present invention.

[0123] Referring to FIG. 6, a plurality of main pixels (PXm) may be arranged in the main display area (MDA). In this specification, a pixel refers to a light-emitting area as the minimum unit for implementing an image. A main pixel group (PXGm) may be composed of a set of a predetermined number of main pixels (PXm). A main pixel group (PXGm) may include a first main pixel (PXmr), a second main pixel (PXmg), and a third main pixel (PXmb) that emit different colors. The first main pixel (PXmr), the second main pixel (PXmg), and the third main pixel (PXmb) may each implement red, green, and blue, respectively. In one embodiment, a main pixel group (PXGm) may include one first main pixel (PXmr), two second main pixels (PXmg), and one third main pixel (PXmb).

[0124] As shown in FIG. 6, the main pixels (PXm) placed in the main display area (MDA) can be arranged in a pentile structure.

[0125] In the first row (1N), a plurality of first main pixels (PXmr) and a plurality of third main pixels (PXmb) are alternately arranged, and in the adjacent second row (2N), a plurality of second main pixels (PXmg) are spaced apart at a predetermined interval, and in the adjacent third row (3N), a plurality of third main pixels (PXmb) and a first main pixel (PXmr) are alternately arranged, and in the adjacent fourth row (4N), a plurality of second main pixels (PXmg) are spaced apart at a predetermined interval, and this arrangement of pixels is repeated up to the Nth row. At this time, the third main pixels (PXmb) and the first main pixels (PXmr) may be provided larger than the second main pixels (PXmg).

[0126] A plurality of first main pixels (PXmr) and third main pixels (PXmb) arranged in the first row (1N) and a plurality of second main pixels (PXmg) arranged in the second row (2N) are arranged in an alternating manner. Accordingly, in the first column (1M), the first main pixels (PXmr) and third main pixels (PXmb) are arranged alternately, and in the adjacent second column (2M), a plurality of second main pixels (PXmg) are arranged at a predetermined interval, and in the adjacent third column (3M), the third main pixels (PXmb) and first main pixels (PXmr) are arranged alternately, and in the adjacent fourth column (4M), a plurality of second main pixels (PXmg) are arranged at a predetermined interval, and this arrangement of pixels is repeated up to the Mth column.

[0127] Alternatively, this pixel arrangement structure can be described as follows: among the vertices of a virtual rectangle (VS) with the center point of the second main pixel (PXmg) as the center point of the rectangle, the first main pixel (PXmr) is placed at the first and third vertices facing each other, and the third main pixel (PXmb) is placed at the remaining vertices, namely the second and fourth vertices. In this case, the virtual rectangle (VS) can be modified in various ways, such as a rectangle, a rhombus, or a square.

[0128] This pixel array structure is called a Pentile Matrix structure or Pentile structure, and by applying a rendering drive that expresses color by sharing adjacent pixels, high resolution can be achieved with a small number of pixels.

[0129] Although FIG. 6 illustrates a plurality of main pixels (PXm) arranged in a pentile matrix structure, the present invention is not limited thereto. For example, the plurality of main pixels (PXm) can be arranged in various shapes, such as a stripe structure, a mosaic array structure, or a delta array structure.

[0130] FIG. 7 is a schematic diagram illustrating a pixel arrangement structure that can be applied to a corner display area of ​​a display device according to one embodiment of the present invention.

[0131] Referring to FIG. 7, a plurality of corner pixels (PXc) may be arranged in a corner display area (CDA). A corner pixel group (PXGc) may be composed of a set of a predetermined number of corner pixels (PXc). A corner pixel (PXc) may include a first corner pixel (PXcr), a second corner pixel (PXcg), and a third corner pixel (PXcb) that emit different colors. The first corner pixel (PXcr), the second corner pixel (PXcg), and the third corner pixel (PXcb) may each implement red, green, and blue, respectively. In this embodiment, a single corner pixel (PXc) may include a total of three corner pixels (PXc), the first corner pixel (PXcr), the second corner pixel (PXcg), and the third corner pixel (PXcb).

[0132] In this embodiment, a first corner pixel (PXcr) and a third corner pixel (PXcb) are alternately arranged in the first row (1J), and a second corner pixel (PXcg) may be arranged in the adjacent second row (2J).

[0133] At this time, the second corner pixel (PXcg) can be arranged across the first column (1I) and the second column (2I). That is, the second corner pixel (PXcg) can be provided in a rectangular shape having a longer side in the x' direction.

[0134] The length in the x' direction of the second corner pixel (PXcg) may be equal to or greater than the sum of the length in the x' direction of the first corner pixel (PXcr) and the length in the x' direction of the third corner pixel (PXcb). Accordingly, the size of the second corner pixel (PXcg) may be larger than the sizes of the first corner pixel (PXcr) and the third corner pixel (PXcb). This arrangement structure is called an S-stripe structure.

[0135] Although FIG. 7 illustrates a plurality of corner pixels (PXc) arranged in an S-stripe structure, the present invention is not limited thereto. For example, the plurality of corner pixels (PXc) can be arranged in various shapes such as a stripe structure, a mosaic array structure, a delta array structure, or a pentile matrix structure.

[0136] In the corner display area (CDA), a basic unit (U) comprising a predetermined number of corner pixel groups (PXGc) and non-pixel areas (NPA) where no pixels are placed can be repeatedly arranged in the x' and y' directions. In FIG. 7, the basic unit (U) may have a shape in which one corner pixel group (PXGc) and the surrounding non-pixel areas (NPA) are grouped into a rectangle. The basic unit (U) is a repetitive shape and does not imply a break in the configuration.

[0137] A corresponding unit (U') can be set in the main display area (MDA) with an area equal to that of the basic unit (U). In this case, the number of main pixels (PXm) included in the corresponding unit (U') can be greater than the number of corner pixels (PXc) included in the basic unit (U). That is, the corner pixels (PXc) included in the basic unit (U) can be 3, and the main pixels (PXm) included in the corresponding unit (U') can be 32.

[0138] In this embodiment, the area occupied by one corner pixel group (PXGc) in the basic unit (U) may be approximately 1 / 4 of the basic unit (U). Although FIG. 7 illustrates that the basic unit (U) contains only one corner pixel group (PXGc), in other embodiments, the basic unit (U) may contain two or more corner pixel groups (PXGc). The number or arrangement method of the corner pixels (PXc) included in the corner pixel group (PXGc) may be designed differently depending on the resolution of the corner display area (CA). Additionally, the area of ​​the corner pixels (PXc) included in the corner pixel group (PXGc) may also be varied.

[0139] FIG. 8 is an equivalent circuit diagram schematically showing a pixel circuit for driving a pixel according to one embodiment of the present invention.

[0140] Referring to FIG. 8, a pixel circuit (PC) can be connected to a display element (DE) to enable light emission of the pixels. The pixel circuit (PC) can be connected to a scan line (SL) and a data line (DL). The display element (DE) may be an organic light-emitting diode (OLED). The cathode of the display element (DE) may be a common electrode to which a second driving voltage (ELVSS) is applied.

[0141] The pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst).

[0142] The first transistor (T1) is a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second transistor (T2) may be a switching transistor that is turned on / off according to the gate-source voltage, substantially the gate voltage. The first transistor (T1) and the second transistor (T2) may be formed as thin-film transistors.

[0143] The first transistor (T1) may be referred to as a driving transistor, and the second transistor (T2) may be referred to as a scan transistor.

[0144] A storage capacitor (Cst) is connected between the driving voltage line (PL) and the gate of the driving transistor (T1). The storage capacitor (Cst) may have an upper electrode (CE2) connected to the driving voltage line (PL) and a lower electrode (CE1) connected to the gate of the driving transistor (T1). The storage capacitor (Cst) can store a voltage corresponding to the difference between the voltage received from the scan transistor (T2) and the first driving voltage (ELVDD) supplied to the driving voltage line (PL).

[0145] The driving transistor (T1) can control the magnitude of the driving current (Id) flowing from the driving voltage line (PL) to the display element (DE) according to the gate-source voltage. The display element (DE) can emit light having a predetermined brightness by the driving current (Id). The driving transistor (T1) may have a gate connected to the lower electrode (CE1) of the storage capacitor (Cst), a source connected to the driving voltage line (PL), and a drain connected to the display element (DE).

[0146] The scan transistor (T2) can transmit a data voltage (Dm) to the gate of the driving transistor (T1) in response to a scan signal (Sn). The scan transistor (T2) may have a gate connected to the scan line (SL), a source connected to the data line (DL), and a drain connected to the gate of the driving transistor (T1).

[0147] FIG. 8 describes a case where the pixel circuit (PC) includes two transistors and one storage capacitor, but the present invention is not limited thereto. For example, the pixel circuit (PC) may include three or more transistors and / or two or more storage capacitors. In one embodiment, the pixel circuit (PC) may include seven transistors and one storage capacitor as shown in FIG. 9, which will be described later.

[0148] FIG. 9 is an equivalent circuit diagram schematically showing a pixel circuit for driving a pixel according to one embodiment of the present invention.

[0149] Referring to FIG. 9, the pixel circuit (PC) can be connected to a display element (DE) to enable light emission of the pixels. The display element (DE) may be an organic light-emitting diode (OLED).

[0150] For example, a pixel circuit (PC) includes first to seventh transistors (T1 to T7) and a storage capacitor (Cst), as illustrated in FIG. 9. The first to seventh transistors (T1 to T7) and the storage capacitor (Cst) are connected to a common electrode to which first to third scan lines (SL, SL-1, SL+1) each transmit first to third scan signals (Sn, Sn-1, Sn+1), a data line (DL) transmits a data voltage (Dm), a light emission control line (EL) transmits a light emission control signal (En), a driving voltage line (PL) transmits a first driving voltage (ELVDD), an initialization voltage line (VL) transmits an initialization voltage (Vint), and a second driving voltage (ELVSS) is applied.

[0151] The first transistor (T1) is a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second to seventh transistors (T2 to T7) may be switching transistors that are turned on / off according to the gate-source voltage, substantially the gate voltage. The first to seventh transistors (T1 to T7) may be formed as thin-film transistors.

[0152] The first transistor (T1) is referred to as a driving transistor, the second transistor (T2) is referred to as a scan transistor, the third transistor (T3) is referred to as a compensation transistor, the fourth transistor (T4) is referred to as a gate initialization transistor, the fifth transistor (T5) is referred to as a first light emission control transistor, the sixth transistor (T6) is referred to as a second light emission control transistor, and the seventh transistor (T7) can be referred to as an anode initialization transistor.

[0153] The storage capacitor (Cst) is connected between the driving voltage line (PL) and the gate of the driving transistor (T1). The storage capacitor (Cst) may have an upper electrode (CE2) connected to the driving voltage line (PL) and a lower electrode (CE1) connected to the gate of the driving transistor (T1).

[0154] The driving transistor (T1) can control the magnitude of the driving current (Id) flowing from the driving voltage line (PL) to the display element (DE) according to the gate-source voltage. The driving transistor (T1) may have a gate connected to the lower electrode (CE1) of the storage capacitor (Cst), a source connected to the driving voltage line (PL) through the first light-emitting control transistor (T5), and a drain connected to the display element (DE) through the second light-emitting control transistor (T6).

[0155] The driving transistor (T1) can output a driving current (Id) to the display element (DE) according to the gate-source voltage. The magnitude of the driving current (Id) is determined based on the difference between the gate-source voltage and the threshold voltage of the driving transistor (T1). The display element (DE) receives the driving current (Id) from the driving transistor (T1) and can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0156] The scan transistor (T2) transmits a data voltage (Dm) to the source of the driving transistor (T1) in response to the first scan signal (Sn). The scan transistor (T2) may have a gate connected to the first scan line (SL), a source connected to the data line (DL), and a drain connected to the source of the driving transistor (T1).

[0157] The compensation transistor (T3) is connected in series between the drain and the gate of the driving transistor (T1) and connects the drain and the gate of the driving transistor (T1) to each other in response to the first scan signal (Sn). The compensation transistor (T3) may have a gate connected to the first scan line (SL), a source connected to the drain of the driving transistor (T1), and a drain connected to the gate of the driving transistor (T1). Although the compensation transistor (T3) is shown as being composed of a single transistor in FIG. 9, in another embodiment, the compensation transistor (T3) may include two transistors connected in series with each other.

[0158] The gate initialization transistor (T4) applies an initialization voltage (Vint) to the gate of the driving transistor (T1) in response to the second scan signal (Sn-1). The gate initialization transistor (T4) may have a gate connected to the second scan line (SL-1), a source connected to the gate of the driving transistor (T1), and a drain connected to the initialization voltage line (VL). In FIG. 9, the gate initialization transistor (T4) is shown as being composed of a single transistor, but in another embodiment, the gate initialization transistor (T4) may include two transistors connected in series with each other.

[0159] The anode initialization transistor (T7) applies an initialization voltage (Vint) to the anode of the display element (DE) in response to the third scan signal (Sn+1). The anode initialization transistor (T7) may have a gate connected to the third scan line (SL+1), a source connected to the anode of the display element (DE), and a drain connected to the initialization voltage line (VL).

[0160] The first light-emitting control transistor (T5) can connect the source of the driving voltage line (PL) and the driving transistor (T1) to each other in response to the light-emitting control signal (En). The first light-emitting control transistor (T5) may have a gate connected to the light-emitting control line (EL), a source connected to the driving voltage line (PL), and a drain connected to the source of the driving transistor (T1).

[0161] The second light-emitting control transistor (T6) can connect the drain of the driving transistor (T1) and the anode of the display element (DE) to each other in response to the light-emitting control signal (En). The second light-emitting control transistor (T6) may have a gate connected to the light-emitting control line (EL), a source connected to the drain of the driving transistor (T1), and a drain connected to the anode of the display element (DE).

[0162] The second scan signal (Sn-1) can be substantially synchronized with the first scan signal (Sn) of the previous row. The third scan signal (Sn+1) can be substantially synchronized with the first scan signal (Sn). According to another example, the third scan signal (Sn+1) can be substantially synchronized with the first scan signal (Sn) of the next row.

[0163] In this embodiment, the first to seventh transistors (T1 to T7) may include a semiconductor layer comprising silicon. As an example, the first to seventh transistors (T1 to T7) may include a semiconductor layer comprising low-temperature polysilicon (LTPS). Polysilicon material has high electron mobility (100 cm² / Vs or higher), low energy consumption, and excellent reliability.

[0164] As another example, the semiconductor layers of the first to seventh transistors (T1 to T7) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc.

[0165] As another example, some semiconductor layers of the first to seventh transistors (T1 to T7) may be formed of low-temperature polysilicon (LTPS), and other semiconductor layers may be formed of oxide semiconductors (IGZO, etc.).

[0166] The specific operation process of a pixel of a display device according to one embodiment is described in detail below. As shown in FIG. 9, the first to seventh transistors (T1 to T7) are assumed to be p-type MOSFETs.

[0167] First, when a high-level light emission control signal (En) is received, the first light emission control transistor (T5) and the second light emission control transistor (T6) are turned off, the driving transistor (T1) stops outputting the driving current (Id), and the display element (DE) stops emitting light.

[0168] Subsequently, during the gate initialization period when a low-level second scan signal (Sn-1) is received, the gate initialization transistor (T4) is turned on, and the initialization voltage (Vint) is applied to the gate of the driving transistor (T1), that is, to the lower electrode (CE1) of the storage capacitor (Cst). The difference (ELVDD - Vint) between the first driving voltage (ELVDD) and the initialization voltage (Vint) is stored in the storage capacitor (Cst).

[0169] Subsequently, during the data writing period when a low-level first scan signal (Sn) is received, the scan transistor (T2) and the compensation transistor (T3) are turned on, and the data voltage (Dm) is received at the source of the driving transistor (T1). The driving transistor (T1) is diode-connected by the compensation transistor (T3) and forward-biased. The gate voltage of the driving transistor (T1) rises from the initialization voltage (Vint). When the gate voltage of the driving transistor (T1) becomes equal to the data compensation voltage (Dm - |Vth|), which is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data voltage (Dm), the driving transistor (T1) is turned off, and the rise of the gate voltage of the driving transistor (T1) stops. Accordingly, the difference (ELVDD - Dm + |Vth|) between the first driving voltage (ELVDD) and the data compensation voltage (Dm - |Vth|) is stored in the storage capacitor (Cst).

[0170] Additionally, during the anode initialization period when a low-level third scan signal (Sn+1) is received, the anode initialization transistor (T7) is turned on, and an initialization voltage (Vint) is applied to the anode of the display element (DE). By applying the initialization voltage (Vint) to the anode of the display element (DE) to completely de-emit the display element (DE), the phenomenon in which the display element (DE) emits light even though the pixel (PX) receives a data voltage (Dm) corresponding to a black gradation in the next frame can be eliminated.

[0171] The first scan signal (Sn) and the third scan signal (Sn+1) can be substantially synchronized, in which case the data write period and the anode initialization period may be the same period.

[0172] Subsequently, when a low-level light emission control signal (En) is received, the first light emission control transistor (T5) and the second light emission control transistor (T6) are turned on, and the driving transistor (T1) outputs a driving current (Id) corresponding to the voltage (ELVDD - Dm) obtained by subtracting the threshold voltage (|Vth|) of the driving transistor (T1) from the voltage stored in the storage capacitor (Cst), that is, the source-gate voltage (ELVDD - Dm + |Vth|) of the driving transistor (T1), and the display element (DE) can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0173] FIG. 10 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention. Specifically, it is an enlarged view of a corner display area (CDA) of a display panel (10), showing the display panel (10) in an unfolded state.

[0174] Referring to FIG. 10, the display panel (10) may include a plurality of strip portions (STP) and a plurality of cut portions (V) arranged corresponding to a corner display area (CDA). The plurality of cut portions (V) may be areas formed by cutting the substrate (100) between the plurality of strip portions (STP). The plurality of cut portions (V) may be through-holes provided by penetrating the display panel (10).

[0175] Each end of a plurality of strip sections (STPs) may be spaced apart from one another with a predetermined spacing (gp). By the spacing (gp), empty spaces are formed between the plurality of strip sections (STPs), and each of these empty spaces may correspond to a plurality of incisions (V). The spacing (gp) between the plurality of strip sections (STPs) may be variable. For example, as shown in FIG. 10, the spacing (gp) between the plurality of strip sections (STPs) may widen as it moves from the front display area (FDA) to the corner display area (CDA). As another example, the spacing (gp) between the plurality of strip sections (STPs) may not be variable and may be constant. That is, the plurality of strip sections (STPs) may be arranged radially or arranged parallel to each other.

[0176] Multiple strip sections (STPs) may be connected in a portion adjacent to the front display area (FDA). Multiple strip sections (STPs) may extend from the front display area (FDA). The extended lengths of the multiple strip sections (STPs) may differ from one another. The extended lengths of the multiple strip sections (STPs) may differ depending on the distance from the center of the corner display area (CDA) for each of the multiple strip sections (STPs). For example, among the multiple strip sections (STPs), the strip sections (STPs) located at the center may have a longer extension towards the corner display area (CDA) than the other strip sections (STPs). As the multiple strip sections (STPs) are positioned further from the center of the corner display area (CDA), the extended lengths of the multiple strip sections (STPs) may decrease.

[0177] Each incision (V) can penetrate the front and bottom surfaces of the display panel (10). Each incision (V) can improve the flexibility of the display panel (10). Additionally, when an external force (such as bending, curving, or pulling) is applied to the display panel (10), the shape of the incisions (V) changes, thereby reducing the stress generated during deformation of the display panel (10) and improving the durability of the display panel (10).

[0178] When an external force is applied to the display panel (10), the area or shape of the cut portion (V) may be changed, and the position of the strip portion (STP) may also be changed. For example, when a force is applied to bend the edges of the display panel (10) and the corner sides between them, the area of ​​the cut portion (V) may be reduced as the gap (gp) between the multiple strip portions (STP) decreases, and adjacent strip portions (STP) may come into contact with each other.

[0179] In this way, when an external force is applied to the display panel (10), there may be changes in the spacing (gp) between the multiple strip sections (STP) and the area of ​​the cut section (V), and there may be no change in the shape of the multiple strip sections (STP). That is, pixel circuits and display elements, etc., can be placed on each of the multiple strip sections (STP), and since the shape of the multiple strip sections (STP) does not change even when an external force is applied to the display panel (10), the pixel circuits and display elements, etc., placed on each of the multiple strip sections (STP) can be protected.

[0180] Since the shape of multiple strip portions (STP) may not change, corner pixels (PXc) may be placed in the corner display area (CDA) of the curvature display panel (10). Through this, the display area where an image is implemented can be extended from the front display area (FDA) and the side display area (SDA) to the corner display area (CDA). The corner pixels (PXc) placed on the strip portions (STP) may be spaced apart from each other along one direction.

[0181] FIG. 11 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention.

[0182] Referring to FIG. 11, a plurality of main pixel circuits (PCm) may be arranged in a matrix in the main display area (MDA). As described above in FIG. 4, the main pixel circuits (PCm) are each electrically connected to main display elements (DEm) to control the light emission of the main display elements (DEm).

[0183] Among the multiple main pixel circuits (PCm), the main pixel circuits (PCm) placed in the same column can be connected to the same data line. For example, among a plurality of main pixel circuits (PCm), the first main pixel circuits (PCm1) of the first column (1C) are connected to the first data line (DL1), the second main pixel circuits (PCm2) of the second column (2C) are connected to the second data line (DL2), the third main pixel circuits (PCm3) of the third column (3C) are connected to the third data line (DL3), the fourth main pixel circuits (PCm4) of the fourth column (4C) are connected to the fourth data line (DL4), the fifth main pixel circuits (PCm5) of the fifth column (5C) are connected to the fifth data line (DL5), the sixth main pixel circuits (PCm6) of the sixth column (6C) are connected to the sixth data line (DL6), the seventh main pixel circuits (PCm7) of the seventh column (7C) are connected to the seventh data line (DL7), and the eighth main pixel of the eighth column (8C) The circuits (PCm8) can be connected to the 8th data line (DL8).

[0184] Among the plurality of main pixel circuits (PCm), main pixel circuits (PCm) placed in the same row can be connected to the same scan line. For example, among the plurality of main pixel circuits (PCm), main pixel circuits (PCm) placed in some rows can be connected to the first main scan line (SLm1), and main pixel circuits (PCm) placed in other rows can be connected to the second main scan line (SLm2).

[0185] A first strip portion (STP1) and a second strip portion (STP2) may be disposed in the corner display area (CDA). The first strip portion (STP1) may extend in a first direction (DR1) from the corner of the main display area (MDA), and the second strip portion (STP2) may extend in a second direction (DR2) from the corner of the main display area (MDA).

[0186] In the first strip section (STP1), a plurality of first auxiliary pixel circuits (or, corner pixel circuits) (PCa1) may be arranged in a line along the first direction (DR1). As described above in FIG. 4, each of the first auxiliary pixel circuits (PCa1) is electrically connected to corner display elements (or, auxiliary display elements) (DEc) to control the light emission of the corner display elements (DEc).

[0187] Some of the plurality of first auxiliary pixel circuits (PCa1), such as the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1'), and other parts, such as the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2'), can be connected to different data lines, respectively. For example, some of the plurality of first auxiliary pixel circuits (PCa1), such as the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1'), can be connected to the first data line (DL1), and other parts of the plurality of first auxiliary pixel circuits (PCa1), such as the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2'), can be connected to the second data line (DL2).

[0188] In one embodiment, as shown in FIG. 11, the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') and the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') may be arranged alternately along the first direction (DR1).

[0189] The first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') and the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') may share scan lines. For example, one of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') (PCa1-1) and one of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') (PCa1-2) may be connected to the first auxiliary scan line (SLa1). The other of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') (PCa1-1') and the other of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') (PCa1-2') may be connected to the third auxiliary scan line (SLa3).

[0190] In one embodiment, as illustrated in FIG. 12 to be described later, the first auxiliary scan line (SLa1) transmits the first auxiliary scan signal (GW[n]), and the third auxiliary scan line (SLa3) transmits the third auxiliary scan signal (GW[n+1]) which is delayed by one horizontal scan period (1H) compared to the first auxiliary scan signal (GW[n]).

[0191] In this case, the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') sharing the first data line (DL1) with the first main pixel circuits (PCm1) of the first column (1C) arranged in a pentile matrix structure can each be electrically connected to auxiliary display elements emitting light of a different color. The first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') sharing the second data line (DL2) with the second main pixel circuits (PCm2) of the second column (2C) arranged in a pentile matrix structure can each be electrically connected to auxiliary display elements emitting light of a different color. For example, one of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') (PCa1-1) and one of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') (PCa1-2) may each be electrically connected to auxiliary display elements that emit light of a first color (e.g., red), and the other of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') (PCa1-1') and the other of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') (PCa1-2') may each be electrically connected to auxiliary display elements that emit light of a second color (e.g., blue). This will be described in more detail in FIGS. 13 and 14.

[0192] The first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') and the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') may share light emission control lines. For example, one (PCa1-1) and another (PCa1-1') of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1'), and one (PCa1-2) and another (PCa1-2') of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') may be connected to the first auxiliary light emission control line (ELa1).

[0193] Although FIG. 11 illustrates that four first auxiliary pixel circuits (PCa1) are connected to the first auxiliary light-emitting control line (ELa1), in other embodiments, the number of first auxiliary pixel circuits (PCa1) connected to the first auxiliary light-emitting control line (ELa1) may be changed. For example, two first auxiliary pixel circuits (PCa1) may be connected to the first auxiliary light-emitting control line (ELa1).

[0194] As a comparative example, auxiliary pixel circuits arranged in a row along the longitudinal direction of the strip section may be connected to the same data line. In this case, the auxiliary pixel circuits are each connected to different scan lines so that different data voltages are applied to the auxiliary pixel circuits. Signal lines for driving the auxiliary pixel circuits (e.g., data lines, scan lines, light emission control lines) may be shared from the main display area to both sides of the strip section. In this case, when the auxiliary pixel circuit is used as the pixel circuit of FIG. 9 described above, the total number of shared signal lines may be 3M+(3 / 2)N+1. M is the number of columns of the auxiliary pixel circuits arranged in a matrix on the strip section, and N is the number of rows of the auxiliary pixel circuits arranged in a matrix on the strip section.

[0195] Meanwhile, as in one embodiment of the present invention, auxiliary pixel circuits arranged in a line along the longitudinal direction of the strip section are each connected to different data lines, and the auxiliary pixel circuits connected to different data lines can share scan lines with each other. In this case, the number of data lines shared from the main display area (MDA) to the strip section increases, but the number of scan lines decreases. Taking the case where the auxiliary pixel circuit is used as the pixel circuit of FIG. 9 described above as an example, the total number of shared signal lines may be 6M + ((3 / 2)N) / 2 + 1. For example, when M is 3 and N is 16, according to the equation of the comparative example, there are 34 lines, and according to the equation of one embodiment, there are 31 lines. Therefore, the total number of signal lines shared from the main display area (MDA) to the strip section decreases. Since the total number of signal lines shared to the strip section decreases, the number of pixels placed in the strip section can be increased, and the resolution of the corner display area (CDA) can be increased.

[0196] In the second strip section (STP2), a plurality of second auxiliary pixel circuits (PCa2) can be arranged in a line along the second direction (DR2).

[0197] Some of the multiple second auxiliary pixel circuits (PCa2), such as the second-1 auxiliary pixel circuits (PCa2-1, PCa2-1'), and other parts, such as the second-2 auxiliary pixel circuits (PCa2-2, PCa2-2'), can be connected to different data lines, respectively. For example, some of the multiple second auxiliary pixel circuits (PCa2), such as the second-1 auxiliary pixel circuits (PCa2-1, PCa2-1'), can be connected to the third data line (DL3), and other parts of the multiple second auxiliary pixel circuits (PCa2), such as the second-2 auxiliary pixel circuits (PCa2-2, PCa2-2'), can be connected to the fourth data line (DL4).

[0198] In one embodiment, as shown in FIG. 11, the second-1 auxiliary pixel circuits (PCa2-1, PCa2-1') and the second-2 auxiliary pixel circuits (PCa2-2, PCa2-2') may be arranged alternately along the second direction (DR2).

[0199] The 2-1 auxiliary pixel circuits (PCa2-1, PCa2-1') and the 2-2 auxiliary pixel circuits (PCa2-2, PCa2-2') may share scan lines. For example, one of the 2-1 auxiliary pixel circuits (PCa2-1, PCa2-1') (PCa2-1) and one of the 2-2 auxiliary pixel circuits (PCa2-2, PCa2-2') (PCa2-2) may be connected to the 2nd auxiliary scan line (SLa2). The other of the 2-1 auxiliary pixel circuits (PCa2-1, PCa2-1') (PCa2-1') and the other of the 2-2 auxiliary pixel circuits (PCa2-2, PCa2-2') (PCa2-2') may be connected to the 4th auxiliary scan line (SLa4).

[0200] In one embodiment, as illustrated in FIG. 12 to be described later, a first auxiliary scan line (SLa1) can transmit a first auxiliary scan signal (GW[n]), and a second auxiliary scan line (SLa2) can transmit a second auxiliary scan signal (GW[n+k]) that is delayed by k horizontal scan period (kH) compared to the first auxiliary scan signal (GW[n]). A fourth auxiliary scan line (SLa4) can transmit a fourth auxiliary scan signal (GW[n+1+k]) that is delayed by 1 horizontal scan period (1H) compared to the second auxiliary scan signal (GW[n+k]). Here, k is an integer greater than or equal to 0. When k is 0, the first auxiliary scan signal (GW[n]) and the second auxiliary scan signal (GW[n+k]) can be substantially synchronized.

[0201] The 2-1 auxiliary pixel circuits (PCa2-1, PCa2-1') and the 2-2 auxiliary pixel circuits (PCa2-2, PCa2-2') may share light emission control lines. For example, one (PCa2-1) and another (PCa2-1') of the 2-1 auxiliary pixel circuits (PCa2-1, PCa2-1'), and one (PCa2-2) and another (PCa2-2') of the 2-2 auxiliary pixel circuits (PCa2-2, PCa2-2') may be connected to the 2 auxiliary light emission control line (ELa2).

[0202] In the first strip section (STP1), a plurality of third auxiliary pixel circuits (PCa3) can be arranged in a line along the first direction (DR1).

[0203] Some of the plurality of third auxiliary pixel circuits (PCa3), such as the third-1 auxiliary pixel circuits (PCa3-1, PCa3-1'), and other parts, such as the third-2 auxiliary pixel circuits (PCa3-2, PCa3-2'), can be connected to different data lines, respectively. For example, some of the plurality of third auxiliary pixel circuits (PCa3), such as the third-1 auxiliary pixel circuits (PCa3-1, PCa3-1'), can be connected to the fifth data line (DL5), and other parts of the plurality of third auxiliary pixel circuits (PCa3), such as the third-2 auxiliary pixel circuits (PCa3-2, PCa3-2'), can be connected to the sixth data line (DL6).

[0204] In one embodiment, as shown in FIG. 11, the third-1 auxiliary pixel circuits (PCa3-1, PCa3-1') and the third-2 auxiliary pixel circuits (PCa3-2, PCa3-2') may be arranged alternately along the first direction (DR1).

[0205] The 3-1 auxiliary pixel circuits (PCa3-1, PCa3-1') and the 3-2 auxiliary pixel circuits (PCa3-2, PCa3-2') may share scan lines. For example, one of the 3-1 auxiliary pixel circuits (PCa3-1, PCa3-1') (PCa3-1) and one of the 3-2 auxiliary pixel circuits (PCa3-2, PCa3-2') (PCa3-2) may be connected to the 1st auxiliary scan line (SLa1). The other of the 3-1 auxiliary pixel circuits (PCa3-1, PCa3-1') (PCa3-1') and the other of the 3-2 auxiliary pixel circuits (PCa3-2, PCa3-2') (PCa3-2') may be connected to the 3rd auxiliary scan line (SLa3).

[0206] The 3-1 auxiliary pixel circuits (PCa3-1, PCa3-1') and the 3-2 auxiliary pixel circuits (PCa3-2, PCa3-2') may share light emission control lines. For example, one (PCa3-1) and another (PCa3-1') of the 3-1 auxiliary pixel circuits (PCa3-1, PCa3-1'), and one (PCa3-2) and another (PCa3-2') of the 3-2 auxiliary pixel circuits (PCa3-2, PCa3-2') may be connected to the first auxiliary light emission control line (ELa1).

[0207] In the first strip section (STP1), a plurality of fourth auxiliary pixel circuits (PCa4) can be arranged in a line along the first direction (DR1).

[0208] Some of the plurality of fourth auxiliary pixel circuits (PCa4), such as the fourth-1 auxiliary pixel circuits (PCa4-1, PCa4-1'), and other parts, such as the fourth-2 auxiliary pixel circuits (PCa4-2, PCa4-2'), can be connected to different data lines, respectively. For example, some of the plurality of fourth auxiliary pixel circuits (PCa4), such as the fourth-1 auxiliary pixel circuits (PCa4-1, PCa4-1'), can be connected to the seventh data line (DL7), and other parts of the plurality of fourth auxiliary pixel circuits (PCa4), such as the fourth-2 auxiliary pixel circuits (PCa4-2, PCa4-2'), can be connected to the eighth data line (DL8).

[0209] In one embodiment, as shown in FIG. 11, the 4-1 auxiliary pixel circuits (PCa4-1, PCa4-1') and the 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2') may be arranged alternately along the first direction (DR1).

[0210] The 4-1 auxiliary pixel circuits (PCa4-1, PCa4-1') and the 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2') may share scan lines. For example, one of the 4-1 auxiliary pixel circuits (PCa4-1, PCa4-1') (PCa4-1) and one of the 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2') (PCa4-2) may be connected to the first auxiliary scan line (SLa1). The other of the 4-1 auxiliary pixel circuits (PCa4-1, PCa4-1') (PCa4-1') and the other of the 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2') (PCa4-2') may be connected to the third auxiliary scan line (SLa3).

[0211] The 4-1 auxiliary pixel circuits (PCa4-1, PCa4-1') and the 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2') may share light emission control lines. For example, one (PCa4-1) and another (PCa4-1') of the 4-1 auxiliary pixel circuits (PCa4-1, PCa4-1'), and one (PCa4-2) and another (PCa4-2') of the 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2') may be connected to the first auxiliary light emission control line (ELa1).

[0212] FIG. 12 illustrates a timing diagram of control signals for operating the pixel circuits illustrated in FIG. 11.

[0213] Referring to FIG. 12, in a non-luminous period where the main light emission control signal (EM[m]) has a high level, the first main scan signal (GW[m]) has a low-level pulse voltage and the second main scan signal (GW[m+1]) has a low-level pulse voltage. The period in which the first main scan signal (GW[m]) has a low-level pulse voltage and the period in which the second main scan signal (GW[m+1]) has a low-level pulse voltage can each be referred to as a data writing period.

[0214] The difference between the timing when the first main scan signal (GW[m]) has a falling edge and the timing when the second main scan signal (GW[m+1]) has a falling edge may be 1 horizontal scan period (1H).

[0215] In a non-luminous period where the auxiliary light emission control signal (EM[n]) has a high level, the first auxiliary scan signal (GW[n]) has a low-level pulse voltage and the third auxiliary scan signal (GW[n+1]) has a low-level pulse voltage. The period in which the first auxiliary scan signal (GW[n]) has a low-level pulse voltage and the period in which the third auxiliary scan signal (GW[n+1]) has a low-level pulse voltage can each be referred to as a data writing period.

[0216] The difference between the timing when the first auxiliary scan signal (GW[n]) has a falling edge and the timing when the third auxiliary scan signal (GW[n+1]) has a falling edge may be 1 horizontal scan period (1H).

[0217] Even though the auxiliary pixel circuits placed in the corner display area (CDA, see FIG. 11) and the main pixel circuits placed in the main display area (MDA, see FIG. 11) share a data line, they can be driven sequentially because data is written at different timings as shown in FIG. 12.

[0218] In one embodiment, a first auxiliary scan line (SLa1) disposed in a first strip section (STP1, see FIG. 11) can transmit a first auxiliary scan signal (GW[n]), and a second auxiliary scan line (SLa2) disposed in a second strip section (STP2, see FIG. 11) can transmit a second auxiliary scan signal (GW[n+k]) that is delayed by k horizontal scan period (kH) compared to the first auxiliary scan signal (GW[n]). A fourth auxiliary scan line (SLa4) disposed in a second strip section (STP2) can transmit a fourth auxiliary scan signal (GW[n+1+k]) that is delayed by 1 horizontal scan period (1H) compared to the second auxiliary scan signal (GW[n+k]). Here, k is an integer greater than or equal to 0. When k is 0, the first auxiliary scan signal (GW[n]) and the second auxiliary scan signal (GW[n+k]) can be substantially synchronized.

[0219] FIG. 13 is a layout diagram showing the arrangement relationship of display elements and pixel circuits arranged in a corner display area of ​​a display panel according to an embodiment of the present invention. Specifically, FIG. 13 shows the arrangement relationship of auxiliary display elements and auxiliary pixel circuits in the first row (1R) of FIG. 11.

[0220] First, referring to FIG. 13, the first-1 auxiliary pixel circuit (PCa1-1), the third-1 auxiliary pixel circuit (PCa3-1), and the fourth-1 auxiliary pixel circuit (PCa4-1) of the first row (1R) are arranged sequentially along the third direction (DR3).

[0221] The first auxiliary display element (DEa1) emits light of a first color (e.g., red) and can be electrically connected to the first-1 auxiliary pixel circuit (PCa1-1). The first auxiliary display element (DEa1) can be connected to the first-1 auxiliary pixel circuit (PCa1-1) by a first connecting electrode (CM1). The first auxiliary display element (DEa1) can overlap with the first-1 auxiliary pixel circuit (PCa1-1). The first auxiliary display element (DEa1) can implement the first corner pixel (PXcr) illustrated in FIG. 7 above.

[0222] The second auxiliary display element (DEa2) emits light of a second color (e.g., green) and can be electrically connected to the third-1 auxiliary pixel circuit (PCa3-1). The second auxiliary display element (DEa2) can be connected to the third-1 auxiliary pixel circuit (PCa3-1) by a second connecting electrode (CM2). The second auxiliary display element (DEa2) can overlap with the first-1 auxiliary pixel circuit (PCa1-1), the third-1 auxiliary pixel circuit (PCa3-1), and the fourth-1 auxiliary pixel circuit (PCa4-1). The second auxiliary display element (DEa2) can implement the second corner pixel (PXcg) illustrated in FIG. 7 above.

[0223] The third auxiliary display element (DEa3) emits light of a third color (e.g., blue) and can be electrically connected to the fourth-1 auxiliary pixel circuit (PCa4-1). The third auxiliary display element (DEa3) can be connected to the fourth-1 auxiliary pixel circuit (PCa4-1) by a third connecting electrode (CM3). The third auxiliary display element (DEa3) can overlap with the fourth-1 auxiliary pixel circuit (PCa4-1). The third auxiliary display element (DEa3) can implement the third corner pixel (PXcb) illustrated in FIG. 7 above.

[0224] Although the first-1 auxiliary pixel circuit (PCa1-1), the third-1 auxiliary pixel circuit (PCa3-1), and the fourth-1 auxiliary pixel circuit (PCa4-1) of the first row (1R) have been described, the first-2 auxiliary pixel circuit (PCa1-2), the third-2 auxiliary pixel circuit (PCa3-2), and the fourth-2 auxiliary pixel circuit (PCa4-2) of the second row (2R) shown in FIG. 11 can be applied in the same way.

[0225] For example, referring to FIG. 11 described above, one of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') (PCa1-1) and one of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') (PCa1-2) can be electrically connected to a plurality of first auxiliary display elements (DEa1) that emit light of a first color (e.g., red).

[0226] FIG. 14 is a layout diagram showing the arrangement relationship of display elements and pixel circuits arranged in a corner display area of ​​a display panel according to an embodiment of the present invention. Specifically, FIG. 14 shows the arrangement relationship of auxiliary display elements and auxiliary pixel circuits in the third row (3R) of FIG. 11.

[0227] Referring to FIG. 14, the first-1 auxiliary pixel circuit (PCa1-1'), the third-1 auxiliary pixel circuit (PCa3-1'), and the fourth-1 auxiliary pixel circuit (PCa4-1') of the third row (3R) are arranged sequentially along the third direction (DR3).

[0228] The first auxiliary display element (DEa1') emits light of a first color (e.g., red) and can be electrically connected to the first-1 auxiliary pixel circuit (PCa1-1'). The first auxiliary display element (DEa1') can be connected to the first-1 auxiliary pixel circuit (PCa1-1') by a first connecting electrode (CM1'). The first connecting electrode (CM1') can extend across the top of the third-1 auxiliary pixel circuit (PCa3-1'). The first connecting electrode (CM1') can overlap with the first-1 auxiliary pixel circuit (PCa1-1'), the third-1 auxiliary pixel circuit (PCa3-1'), and the fourth-1 auxiliary pixel circuit (PCa4-1'). The first auxiliary display element (DEa1') can overlap with the first-1 auxiliary pixel circuit (PCa1-1'). The first auxiliary display element (DEa1') can implement the first corner pixel (PXcr) illustrated in FIG. 7 above.

[0229] The second auxiliary display element (DEa2') emits light of a second color (e.g., green) and can be electrically connected to the third-1 auxiliary pixel circuit (PCa3-1'). The second auxiliary display element (DEa2') can be connected to the third-1 auxiliary pixel circuit (PCa3-1') by a second connecting electrode (CM2'). The second auxiliary display element (DEa2') can overlap with the first-1 auxiliary pixel circuit (PCa1-1'), the third-1 auxiliary pixel circuit (PCa3-1'), and the fourth-1 auxiliary pixel circuit (PCa4-1'). The second auxiliary display element (DEa2') can implement the second corner pixel (PXcg) illustrated in FIG. 7 above.

[0230] The third auxiliary display element (DEa3') emits light of a third color (e.g., blue) and can be electrically connected to the fourth-1 auxiliary pixel circuit (PCa4-1'). The third auxiliary display element (DEa3') can be connected to the fourth-1 auxiliary pixel circuit (PCa4-1') by a third connecting electrode (CM3'). The third connecting electrode (CM3') can extend across the top of the third-1 auxiliary pixel circuit (PCa3-1'). The third connecting electrode (CM3') can overlap with the first-1 auxiliary pixel circuit (PCa1-1'), the third-1 auxiliary pixel circuit (PCa3-1'), and the fourth-1 auxiliary pixel circuit (PCa4-1'). The third auxiliary display element (DEa3') can overlap with the fourth-1 auxiliary pixel circuit (PCa4-1'). The third auxiliary display element (DEa3) can implement the third corner pixel (PXcb) illustrated in FIG. 7 above.

[0231] Although the first-1 auxiliary pixel circuit (PCa1-1'), the third-1 auxiliary pixel circuit (PCa3-1'), and the fourth-1 auxiliary pixel circuit (PCa4-1') of the third row (3R) have been described, the first-2 auxiliary pixel circuit (PCa1-2'), the third-2 auxiliary pixel circuit (PCa3-2'), and the fourth-2 auxiliary pixel circuit (PCa4-2') of the fourth row (4R) shown in FIG. 11 can be applied in the same way.

[0232] For example, referring to the aforementioned FIG. 11, another one (PCa1-1') of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') and another one (PCa1-2') of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') can be electrically connected to a plurality of third auxiliary display elements (DEa3') that emit light of a third color (e.g., blue).

[0233] FIG. 15 is an exemplary cross-sectional view of the auxiliary pixel circuits and auxiliary display elements of FIG. 14 taken along IV-IV'. In FIG. 15, the same reference numerals as in FIG. 5 refer to the same components, and their redundant description is omitted.

[0234] Referring to FIG. 15, the display panel (10) may include a substrate (100), a first-1 auxiliary pixel circuit (PCa1-1'), a third-1 auxiliary pixel circuit (PCa3-1'), a fourth-1 auxiliary pixel circuit (PCa4-1'), a second auxiliary display element (DEa2'), and a third auxiliary display element (DEa3') disposed on the substrate (100). The second auxiliary display element (DEa2') may implement a second corner pixel (PXcg), and the third auxiliary display element (DEa3) may implement a third corner pixel (PXcb).

[0235] In some corner display areas (CDA), the 4-1 auxiliary pixel circuit (PCa4-1') may overlap with the 3rd auxiliary display element (DEa3') and may not overlap with the 1st auxiliary display element (DEa1', see FIG. 14). Additionally, the 1-1 auxiliary pixel circuit (PCa1-1') may not overlap with the 3rd auxiliary display element (DEa3'). Accordingly, the 1-1 auxiliary pixel circuit (PCa1-1') may be connected to the 3rd auxiliary display element (DEa3') that implements the 3rd corner pixel (PXcb) through the 3rd connecting electrode (CM3').

[0236] A third connecting electrode (CM3') is disposed on the first organic insulating layer (116), and one end of the third connecting electrode (CM3') can be connected to the first-1 auxiliary pixel circuit (PCa1-1') through a contact hole defined in the first organic insulating layer (116). The other end of the third connecting electrode (CM3') can be connected to the pixel electrode (121) of the third auxiliary display element (DEa3') that implements the third corner pixel (PXcb). A second organic insulating layer (117) is disposed between the third connecting electrode (CM3') and the pixel electrode (121), and the pixel electrode (121) can be connected to the third connecting electrode (CM3') through a contact hole defined in the second organic insulating layer (117). The third connecting electrode (CM3') can be disposed overlapping with the third-1 auxiliary pixel circuit (PCa3-1').

[0237] FIG. 16 illustrates the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to an embodiment of the present invention, and FIG. 17 illustrates a timing diagram of control signals for operating the pixel circuits shown in FIG. 16. FIG. 16 and FIG. 17 are modified embodiments of FIG. 11 and FIG. 12, respectively, and differ in scan signal timing. Hereinafter, overlapping content will be replaced by the description of FIG. 11 and FIG. 12, and the differences will be explained primarily.

[0238] First, referring to FIG. 17, unlike in FIG. 12, the first auxiliary scan line (SLa1) can transmit the first auxiliary scan signal (GW[n]), and the third auxiliary scan line (SLa3) can transmit the third auxiliary scan signal (GW[n+2]) which is delayed by 2 horizontal scan periods (2H) compared to the first auxiliary scan signal (GW[n]).

[0239] In this case, as illustrated in FIG. 16, the first main pixel circuits (PCm1) of the first column (1C) arranged in a pentile matrix structure and the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') sharing the first data line (DL1) can each be electrically connected to auxiliary display elements that emit light of the same color. The second main pixel circuits (PCm2) of the second column (2C) arranged in a pentile matrix structure and the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') sharing the second data line (DL2) can each be electrically connected to auxiliary display elements that emit light of the same color. For example, one (PCa1-1) and another (PCa1-1') of the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1'), and one (PCa1-2) and another (PCa1-2') of the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') can each be electrically connected to auxiliary display elements that emit light of a first color (e.g., red).

[0240] FIG. 18 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to an embodiment of the present invention. FIG. 18 is a modified embodiment of FIG. 11, differing in the structure of the auxiliary pixel circuits. Hereinafter, redundant content will be replaced by the description of FIG. 11, and the differences will be explained primarily.

[0241] Referring to FIG. 18, the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') and the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') may not be arranged alternately along the first direction (DR1). For example, the first-1 auxiliary pixel circuits (PCa1-1, PCa1-1') may be arranged adjacent to each other, and the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2') may be arranged adjacent to each other.

[0242] In this case, the above description in FIG. 13 may be applied to the auxiliary pixel circuits of the first row (1R') and the third row (3R') of FIG. 18, and the above description in FIG. 14 may be applied to the auxiliary pixel circuits of the second row (2R') and the fourth row (4R') of FIG. 18.

[0243] FIG. 19 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to an embodiment of the present invention. FIG. 19 is a modified embodiment of FIG. 11, and differs in the structure of the auxiliary pixel circuits. Hereinafter, redundant content will be replaced by the description of FIG. 11, and the differences will be explained primarily.

[0244] Referring to FIG. 19, unlike FIG. 11 described above, the first-2 auxiliary pixel circuits (PCa1-2, PCa1-2'), which are other parts of the plurality of first auxiliary pixel circuits (PCa1), can be connected to the seventh data line (DL7). The third-2 auxiliary pixel circuits (PCa3-2, PCa3-2'), which are other parts of the plurality of third auxiliary pixel circuits (PCa3), can be connected to the ninth data line (DL9), which is connected to the ninth main pixel circuits (PCm9) of the ninth column (9C) among the plurality of main pixel circuits (PCm). The fourth-1 auxiliary pixel circuits (PCa4-1, PCa4-1'), which are some parts of the plurality of fourth auxiliary pixel circuits (PCa4), can be connected to the eighth data line (DL8). The 4-2 auxiliary pixel circuits (PCa4-2, PCa4-2'), which are other parts of the plurality of 4th auxiliary pixel circuits (PCa4), can be connected to the 2nd data line (DL2).

[0245] In this case, the details described in FIG. 13 may be applied to the auxiliary pixel circuits of the first row (1R'') and the fourth row (4R'') of FIG. 19, and the details described in FIG. 14 may be applied to the auxiliary pixel circuits of the second row (2R'') and the third row (3R'') of FIG. 19.

[0246] Although the explanation was based on the first strip section (STP1), the same can be applied to the second strip section (STP2). For example, the first and second auxiliary pixel circuits (PCa1-2, PCa1-2'), which are different parts of the plurality of first auxiliary pixel circuits (PCa1), can be connected to the 10th data line (DL10) connected to the 10th main pixel circuits (PCm10) of the 10th column (10C) among the plurality of main pixel circuits (PCm).

[0247] FIG. 20 shows the pixel circuit array structure and some signal lines of the main display area and corner display area of ​​a display panel according to one embodiment of the present invention.

[0248] Referring to FIG. 20, a plurality of main pixel circuits can be arranged in a matrix in the main display area (MDA).

[0249] Among the plurality of main pixel circuits, main pixel circuits arranged in the same column may be connected to the same data line. For example, among the plurality of main pixel circuits, the first main pixel circuits (PCm1') in the first column (1C') may be connected to the first data line (DL1'), the second main pixel circuits (PCm2') in the second column (2C') may be connected to the second data line (DL2'), and the third main pixel circuits (PCm3') in the third column (3C') may be connected to the third data line (DL3').

[0250] Among a plurality of main pixel circuits, main pixel circuits placed in the same row can be connected to the same scan line. For example, among a plurality of main pixel circuits, main pixel circuits placed in some rows can be connected to a first main scan line (SLm1'), and main pixel circuits placed in other rows can be connected to a second main scan line (SLm2').

[0251] A first strip section (STP1) may be placed in the corner display area (CDA). The first strip section (STP1) may extend from the corner of the main display area (MDA) in a first direction (DR1).

[0252] In the first strip section (STP1), a plurality of first auxiliary pixel circuits (PCa1') can be arranged in a line along the first direction (DR1).

[0253] Some of the plurality of first auxiliary pixel circuits (PCa1'), such as the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), some of the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and some of the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3'''), can be connected to different data lines, respectively. For example, some of the plurality of first auxiliary pixel circuits (PCa1'), such as first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), may be connected to the first data line (DL1'), some of the plurality of first auxiliary pixel circuits (PCa1'), such as first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), may be connected to the second data line (DL2'), and some of the plurality of first auxiliary pixel circuits (PCa1'), such as first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3'''), may be connected to the third data line (DL3').

[0254] In one embodiment, as shown in FIG. 20, the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') may be arranged alternately along the first direction (DR1).

[0255] The first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') may share scan lines with each other. For example, one of the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1''') (PCa1-1''), one of the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2''') (PCa1-2''), and one of the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') (PCa1-3'') may be connected to the first auxiliary scan line (SLa1'). The other one (PCa1-1''') of the 1-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), the other one (PCa1-2''') of the 1-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and the other one (PCa1-3''') of the 1-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') can be connected to the 2nd auxiliary scan line (SLa2').

[0256] In one embodiment, the first auxiliary scan line (SLa1') transmits a first auxiliary scan signal, and the second auxiliary scan line (SLa2') transmits a second auxiliary scan signal that is delayed by one horizontal scan period compared to the first auxiliary scan signal.

[0257] In this case, the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1''') sharing the first data line (DL1') with the first main pixel circuits (PCm1') of the first column (1C') arranged in a pentile matrix structure can each be electrically connected to auxiliary display elements emitting light of a different color. The first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2''') sharing the second data line (DL2') with the second main pixel circuits (PCm2') of the second column (2C') arranged in a pentile matrix structure can each be electrically connected to auxiliary display elements emitting light of a different color. The third main pixel circuits (PCm3') of the third column (3C') arranged in a pentile matrix structure and the first-third auxiliary pixel circuits (PCa1-3'', PCa1-3''') sharing the third data line (DL3') can each be electrically connected to auxiliary display elements that emit light of different colors. For example, one of the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), one of the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and one of the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') are each electrically connected to auxiliary display elements that emit light of a first color (e.g., red), and another of the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), another of the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') The other one (PCa1-3''') can be electrically connected to auxiliary display elements that emit light of a second color (e.g., blue).

[0258] In other words, the above description in FIG. 13 applies to the auxiliary pixel circuits of the first row (1R'''), second row (2R'''), and third row (3R''') of FIG. 20, and the above description in FIG. 14 may apply to the auxiliary pixel circuits of the fourth row (4R'''), fifth row (5R'''), and sixth row (6R''') of FIG. 20.

[0259] In another embodiment, the first auxiliary scan line (SLa1') transmits a first auxiliary scan signal, and the second auxiliary scan line (SLa2') transmits a second auxiliary scan signal that is delayed by two horizontal scan periods compared to the first auxiliary scan signal.

[0260] In this case, the first main pixel circuits (PCm1') of the first column (1C') arranged in a pentile matrix structure and the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1''') sharing the first data line (DL1') can each be electrically connected to auxiliary display elements that emit light of the same color. The second main pixel circuits (PCm2') of the second column (2C') arranged in a pentile matrix structure and the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2''') sharing the second data line (DL2') can each be electrically connected to auxiliary display elements that emit light of the same color. The third main pixel circuits (PCm3') of the third column (3C') arranged in a pentile matrix structure and the first-third auxiliary pixel circuits (PCa1-3'', PCa1-3''') sharing the third data line (DL3') can each be electrically connected to auxiliary display elements that emit light of the same color. For example, one (PCa1-1'') and another (PCa1-1''') of the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), one (PCa1-2'') and another (PCa1-2''') of the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and one (PCa1-3'') and another (PCa1-3''') of the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') may each be electrically connected to auxiliary display elements that emit light of a first color (e.g., red).

[0261] In other words, the above description in FIG. 13 can be applied to the auxiliary pixel circuits of the first row (1R'''), second row (2R'''), third row (3R'''), fourth row (4R'''), fifth row (5R'''), and sixth row (6R''') of FIG. 20.

[0262] The 1-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), 1-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and 1-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') can share light emission control lines with each other. For example, one (PCa1-1'') and another (PCa1-1''') of the first-1 auxiliary pixel circuits (PCa1-1'', PCa1-1'''), one (PCa1-2'') and another (PCa1-2''') of the first-2 auxiliary pixel circuits (PCa1-2'', PCa1-2'''), and one (PCa1-3'') and another (PCa1-3''') of the first-3 auxiliary pixel circuits (PCa1-3'', PCa1-3''') can be connected to an auxiliary light emission control line (ELa).

[0263] So far, the explanation has been based on the first auxiliary pixel circuits (PCa1') placed in some columns of the first strip section (STP1), but the same can be applied to auxiliary pixel circuits placed in other columns.

[0264] Although the present invention has primarily described display panels and display devices so far, it is not limited thereto. For example, a method for manufacturing such a display panel and a method for manufacturing a display device are also considered to fall within the scope of the present invention.

[0265] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0266] 1: Display device 10: Display panel MDA: Main display area FDA: Front display area SDA: Side display area CDA: Corner display area STP1, STP2: 1st and 2nd strip sections PCm: Main pixel circuit PCa1, PCa2, PCa3, PCa4: 1st to 4th auxiliary pixel circuits

Claims

Claim 1 A substrate comprising a main display area and a first strip portion extending in a first direction from the main display area; a plurality of main pixel circuits arranged in a matrix in the main display area, wherein all main pixel circuits arranged in a first column among the plurality of main pixel circuits are defined as first main pixel circuits, and all main pixel circuits arranged in a second column among the plurality of main pixel circuits are defined as second main pixel circuits; a plurality of first auxiliary pixel circuits arranged in a row along the first direction in the first strip portion, wherein the plurality of first auxiliary pixel circuits include first-1 auxiliary pixel circuits and first-2 auxiliary pixel circuits; a first data line connected to all of the first main pixel circuits and the first-1 auxiliary pixel circuits; a second data line connected to all of the second main pixel circuits and the first-2 auxiliary pixel circuits; and a first scan line connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits. Claim 2 In claim 1, the substrate further comprises a second strip portion extending in a second direction intersecting the first direction from the main display area, wherein all main pixel circuits arranged in a third column among the plurality of main pixel circuits are defined as third main pixel circuits, and all main pixel circuits arranged in a fourth column among the plurality of main pixel circuits are defined as fourth main pixel circuits, and the display panel further comprises a plurality of second auxiliary pixel circuits arranged in a row along the second direction in the second strip portion, wherein the plurality of second auxiliary pixel circuits include second-1 auxiliary pixel circuits and second-2 auxiliary pixel circuits; a third data line connected to all the third main pixel circuits and the second-1 auxiliary pixel circuits; a fourth data line connected to all the fourth main pixel circuits and the second-2 auxiliary pixel circuits; and a second scan line connected to one of the second-1 auxiliary pixel circuits and one of the second-2 auxiliary pixel circuits. Claim 3 In claim 2, the first scan line transmits a first scan signal, and the second scan line transmits a second scan signal substantially synchronized with the first scan signal, in a display panel. Claim 4 In claim 2, the first scan line transmits a first scan signal, and the second scan line transmits a second scan signal which is a signal that is delayed by n horizontal scanning periods from the first scan signal. (Here, n is a natural number.) Claim 5 In claim 1, the substrate further includes a corner display area adjacent to the corner of the main display area, and the first strip portion is disposed in the corner display area and is a display panel extending in the first direction from the corner of the main display area. Claim 6 A display panel according to claim 1, further comprising: a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits; and a light emission control line connected to the one of the first-1 auxiliary pixel circuits and the other, and the one of the first-2 auxiliary pixel circuits and the other. Claim 7 In claim 1, the first-1 auxiliary pixel circuits and the first-2 auxiliary pixel circuits are alternately arranged along the first direction in a display panel. Claim 8 A display panel according to claim 1, further comprising a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits, wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal delayed by one horizontal scan period compared to the first scan signal. Claim 9 A display panel further comprising: a plurality of first auxiliary display elements electrically connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits, respectively, and emitting light of a first color; and a plurality of second auxiliary display elements electrically connected to the other of the first-1 auxiliary pixel circuits and the other of the first-2 auxiliary pixel circuits, respectively, and emitting light of a second color different from the first color. Claim 10 A display panel further comprising: a plurality of first auxiliary display elements electrically connected to one of the first-1 auxiliary pixel circuits and the other of the first-2 auxiliary pixel circuits, each emitting light of a first color; and a plurality of second auxiliary display elements electrically connected to the other of the first-1 auxiliary pixel circuits and the one of the first-2 auxiliary pixel circuits, each emitting light of a second color different from the first color. Claim 11 A display panel according to claim 1, further comprising a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits, wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal delayed by 2 horizontal scanning periods from the first scan signal. Claim 12 A display panel according to claim 11, further comprising a plurality of auxiliary display elements electrically connected to one of the first-1 auxiliary pixel circuits and the other, and one of the first-2 auxiliary pixel circuits and the other, and emitting light of a first color. Claim 13 A display panel according to claim 1, further comprising: a first auxiliary display element electrically connected to one of the first-1 auxiliary pixel circuits and emitting light of a first color; and a second auxiliary display element electrically connected to one of the first-2 auxiliary pixel circuits and emitting light of a second color different from the first color. Claim 14 In claim 1, all main pixel circuits arranged in a third column among the plurality of main pixel circuits are defined as third main pixel circuits, and the plurality of first auxiliary pixel circuits further include first-third auxiliary pixel circuits, and the display panel further includes a third data line connected to all of the third main pixel circuits and the first-third auxiliary pixel circuits, and the first scan line is connected to one of the first-third auxiliary pixel circuits. Claim 15 A display panel comprising a main display area and a first strip portion extending in a first direction from a corner of the main display area and bent at a preset first radius of curvature; and a cover window covering the display panel having a shape corresponding to the shape of the display panel, wherein the display panel comprises a plurality of main pixel circuits arranged in a matrix in the main display area, wherein all main pixel circuits arranged in a first column among the plurality of main pixel circuits are defined as first main pixel circuits, and all main pixel circuits arranged in a second column among the plurality of main pixel circuits are defined as second main pixel circuits; a plurality of first auxiliary pixel circuits arranged in a row along the first direction in the first strip portion, wherein the plurality of first auxiliary pixel circuits include first-1 auxiliary pixel circuits and first-2 auxiliary pixel circuits; and a first data line connected to all of the first main pixel circuits and the first-1 auxiliary pixel circuits. A display device comprising: a second data line connected to all of the above-mentioned second main pixel circuits and the above-mentioned first-second auxiliary pixel circuits; and a first scan line connected to one of the above-mentioned first-first auxiliary pixel circuits and one of the above-mentioned first-second auxiliary pixel circuits. Claim 16 In claim 15, all main pixel circuits arranged in a third column among the plurality of main pixel circuits are defined as third main pixel circuits, and all main pixel circuits arranged in a fourth column among the plurality of main pixel circuits are defined as fourth main pixel circuits, and the display panel further comprises: a second strip portion that extends from the corner of the main display area in a second direction intersecting the first direction and is bent at a preset second radius of curvature; a plurality of second auxiliary pixel circuits arranged in a row along the second direction in the second strip portion, wherein the plurality of second auxiliary pixel circuits include second-1 auxiliary pixel circuits and second-2 auxiliary pixel circuits; a third data line connected to all the third main pixel circuits and the second-1 auxiliary pixel circuits; a fourth data line connected to all the fourth main pixel circuits and the second-2 auxiliary pixel circuits; and a second scan line connected to one of the second-1 auxiliary pixel circuits and one of the second-2 auxiliary pixel circuits. Claim 17 In claim 16, a display device wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal substantially synchronized with the first scan signal. Claim 18 In claim 16, the first scan line transmits a first scan signal, and the second scan line transmits a second scan signal which is a signal that is delayed by n horizontal scanning periods from the first scan signal (where n is a natural number). Claim 19 In claim 15, the display panel further comprises: a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits; and a light emission control line connected to the one of the first-1 auxiliary pixel circuits and the other, and the one of the first-2 auxiliary pixel circuits and the other. Claim 20 In claim 15, the first-1 auxiliary pixel circuits and the first-2 auxiliary pixel circuits are alternately arranged along the first direction in a display device. Claim 21 In claim 15, the display panel further comprises a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits, wherein the first scan line transmits a first scan signal and the second scan line transmits a second scan signal that is delayed by one horizontal scan period or two horizontal scan periods from the first scan signal. Claim 22 In claim 15, the display panel further comprises: a first auxiliary display element electrically connected to one of the first-1 auxiliary pixel circuits and emitting light of a first color; and a second auxiliary display element electrically connected to one of the first-2 auxiliary pixel circuits and emitting light of a second color different from the first color. Claim 23 In claim 15, all main pixel circuits arranged in a third column among the plurality of main pixel circuits are defined as third main pixel circuits, and the plurality of first auxiliary pixel circuits further include first-third auxiliary pixel circuits, and the display panel further includes a third data line connected to all of the third main pixel circuits and the first-third auxiliary pixel circuits, and the first scan line is connected to one of the first-third auxiliary pixel circuits. Claim 24 A display panel according to claim 1, wherein the first data line is connected to at least two of the first-1 auxiliary pixel circuits and the second data line is connected to at least two of the first-2 auxiliary pixel circuits. Claim 25 A display device according to claim 15, wherein the first data line is connected to at least two of the first-1 auxiliary pixel circuits and the second data line is connected to at least two of the first-2 auxiliary pixel circuits. Claim 26 A substrate comprising a main display area and a first strip portion extending in a first direction from the main display area; a plurality of main pixel circuits arranged in a matrix in the main display area, wherein the plurality of main pixel circuits include a first main pixel circuit arranged in a first column of the matrix and a second main pixel circuit arranged in a second column of the matrix; a plurality of first auxiliary pixel circuits arranged in a row in the first strip portion, wherein the plurality of first auxiliary pixel circuits include a first-1 auxiliary pixel circuit and a first-2 auxiliary pixel circuit; a first scan line connected to one of the first-1 auxiliary pixel circuits and one of the first-2 auxiliary pixel circuits; a second scan line connected to another of the first-1 auxiliary pixel circuits and another of the first-2 auxiliary pixel circuits; a first data line connected to the first main pixel circuits, the first of the first-1 auxiliary pixel circuits, and the other of the first-1 auxiliary pixel circuits; the second main pixel circuits, the A display panel comprising one of the first-2 auxiliary pixel circuits and a second data line connected to the other of the first-2 auxiliary pixel circuits, wherein the one of the first-1 auxiliary pixel circuits, the other of the first-1 auxiliary pixel circuits, the one of the first-2 auxiliary pixel circuits, and the other of the first-2 auxiliary pixel circuits are arranged in a line along the first direction within the first strip portion.

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