Display apparatus

Abstract

The present invention provides a display device capable of preventing pixel defects caused by static electricity generated from the outside, comprising: a first pixel and a second pixel arranged adjacently along a row direction; a first vertical power line extending in a column direction on the first pixel and configured to transmit a driving voltage to the first pixel; a second vertical power line extending in a column direction on the second pixel and configured to transmit the driving voltage to the second pixel; and a semiconductor pattern comprising a first pixel area included in the first pixel, a second pixel area included in the second pixel, and a connection area connecting the first vertical power line and the second vertical power line to each other.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] A display device includes multiple pixels that receive electrical signals and emit light to display an image externally. Each pixel includes a light-emitting element; for example, in the case of an organic light-emitting display, it includes an Organic Light Emitting Diode (OLED) as the light-emitting element. Generally, an organic light-emitting display forms thin-film transistors and organic light-emitting diodes on a substrate, and operates by the organic light-emitting diode emitting light on its own.

[0004] Recently, as the applications of display devices have become more diverse, various design attempts are being made to improve the quality of display devices. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device capable of preventing pixel defects caused by static electricity generated from the outside.

[0006] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description of the present invention. means of solving the problem

[0007] According to one aspect of the present invention, a display device is provided comprising: a first pixel and a second pixel arranged adjacently along a row direction; a first vertical power line extending in a column direction on the first pixel and configured to deliver a driving voltage to the first pixel; a second vertical power line extending in a column direction on the second pixel and configured to deliver the driving voltage to the second pixel; and a semiconductor pattern comprising a first pixel area included in the first pixel, a second pixel area included in the second pixel, and a connection area connecting the first vertical power line and the second vertical power line to each other.

[0008] According to one example, the display device may further include an insulating layer interposed between the semiconductor pattern and the first and second vertical power lines; a first contact plug that penetrates the insulating layer and connects the first vertical power line to one end of the connection area of ​​the semiconductor pattern; and a second contact plug that penetrates the insulating layer and connects the second vertical power line to the other end of the connection area of ​​the semiconductor pattern.

[0009] According to one example, the display device may further include a third pixel disposed adjacent to the second pixel along the row direction; a first voltage wiring configured to transmit a first initialization voltage; a second voltage wiring configured to transmit a second initialization voltage; and a third contact plug connecting the second pixel and the third pixel to the second voltage wiring.

[0010] According to one example, the display device may further include a fourth contact plug connecting the first pixel to the first voltage line; a fifth contact plug connecting the second pixel to the first voltage line; and a sixth contact plug connecting the third pixel to the first voltage line.

[0011] According to one example, the display device comprises the first to third pixels and a plurality of pixels arranged along the row direction and the column direction; a plurality of first vertical power lines extending in the column direction on a pixel in row i-j-1 of the plurality of pixels and configured to transmit the driving voltage to the pixel in row i-j-1; a plurality of second vertical power lines extending in the column direction on a pixel in row i-j of the plurality of pixels and configured to transmit the driving voltage to the pixel in row i-j; and a plurality of third contact plugs connecting the pixel in row i-j and the pixel in row i-j+1 of the plurality of pixels to the second voltage wiring, and the semiconductor pattern may further include a plurality of connection areas connecting the plurality of first vertical power lines and the plurality of second vertical power lines to each other.

[0012] According to one example, the semiconductor pattern may further include a plurality of pixel regions each included in pixels arranged along the row direction among the plurality of pixels, and a plurality of contact regions each corresponding to the plurality of third contact plugs.

[0013] According to one example, the plurality of connection regions each connect the pixel region in row i, column j-1 and the pixel region in row i, column j among the plurality of pixel regions, and the plurality of contact regions each connect the pixel region in row i, column j and the pixel region in row i, column j+1 among the plurality of pixel regions.

[0014] According to one example, the plurality of connection regions and the plurality of contact regions may be arranged alternately along the row direction.

[0015] According to one example, the plurality of first vertical power lines and the plurality of second vertical power lines may be arranged alternately along the row direction, and the plurality of third contact plugs may be arranged along the column direction.

[0016] According to one example, each of the first to third pixels may include: a light-emitting element; a driving transistor that controls the current flowing to the light-emitting element according to a gate-source voltage; a scan transistor that transmits a data voltage to the driving transistor in response to a first scan signal; a storage capacitor having a first electrode and a second electrode connected to the gate of the driving transistor; a first initialization transistor that applies the first initialization voltage to the electrode of the driving transistor in response to a second scan signal; and a second initialization transistor that applies the second initialization voltage to the electrode of the light-emitting element in response to a third scan signal.

[0017] According to one example, the display device further comprises a first data line extending in the column direction and configured to transmit a first data voltage to the first pixel; and a second data line extending in the column direction and configured to transmit a second data voltage to the second pixel, wherein the first data line and the second data line may be positioned between the first vertical power line and the second vertical power line.

[0018] According to one example, the connection area of ​​the semiconductor pattern can always electrically connect the first vertical power line and the second vertical power line.

[0019] According to one example, the display device may further include a horizontal power line that extends in the row direction on the first pixel and the second pixel and is electrically connected to the first vertical power line and the second vertical power line.

[0020] According to one example, the connection area can connect the first pixel area and the second pixel area to each other.

[0021] According to another aspect of the present invention, a display device is provided comprising: first to third pixels arranged sequentially along a row direction; a first voltage wiring configured to transmit a first initialization voltage; a second voltage wiring configured to transmit a second initialization voltage; a power line configured to transmit a driving voltage; a first contact plug connecting the first pixel and the second pixel to the power line; and a second contact plug connecting the second pixel and the third pixel to the second voltage wiring.

[0022] According to one example, the display device may further include a third contact plug connecting the first pixel to the first voltage line; a fourth contact plug connecting the second pixel to the first voltage line; and a fifth contact plug connecting the third pixel to the first voltage line.

[0023] According to one example, the display device may further include the first to third pixels and a plurality of pixels arranged along the row direction and column direction; a plurality of first contact plugs connecting the pixel in row i, column j-1 and the pixel in row i, column j among the plurality of pixels to the power line; and a plurality of second contact plugs connecting the pixel in row i, column j and the pixel in row i, column j+1 among the plurality of pixels to the second voltage line.

[0024] According to one example, the plurality of first contact plugs and the plurality of second contact plugs are alternately arranged along the row direction, and the plurality of first contact plugs and the plurality of second contact plugs may each be arranged along the column direction.

[0025] According to one example, the power line includes a plurality of vertical power lines extending in the column direction, and the second voltage wiring includes a plurality of vertical wirings extending in the column direction, and the plurality of vertical power lines and the plurality of vertical wirings can be arranged alternately along the row direction.

[0026] According to one example, the power line may further include a plurality of horizontal power lines that extend in the row direction and are electrically connected to a plurality of vertical power lines.

[0027] Other aspects, features, and advantages other than those described above will become clear from the specific details, claims, and drawings for implementing the invention below.

[0028] These general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0029] According to various embodiments of the present invention, by forming a semiconductor pattern that extends continuously in one direction as a single unit, pixel defect problems, such as damage to the semiconductor pattern caused by external static electricity, can be improved. Accordingly, defects in the display device can be prevented. Brief explanation of the drawing

[0030] FIG. 1 is a schematic block diagram of a display device according to one embodiment. FIG. 2 schematically illustrates a plurality of pixels according to one embodiment. FIG. 3a illustrates equivalent circuit diagrams of each of a plurality of pixels according to one embodiment. FIG. 3b is a plan view schematically illustrating a plurality of pixels according to one embodiment. FIG. 4 illustrates a semiconductor pattern according to one embodiment. FIG. 5 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 6 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 7 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 8 illustrates equivalent circuit diagrams of each of a plurality of pixels according to another embodiment. FIG. 9 illustrates a semiconductor pattern according to another embodiment. FIG. 10 is a cross-sectional view schematically illustrating a display device according to another embodiment. Specific details for implementing the invention

[0031] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0033] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0034] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0035] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0036] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of the other part, but also cases where another film, region, or component is interposed therein.

[0037] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0038] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0039] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0040] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0041] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0042] FIG. 1 is a schematic block diagram of a display device according to one embodiment.

[0043] The display device may be an organic light-emitting display that includes a light-emitting element whose brightness changes according to an electric current, such as an organic light-emitting diode. Alternatively, the display device may be an inorganic light-emitting display (or inorganic EL display) or a quantum dot light-emitting display. That is, the light-emitting layer of the light-emitting element provided in the display device may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, an inorganic material and a quantum dot, or an organic material, an inorganic material, and a quantum dot. Below, the description will focus on the case where the display device is an organic light-emitting display.

[0044] Referring to FIG. 1, the organic light-emitting display device (100) includes a display unit (110), a gate driving unit (120), a data driving unit (130), a timing control unit (140), and a voltage generating unit (150).

[0045] The display unit (110) includes pixels (PX), such as the pixel (PXij) located in the i-th row and j-th column. For ease of understanding, only one pixel (PXij) is shown in FIG. 1, but m x n pixels (PX) can be arranged, for example, in a matrix form. Here, i is a natural number between 1 and m, and j is a natural number between 1 and n.

[0046] In FIG. 1, the invention is described with reference to a pixel (PX) comprising seven transistors and one capacitor solely for exemplary purposes. However, the present invention is not applicable only to a pixel (PX) employing this specific pixel circuit, but can be equally applied to other pixel circuits, such as a pixel (PX) employing a pixel circuit comprising two transistors and one capacitor.

[0047] Pixels (PX) are connected to first scan lines (SL1_1 to SL1_m), second scan lines (SL2_1 to SL2_m+1), light emission control lines (EML_1 to EML_m), and data lines (DL_1 to DL_n). Pixels (PX) are connected to a power line (PL), a first voltage line (VL1), and a second voltage line (VL2). For example, as shown in FIG. 1, a pixel (PXij) located in row i, column j may be connected to a first scan line (SL1_i), a second scan line (SL2_i), a light emission control line (EML_i), a data line (DL_j), a power line (PL), a first voltage line (VL1), a second voltage line (VL2), and a second scan line (SL2_i+1). The second scan line (SL2_i+1) may be referred to as a third scan line with respect to the pixel (PXij).

[0048] According to another example, a pixel (PXij) may be connected to some of the lines of the first scan line (SL1_i), the second scan line (SL2_i), the light emission control line (EML_i), the data line (DL_j), the power line (PL), the first voltage line (VL1), the second voltage line (VL2), and the second scan line (SL2_i+1). For example, the pixel (PXij) may be connected to the first scan line (SL1_i), the data line (DL_j), and the power line (PL).

[0049] Data lines (DL_1 to DL_n) may be extended in a first direction (or, column direction) (DR1) and connected to pixels (PX) located in the same column. First scan lines (SL1_1 to SL1_m), second scan lines (SL2_1 to SL2_m+1), and light emission control lines (EML_1 to EML_m) may be extended in a second direction (or, row direction) (DR2) and connected to pixels (PX) located in the same row.

[0050] A power line (PL) may include a plurality of vertical power lines extending in a first direction (DR1), and the plurality of vertical power lines may be connected to pixels (PX) located in the same column. In one embodiment, as shown in FIG. 8 which will be described later, the plurality of vertical power lines may be shared between pixels (PX) adjacent to each other in a second direction (DR2).

[0051] A power line (PL) may include a plurality of horizontal power lines as illustrated in FIG. 3a, which will be described later, and the plurality of horizontal power lines may be connected to pixels (PX) located in the same row. The plurality of horizontal power lines may each be connected to the plurality of vertical power lines.

[0052] Each of the first voltage line (VL1) and the second voltage line (VL2) may include a plurality of vertical lines extending in a first direction (DR1), and the plurality of vertical lines may be connected to pixels (PX) located in the same column. In one embodiment, as shown in FIGS. 3a and FIGS. 8 to be described later, the plurality of vertical lines of the second voltage line (VL2) may be shared between pixels (PX) adjacent to each other in a second direction (DR2).

[0053] At least one of the first voltage wiring (VL1) and the second voltage wiring (VL2) may include a plurality of horizontal wirings as shown in FIG. 3a, which will be described later, and may be connected to each of the plurality of vertical wirings.

[0054] Each of the first scan lines (SL1_1 to SL1_m) transmits first scan signals (GW_1 to GW_m) output from the gate driver (120) to pixels (PX) in the same row, each of the second scan lines (SL2_1 to SL2_m) transmits second scan signals (GI_1 to GI_m) output from the gate driver (120) to pixels (PX) in the same row, and each of the second scan lines (SL2_2 to SL2_m+1) transmits third scan signals (GB_1 to GB_m) output from the gate driver (120) to pixels (PX) in the same row. The second scan signal (GI_i) and the third scan signal (GB_i-1) may be the same signal transmitted through the second scan line (SL2_i).

[0055] Each of the light emission control lines (EML_1 to EML_m) transmits light emission control signals (EM_1 to EM_m) output from the gate driver (120) to pixels (PX) in the same row. Each of the data lines (DL_1 to DL_n) transmits data voltages (Dm_1 to Dm_n) output from the data driver (130) to pixels (PX) in the same column. A pixel (PXij) located in the i-th row and j-th column receives first to third scan signals (GW_i, GI_i, GB_i), a data voltage (Dm_j), and a light emission control signal (EM_i).

[0056] The power line (PL) transmits a first driving voltage (ELVDD) output from the voltage generating unit (150) to the pixels (PX). The first voltage line (VL1) transmits a first initialization voltage (VINT1) output from the voltage generating unit (150) to the pixels (PX). The second voltage line (VL2) transmits a second initialization voltage (VINT2) output from the voltage generating unit (150) to the pixels (PX).

[0057] A pixel (PXij) includes a light-emitting element and a driving transistor that controls the magnitude of the current flowing to the light-emitting element based on a data voltage (Dm_j). The data voltage (Dm_j) is output from a data driving unit (130) and received by the pixel (PXij) via a data line (DL_j). The light-emitting element may be, for example, an organic light-emitting diode. By the light-emitting element emitting light with a brightness corresponding to the magnitude of the current received from the driving transistor, the pixel (PXij) can express a gradation corresponding to the data voltage (Dm_j). The pixel (PX) may correspond to a part of a unit pixel capable of displaying full color, for example, a subpixel. The pixel (PXij) may further include at least one switching transistor and at least one capacitor. The pixel (PXij) will be described in more detail below.

[0058] The voltage generation unit (150) can generate voltages required for driving the pixel (PXij). For example, the voltage generation unit (150) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT1), and a second initialization voltage (VINT2). The level of the first driving voltage (ELVDD) may be higher than the level of the second driving voltage (ELVSS). The level of the second initialization voltage (VINT2) may be higher than the level of the first initialization voltage (VINT1). The level of the second initialization voltage (VINT2) may be higher than the level of the second driving voltage (ELVSS). The difference between the second initialization voltage (VINT2) and the second driving voltage (ELVSS) may be smaller than the threshold voltage required for the light-emitting element of the pixel (PX) to emit light.

[0059] Although not shown in FIG. 1, the voltage generation unit (150) may generate a first gate voltage (VGH) and a second gate voltage (VGL) for controlling the switching transistor of the pixel (PXij) and provide them to the gate driver (120). When the first gate voltage (VGH) is applied to the gate of the switching transistor, the switching transistor is turned off, and when the second gate voltage (VGL) is applied to the gate of the switching transistor, the switching transistor can be turned on. The first gate voltage (VGH) may be referred to as the turn-off voltage, and the second gate voltage (VGL) may be referred to as the turn-on voltage. The switching transistors of the pixel (PXij) may be p-type MOSFETs, and the level of the first gate voltage (VGH) may be higher than the level of the second gate voltage (VGL). Although not shown in FIG. 1, the voltage generation unit (150) may generate gamma reference voltages and provide them to the data driver (130).

[0060] The timing control unit (140) can control the display unit (110) by controlling the operation timing of the gate driving unit (120) and the data driving unit (130). The pixels (PX) of the display unit (110) receive a new data voltage (Dm) for each frame period and emit light with a brightness corresponding to the data voltage (Dm), thereby displaying an image corresponding to the image source data (RGB) of one frame.

[0061] According to one embodiment, a frame period may include a gate initialization period, a data write and anode initialization period, and a light emission period. During the initialization period, a first initialization voltage (VINT1) may be applied to pixels (PX) in synchronization with a second scan signal (GI). During the data write and anode initialization period, a data voltage (Dm) may be provided to pixels (PX) in synchronization with a first scan signal (GW), and a second initialization voltage (VINT2) may be applied to pixels (PX) in synchronization with a third scan signal (GB). During the light emission period, pixels (PX) of the display unit (110) emit light.

[0062] The timing control unit (140) receives image source data (RGB) and a control signal (CONT) from the outside. The timing control unit (140) can convert the image source data (RGB) into image data (DATA) based on the characteristics of the display unit (110) and pixels (PX). The timing control unit (140) can provide the image data (DATA) to the data driving unit (130).

[0063] The control signal (CONT) may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a clock signal (CLK), etc. The timing control unit (140) can control the operation timing of the gate driver (120) and the data driver (130) using the control signal (CONT). The timing control unit (140) can determine the frame period by counting the data enable signal (DE) of the horizontal scanning period. In this case, the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) supplied from the outside may be omitted. The image source data (RGB) includes luminance information of the pixels (PX). The luminance is a fixed number, for example, 1024 (=2 10 ), 256(=2 8 ) or 64(=2 6It can have ) shades of gray.

[0064] The timing control unit (140) can generate control signals including a gate timing control signal (GDC) for controlling the operation timing of the gate driving unit (120) and a data timing control signal (DDC) for controlling the operation timing of the data driving unit (130).

[0065] The gate timing control signal (GDC) may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE) signal. The gate start pulse (GSP) is supplied to a gate driver (120) that generates the first scan signal at the start of the scan period. The gate shift clock (GSC) is a clock signal commonly input to the gate driver (120) and is a clock signal for shifting the gate start pulse (GSP). The gate output enable (GOE) signal controls the output of the gate driver (120).

[0066] The data timing control signal (DDC) may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable (SOE) signal. The source start pulse (SSP) controls the start time of data sampling of the data driver (130) and is provided to the data driver (130) at the start time of the scanning period. The source sampling clock (SSC) is a clock signal that controls the sampling operation of data within the data driver (130) based on the rising or falling edge. The source output enable signal (SOE) controls the output of the data driver (130). Meanwhile, the source start pulse (SSP) supplied to the data driver (130) may be omitted depending on the data transmission method.

[0067] The gate driver (120) sequentially generates first scan signals (GW_1 to GW_m), second scan signals (GI_1 to GI_m), and third scan signals (GB_1 to GB_m) in response to a gate timing control signal (GDC) supplied from the timing control unit (140) using first and second gate voltages (VGH, VGL) provided from the voltage generation unit (150).

[0068] The data driver (130) samples and latches image data (DATA) supplied from the timing control unit (140) in response to a data timing control signal (DDC) supplied from the timing control unit (140) and converts it into data of a parallel data system. When converting to data of a parallel data system, the data driver (130) converts the image data (DATA) into a gamma reference voltage and converts it into an analog data voltage. The data driver (130) provides data voltages (Dm_1 to Dm_n) to pixels (PX) through data lines (DL_1 to DL_n). Pixels (PX) receive data voltages (Dm_1 to Dm_n) in response to first scan signals (GW_1 to GW_m).

[0069] FIG. 2 schematically illustrates a plurality of pixels according to one embodiment.

[0070] Referring to FIG. 2, the display unit (110) of the display device includes pixels such as a pixel (PXi(j-1)) located in the i-th row and j-1 column (hereinafter referred to as the first pixel), a pixel (PXij) located in the i-th row and j column (hereinafter referred to as the second pixel), and a pixel (PXi(j+1)) located in the i-th row and j+1 column (hereinafter referred to as the third pixel).

[0071] Pixels (PX) can be arranged in a first direction (or column direction) (DR1) and a second direction (or row direction) (DR2). For example, pixels (PX) can be arranged in a matrix form.

[0072] In one embodiment, as described above in FIG. 1, the power line (PL) may include a plurality of vertical power lines extending in a first direction (DR1). For example, the power line (PL) may include a first vertical power line (PLv1) and a second vertical power line (PLv2). The first vertical power line (PLv1) may extend in a first direction (DR1) on a first pixel (PXi(j-1)) and may transmit a first driving voltage (ELVDD) to the first pixel (PXi(j-1)). The second vertical power line (PLv2) may extend in a first direction (DR1) on a second pixel (PXij) and may transmit a first driving voltage (ELVDD) to the second pixel (PXij).

[0073] In one embodiment, the first vertical power line (PLv1) and the second vertical power line (PLv2) can be connected to each other through a connection area (Aca) of the semiconductor pattern (Act, see FIG. 4). The connection area (Aca) of the semiconductor pattern (Act) can always electrically connect the first vertical power line (PLv1) and the second vertical power line (PLv2). For example, as shown in FIG. 2, the first vertical power line (PLv1) can be connected to one end of the connection area (Aca) of the semiconductor pattern (Act) through a first contact plug (CP1). The second vertical power line (PLv2) can be connected to the other end of the connection area (Aca) of the semiconductor pattern (Act) through a second contact plug (CP2). Since the first vertical power line (PLv1) and the second vertical power line (PLv2) are connected to one end and the other end, respectively, of the connection area (Aca) of the semiconductor pattern (Act), the first vertical power line (PLv1) and the second vertical power line (PLv2) can be connected to each other.

[0074] The first contact plug (CP1) and the second contact plug (CP2) may correspond to a part of the conductive layer as shown in FIG. 5, which will be described later. The first contact plug (CP1) and the second contact plug (CP2) may correspond to a part of the conductive layer embedded within a contact hole formed in the insulating layer.

[0075] In one embodiment, the second pixel (PXij) and the third pixel (PXi(j+1)) may share a third contact plug (CP3). The third contact plug (CP3) may be connected to a second voltage wiring (VL2) to which a second initialization voltage (VINT2) is applied. The third contact plug (CP3) may correspond to a part of the conductive layer as illustrated in FIG. 5, which will be described later. The third contact plug (CP3) may correspond to a part of the conductive layer embedded within a contact hole formed in the insulating layer.

[0076] Since the second pixel (PXij) and the third pixel (PXi(j+1)) share the third contact plug (CP3), the second pixel (PXij) and the third pixel (PXi(j+1)) can be connected to the second voltage wiring (VL2) through the third contact plug (CP3). In other words, the third contact plug (CP3) can connect the second pixel (PXij) and the third pixel (PXi(j+1)) to the second voltage wiring (VL2).

[0077] FIG. 3a illustrates equivalent circuit diagrams of each of a plurality of pixels according to one embodiment, and FIG. 3b is a plan view schematically illustrating a plurality of pixels according to one embodiment.

[0078] FIGS. 3a and 3b illustrate a first pixel (PXi(j-1)), a second pixel (PXij), and a third pixel (PXi(j+1)). Since the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) are located in the same row, the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) can be connected to the same first to third scan lines (GWL_i, GIL_i, GBL_i) and light emission control line (EML_i). The first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) can be arranged sequentially in a second direction (DR2) and be adjacent to each other.

[0079] Referring to FIGS. 3a and 3b, the first pixel (PXi(j-1)) is connected to first to third scan lines (GWL_i, GIL_i, GBL_i) that respectively transmit first to third scan signals (GW_i, GI_i, GB_i), a data line (DL_j-1) that transmits a data voltage (Dm_j-1) (hereinafter referred to as the first data line), and a light emission control line (EML_i) that transmits a light emission control signal (EM_i). The first pixel (PXi(j-1)) is connected to a power line (PL) that transmits a first driving voltage (ELVDD), a first voltage line (VL1) that transmits a first initialization voltage (VINT1), and a second voltage line (VL2) that transmits a second initialization voltage (VINT2). The first pixel (PXi(j-1)) is connected to a common electrode to which a second driving voltage (ELVSS) is applied.

[0080] The first scan line (GWL_i) corresponds to the first scan line (SL1_i) of FIG. 1, the second scan line (GIL_i) corresponds to the second scan line (SL2_i) of FIG. 1, and the third scan line (GBL_i) corresponds to the second scan line (SL2_i+1) of FIG. 1.

[0081] The second pixel (PXij) is connected to first to third scan lines (GWL_i, GIL_i, GBL_i) that respectively transmit first to third scan signals (GW_i, GI_i, GB_i), a data line (DL_j) that transmits a data voltage (Dm_j) (hereinafter referred to as the second data line), and a light emission control line (EML_i) that transmits a light emission control signal (EM_i). The second pixel (PXij) is connected to a power line (PL) that transmits a first driving voltage (ELVDD), a first voltage line (VL1) that transmits a first initialization voltage (VINT1), and a second voltage line (VL2) that transmits a second initialization voltage (VINT2). The second pixel (PXij) is connected to a common electrode to which a second driving voltage (ELVSS) is applied. The second pixel (PXij) may correspond to the pixel (PXij) of FIG. 1.

[0082] The third pixel (PXi(j+1)) is connected to first to third scan lines (GWL_i, GIL_i, GBL_i) that respectively transmit first to third scan signals (GW_i, GI_i, GB_i), a data line (DL_j+1) that transmits a data voltage (Dm_j+1) (hereinafter referred to as the third data line), and a light emission control line (EML_i) that transmits a light emission control signal (EM_i). The third pixel (PXi(j+1)) is connected to a power line (PL) that transmits a first driving voltage (ELVDD), a first voltage line (VL1) that transmits a first initialization voltage (VINT1), and a second voltage line (VL2) that transmits a second initialization voltage (VINT2). The third pixel (PXi(j+1)) is connected to a common electrode to which a second driving voltage (ELVSS) is applied.

[0083] The power line (PL) may include a plurality of first vertical power lines (PLv1) and a plurality of second vertical power lines (PLv2). The first vertical power lines (PLv1) and the second vertical power lines (PLv2) may each extend in a first direction (DR1) to deliver a first driving voltage (ELVDD) to pixels (PX) arranged in the same column.

[0084] In one embodiment, the pixel row in which the first vertical power lines (PLv1) transmit the first driving voltage (ELVDD) and the pixel row in which the second vertical power lines (PLv2) transmit the first driving voltage (ELVDD) may be different.

[0085] For example, the pixel rows in which the first vertical power lines (PLv1) transmit the first driving voltage (ELVDD) and the pixel rows in which the second vertical power lines (PLv2) transmit the first driving voltage (ELVDD) can be arranged alternately. In other words, the first vertical power lines (PLv1) and the second vertical power lines (PLv2) can be arranged alternately along the second direction (DR2). In other words, the first vertical power lines (PLv1) can transmit the first driving voltage (ELVDD) to pixels (PX) placed in odd columns, and the second vertical power lines (PLv2) can transmit the first driving voltage (ELVDD) to pixels (PX) placed in even columns. Alternatively, the first vertical power lines (PLv1) can each deliver a first driving voltage (ELVDD) to pixels (PX) arranged in even columns, and the second vertical power lines (PLv2) can each deliver a first driving voltage (ELVDD) to pixels (PX) arranged in odd columns.

[0086] In one embodiment, the first vertical power lines (PLv1) and the second vertical power lines (PLv2) can be connected to each other through connection areas (Aca) of the semiconductor pattern (Act, see FIG. 4). The connection areas (Aca) of the semiconductor pattern (Act) can always electrically connect the first vertical power lines (PLv1) and the second vertical power lines (PLv2).

[0087] For example, among a plurality of first vertical power lines (PLv1) and a plurality of second vertical power lines (PLv2), a first vertical power line (PLv1) and a second vertical power line (PLv2) adjacent to each other in the second direction (DR2) can be connected to each other through a connection area (Aca) of a semiconductor pattern (Act). As shown in FIGS. 3a and 3b, a first vertical power line (PLv1) placed on a first pixel (PXi(j-1)) can be connected to one end of the connection area (Aca) of the semiconductor pattern (Act) through a first contact plug (CP1), and a second vertical power line (PLv2) placed on a second pixel (PXij) can be connected to the other end of the connection area (Aca) of the semiconductor pattern (Act) through a second contact plug (CP2). A first vertical power line (PLv1) placed on a first pixel (PXi(j-1)) and a second vertical power line (PLv2) placed on a second pixel (PXij) are adjacent to each other in a second direction (DR2) and can be connected to each other through a connection area (Aca) of a semiconductor pattern (Act). Additionally, although not fully illustrated in FIGS. 3a and 3b, a first vertical power line (PLv1) placed on a third pixel (PXi(j+1)) can be connected to one end of a connection area (Aca) of a semiconductor pattern (Act) through a first contact plug (CP1), and a second vertical power line (PLv2) placed on a pixel located in the i-th row and j+2 column can be connected to the other end of a connection area (Aca) of a semiconductor pattern (Act) through a second contact plug (CP2). A first vertical power line (PLv1) placed on a third pixel (PXi(j+1)) and a second vertical power line (PLv2) placed on a pixel located in the i-th row and j+2 column are adjacent to each other in the second direction (DR2) and can be connected to each other through a connection area (Aca) of a semiconductor pattern (Act).

[0088] The power line (PL) may include a plurality of horizontal power lines (PLh). Each of the horizontal power lines (PLh) may extend in a second direction (DR2) to deliver a first driving voltage (ELVDD) to pixels (PX) arranged in the same row.

[0089] Horizontal power lines (PLh) can be connected to first vertical power lines (PLv1) and second vertical power lines (PLv2). For example, as shown in FIGS. 3a and 3b, the horizontal power line (PLh) can be connected to the first vertical power lines (PLv1) through ten contact plugs (CP10) and to the second vertical power lines (PLv2) through eleven contact plugs (CP11).

[0090] Data lines (DL_j-1, DL_j, DL_j+1) can each extend in a first direction (DR1) to transmit data voltages (Dm_j-1, Dm_j, Dm_j+1) to pixels (PX) placed in the same column. For example, as shown in FIG. 3b, data lines (DL_j-1, DL_j, DL_j+1) can be connected to first to third pixels (PXi(j-1)), PXij, PXi(j+1)) respectively through thirteenth contact plugs (CP13).

[0091] In one embodiment, data lines (DL_j-1, DL_j, DL_j+1) may be positioned between a first vertical power line (PLv1) and a second vertical power line (PLv2) that are adjacent to each other in a second direction (DR2). For example, as illustrated in FIGS. 3a and 3b, the first data line (DL_j-1) and the second data line (DL_j) may be positioned between the first vertical power line (PLv1) positioned on the first pixel (PXi(j-1)) and the second vertical power line (PLv2) positioned on the second pixel (PXij). Although not fully illustrated in FIGS. 3a and 3b, a third data line (DL_j+1) may be positioned between the first vertical power line (PLv1) positioned on the third pixel (PXi(j+1)) and the second vertical power line (PLv2) positioned on the pixel located in the i-th row and j+2-th column.

[0092] In one embodiment, as shown in FIGS. 3a and 3b, the data lines (DL_j-1, DL_j, DL_j+1) may overlap at least partially with the connection regions (Aca) of the semiconductor pattern (Act).

[0093] The first voltage wiring (VL1) may include a plurality of first vertical wirings (VL1v) and a plurality of first horizontal wirings (VL1h). Each of the first vertical wirings (VL1v) may extend in a first direction (DR1) to deliver a first initialization voltage (VINT1) to pixels (PX) arranged in the same column, and each of the first horizontal wirings (VL1h) may extend in a second direction (DR2) to deliver a first initialization voltage (VINT1) to pixels (PX) arranged in the same row. For example, as shown in FIGS. 3a and 3b, the first pixel (PXi(j-1)) can be connected to the first longitudinal wiring (VL1v) of the first voltage wiring (VL1) through the fourth contact plug (CP4), the second pixel (PXij) can be connected to the first longitudinal wiring (VL1v) of the first voltage wiring (VL1) through the fifth contact plug (CP5), and the third pixel (PXi(j+1)) can be connected to the first longitudinal wiring (VL1v) of the first voltage wiring (VL1) through the sixth contact plug (CP6).

[0094] The first vertical wires (VL1v) and the first horizontal wires (VL1h) can be connected to each other. For example, as shown in FIGS. 3a and 3b, the first vertical wires (VL1v) and the first horizontal wires (VL1h) can be connected to each other through eighth contact plugs (CP8).

[0095] In FIG. 3a and FIG. 3b, the first voltage wiring (VL1) is illustrated as including first vertical wiring (VL1v) and first horizontal wiring (VL1h), but in another embodiment, one of the first vertical wiring (VL1v) or the first horizontal wiring (VL1h) may be omitted. In yet another embodiment, some of the first vertical wiring (VL1v) may be omitted or some of the first horizontal wiring (VL1h) may be omitted.

[0096] The second voltage wiring (VL2) may include a plurality of second vertical wirings (VL2v) and a plurality of second horizontal wirings (VL2h). Each of the second vertical wirings (VL2v) may extend in a first direction (DR1) to deliver a second initialization voltage (VINT2) to pixels (PX) placed in the same column, and each of the second horizontal wirings (VL2h) may extend in a second direction (DR2) to deliver a second initialization voltage (VINT2) to pixels (PX) placed in the same row.

[0097] The second vertical wires (VL2v) and the second horizontal wires (VL2h) can be connected to each other. For example, as shown in FIGS. 3a and 3b, the second vertical wires (VL2v) and the second horizontal wires (VL2h) can be connected to each other through the ninth contact plugs (CP9).

[0098] In FIGS. 3a and 3b, the second voltage wiring (VL2) is illustrated as including second vertical wiring (VL2v) and second horizontal wiring (VL2h), but in another embodiment, one of the second vertical wiring (VL2v) or the second horizontal wiring (VL2h) may be omitted. In yet another embodiment, some of the second vertical wiring (VL2v) may be omitted or some of the second horizontal wiring (VL2h) may be omitted.

[0099] In one embodiment, the second pixel (PXij) and the third pixel (PXi(j+1)) may share a third contact plug (CP3). Since the second pixel (PXij) and the third pixel (PXi(j+1)) share the third contact plug (CP3), the second pixel (PXij) and the third pixel (PXi(j+1)) may be connected to the second voltage wiring (VL2) through the third contact plug (CP3). The second pixel (PXij) and the third pixel (PXi(j+1)) may receive the second initialization voltage (VINT2) through the third contact plug (CP3). In other words, the third contact plug (CP3) may connect the second pixel (PXij) and the third pixel (PXi(j+1)) to the second voltage wiring (VL2).

[0100] In one embodiment, the second pixel (PXij) and the third pixel (PXi(j+1)) may share the second voltage wiring (VL2). For example, as illustrated in FIGS. 3a and 3b, the second pixel (PXij) and the third pixel (PXi(j+1)) may share the second vertical wiring (VL2v) of the second voltage wiring (VL2). In this case, the number of second vertical wirings (VL2v) of the second voltage wiring (VL2) per unit area may be smaller than the number of first vertical wirings (VL1v) of the first voltage wiring (VL1) per unit area.

[0101] In one embodiment, as shown in FIG. 3b, the third scan line (GBL_i) may surround at least a portion of the third contact plug (CP3). A portion (GBLp) of the third scan line (GBL_i) adjacent to the third contact plug (CP3) may be bent at least once. For example, the planar shape of the portion (GBLp) of the third scan line (GBL_i) may be an omega (Ω) shape.

[0102] In one embodiment, as shown in FIG. 3b, the second horizontal wire (VL2h) may surround at least a portion (GBLp) of the third scan line (GBL_i). A portion (VL2hp) of the second horizontal wire (VL2h) adjacent to a portion (GBLp) of the third scan line (GBL_i) may be bent at least once. In other words, a portion (VL2hp) of the second horizontal wire (VL2h) adjacent to the third contact plug (CP3) may be bent at least once. For example, the planar shape of a portion (VL2hp) of the second horizontal wire (VL2h) may be an omega (Ω) shape.

[0103] Meanwhile, although not shown in FIG. 3a and FIG. 3b, pixels arranged in the i-1 row, pixels arranged in the i+1 row, etc., can be configured in the same way as pixels arranged in the i-th row. In this case, the first contact plugs (CP1), the second contact plugs (CP2), and the third contact plugs (CP3), etc., can each be arranged along the first direction (DR1).

[0104] Hereinafter, the elements included in the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) will be described. Since the equivalent circuit diagrams of the first pixel (PXi(j-1)) and the third pixel (PXi(j+1)) can be applied identically to the equivalent circuit diagram of the second pixel (PXij), the explanation will be based on the second pixel (PXij).

[0105] The second pixel (PXij) includes a light-emitting element (OLED), first to seventh transistors (T1 to T7), and a storage capacitor (Cst). The light-emitting element (OLED) may be an organic light-emitting diode having an anode and a cathode. The cathode may be a common electrode to which a second driving voltage (ELVSS) is applied. Meanwhile, in FIG. 3b, the light-emitting element (OLED) is omitted.

[0106] The first transistor (T1) is a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second to seventh transistors (T2 to T7) may be switching transistors that are turned on / off according to the gate-source voltage, substantially the gate voltage. The first to seventh transistors (T1 to T7) may be formed as thin-film transistors.

[0107] The first transistor (T1) is referred to as a driving transistor, the second transistor (T2) is referred to as a scan transistor, the third transistor (T3) is referred to as a compensation transistor, the fourth transistor (T4) is referred to as a gate initialization transistor, the fifth transistor (T5) is referred to as a first light emission control transistor, the sixth transistor (T6) is referred to as a second light emission control transistor, and the seventh transistor (T7) can be referred to as an anode initialization transistor.

[0108] A storage capacitor (Cst) is connected between the power line (PL) and the gate of the driving transistor (T1). The storage capacitor (Cst) may have an upper electrode (CE2) connected to the power line (PL) and a lower electrode (CE1) connected to the gate of the driving transistor (T1). For example, as shown in FIGS. 3a and 3b, the storage capacitor (Cst) is connected between the horizontal power line (PLh) of the power line (PL) and the gate of the driving transistor (T1). The storage capacitor (Cst) may have an upper electrode (CE2) connected to the horizontal power line (PLh) of the power line (PL) and a lower electrode (CE1) connected to the gate of the driving transistor (T1).

[0109] The driving transistor (T1) can control the magnitude of the current (Id) flowing from the power line (PL) to the light-emitting element (OLED) according to the gate-source voltage. The driving transistor (T1) may have a gate connected to the lower electrode (CE1) of the storage capacitor (Cst), a source connected to the power line (PL) through the first light-emitting control transistor (T5), and a drain connected to the light-emitting element (OLED) through the second light-emitting control transistor (T6).

[0110] The driving transistor (T1) can output a driving current (Id) to the light-emitting element (OLED) according to the gate-source voltage. The magnitude of the driving current (Id) is determined based on the difference between the gate-source voltage and the threshold voltage of the driving transistor (T1). The light-emitting element (OLED) receives the driving current (Id) from the driving transistor (T1) and can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0111] The scan transistor (T2) transmits a data voltage (Dm_j) to the source of the driving transistor (T1) in response to the first scan signal (GW_i). The scan transistor (T2) may have a gate connected to the first scan line (GWL_i), a source connected to the data line (GL_j), and a drain connected to the source of the driving transistor (T1).

[0112] The first and second compensation transistors (T3a, T3b) are connected in series between the drain and gate of the driving transistor (T1) and connect the drain and gate of the driving transistor (T1) to each other in response to the first scan signal (GW_i). The first compensation transistor (T3a) may have a gate connected to the first scan line (GWL_i), a source connected to the drain of the driving transistor (T1), and a drain connected to the source of the second compensation transistor (T3b). The second compensation transistor (T3b) may have a gate connected to the first scan line (GWL_i), a source connected to the drain of the first compensation transistor (T3a), and a drain connected to the gate of the driving transistor (T1). For example, as shown in FIG. 3b, the drain of the second compensation transistor (T3b) can be connected to the gate of the driving transistor (T1) through the connection pattern (CLP), the 7-1 contact plug (CP7a), and the 7-2 contact plug (CP7b).

[0113] In FIGS. 3a and 3b, the compensation transistor (T3) is illustrated as comprising two transistors connected in series, but the compensation transistor (T3) may be composed of a single transistor. As another example, the compensation transistor (T3) may comprise three or more transistors connected in series.

[0114] The gate initialization transistor (T4) applies a first initialization voltage (VINT1) to the gate of the driving transistor (T1) in response to a second scan signal (GI_i). The gate initialization transistor (T4) may have a gate connected to the second scan line (GIL_i), a source connected to the gate of the driving transistor (T1), and a drain connected to the first voltage line (VL1).

[0115] As illustrated in FIGS. 3a and 3b, the gate initialization transistor (T4) may include a first gate initialization transistor (T4a) and a second gate initialization transistor (T4b) connected in series with each other between the gate of the driving transistor (T1) and the first voltage line (VL1). The first gate initialization transistor (T4a) may have a gate connected to the second scan line (GIL_i), a source connected to the gate of the driving transistor (T1), and a drain connected to the source of the second gate initialization transistor (T4b). The second gate initialization transistor (T4b) may have a gate connected to the second scan line (GIL_i), a source connected to the drain of the first gate initialization transistor (T4a), and a drain connected to the first voltage line (VL1).

[0116] In FIGS. 3a and 3b, the gate initialization transistor (T4) is illustrated as comprising two transistors connected in series, but the gate initialization transistor (T4) may comprise three or more transistors connected in series. As another example, the gate initialization transistor (T4) may be composed of a single transistor.

[0117] In one embodiment, as shown in FIG. 3b, a shielding electrode (Esh) may be positioned between the first scan line (GWL_i) and the second scan line (GIL_i). The shielding electrode (Esh) may be connected to the first vertical power line (PLv1) or the second vertical power line (PLv2) through the 14th contact plug (CP14). The shielding electrode (Esh) may serve to shield adjacent conductive layers (or metal layers) to prevent the formation of unnecessary capacitors.

[0118] The anode initialization transistor (T7) applies a second initialization voltage (VINT2) to the anode of the light-emitting element (OLED) in response to a third scan signal (GB_i). The anode initialization transistor (T7) may have a gate connected to the third scan line (GBL_i), a source connected to the anode of the light-emitting element (OLED), and a drain connected to the second voltage line (VL2).

[0119] Meanwhile, the second pixel (PXij) and the third pixel (PXi(j+1)) may share a third contact plug (CP3) connected to the second voltage line (VL2). The second pixel (PXij) and the third pixel (PXi(j+1)) may share a third contact plug (CP3) connected to the vertical line (VL2v) of the second voltage line (VL2). When the anode initialization transistors (T7) of the second pixel (PXij) and the third pixel (PXi(j+1)) are turned on in response to the third scan signal (GB_i), the second initialization voltage (VINT2) transmitted through the third contact plug (CP3) may be applied to the anodes of the light-emitting elements (OLEDs) of the second pixel (PXij) and the third pixel (PXi(j+1)).

[0120] The first light-emitting control transistor (T5) can connect the source of the power line (PL) and the source of the driving transistor (T1) to each other in response to the light-emitting control signal (EM_i). The first light-emitting control transistor (T5) may have a gate connected to the light-emitting control line (EML_i), a source connected to the power line (PL), and a drain connected to the source of the driving transistor (T1).

[0121] The second light-emitting control transistor (T6) can connect the drain of the driving transistor (T1) and the anode of the light-emitting element (OLED) to each other in response to a light-emitting control signal (EM_i). The second light-emitting control transistor (T6) may have a gate connected to the light-emitting control line (EML_i), a source connected to the drain of the driving transistor (T1), and a drain connected to the anode of the light-emitting element (OLED). For example, as shown in FIG. 3b, the drain of the second light-emitting control transistor (T6) may be connected to the anode of the light-emitting element (OLED) through a connection wire (CML), a 15th contact plug (CP15), and a 16th contact plug (CP16).

[0122] The second scan signal (GI_i) can be substantially synchronized with the first scan signal (GW_i-1) of the previous row. The third scan signal (GB_i) can be substantially synchronized with the first scan signal (GW_i). According to another example, the third scan signal (GB_i) can be substantially synchronized with the first scan signal (GW_i+1) of the next row.

[0123] The specific operation process of a pixel of an organic light-emitting display device according to one embodiment is described in detail below.

[0124] First, when a high-level light emission control signal (EM_i) is received, the first light emission control transistor (T5) and the second light emission control transistor (T6) are turned off, the driving transistor (T1) stops outputting the driving current (Id), and the light-emitting element (OLED) stops emitting light.

[0125] Subsequently, during the gate initialization period when a low-level second scan signal (GI_i) is received, the gate initialization transistor (T4) is turned on, and the first initialization voltage (VINT1) is applied to the gate of the driving transistor (T1), that is, to the lower electrode of the storage capacitor (Cst). The difference (ELVDD - VINT1) between the first driving voltage (ELVDD) and the first initialization voltage (VINT1) is stored in the storage capacitor (Cst).

[0126] Subsequently, during the data writing period when a low-level first scan signal (GW_i) is received, the scan transistor (T2) and the compensation transistor (T3) are turned on, and the data voltage (Dm_j) is received at the source of the driving transistor (T1). The driving transistor (T1) is diode-connected by the compensation transistor (T3) and forward-biased. The gate voltage of the driving transistor (T1) rises from the first initialization voltage (VINT1). When the gate voltage of the driving transistor (T1) becomes equal to the data compensation voltage (Dm_j - |Vth|), which is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data voltage (Dm_j), the driving transistor (T1) is turned off, and the rise of the gate voltage of the driving transistor (T1) stops. Accordingly, the difference (ELVDD - Dm_j + |Vth|) between the first driving voltage (ELVDD) and the data compensation voltage (Dm_j - |Vth|) is stored in the storage capacitor (Cst).

[0127] Additionally, during the anode initialization period when a low-level third scan signal (GB_i) is received, the anode initialization transistor (T7) is turned on, and the second initialization voltage (VINT2) is applied to the anode of the light-emitting element (OLED). By applying the second initialization voltage (VINT2) to the anode of the light-emitting element (OLED) to completely de-emit the light-emitting element (OLED), the phenomenon in which the light-emitting element (OLED) emits light in response to the black gradation in the next frame can be eliminated.

[0128] The level of the second initialization voltage (VINT2) is higher than the level of the first initialization voltage (VINT1) and may be lower than the voltage level that is as high as the threshold voltage of the light-emitting element (OLED) at the second driving voltage (ELVSS). Since the light-emitting element (OLED) has a relatively large size, it has a significantly large capacitance. Furthermore, because the level of the first initialization voltage (VINT1) is too low, the light-emitting element (OLED) begins to emit light in the next frame after a significant delay. However, according to the present embodiment, by initializing the anode of the light-emitting element (OLED) with a second initialization voltage (VINT2) having a level higher than the level of the first initialization voltage (VINT1), the light-emitting element (OLED) can begin to emit light in the next frame within a short period of time. That is, the problem of light emission delay can be resolved.

[0129] The first scan signal (GW_i) and the third scan signal (GB_i) can be substantially synchronized, in which case the data write period and the anode initialization period may be the same period.

[0130] Subsequently, when a low-level light emission control signal (EM_i) is received, the first light emission control transistor (T5) and the second light emission control transistor (T6) are turned on, and the driving transistor (T1) outputs a driving current (Id) corresponding to the voltage stored in the storage capacitor (Cst), that is, the voltage obtained by subtracting the threshold voltage (|Vth|) of the driving transistor (T1) from the source-gate voltage (ELVDD - Dm_j + |Vth|) of the driving transistor (T1), and the light-emitting element (OLED) can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0131] FIG. 4 illustrates a semiconductor pattern according to one embodiment.

[0132] Referring to FIG. 4, the display device may include a semiconductor pattern (Act).

[0133] The semiconductor pattern (Act) can be continuously extended along the second direction (DR2). The semiconductor pattern (Act) can be formed integrally by extending along the second direction (DR2) without any breaks. The semiconductor pattern (Act) illustrated in FIG. 4 may be partially extended in the first direction (DR1), but may be extended in the second direction (DR2) when viewed as a whole. In other words, the semiconductor pattern (Act) may include a portion that extends in the first direction (DR1) microscopically, but may be extended in the second direction (DR2) as a whole.

[0134] The semiconductor pattern (Act) may include a plurality of pixel regions (Ai(j-1), Aij, Ai(j+1)), a plurality of connection regions (Aca) and a plurality of contact regions (Acp) disposed between the plurality of pixel regions (Ai(j-1), Aij, Ai(j+1)).

[0135] A plurality of pixel regions (Ai(j-1), Aij, Ai(j+1)) may each be included in a plurality of pixels (PXi(j-1), PXij, PXi(j+1)). A plurality of connection regions (Aca) may each correspond to a plurality of first contact plugs (CP1) and a plurality of second contact plugs (CP2), and a plurality of contact regions (Acp) may each correspond to a plurality of third contact plugs (CP3). Alternatively, as shown in FIGS. 5 and 6 to be described later, a plurality of connection regions (Aca) may each be in direct contact with a plurality of first contact plugs (CP1) and a plurality of second contact plugs (CP2), and a plurality of contact regions (Acp) may each be in direct contact with a plurality of third contact plugs (CP3).

[0136] In addition, multiple connection areas (Aca) can connect the first vertical power lines (PLv1) and the second vertical power lines (PLv2) to each other as described above in FIG. 3a.

[0137] In one embodiment, the connection regions (Aca) and contact regions (Acp) may be arranged alternately along the second direction (DR2).

[0138] For example, the connection area (Aca) can connect the pixel area (Ai(j-1)) of the first pixel (PXi(j-1)) and the pixel area (Aij) of the second pixel (PXij), and the contact area (Acp) can connect the pixel area (Aij) of the second pixel (PXij) and the pixel area (Ai(j+1)) of the third pixel (PXi(j+1)). Although not fully illustrated in FIG. 4, the pixel area (Ai(j-1)) of the first pixel (PXi(j-1)) and the pixel area of ​​the pixel placed in the previous column can be connected to each other by the contact area (Acp), and the pixel area (Ai(j+1)) of the third pixel (PXi(j+1)) and the pixel area of ​​the pixel placed in the next column can be connected to each other by the connection area (Aca).

[0139] As a comparative example, the semiconductor pattern may include multiple island patterns that are spaced apart from each other and are not continuously extended along the row direction. The island patterns included in each of the multiple pixels may not be connected to each other. Static electricity may be generated (or introduced) from the outside due to processes such as forming the semiconductor pattern and then proceeding with subsequent processes. If the semiconductor pattern includes spaced-apart island patterns, the generated (or introduced) static electricity may be isolated within each of the island patterns. Consequently, the semiconductor pattern affected by static electricity is damaged, and pixel defects may be caused by the damaged semiconductor pattern.

[0140] However, as in one embodiment of the present invention, when the semiconductor pattern (Act) is continuously extended along the second direction (DR2), static electricity generated (or introduced) from the outside is not isolated and can be dispersed (or moved) along the second direction (DR2). Therefore, since static electricity is not isolated within the semiconductor pattern (Act) and can be dispersed along the second direction (DR2), damage to the semiconductor pattern (Act) can be prevented.

[0141] FIG. 5 is a cross-sectional view schematically illustrating a display device according to one embodiment.

[0142] FIG. 5 schematically illustrates a portion of each of the first pixel (PXi(j-1)), second pixel (PXij), and third pixel (PXi(j+1)) based on FIG. 3a and FIG. 4, and some components may be omitted.

[0143] A first pixel (PXi(j-1)) may include a first light-emitting control transistor (T5i(j-1)), a second pixel (PXij) may include a driving transistor (T1ij), a first light-emitting control transistor (T5ij), and an anode initialization transistor (T7ij), and a third pixel (PXi(j+1)) may include an anode initialization transistor (T7i(j+1)).

[0144] The first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) may include an active region (A5i(j-1)) and a gate electrode (G). The active region (A5i(j-1)) of the first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) may correspond to a part of the pixel region (Ai(j-1), see FIG. 4) of the first pixel (PXi(j-1)).

[0145] The driving transistor (T1ij) of the second pixel (PXij) may include an active region (A1ij) and a gate electrode (G), the first light emission control transistor (T5ij) of the second pixel (PXij) may include an active region (A5ij) and a gate electrode (G), and the anode initialization transistor (T7ij) of the second pixel (PXij) may include an active region (A7ij) and a gate electrode (G). The active region (A1ij) of the driving transistor (T1ij) of the second pixel (PXij), the active region (A5ij) of the first light emission control transistor (T5ij) of the second pixel (PXij), and the active region (A7ij) of the anode initialization transistor (T7ij) of the second pixel (PXij) may each correspond to a part of the pixel region (Aij) of the second pixel (PXij).

[0146] The anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) may include an active region (A7i(j+1)) and a gate electrode (G). The active region (A7i(j+1)) of the anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) may correspond to a part of the pixel region (Ai(j+1), see FIG. 4) of the third pixel (PXi(j+1)).

[0147] The active region (A5i(j-1)) of the first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) is connected to the connection region (Aca) to receive the first driving voltage (ELVDD, see FIG. 3a) from the first vertical power line (PLv1). The active region (A5ij) of the first light-emitting control transistor (T5ij) of the second pixel (PXij) is connected to the connection region (Aca) to receive the first driving voltage (ELVDD) from the second vertical power line (PLv2).

[0148] The active region (A5i(j-1)) of the first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) and the active region (A5ij) of the first light-emitting control transistor (T5ij) of the second pixel (PXij) can be connected to each other by a connection region (Aca).

[0149] The active region (A7ij) of the anode initialization transistor (T7ij) of the second pixel (PXij) is connected to the contact region (Acp) to receive the second initialization voltage (VINT2, see FIG. 3a) from the second voltage wiring (VL2). The active region (A7i(j+1)) of the anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) is connected to the contact region (Acp) to receive the second initialization voltage (VINT2) from the second voltage wiring (VL2).

[0150] The active region (A7ij) of the anode initialization transistor (T7ij) of the second pixel (PXij) and the active region (A7i(j+1)) of the anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) can be connected to each other by a contact region (Acp).

[0151] Hereinafter, the multilayer film and the like stacked on the display device will be described in detail with reference to FIG. 5.

[0152] The substrate (200) may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. If the substrate (200) has flexible or bendable properties, the substrate (200) may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0153] The substrate (200) may have a single-layer or multi-layer structure of the material, and in the case of a multi-layer structure, may further include an inorganic layer. In some embodiments, the substrate (200) may have an organic / inorganic / organic structure.

[0154] The buffer layer (211) can reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (200) and can provide a flat surface on the substrate (200). The buffer layer (211) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0155] A barrier layer (not shown) may be further included between the substrate (200) and the buffer layer (211). The barrier layer may serve to prevent or minimize the penetration of impurities from the substrate (200), etc., into the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), connection region (Aca), and contact region (Acp). The barrier layer may include an inorganic material such as an oxide or nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0156] Active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), a connection region (Aca), and a contact region (Acp) may be disposed on the buffer layer (211). The active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), the connection region (Aca), and the contact region (Acp) may comprise amorphous silicon or polysilicon.

[0157] In another embodiment, the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), the connection region (Aca), and the contact region (Acp) may comprise an oxide semiconductor material. The active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), the connection region (Aca), and the contact region (Acp) may comprise, for example, an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0158] For example, the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), connection region (Aca), and contact region (Acp) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. Since oxide semiconductors have a wide band gap (approx. 3.1 eV), high carrier mobility, and low leakage current, the voltage drop is not large even with a long driving time, so there is an advantage that the brightness change due to voltage drop is not large even during low-frequency driving.

[0159] Each of the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)) may include a channel region and source and drain regions positioned on either side of the channel region. The active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)) may be composed of a single layer or multiple layers.

[0160] A first gate insulating layer (213) and a second gate insulating layer (215) may be laminated and disposed on a substrate (200) to cover active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), a connection region (Aca), and a contact region (Acp). The first gate insulating layer (213) and the second gate insulating layer (215) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0161] Gate electrodes (G) may be disposed on the first gate insulating layer (213). Each of the gate electrodes (G) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, each of the gate electrodes (G) may be formed as a multilayer structure of Ti / Al / Ti.

[0162] The gate electrodes (G) can each overlap at least partially with the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)). For example, the gate electrodes (G) can overlap with the channel regions of each of the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)).

[0163] In one embodiment, the storage capacitor (Cst) is provided with a lower electrode (CE1) and an upper electrode (CE2) and may overlap with the driving transistor (T1ij) as shown in FIG. 5. For example, the gate electrode (G) of the driving transistor (T1ij) may function as the lower electrode (CE1) of the storage capacitor (Cst). Alternatively, the storage capacitor (Cst) may not overlap with the driving transistor (T1ij) and may exist separately.

[0164] The upper electrode (CE2) of the storage capacitor (Cst) overlaps with the lower electrode (CE1) with the second gate insulating layer (215) in between, forming a capacitance. In this case, the second gate insulating layer (215) can function as a dielectric layer of the storage capacitor (Cst). The upper electrode (CE2) of the storage capacitor (Cst) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the upper electrode (CE2) of the storage capacitor (Cst) may be formed as a multilayer structure of Ti / Al / Ti.

[0165] An interlayer insulating layer (217) may be provided on the second gate insulating layer (215) to cover the upper electrode (CE2) of the storage capacitor (Cst). The interlayer insulating layer (217) may be silicon oxide (SiO2) or silicon nitride (SiN X It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0166] A conductive layer may be disposed on the interlayer insulating layer (217). The conductive layer may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the conductive layer may be formed as a multilayer structure of Ti / Al / Ti.

[0167] The conductive layer may include a connecting wire (CML), a first vertical power line (PLv1), a second vertical power line (PLv2), and a second voltage wire (VL2).

[0168] The connecting wiring (CML), the first longitudinal power line (PLv1), the second longitudinal power line (PLv2), and the second voltage wiring (VL2) can be connected to the active regions (A5i(j-1), A1ij, A5ij, A7ij, A7i(j+1)), the connecting region (Aca), and the contact region (Acp), respectively, through contact holes formed in the insulating layers.

[0169] For example, the connection wiring (CML) can be connected to the anode initialization transistor (T7ij) of the first pixel (PXij) through a contact hole formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the connection wiring (CML) can be embedded in the contact hole, and the portion of the connection wiring (CML) embedded in the contact hole can be referred to as the 15th contact plug (CP15).

[0170] The pixel electrode (310) of the light-emitting element (300) can be connected to the connecting wire (CML) through a contact hole formed in the planarization layer (219). A portion of the pixel electrode (310) can be embedded in the contact hole, and the portion of the pixel electrode (310) embedded in the contact hole can be referred to as the 16th contact plug (CP16). Since the pixel electrode (310) is connected to the connecting wire (CML) and the connecting wire (CML) is connected to the anode initialization transistor (T7ij) of the first pixel (PXij), the connecting wire (CML) can connect the light-emitting element (300) and the anode initialization transistor (T7ij) of the first pixel (PXij).

[0171] The first vertical power line (PLv1) can be connected to a connection region (Aca) through a first contact hole (CNT1) formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the first vertical power line (PLv1) can be embedded in the first contact hole (CNT1), and the portion of the first vertical power line (PLv1) embedded in the first contact hole (CNT1) can be referred to as a first contact plug (CP1). In other words, the first vertical power line (PLv1) and the first contact plug (CP1) can be a single unit.

[0172] The second vertical power line (PLv2) can be connected to a connection region (Aca) through a second contact hole (CNT2) formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the second vertical power line (PLv2) can be embedded in the second contact hole (CNT2), and the portion of the second vertical power line (PLv2) embedded in the second contact hole (CNT2) can be referred to as a second contact plug (CP2). In other words, the second vertical power line (PLv2) and the second contact plug (CP2) can be integral.

[0173] The second voltage wiring (VL2) can be connected to a contact region (Acp) through a third contact hole (CNT3) formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the second voltage wiring (VL2) can be embedded in the third contact hole (CNT3), and the portion of the second voltage wiring (VL2) embedded in the third contact hole (CNT3) can be referred to as a third contact plug (CP3). In other words, the second voltage wiring (VL2) and the third contact plug (CP3) can be integral.

[0174] The conductive layer can be covered by an inorganic protective layer (not shown). The inorganic protective layer is silicon nitride (SiN X ) and silicon oxide (SiO X It may be a single film or a multilayer film. The inorganic protective layer may be introduced to cover and protect some wiring placed on the interlayer insulating layer (217).

[0175] A flattening layer (219) is disposed on the interlayer insulating layer (217), and a light-emitting element (300) can be disposed on the flattening layer (219).

[0176] The flattening layer (219) may be formed as a single layer or a multilayer film made of organic material and provides a flat upper surface. Such flattening layer (219) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0177] A light-emitting element (300) may be disposed on the flattening layer (219). The light-emitting element (300) may include a pixel electrode (310), an intermediate layer (320) including an organic light-emitting layer, and a counter electrode (330).

[0178] The pixel electrode (310) may be a (semi)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode (310) may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some embodiments, the pixel electrode (310) may be provided as ITO / Ag / ITO.

[0179] A pixel defining film (221) may be disposed on the flattening layer (219). Additionally, the pixel defining film (221) may serve to prevent arcs from occurring at the edge of the pixel electrode (310) by increasing the distance between the edge of the pixel electrode (310) and the opposing electrode (330) above the pixel electrode (310).

[0180] The pixel definition film (221) may be formed from one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene and phenolic resin.

[0181] An intermediate layer (320) may be disposed within an opening formed by a pixel defining film (221). The intermediate layer (320) may include an organic light-emitting layer. The organic light-emitting layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be optionally disposed below and above the organic light-emitting layer.

[0182] The intermediate layer (320) may be disposed corresponding to each of the plurality of pixel electrodes (310). However, it is not limited thereto. Various variations are possible, such as the intermediate layer (320) including a layer that is integral across the plurality of pixel electrodes (310).

[0183] The counter electrode (330) may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode (330) may be a transparent or translucent electrode and may be formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film. The counter electrode (330) is disposed across the display portion and may be disposed on top of the intermediate layer (320) and the pixel defining film (221). The counter electrode (330) may be formed integrally in a plurality of light-emitting elements (300) and may correspond to a plurality of pixel electrodes (310).

[0184] The light-emitting element (300) may be covered with an encapsulation layer (not shown). The encapsulation layer may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0185] The inorganic encapsulation layer may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer and the second inorganic encapsulation layer may be a single layer or a multilayer containing the aforementioned materials. The organic encapsulation layer may include a polymer-based material. Polymer-based materials may include acrylic resins such as polymethyl methacrylate and polyacrylic acid, epoxy resins, polyimide, and polyethylene. In one embodiment, the organic encapsulation layer may include an acrylate polymer.

[0186] FIG. 6 is a cross-sectional view schematically illustrating a display device according to one embodiment.

[0187] Referring to FIG. 6, between the connection region (Aca) of the semiconductor pattern (Act, see FIG. 4) and the first vertical power line (PLv1) and the second vertical power line (PLv2), an insulating layer such as a first gate insulating layer (213), a second gate insulating layer (215), and an interlayer insulating layer (217) may be interposed.

[0188] The first vertical power line (PLv1) can be connected to one end of the connection region (Aca) of the semiconductor pattern (Act) through a first contact hole (CNT1) formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the first vertical power line (PLv1) can be embedded in the first contact hole (CNT1), and the portion of the first vertical power line (PLv1) embedded in the first contact hole (CNT1) can be referred to as the first contact plug (CP1). That is, the first contact plug (CP1) can penetrate the insulating layer to connect the first vertical power line (PLv1) to one end of the connection region (Aca) of the semiconductor pattern (Act).

[0189] The second vertical power line (PLv2) can be connected to the other end of the connection region (Aca) of the semiconductor pattern (Act) through a second contact hole (CNT2) formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the second vertical power line (PLv2) can be embedded in the second contact hole (CNT2), and the portion of the second vertical power line (PLv2) embedded in the second contact hole (CNT2) can be referred to as a second contact plug (CP2). That is, the second contact plug (CP2) can penetrate the insulating layer to connect the second vertical power line (PLv2) to the other end of the connection region (Aca) of the semiconductor pattern (Act).

[0190] In this way, the first vertical power line (PLv1) and the second vertical power line (PLv2) can be connected to each other through the connection area (Aca) of the semiconductor pattern (Act).

[0191] FIG. 7 is a cross-sectional view schematically illustrating a display device according to one embodiment.

[0192] Referring to FIG. 7, the first voltage line (VL1) may include a first vertical line (VL1v) and a first horizontal line (VL1h). The second voltage line (VL2) may include a second vertical line (VL2v) and a second horizontal line (VL2h). The power line (PL) may include a first vertical power line (PLv1) and a horizontal power line (PLh). Meanwhile, as described above in FIG. 3a, the power line (PL) may include a second vertical power line (PLv2). Although FIG. 7 describes the first vertical power line (PLv1), the same can be applied to the second vertical power line (PLv2).

[0193] An interlayer insulation layer (217) may be interposed between the first vertical wiring (VL1v) and the first horizontal wiring (VL1h). The first vertical wiring (VL1v) may be connected to the first horizontal wiring (VL1h) through an eighth contact hole (CNT8) formed in the interlayer insulation layer (217). A portion of the first vertical wiring (VL1v) may be embedded in the eighth contact hole (CNT8), and the portion of the first vertical wiring (VL1v) embedded in the eighth contact hole (CNT8) may be referred to as an eighth contact plug (CP8). That is, the eighth contact plug (CP8) can penetrate the insulation layer to connect the first vertical wiring (VL1v) to the first horizontal wiring (VL1h).

[0194] An interlayer insulation layer (217) may be interposed between the second vertical wiring (VL2v) and the second horizontal wiring (VL2h). The second vertical wiring (VL2v) may be connected to the second horizontal wiring (VL2h) through a ninth contact hole (CNT9) formed in the interlayer insulation layer (217). A portion of the second vertical wiring (VL2v) may be embedded in the ninth contact hole (CNT9), and the portion of the second vertical wiring (VL2v) embedded in the ninth contact hole (CNT9) may be referred to as a ninth contact plug (CP9). That is, the ninth contact plug (CP9) can penetrate the insulation layer to connect the second vertical wiring (VL2v) to the second horizontal wiring (VL2h).

[0195] An interlayer insulation layer (217) may be interposed between the first vertical power line (PLv1) and the horizontal power line (PLh). The first vertical power line (PLv1) may be connected to the horizontal power line (PLh) through a tenth contact hole (CNT10) formed in the interlayer insulation layer (217). A portion of the first vertical power line (PLv1) may be embedded in the tenth contact hole (CNT10), and the portion of the first vertical power line (PLv1) embedded in the tenth contact hole (CNT10) may be referred to as a tenth contact plug (CP10). That is, the tenth contact plug (CP10) can penetrate the insulation layer to connect the first vertical power line (PLv1) to the horizontal power line (PLh).

[0196] Meanwhile, in FIG. 7, the horizontal power line (PLh) is shown placed on the second gate insulating layer (215) and the first vertical power line (PLv1) is shown placed on the interlayer insulating layer (217); however, as another embodiment, the horizontal power line (PLh) may be placed on the interlayer insulating layer (217) and the first vertical power line (PLv1) may be placed on the second gate insulating layer (215). As another example, the horizontal power line (PLh) may be placed on the first gate insulating layer (213).

[0197] As another example, the horizontal power line (PLh) and the first vertical power line (PLv1) can be formed on the same layer. That is, the horizontal power line (PLh) and the first vertical power line (PLv1) can be in direct contact. In this case, the tenth contact plug (CP10) can correspond to the part where the horizontal power line (PLh) and the first vertical power line (PLv1) come into contact. In other words, the tenth contact plug (CP10) can correspond to the part where the horizontal power line (PLh) and the first vertical power line (PLv1) intersect each other.

[0198] Although the explanation was based on the horizontal power line (PLh) and the first vertical power line (PLv1), the same can be applied to the first vertical wiring (VL1v) and the first horizontal wiring (VL1h), and / or the second vertical wiring (VL2v) and the second horizontal wiring (VL2h).

[0199] FIG. 8 illustrates equivalent circuit diagrams of each of a plurality of pixels according to another embodiment.

[0200] FIG. 8 illustrates a first pixel (PXi(j-1)), a second pixel (PXij), and a third pixel (PXi(j+1)). Since the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) are located in the same row, the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) can be connected to the same first to third scan lines (GWL_i, GIL_i, GBL_i) and light emission control line (EML_i). The first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) can be arranged sequentially in a second direction (DR2) and be adjacent to each other.

[0201] In one embodiment, among the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) arranged sequentially along the second direction (DR2), the first pixel (PXi(j-1)) and the second pixel (PXij) may share a first contact plug (CP1'), and the second pixel (PXij) and the third pixel (PXi(j+1)) may share a second contact plug (CP2').

[0202] The first contact plug (CP1') can be connected to a power line (PL) to which a first driving voltage (ELVDD) is applied, and the second contact plug (CP2') can be connected to a second voltage line (VL2) to which a second initialization voltage (VINT2) is applied.

[0203] Since the first pixel (PXi(j-1)) and the second pixel (PXij) share the first contact plug (CP1'), the first pixel (PXi(j-1)) and the second pixel (PXij) can be connected to the power line (PL) through the first contact plug (CP1'). Since the second pixel (PXij) and the third pixel (PXi(j+1)) share the second contact plug (CP2'), the second pixel (PXij) and the third pixel (PXi(j+1)) can be connected to the second voltage wiring (VL2) through the second contact plug (CP2').

[0204] In other words, the first contact plug (CP1') can connect the first pixel (PXi(j-1)) and the second pixel (PXij) to the power line (PL), and the second contact plug (CP2') can connect the second pixel (PXij) and the third pixel (PXi(j+1)) to the second voltage line (VL2).

[0205] The first contact plug (CP1') and the second contact plug (CP2') may correspond to a portion of the conductive layer as illustrated in FIG. 10, which will be described later. The first contact plug (CP1') and the second contact plug (CP2') may correspond to a portion of the conductive layer embedded within a contact hole formed in the insulating layer.

[0206] Based on the second pixel (PXij), the second pixel (PXij) may share the first contact plug (CP1') with the first pixel (PXi(j-1)) placed in the previous column and the second contact plug (CP2') with the third pixel (PXi(j+1)) placed in the next column.

[0207] The first pixel (PXi(j-1)) may share the second contact plug (CP2') with pixels placed in the previous column, such as the second pixel (PXij) and the third pixel (PXi(j+1)). Additionally, the third pixel (PXi(j+1)) may share the first contact plug (CP1') with pixels placed in the next column, such as the first pixel (PXi(j-1)) and the second pixel (PXij).

[0208] In this case, based on the first pixel (PXi(j-1)), the first pixel (PXi(j-1)) may share the second contact plug (CP2') with the pixel placed in the previous column and the first contact plug (CP1') with the second pixel (PXij) placed in the next column. Based on the third pixel (PXi(j+1)), the third pixel (PXi(j+1)) may share the second contact plug (CP2') with the second pixel (PXij) placed in the previous column and the first contact plug (CP1') with the pixel placed in the next column.

[0209] In other words, pixels arranged in the i-th row can be connected to each other through first contact plugs (CP1') and second contact plugs (CP2') arranged alternately along the second direction (DR2).

[0210] Although not shown in FIG. 8, pixels placed in the i-1 row, pixels placed in the i+1 row, etc., can be configured in the same way as pixels placed in the i-th row. In this case, the first contact plugs (CP1') and the second contact plugs (CP2'), etc., can each be placed along the first direction (DR1).

[0211] The power line (PL) may include a plurality of vertical power lines (PLv) and a plurality of horizontal power lines (PLh). Each of the vertical power lines (PLv) may extend in a first direction (DR1) to deliver a first driving voltage (ELVDD) to pixels (PX) arranged in the same column, and each of the horizontal power lines (PLh) may extend in a second direction (DR2) to deliver a first driving voltage (ELVDD) to pixels (PX) arranged in the same row.

[0212] Horizontal power lines (PLh) can be connected to vertical power lines (PLv). For example, as shown in FIG. 8, the horizontal power line (PLh) can be connected to the vertical power lines (PLv) through the 12th contact plugs (CP12).

[0213] In one embodiment, the first pixel (PXi(j-1)) and the second pixel (PXij) may share a power line (PL). For example, as shown in FIG. 8, the first pixel (PXi(j-1)) and the second pixel (PXij) may share a vertical power line (PLv) of the power line (PL). In this case, the number of vertical power lines (PLv) of the power line (PL) per unit area may be smaller than the number of data lines per unit area.

[0214] In one embodiment, the second pixel (PXij) and the third pixel (PXi(j+1)) may share the second voltage wiring (VL2). For example, as shown in FIG. 8, the second pixel (PXij) and the third pixel (PXi(j+1)) may share the second vertical wiring (VL2v) of the second voltage wiring (VL2). In this case, the number of second vertical wirings (VL2v) of the second voltage wiring (VL2) per unit area may be smaller than the number of first vertical wirings (VL1v) of the first voltage wiring (VL1) per unit area.

[0215] In one embodiment, the vertical power lines (PLv) of the power line (PL) and the second vertical lines (VL2v) of the second voltage line (VL2) may be arranged alternately along the second direction (DR2).

[0216] FIG. 9 illustrates a semiconductor pattern according to another embodiment.

[0217] Referring to FIG. 9, the display device may include a semiconductor pattern (Act).

[0218] The semiconductor pattern (Act) can be continuously extended along the second direction (DR2). The semiconductor pattern (Act) can be formed integrally by extending along the second direction (DR2) without any breaks. The semiconductor pattern (Act) illustrated in FIG. 9 is partially extended in the first direction (DR1), but can be extended in the second direction (DR2) when viewed as a whole. In other words, the semiconductor pattern (Act) includes a portion that extends in the first direction (DR1) microscopically, but can be extended in the second direction (DR2) as a whole.

[0219] A semiconductor pattern (Act) may include a plurality of pixel regions (Ai(j-1), Aij, Ai(j+1)), a plurality of first contact regions (Acp1) and a plurality of second contact regions (Acp2) disposed between the plurality of pixel regions (Ai(j-1), Aij, Ai(j+1)).

[0220] A plurality of pixel regions (Ai(j-1), Aij, Ai(j+1)) may each be included in a plurality of pixels (PXi(j-1), PXij, PXi(j+1)). A plurality of first contact regions (Acp1) may each correspond to a plurality of first contact plugs (CP1'), and a plurality of second contact regions (Acp2) may each correspond to a plurality of second contact plugs (CP2'). Alternatively, as illustrated in FIG. 10 to be described later, a plurality of first contact regions (Acp1) may each be in direct contact with a plurality of first contact plugs (CP1'), and a plurality of second contact regions (Acp2) may each be in direct contact with a plurality of second contact plugs (CP2').

[0221] In one embodiment, the first contact regions (Acp1) and the second contact regions (Acp2) may be arranged alternately along the second direction (DR2).

[0222] The first contact area (Acp1) can connect the pixel area (Ai(j-1)) of the first pixel (PXi(j-1)) and the pixel area (Aij) of the second pixel (PXij), and the second contact area (Acp2) can connect the pixel area (Aij) of the second pixel (PXij) and the pixel area (Ai(j+1)) of the third pixel (PXi(j+1)). As described above in FIG. 8, the first pixel (PXi(j-1)) shares the second contact plug (CP2') with the pixels placed in the previous column, such as the second pixel (PXij) and the third pixel (PXi(j+1)), and the third pixel (PXi(j+1)) can share the first contact plug (CP1') with the pixels placed in the next column, such as the first pixel (PXi(j-1)) and the second pixel (PXij). Accordingly, the pixel area (Ai(j-1)) of the first pixel (PXi(j-1)) and the pixel area of ​​the pixel placed in the previous column are connected to each other by the second contact area (Acp2), and the pixel area (Ai(j+1)) of the third pixel (PXi(j+1)) and the pixel area of ​​the pixel placed in the next column can be connected to each other by the first contact area (Acp1).

[0223] As a comparative example, the semiconductor pattern may include multiple island patterns that are spaced apart from each other and are not continuously extended along the row direction. The island patterns included in each of the multiple pixels may not be connected to each other. Static electricity may be generated (or introduced) from the outside due to processes such as forming the semiconductor pattern and then proceeding with subsequent processes. If the semiconductor pattern includes spaced-apart island patterns, the generated (or introduced) static electricity may be isolated within each of the island patterns. Consequently, the semiconductor pattern affected by static electricity is damaged, and pixel defects may be caused by the damaged semiconductor pattern.

[0224] However, as in one embodiment of the present invention, when the semiconductor pattern (Act) is continuously extended along the second direction (DR2), static electricity generated (or introduced) from the outside is not isolated and can be dispersed (or moved) along the second direction (DR2). Therefore, since static electricity is not isolated within the semiconductor pattern (Act) and can be dispersed along the second direction (DR2), damage to the semiconductor pattern (Act) can be prevented.

[0225] FIG. 10 is a cross-sectional view schematically illustrating a display device according to another embodiment.

[0226] FIG. 10 illustrates a portion of each of the first pixel (PXi(j-1)), the second pixel (PXij), and the third pixel (PXi(j+1)) based on FIG. 8 and FIG. 9, and some components may be omitted.

[0227] A first pixel (PXi(j-1)) may include a first light-emitting control transistor (T5i(j-1)), a second pixel (PXij) may include a driving transistor (T1ij), a first light-emitting control transistor (T5ij), and an anode initialization transistor (T7ij), and a third pixel (PXi(j+1)) may include an anode initialization transistor (T7i(j+1)).

[0228] The first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) may include an active region (A5i(j-1)) and a gate electrode (G). The active region (A5i(j-1)) of the first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) may correspond to a part of the pixel region (Ai(j-1), see FIG. 9) of the first pixel (PXi(j-1)).

[0229] The driving transistor (T1ij) of the second pixel (PXij) may include an active region (A1ij) and a gate electrode (G), the first light emission control transistor (T5ij) of the second pixel (PXij) may include an active region (A5ij) and a gate electrode (G), and the anode initialization transistor (T7ij) of the second pixel (PXij) may include an active region (A7ij) and a gate electrode (G). The active region (A1ij) of the driving transistor (T1ij) of the second pixel (PXij), the active region (A5ij) of the first light emission control transistor (T5ij) of the second pixel (PXij), and the active region (A7ij) of the anode initialization transistor (T7ij) of the second pixel (PXij) may each correspond to a part of the pixel region (Aij) of the second pixel (PXij).

[0230] The anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) may include an active region (A7i(j+1)) and a gate electrode (G). The active region (A7i(j+1)) of the anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) may correspond to a part of the pixel region (Ai(j+1), see FIG. 9) of the third pixel (PXi(j+1)).

[0231] The active region (A5i(j-1)) of the first light-emitting control transistor (T5i(j-1)) of the first pixel (PXi(j-1)) and the active region (A5ij) of the first light-emitting control transistor (T5ij) of the second pixel (PXij) can be connected to each other by a first contact region (Acp1). The active region (A7ij) of the anode initialization transistor (T7ij) of the second pixel (PXij) and the active region (A7i(j+1)) of the anode initialization transistor (T7i(j+1)) of the third pixel (PXi(j+1)) can be connected to each other by a second contact region (Acp2).

[0232] An insulating layer, such as a first gate insulating layer (213), a second gate insulating layer (215), and an interlayer insulating layer (217), may be interposed between the first contact region (Acp1) of the semiconductor pattern (Act, see FIG. 9) and the power line (PL).

[0233] The power line (PL) can be connected to the first contact region (Acp1) of the semiconductor pattern (Act) through a first contact hole (CNT1') formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the power line (PL) can be embedded in the first contact hole (CNT1'), and the portion of the power line (PL) embedded in the first contact hole (CNT1') can be referred to as the first contact plug (CP1'). That is, the first contact plug (CP1') can penetrate the insulating layer to connect the power line (PL) to the first contact region (Acp1) of the semiconductor pattern (Act).

[0234] An insulating layer, such as a first gate insulating layer (213), a second gate insulating layer (215), and an interlayer insulating layer (217), may be interposed between the second contact region (Acp2) of the semiconductor pattern (Act) and the second voltage wiring (VL2).

[0235] The second voltage wiring (VL2) can be connected to the second contact region (Acp2) of the semiconductor pattern (Act) through a second contact hole (CNT2') formed in the first gate insulating layer (213), the second gate insulating layer (215), and the interlayer insulating layer (217). A portion of the second voltage wiring (VL2) can be embedded in the second contact hole (CNT2'), and the portion of the second voltage wiring (VL2) embedded in the second contact hole (CNT2') can be referred to as a second contact plug (CP2'). That is, the second contact plug (CP2') can penetrate the insulating layer to connect the second voltage wiring (VL2) to the second contact region (Acp2) of the semiconductor pattern (Act).

[0236] Although the present invention has primarily described display devices so far, it is not limited thereto. For example, a method for manufacturing such a display device is also considered to fall within the scope of the present invention.

[0237] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0238] 100: Display device 110: Display unit PX: Pixel VL1: First voltage wiring VL2: Second voltage wiring PL: Power line VINT1: First initialization voltage VINT2: Second initialization voltage ELVDD: First driving voltage ELVSS: Second driving voltage CP1, CP2, CP3: First to third contact plugs Act: Semiconductor pattern Aca: Connection area Acp: Contact area

Claims

Claim 1 A display device comprising: a substrate; a semiconductor pattern disposed on the substrate and having a first pixel area, a second pixel area, and a connection area; a first pixel including the first pixel area of ​​the semiconductor pattern; a second pixel including the second pixel area of ​​the semiconductor pattern and disposed adjacent to the first pixel along a row direction; a first vertical power line extending in a column direction on the first pixel area of ​​the semiconductor pattern and configured to deliver a driving voltage to the first pixel; and a second vertical power line extending in a column direction on the second pixel area of ​​the semiconductor pattern and configured to deliver the driving voltage to the second pixel, and electrically connected to the first vertical power line through the connection area of ​​the semiconductor pattern. Claim 2 A display device according to claim 1, further comprising: an insulating layer interposed between the semiconductor pattern and the first and second vertical power lines; a first contact plug penetrating the insulating layer and connecting the first vertical power line to one end of the connection area of ​​the semiconductor pattern; and a second contact plug penetrating the insulating layer and connecting the second vertical power line to the other end of the connection area of ​​the semiconductor pattern. Claim 3 A display device according to claim 1, further comprising: a third pixel disposed adjacent to the second pixel along the row direction; a first voltage wiring configured to transmit a first initialization voltage; a second voltage wiring configured to transmit a second initialization voltage; and a third contact plug connecting the second pixel and the third pixel to the second voltage wiring. Claim 4 A display device according to claim 3, further comprising: a fourth contact plug connecting the first pixel to the first voltage line; a fifth contact plug connecting the second pixel to the first voltage line; and a sixth contact plug connecting the third pixel to the first voltage line. Claim 5 A display device according to claim 3, comprising: a plurality of pixels arranged along the row direction and the column direction, including the first to third pixels; a plurality of first vertical power lines extending in the column direction on a pixel in row i and column j-1 among the plurality of pixels and configured to transmit the driving voltage to the pixel in row i and column j-1; a plurality of second vertical power lines extending in the column direction on a pixel in row i and column j among the plurality of pixels and configured to transmit the driving voltage to the pixel in row i and column j; and a plurality of third contact plugs connecting the pixel in row i and column j and the pixel in row i+1 among the plurality of pixels to the second voltage wiring, wherein the semiconductor pattern further comprises a plurality of connection regions connecting the plurality of first vertical power lines and the plurality of second vertical power lines to each other. (Here, i is a natural number, and j is a natural number that is odd or even.) Claim 6 In claim 5, the semiconductor pattern further comprises a plurality of pixel regions each included in pixels arranged along the row direction among the plurality of pixels, and a plurality of contact regions each corresponding to the plurality of third contact plugs. Claim 7 A display device according to claim 6, wherein the plurality of connection regions each connect the pixel region in row i, column j-1 and the pixel region in row i, column j among the plurality of pixel regions, and the plurality of contact regions each connect the pixel region in row i, column j and the pixel region in row i, column j+1 among the plurality of pixel regions. (Here, i is a natural number and j is a natural number that is odd or even.) Claim 8 In claim 6, the plurality of connection regions and the plurality of contact regions are alternately arranged along the row direction in a display device. Claim 9 A display device according to claim 5, wherein the plurality of first vertical power lines and the plurality of second vertical power lines are alternately arranged along the row direction, and the plurality of third contact plugs are arranged along the column direction. Claim 10 In claim 3, each of the first to third pixels comprises: a light-emitting element; a driving transistor that controls a current flowing to the light-emitting element according to a gate-source voltage; a scan transistor that transmits a data voltage to the driving transistor in response to a first scan signal; a storage capacitor having a first electrode and a second electrode connected to the gate of the driving transistor; a first initialization transistor that applies the first initialization voltage to the electrode of the driving transistor in response to a second scan signal; and a second initialization transistor that applies the second initialization voltage to the electrode of the light-emitting element in response to a third scan signal. Claim 11 A display device according to claim 1, further comprising: a first data line extending in the column direction and configured to transmit a first data voltage to the first pixel; and a second data line extending in the column direction and configured to transmit a second data voltage to the second pixel, wherein the first data line and the second data line are disposed between the first vertical power line and the second vertical power line. Claim 12 In claim 1, the connection area of ​​the semiconductor pattern is a display device that always electrically connects the first vertical power line and the second vertical power line. Claim 13 A display device according to claim 1, further comprising a horizontal power line extending in the row direction on the first pixel and the second pixel and electrically connected to the first vertical power line and the second vertical power line. Claim 14 In claim 1, the connection area is a display device that connects the first pixel area and the second pixel area to each other. Claim 15 A display device comprising: first to third pixels arranged sequentially along a row direction; a first voltage wiring configured to transmit a first initialization voltage to the first to third pixels; a second voltage wiring configured to transmit a second initialization voltage different from the first initialization voltage to the first to third pixels; a power line configured to transmit a driving voltage different from the first initialization voltage and the second initialization voltage to the first to third pixels; a first contact plug connecting the power line to the first pixel and the second pixel; and a second contact plug connecting the second voltage wiring to the second pixel and the third pixel. Claim 16 A display device according to claim 15, further comprising: a third contact plug connecting the first pixel to the first voltage line; a fourth contact plug connecting the second pixel to the first voltage line; and a fifth contact plug connecting the third pixel to the first voltage line. Claim 17 A display device according to claim 15, further comprising: a plurality of pixels arranged along the row direction and column direction, including the first to third pixels; a plurality of first contact plugs connecting the pixel in row i, column j-1 and the pixel in row i, column j among the plurality of pixels to the power line; and a plurality of second contact plugs connecting the pixel in row i, column j and the pixel in row i, column j+1 among the plurality of pixels to the second voltage line. (wherein i is a natural number and j is an odd or even natural number.) Claim 18 A display device according to claim 17, wherein the plurality of first contact plugs and the plurality of second contact plugs are alternately arranged along the row direction, and the plurality of first contact plugs and the plurality of second contact plugs are each arranged along the column direction. Claim 19 A display device according to claim 17, wherein each of the power lines includes a plurality of vertical power lines extending in the column direction, and each of the second voltage lines includes a plurality of vertical lines extending in the column direction, and the plurality of vertical power lines and the plurality of vertical lines are alternately arranged along the row direction. Claim 20 In claim 19, the display device further comprises a plurality of horizontal power lines, each of which extends in the row direction and is electrically connected to a plurality of vertical power lines.

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