Logic built-in self test device and operating method thereof

Abstract

A logic beast device and a method of operation thereof are disclosed. The logic beast device of the present invention may include a scan circuit comprising a plurality of connected scan chains each comprising a plurality of scan cells and at least one piece of hardware, a pattern generator for generating a test pattern to be provided to the scan circuit, a state storage register for storing the test pattern, a multi-input signature register for storing the output of the scan circuit, and an automatic test pattern generator for generating a deterministic pattern for determining the location where at least one piece of hardware is to be placed.

Description

Technology Field

[0001] The present invention relates to a logic beast device and a method of operation thereof. Background Technology

[0002] Logic Beast is a technology designed to detect circuit defects without the aid of external test equipment by embedding test hardware within digital circuits. This technology is primarily utilized to achieve high test coverage and reduce testing costs.

[0003] Conventional logic beast technology uses a Pseudo Random Pattern Generator (PRPG) to generate random patterns and analyzes test responses through a Multiple Input Signature Register (MISR) to check for internal circuit defects. However, due to the limitations of random patterns, this method requires a large number of patterns to achieve high test coverage, which results in longer test times and high power consumption during the scan cell shift process. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a logic beast device and a method of operation thereof that have high test coverage, reduced test time, and improved test efficiency using a relatively small number of test patterns. means of solving the problem

[0005] To solve the above technical problem, a logic beast device according to an embodiment of the present invention may include a scan circuit comprising a plurality of connected scan chains each comprising a plurality of scan cells and at least one piece of hardware, a pattern generation unit that generates a test pattern to be provided to the scan circuit, a state storage register that stores the test pattern, a multi-input signature register that stores the output of the scan circuit, and a beast control unit that includes an automatic test pattern generator that generates a deterministic pattern determining the location where the at least one piece of hardware is to be placed.

[0006] In one embodiment of the present invention, the pattern generation unit may include a linear feedback shift register (LFSR) and a phase shifter.

[0007] In one embodiment of the present invention, the beast control unit can determine the location where at least one piece of hardware is to be placed based on the deterministic pattern.

[0008] In one embodiment of the present invention, the beast control unit may determine the scan cell containing a relatively large number of designated bits included in the deterministic pattern among the plurality of scan cells as the location where the at least one hardware is to be placed.

[0009] In one embodiment of the present invention, the beast control unit may provide a control signal corresponding to a first logic value to at least one hardware during the N-1 cycle (where N is a natural number), and provide a second logic value obtained by inverting the first logic value to one or more hardware during the Nth cycle. Effects of the invention

[0010] The present invention has the effect of achieving high test coverage, reduced test time, and improved test efficiency by utilizing a relatively small number of test patterns. Brief explanation of the drawing

[0011] FIG. 1 is a drawing for explaining a logic beast device according to an embodiment of the present invention. FIG. 2 is a flowchart for explaining the operation method of a logic beast device according to an embodiment of the present invention. Figure 3 is a diagram illustrating a method for adding hardware modules using a deterministic pattern. Figure 4 is a diagram illustrating how a test pattern is used in the scan test process. Specific details for implementing the invention

[0012] The present invention is capable of various modifications and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0013] In describing the present invention, if it is determined that a detailed description of related known technology may obscure the essence of the present invention, such detailed description is omitted.

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0016] FIG. 1 is a drawing for explaining a logic beast device according to an embodiment of the present invention.

[0017] Referring to FIG. 1, the logic beast device (100) may include a beast control unit (110), a state storage register (120), a pattern generation unit (130), a scan circuit (140), and a Multi Input Signature Register (MISR, 150). In an embodiment, although not shown in FIG. 1, the logic beast device (100) may further include an Automatic Test Pattern Generation (ATPG). The Automatic Test Pattern Generation (ATPG) may be included in the beast control unit (110).

[0018] The state storage register (120) can store a pattern (or seed) generated by the pattern generation unit (130).

[0019] The pattern generation unit (130) can generate a test pattern. In an embodiment, the pattern generation unit (130) may include a pseudo random pattern generator (PRPG) composed of a linear feedback shift register (LFSR) and a phase shifter.

[0020] The scan circuit (140) may include a plurality of scan chains (141) and at least one piece of hardware (142). Each scan chain may include a plurality of scan cells. In an embodiment, the lengths of each scan chain may differ from one another. The scan chain may include a plurality of flip-flops connected in a chain form and a logic circuit connected thereto. The scan chain may load test data provided by the pattern generator (130) into the flip-flops of the scan chain, capture the output of the logic circuit connected to the flip-flops, and provide the captured data to a multiple input signature register (150).

[0021] At least one piece of hardware may be an exclusive OR element (XOR gate). The XOR gate may be placed at a position corresponding to a selected scan cell among a plurality of scan cells included in a scan chain. The XOR gate may receive the output of the previous scan chain and a signal bit provided by the beast control unit (110). If any one of the inputs of the XOR gate is a logical value “0”, the output of the XOR gate is the same as the remaining input, and if any one of the inputs of the XOR gate is a logical value “1”, the output of the XOR gate may be the inverted value of the remaining input.

[0022] The multi-input signature register (150) can output compressed results according to the test operation.

[0023] The beast control unit (110) can control the overall operation of the logic beast device (100). According to an embodiment of the present invention, the beast control unit (110) can determine a specified bit using a deterministic pattern (or deterministic pattern) generated by an Automatic Test Pattern Generation (ATPG).

[0024] The beast control unit (110) can add hardware to the location of the scan cell corresponding to the specified bit. Afterward, the beast control unit (110) can perform a scan test. The beast control unit (110) can control the state storage register (120) to store the test pattern generated by the pattern generation unit (130).

[0025] Assuming there are N total test cycles, the beast control unit (110) can provide a signal bit corresponding to a logic value “0” to the XOR gate during N-1 cycles. During N-1 cycles, the test pattern can be provided to the scan circuit (140) while shifting.

[0026] Subsequently, the beast control unit (110) can provide the initial test pattern stored in the state storage register (120) to the pattern generation unit (130). In N cycles, the beast control unit (110) can provide a signal bit corresponding to a logic value “0” to the XOR gate.

[0028] FIG. 2 is a flowchart for explaining the operation method of a logic beast device according to an embodiment of the present invention.

[0029] Referring to FIG. 2, in step S210, the logic beast device can generate a deterministic pattern (or decision pattern) through an Automatic Test Pattern Generation (ATPG).

[0030] In step S220, the logic beast device analyzes the generated deterministic pattern (or deterministic pattern) and can identify the location of a scan cell containing a large number of specified bits among a plurality of scan cells. Specifically, the logic beast device can obtain a target index, which is the index of the scan cell containing the most bits specified as “0” or “1”.

[0031] In step S230, the logic beast device can add hardware to the scan cell. Specifically, the logic beast device can add an exclusive OR element (XOR gate) to the location of the scan cell corresponding to the target index.

[0032] In steps S240 through S300, the logic beast device can perform a scan test. Specifically, in step S240, the logic beast device can activate a pseudo random pattern generator (PRPG) composed of a linear feedback shift register (LFSR) and a phase shifter. The pseudo random pattern generator (PRPG) can generate a test pattern used in the scan test.

[0033] In step S250, the logic beast device can store an initial start state. Specifically, the logic beast device can store a seed value in a state storage register (120) the test pattern (or seed) generated by the pattern generation unit (130) described with reference to FIG. 1.

[0034] Assuming there are N total test cycles, steps S280 through S300 may be repeated during N-1 cycles (when test_count is 1). During N-1 cycles, the test pattern may be shifted in step S280. In step S290, the test result may be captured. When N-1 cycles are completed, in step S300, the signal bit may be inverted and test_count may be changed to 0.

[0035] In the N cycle, steps S260 and S270 can be performed.

[0036] In step S260, the logic beast device can shift the test pattern.

[0037] In step S270, the logic beast device can capture the test results.

[0038] Through the operation described above, the logic beast device can input an inverted value to only a specific scan cell by changing the control signal (signal bit) provided to the hardware to 1 in the last Nth cycle. This allows two tests to be performed with a single test pattern.

[0040] Figure 3 is a diagram illustrating a method for adding hardware modules using a deterministic pattern.

[0041] Figure 3 illustrates an example of a deterministic pattern (or decision pattern) generated through an Automatic Test Pattern Generation (ATPG).

[0042] Referring to FIG. 3, in an embodiment of the present invention, it is assumed that there are 10 scan cells (first scan cell to tenth scan cells). The scan cell index (Scan Cell Index) corresponds to each of the first to tenth scan cells and may be a number for identifying the scan cells (1 to 10).

[0043] An Automatic Test Pattern Generation (ATPG) can generate a deterministic pattern. The deterministic pattern may include first to fifth patterns. The first to fifth patterns may include expected result values ​​for each scan cell. For example, a value indicated as “0” or “1” may be a specified bit. It may represent either a value of “0” or “1” indicated as “X”.

[0044] According to the deterministic pattern (or deterministic pattern) illustrated in FIG. 3, the ratio of designated bits of the second scan cell, the sixth scan cell, and the ninth scan cell is 80%, which is a higher ratio compared to other scan cells. Therefore, exclusive OR elements (XOR gates) can be added at positions corresponding to the second scan cell, the sixth scan cell, and the ninth scan cell.

[0046] Figure 4 is a diagram illustrating how a test pattern is used in the scan test process.

[0047] Referring to FIG. 4, the pseudo-random pattern generator (130) described with reference to FIG. 1 may include a linear random shift register (131) and a phase shifter (132).

[0048] S400 is a diagram illustrating the state in which a seed (or test pattern) is stored in a state storage register (120) described with reference to FIG. 1 before the start of the test. In step S400, the seed (0, 1, 1 ..., 0, 0, 1) generated by the pseudo-random pattern generator (130) is stored in a linear random shift register (131).

[0049] Step S410 is a diagram describing the state in which the test has started. In Step S410, the seed (0, 1, 1 ..., 0, 0, 1) may be stored in the state storage register (120).

[0050] Assuming there are N total test cycles, step S420 is a diagram describing the state after the test results are captured (After Capture Cycle) while the test pattern is shifted during N-1 cycles. The seed (0, 1, 1 ..., 0, 0, 1) stored in the state storage register (120) can be moved back to the linear random shift register (131).

[0051] Through the above process, testing of a specific scan cell can be performed repeatedly using the same seed. In conclusion, the present invention can improve the disadvantages of the existing method by combining three elements: the generation of a deterministic pattern, the analysis of a specified bit, and the addition of scan cell hardware (XOR gate).

[0053] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. In this application, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Explanation of the symbols

[0054] 100: Logic Beast Device 110: Beast Control Unit 120: State storage register 130: Pattern generation section 140: Scan circuit 141: Scan Chain 142: Hardware

Claims

Claim 1 A logic beast device comprising: a scan circuit including a plurality of connected scan chains each including a plurality of scan cells and at least one piece of hardware; a pattern generator that generates a test pattern to be provided to the scan circuit; a state storage register that stores the test pattern; a multi-input signature register that stores the output of the scan circuit; and a beast control unit that includes an automatic test pattern generator that generates a deterministic pattern to determine the location where the at least one piece of hardware is to be placed, wherein the beast control unit determines the location where the at least one piece of hardware is to be placed based on the deterministic pattern. Claim 2 In claim 1, the pattern generation unit is a logic beast device comprising a Linear Feedback Shift Register (LFSR) and a Phase Shifter. Claim 3 delete Claim 4 In claim 1, the beast control unit is a logic beast device that determines a scan cell containing a relatively large number of designated bits included in the deterministic pattern among the plurality of scan cells as the location where the at least one or more hardware is to be placed. Claim 5 In claim 1, the beast control unit is a logic beast device that provides a control signal corresponding to a first logic value to at least one hardware during the N-1 cycle (N is a natural number) and provides a second logic value obtained by inverting the first logic value to one or more hardware during the N cycle.

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