Electrostatic discharge protection circuit

Abstract

The present invention includes an electrostatic discharge protection circuit comprising: dummy patterns and pull-down switches arranged parallel to each other along a first direction; clamp switches arranged parallel to each other along the first direction between the dummy patterns and the pull-down switches; and a resistor arranged parallel to the pull-down switches and configured to transmit a power voltage supplied through a power terminal to a first gate pattern of the pull-down switches, wherein the drains of the clamp switches are commonly connected to the power terminal, the sources of the clamp switches are commonly connected to a ground terminal, and the first end of the pull-down switch and the second end of the resistor are connected to each other through a first wiring extended along the first direction.

Description

Technology Field

[0001] The present invention relates to an electrostatic discharge protection circuit, and more specifically, to an electrostatic discharge protection circuit comprising clamp switches. Background Technology

[0003] Electrostatics refers to the movement of electric charge caused by friction between two objects with different electric potentials. Electrostatics is a phenomenon in which high currents are generated within a short period of time, and it can occur not only in electronic devices but also in people or various objects. When electrostatics occur in electronic devices, the components constituting the device can be damaged by the static electricity.

[0004] Therefore, in electronic devices, an electrostatic discharge protection circuit may be used to protect components from static electricity. The problem to be solved

[0006] An embodiment of the present invention provides an electrostatic discharge protection circuit with reduced size. means of solving the problem

[0008] An electrostatic discharge protection circuit according to an embodiment of the present invention comprises: dummy patterns and pull-down switches arranged parallel to each other along a first direction; clamp switches arranged parallel to each other along the first direction between the dummy patterns and the pull-down switches; and a resistor arranged parallel to each other with the pull-down switches and configured to transmit a power voltage supplied through a power terminal to a first gate pattern of the pull-down switches, wherein the drains of the clamp switches are commonly connected to the power terminal and the sources of the clamp switches are commonly connected to a ground terminal, and the first end of the pull-down switch and the second end of the resistor are connected to each other through a first wiring extended along the first direction. Effects of the invention

[0010] This technology can reduce the size of the electrostatic discharge protection circuit. Brief explanation of the drawing

[0012] FIG. 1 is a drawing for explaining an electronic device including an electrostatic discharge protection circuit according to an embodiment of the present invention. FIG. 2 is a drawing for explaining an electrostatic discharge protection circuit according to an embodiment of the present invention. FIG. 3 is a layout diagram illustrating the structure of an electrostatic discharge protection circuit according to an embodiment of the present invention. Figure 4 is a diagram illustrating the structure of the I-I' cross-section of the electrostatic discharge protection circuit shown in Figure 3. Figure 5 is a diagram illustrating the structure of the II-II' cross-section of the electrostatic discharge protection circuit shown in Figure 3. Figure 6 is a diagram illustrating the structure of the III-III' cross-section of the electrostatic discharge protection circuit shown in Figure 3. FIGS. 7a to 7f are drawings for explaining a method of manufacturing an electrostatic discharge protection circuit according to an embodiment of the present invention. Specific details for implementing the invention

[0013] Specific structural or functional descriptions of embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0015] FIG. 1 is a drawing for explaining an electronic device including an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0016] Referring to FIG. 1, an electronic device (1000) may include an electrostatic discharge protection circuit (ESD protection circuit; 100) and an internal circuit (200).

[0017] The electrostatic discharge protection circuit (100) can be configured to discharge the electrostatic discharge from the power terminal (VDD) through the ground terminal (GND) when electrostatic discharge occurs at the power terminal (VDD) connected to the internal circuit (200).

[0018] The internal circuit (200) is a circuit configured to perform a main operation, and can receive power voltage through a power terminal (VDD) and be grounded through a ground terminal (GND). For example, the internal circuit (200) may include a circuit configured to store data, a circuit configured to output an image, or a circuit configured to communicate data, and may also be composed of various circuits depending on the electronic device (1000).

[0020] FIG. 2 is a drawing for explaining an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0021] Referring to FIG. 2, the electrostatic discharge protection circuit (100) may include a clamp switch group (CSG), a pull-down switch (PD), and a resistor (RES).

[0022] A clamp switch group (CSG) may be connected between a first node (N1) connected to a power terminal (VDD) and a second node (N2) connected to a ground terminal (GND). The clamp switch group (CSG) may be configured to discharge the voltage of the first node (N1) to the ground terminal (GND) through the second node (N2) when electrostatic discharge occurs. For example, the clamp switch group (CSG) may include first to nth clamp switches (C1 to Cn; n is a positive integer). Each of the first to nth clamp switches (C1 to Cn) may be composed of an NMOS transistor. For example, the first to nth clamp switches (C1 to Cn) may be connected in a gate-coupled NMOS (GCNMOS) structure. For example, the first to nth clamp switches (C1 to Cn) may be connected in series with each other between the second and first nodes (N2, N1). The source of the first clamp switch (C1) can be connected to the second node (N2), and the drain of the nth clamp switch (Cn) can be connected to the first node (N1). Among the first to nth clamp switches (C1 to Cn), the drains of the odd-numbered switches can be commonly connected to the first node (N1), and the sources can be commonly connected to the second node (N2). In other words, the drains of the even-numbered switches among the first to nth clamp switches (C1 to Cn) can be commonly connected to the second node (N2), and the sources can be commonly connected to the first node (N1). Preferably, the first to nth clamp switches (C1 to Cn) can be configured in an odd number so that static electricity generated at the first node (N1) can be discharged through the second node (N2). The gates of the first to nth clamp switches (C1~Cn) can be commonly connected to the third node (N3).

[0023] The pull-down switch (PD) can be composed of an NMOS transistor connected between the second node (N2) and the third node (N3). The gate of the pull-down switch (PD) can be connected to the fourth node (N4), and the resistor (RES) can be connected between the fourth node (N4) and the first node (N1).

[0024] A plurality of conductive films and insulating films may be included in a structure connecting the drain of a pull-down switch (PD) and the gates of the first to nth clamp switches (C1 to Cn), and such a structure may perform the function of a capacitor (CAP) between the pull-down switch (PD) and the first to nth clamp switches (C1 to Cn). Accordingly, the first to nth clamp switches (C1 to Cn) may be turned on in response to a voltage charged in the capacitor (CAP).

[0026] FIG. 3 is a layout diagram for explaining the structure of an electrostatic discharge protection circuit (100) according to an embodiment of the present invention, FIG. 4 is a diagram for explaining the structure of the I-I' cross-section of the electrostatic discharge protection circuit (100) shown in FIG. 3, FIG. 5 is a diagram for explaining the structure of the II-II' cross-section of the electrostatic discharge protection circuit (100) shown in FIG. 3, and FIG. 6 is a diagram for explaining the structure of the III-III' cross-section of the electrostatic discharge protection circuit (100) shown in FIG. 3.

[0027] Referring to FIGS. 3 to 6, the electrostatic discharge protection circuit (100) may include a first N-well (1NW) formed within a substrate (SUB), a second N-well (2NW) formed within the first N-well (1NW), and a first P-well (1PW) formed within the second N-well (2NW). It may also include first to n clamp switches (C1~Cn), a pull-down switch (PD), a resistor (RES), and a dummy pattern (DPT) formed on the upper part of the first P-well (1PW).

[0028] When the substrate (SUB) is formed of P-type silicon, the first N-well (1NW) may be a deep N-well formed in a square shape within the substrate (SUB). The second N-well (2NW) may be formed in a square pattern with the left, right, and bottom sides surrounded by the first N-well (1NW). The first N-well (1NW) and the second N-well (2NW) are regions in which N-type impurities are injected into the substrate (SUB), and the concentration of impurities injected into the second N-well (2NW) may be higher than the concentration of impurities injected into the first N-well (1NW).

[0029] A first junction region (1JC) may be formed inside the second N-well (2NW). The first junction region (1JC) is a region corresponding to the first node (N1) of the electrostatic discharge protection circuit (100) and may be connected to a power terminal (VDD). The first junction region (1JC) is a region into which N-type impurities are injected, and may be formed to have a higher concentration than the concentration of impurities injected into the second well (2NW).

[0030] A first P-well (1PW) having the same depth as the second N-well (2NW) may be formed in the inner region of the second N-well (2NW). The first P-well (1PW) may be formed by injecting P-type impurities into the substrate (SUB). A second junction region (2JC) may be formed inside the first P-well (1PW). The second junction region (2JC) is a region corresponding to the second node (N2) of the electrostatic discharge protection circuit (100) and may be connected to a ground terminal (GND).

[0031] The first to nth clamp switches (C1~Cn), pull-down switch (PD), resistor (RES), and dummy pattern (DPT) included in the electrostatic discharge protection circuit (100) may be formed on the upper part (D3) of the first P-well (1PW) surrounded by the second junction region (2JC). Each of the first to nth clamp switches (C1~Cn), pull-down switch (PD), resistor (RES), and dummy pattern (DPT) may include an insulating film (IS) and a gate pattern (GT) stacked on the upper part of the first P-well (1PW).

[0032] The first to nth clamp switches (C1 to Cn) may be arranged in series along a first direction (D1). Each of the first to nth clamp switches (C1 to Cn) may include gate patterns (GT) extended along a second direction (D2) orthogonal to the first direction (D1), and third junction regions (3JC) extended along the second direction (D2) and arranged parallel to each other. Clamp switches adjacent to each other among the first to nth clamp switches (C1 to Cn) may share a drain or a source. For example, the first and second clamp switches (C1, C2) may share a drain connected to the first node (N1), and the second and third clamp switches (C2, C3) may share a source connected to the second node (N2).

[0033] The gate patterns (GT) of the first to nth clamp switches (C1 to Cn) extend in a second direction (D2), and the ends of the gate patterns (GT) can be commonly connected to the metal wiring (ML) corresponding to the third node (N3) through contacts (CT) (see FIG. 6). The metal wiring (ML) corresponding to the third node (N3) is also connected to the junction area of ​​the pull-down switch (PD) through contacts (CT). For example, the metal wiring (ML) corresponding to the third node (N3) can be connected through a contact (CT) formed on the upper part of the drain of the pull-down switch (PD). Since an insulating material is filled between the contacts (CT) and the gate patterns (GT) commonly connected to the metal wiring (ML) corresponding to the third node (N3), a capacitor (CAP) can be formed in which the contacts (CT) and gate patterns (GT) formed of a conductive material and the insulating material are alternately arranged. The voltage charged in the capacitor (CAP) can be applied to the gate patterns (GT) of the first to nth clamp switches (C1~Cn).

[0034] A pull-down switch (PD) may be arranged to the right of the first clamp switch (C1), and a resistor (RES) may be arranged to the right of the pull-down switch (PD).

[0035] The gate pattern (GT) of the pull-down switch (PD) may extend along a second direction (D2), and a junction region protruding upward from the gate pattern (GT) of the pull-down switch (PD) in the second direction (D2) may be commonly connected to the gate patterns (GT) of the first to nth clamp switches (C1 to Cn) through a third node (N3). For example, the junction region protruding upward from the pull-down switch (PD) in the second direction (D2) may be in contact with the third node (N3) through a contact (CT). The gate patterns (GT) of the first to nth clamp switches (C1 to Cn) may be commonly in contact with the third node (N3) through different contacts (CT). The junction region protruding downward from the gate pattern (GT) of the pull-down switch (PD) in the second direction (D2) may be in contact with the second junction region (2JC) through a contact (CT).

[0036] The gate pattern (GT) of the pull-down switch (PD) can be in contact with the resistor (RES) through the fourth node (N4). For example, in this embodiment, the pull-down switch (PD) and the resistor (RES) are not connected to each other through contacts, but can be connected to each other through the fourth node (N4) formed on the same plane. That is, the insulating film (IS) of the pull-down switch (PD), the fourth node (N4), and the resistor (RES) can be formed as a single pattern, and the gate pattern (GT) can also be formed as a single pattern stacked on the insulating film (IS). The resistor (RES) can be in contact with the first junction region (1JC) through contacts.

[0037] A dummy pattern (DPT) may be arranged in an adjacent area spaced to the left of the nth clamp switch (Cn). The dummy pattern (DPT) may be an auxiliary pattern for forming the gate pattern (GT) of the nth clamp switch (Cn) into a desired pattern during the manufacturing process of the electrostatic discharge protection circuit (100). For example, due to the characteristics of the manufacturing process, during the patterning and flattening processes for forming the gate patterns (GT), defects may occur in which a part of the pattern collapses between areas with high and low density of patterns. Therefore, in this embodiment, to prevent physical defects of the nth clamp switch (Cn) that may occur during the manufacturing process, a dummy pattern (DPT) may be formed in an area adjacent to the nth clamp switch (Cn) where clamp switches are not formed.

[0038] In this embodiment, a dummy pattern (DPT) is formed to prevent physical defects in the nth clamp switch (Cn), but a dummy pattern to prevent physical defects in the first clamp switch (C1) is not used. In this embodiment, to prevent physical defects that may occur in the first clamp switch (C1), a pull-down switch (PD) is formed in an area adjacent to the gate pattern (GT) of the first clamp switch (C1). For example, conventionally, a dummy pattern was formed between the first clamp switch (C1) and the pull-down switch (PD) to prevent physical defects in the first clamp switch (C1). However, since the size of the electrostatic discharge protection circuit (100) increases as the number of dummy patterns that are not electrically used increases, in this embodiment, instead of omitting the dummy pattern in the area adjacent to the first clamp switch (C1), a pull-down switch (PD) can be formed in the area adjacent to the first clamp switch (C1). The pull-down switch (PD) may be formed to maintain a certain first gap (1DS) from the first clamp switch (C1) so that the gate of the pull-down switch (PD) does not come into direct contact with the third junction area (3JC) for the source of the first clamp switch (C1). For example, the first gap (1DS) may be set as the minimum gap among the areas where the gap range in which the gate of the first clamp switch (C1) does not collapse and the gap range in which the first clamp switch (C1) and the pull-down switch (PD) are not electrically interfered with overlap each other.

[0039] In this embodiment, the gate pattern (GT) of the pull-down switch (PD), the gate pattern (GT) of the fourth node (N4), and the gate pattern (GT) of the resistor (RES) are formed as a single gate pattern (GT) (see FIG. 5), so separate contacts are not used to electrically connect the pull-down switch (PD) and the resistor (RES). Therefore, the second gap (2DS) between the pull-down switch (PD) and the resistor (RES) can be equal to the length of the fourth node (N4).

[0041] FIGS. 7a to 7f are drawings for explaining a method of manufacturing an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0042] Referring to FIG. 7a, a first N-well (1NW) can be formed by injecting N-type impurities into a substrate (SUB) at a first concentration. The first N-well (1NW) is a well that defines the region where semiconductor devices are to be formed, and can be formed as a deep well with the deepest depth.

[0043] Referring to FIG. 7b, a second N-well (2NW) and a first P-well (1PW) may be formed inside the first N-well (1NW), having the same depth as the first N-well (1NW) but a shallower depth than the first N-well (1NW). For example, the second N-well (2NW) may be formed by injecting N-type impurities into the first N-well (1NW) at a second concentration higher than the first concentration, and the first P-well (1PW) may be formed by injecting P-type impurities into the second N-well (2NW). Thus, the second N-well (2NW) may be surrounded on the left, right, and bottom by the first N-well (1NW), and the first P-well (1PW) may be surrounded on the left and right by the second N-well (2NW) and surrounded on the bottom by the first N-well (1NW).

[0044] Referring to FIG. 7c, a first junction region (1JC) with an exposed upper surface may be formed inside the second N-well (2NW). For example, the first junction region (1JC) may correspond to the first node (N1 in FIG. 2) of the electrostatic discharge protection circuit. The first junction region (1JC) may be formed by injecting N-type impurities at a third concentration higher than the second concentration of the second N-well (2NW). A second junction region (2JC) with an exposed upper surface may be formed in the first P-well (1PW). For example, the second junction region (2JC) may correspond to the second node (N2 in FIG. 2) of the electrostatic discharge protection circuit. The second junction region (2JC) may be formed by injecting P-type impurities at a concentration higher than the concentration of P-type impurities injected into the first P-well (1PW).

[0045] Referring to FIG. 7d, an insulating film (IS) is formed on the upper part of the entire structure in which the first and second junction regions (1JC, 2JC) are formed, and a conductive film for a gate pattern (GT) can be formed on the upper part of the insulating film (IS). The insulating film (IS) can be formed as an oxide film or a silicon oxide film, and the gate pattern (GT) can be formed as an electrically conductive material such as polysilicon, tungsten, or nickel, and various other materials may also be formed.

[0046] Referring to FIG. 7e, a conductive film and an insulating film (IS) for a gate pattern (GT) can be patterned to form patterns for the first to nth clamp switches (C1~Cn), a pull-down switch (PD), and a resistor (RES), as well as a dummy pattern (DPT). At this time, the pattern for the pull-down switch (PD) and the dummy pattern (DPT) can be used to prevent physical defects in the patterns for the first to nth clamp switches (C1~Cn) by maintaining the density of the pattern around the area where the first to nth clamp switches (C1~Cn) are formed.

[0047] Referring to FIG. 7f, third junction regions (3JC) can be formed by injecting impurities into the first P-well (1PW) exposed between the patterns for the first to nth clamp switches (C1 to Cn). Since the third junction regions (3JC) become the drain or source of the clamp switches, the first to nth clamp switches (C1 to Cn) can be formed by forming the third junction regions (3JC). Although not shown in the cross-sectional view of FIG. 7f, when the third junction region (3JC) is formed between the first to nth clamp switches (C1 to Cn), the drain and source of the pull-down switch (PD) can also be formed simultaneously. Explanation of the symbols

[0049] 100: Electrostatic discharge protection circuit 200: Internal circuit CSG: Clamp switch group C1~Cn: Clamp switches PD: Pull-down switch RES: Resistor DPT: Dummy Pattern NW: N-Well PW: P-well

Claims

Claim 1 An electrostatic discharge protection circuit comprising: dummy patterns and pull-down switches arranged parallel to each other along a first direction; clamp switches arranged parallel to each other along the first direction between the dummy patterns and the pull-down switches; and a resistor arranged parallel to the pull-down switches and configured to transmit a power voltage supplied through a power terminal to a first gate pattern of the pull-down switches, wherein the drains of the clamp switches are commonly connected to the power terminal and the sources of the clamp switches are commonly connected to a ground terminal, and the first end of the pull-down switch and the second end of the resistor are connected to each other through a first wiring extended along the first direction, and the pull-down switches, the resistor, and the first wiring are formed on the same layer. Claim 2 An electrostatic discharge protection circuit according to claim 1, wherein the first gate pattern extends along a second direction orthogonal to the first direction and has a first end and a third end in the opposite direction from the first end. Claim 3 In paragraph 2, the pull-down switch comprises an electrostatic discharge protection circuit including a source in contact with the first end; and a drain in contact with the third end. Claim 4 An electrostatic discharge protection circuit according to claim 1, wherein the clamp switches extend along a second direction orthogonal to the first direction and include second gate patterns arranged parallel to each other along the first direction. Claim 5 In claim 4, the drains and sources of the clamp switches are alternately arranged parallel to each other along the first direction between the second gate patterns in an electrostatic discharge protection circuit. Claim 6 In paragraph 4, the fourth ends of the second gate patterns are connected to the drain of the pull-down switch through contacts and second wiring in an electrostatic discharge protection circuit. Claim 7 In claim 6, the above contacts comprise: first contacts formed on the upper portions of the fourth ends; and a second contact formed on the upper portion of the drain of the pull-down switch, forming an electrostatic discharge protection circuit. Claim 8 In claim 7, the second wiring is an electrostatic discharge protection circuit disposed above the first contacts and the second contact. Claim 9 In claim 1, the dummy pattern, the clamp switches, the pull-down switch, the first wiring, and the resistor are an electrostatic discharge protection circuit formed on the upper part of the first well. Claim 10 An electrostatic discharge protection circuit according to claim 9, further comprising a first junction area formed such that the upper surface is exposed inside the first well and is formed as a square pattern surrounding the dummy pattern, the clamp switches, the pull-down switch, the first wiring, and the resistor. Claim 11 In item 10, the first junction area is an electrostatic discharge protection circuit connected to the ground terminal. Claim 12 In claim 9, the first well is an electrostatic discharge protection circuit formed by injecting P-type impurities into a substrate. Claim 13 In claim 9, an electrostatic discharge protection circuit is formed such that the source of the first clamp switch and the first well are formed between the gate pattern of the first clamp switch adjacent to the pull-down switch among the clamp switches and the gate pattern of the pull-down switch. Claim 14 An electrostatic discharge protection circuit according to claim 10, formed by injecting N-type impurities into a substrate and further comprising a second well surrounding the first well. Claim 15 In paragraph 14, the depth of the second well is the same as the depth of the first well in the electrostatic discharge protection circuit. Claim 16 An electrostatic discharge protection circuit according to claim 14, further comprising a second junction area formed such that the upper surface is exposed inside the second well and is formed in a square pattern surrounding the first well in an area spaced apart from the first well. Claim 17 In Clause 16, the second junction area is an electrostatic discharge protection circuit connected to the power terminal. Claim 18 In claim 14, an electrostatic discharge protection circuit formed by injecting the N-type impurity into the substrate and further comprising a third well surrounding the second well. Claim 19 In paragraph 18, an electrostatic discharge protection circuit in which the concentration of the N-type impurity contained in the third well is lower than the concentration of the N-type impurity contained in the second well. Claim 20 In paragraph 18, the electrostatic discharge protection circuit in which the depth of the third well is deeper than the depth of the second well.

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