Single photon detector

Abstract

A single-photon detector comprises a high-concentration doping region having a first conductivity type, a buried region provided on the high-concentration doping region having a second conductivity type different from the first conductivity type, a first well provided between the high-concentration doping region and the buried region having a second conductivity type, a second well provided between the high-concentration doping region and the first well having a second conductivity type, and a contact electrically connected to the buried region having a second conductivity type, a single-photon avalanche diode having a first surface and a second surface facing each other, and an output pattern electrically connected to the high-concentration doping region and configured to reflect light transmitted through the single-photon avalanche diode, and a bias pattern electrically connected to the contact and configured to reflect light transmitted through the single-photon avalanche diode, and a connection layer provided on the first surface.

Description

Technology Field

[0001] The present disclosure relates to a single-photon detector. Background Technology

[0002] An avalanche photodiode (APD) is a solid-state photodetector in which a high bias voltage is applied to a pn junction to provide high gain due to avalanche multiplication. When an incident photon with energy greater than the semiconductor bandgap reaches the photodiode, electron-hole pairs (EHPs) are generated. A high electric field rapidly accelerates photo-generated electrons toward the positive side; impact ionization by these accelerated electrons generates additional electron-hole pairs in succession, and then all of these electrons are accelerated toward the positive side. Similarly, holes are rapidly accelerated toward the negative side, causing the same phenomenon. This process repeats, leading to the avalanche multiplication of photo-generated electrons or holes. Therefore, an APD is a semiconductor-based device that operates similarly to a photomultiplier tube. A linear mode APD is an effective amplifier that sets the gain by controlling the bias voltage and can obtain gains of tens to thousands in linear mode.

[0003] A single-photon avalanche diode (SPAD) is an APD in which the pn junction is biased above its breakdown voltage to operate in Geiger mode. A single incident photon triggers the avalanche phenomenon, which can generate a very large current, thereby allowing for the generation of easily measurable pulses in conjunction with a quenching resistor or circuit. In other words, a SPAD operates as a device that generates large pulses compared to a linear mode APD. After triggering the avalanche, a quenching resistor or circuit is used to reduce the bias voltage below the breakdown voltage to quench the avalanche process. Once quenched, the bias voltage is raised back above the breakdown voltage to reset the SPAD for the detection of another photon.

[0004] SPADs can be configured with quenching resistors or circuits, as well as recharge circuits, memory, gate circuits, counters, time-to-digital converters, etc. Since SPAD pixels are semiconductor-based, they can be easily configured into arrays. The problem to be solved

[0005] The problem to be solved is to provide a single-photon detector with improved noise characteristics.

[0006] The problem to be solved is to provide a single-photon detector with improved efficiency.

[0007] The problem to be solved is to provide a single-photon detector with a low breakdown voltage.

[0008] The problem to be solved is to provide a single-photon detector that operates without the formation of a guard ring.

[0009] The problem to be solved is to provide a single-photon detector that operates more stably.

[0010] The problem to be solved is to provide a single-photon detector including an enhanced guard ring.

[0011] However, the problems to be solved are not limited to the above disclosure. means of solving the problem

[0012] In one aspect, a single-photon detector may be provided comprising: a high-concentration doping region having a first conductivity type; a buried region provided on the high-concentration doping region and having a second conductivity type different from the first conductivity type; a first well provided between the high-concentration doping region and the buried region and having the second conductivity type; a second well provided between the high-concentration doping region and the first well and having the second conductivity type; and a contact electrically connected to the buried region and having the second conductivity type, and a single-photon avalanche diode having a first surface and a second surface facing each other; and a connection layer provided on the first surface, comprising an output pattern electrically connected to the high-concentration doping region and configured to reflect light transmitted through the single-photon avalanche diode, and a bias pattern electrically connected to the contact and configured to reflect light transmitted through the single-photon avalanche diode.

[0013] The end of the high-concentration doping region may protrude from the side of the second well.

[0014] The first well can be extended along the side of the second well and come into contact with the end of the high-concentration doping region.

[0015] The single-photon avalanche diode may further include a guard ring provided on the side of the high-concentration doping region, having the first conductivity type and having a doping concentration lower than that of the high-concentration doping region.

[0016] The first well can be extended to the area between the guard ring and the second well.

[0017] The side of the first well may be exposed on the guard ring.

[0018] The above-mentioned buried area can be extended between the guard ring and the contact.

[0019] The single-photon avalanche diode may further include a low-concentration doping region provided between the second well and the high-concentration doping region and having the second conductivity type.

[0020] The single-photon avalanche diode may further include a guard ring that extends from the side of the high-concentration doping region onto the side of the second well, has the first conductivity type, and has a doping concentration lower than that of the high-concentration doping region.

[0021] The single-photon avalanche diode may further include a relaxation region provided between the first well and the contact, having the second conductivity type and having a lower doping concentration than the contact.

[0022] The first well can extend between the guard ring and the contact.

[0023] The output pattern and the bias pattern may be spaced apart from each other along a direction parallel to the first plane.

[0024] The above connection layer may further include a shield pattern provided between the output pattern and the bias pattern and configured to reflect light transmitted through the single-photon avalanche diode.

[0025] The shield pattern, the output pattern, and the bias pattern may be spaced apart from each other along a direction parallel to the first plane.

[0026] The single-photon avalanche diode may further include a relaxation region provided between the buried region and the contact, having the first conductivity type and having a lower doping concentration than the contact.

[0027] The single-photon avalanche diode may further include an additional relaxation region provided between the buried region and the relaxation region, extending along a direction perpendicular to the first plane and having the second conductivity type.

[0028] The first well extends along the side of the second well and contacts the high-concentration doping region, and the end of the high-concentration doping region may protrude from the side of the first well.

[0029] It may further include a lens provided on the second surface and configured to collect incident light and transmit it to the single-photon avalanche diode.

[0030] It may further include diffraction patterns provided on the second surface above and diffracting incident light to increase the absorption length of light within the single-photon avalanche diode.

[0031] It may further include a control layer provided on the opposite side of the single-photon avalanche diode with respect to the connection layer, which includes a circuit required for the operation of the single-photon avalanche diode. Effects of the invention

[0032] The present disclosure can provide a single-photon detector having improved noise characteristics.

[0033] The present disclosure can provide a single-photon detector having improved efficiency.

[0034] The present disclosure can provide a single-photon detector having a low breakdown voltage.

[0035] The present disclosure can provide a single-photon detector that operates without forming a guard ring.

[0036] The present disclosure can provide a single-photon detector that operates more stably.

[0037] The present disclosure may provide a single-photon detector comprising an enhanced guard ring.

[0038] The effects of the invention are not limited to the above disclosure. Brief explanation of the drawing

[0039] FIG. 1 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 2 is a cross-sectional view along line A-A' of the single-photon avalanche diode of Figure 1. FIG. 3 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 4 is a cross-sectional view along the B-B' line of the single-photon avalanche diode of Figure 3. FIG. 5 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 6 is a cross-sectional view along the C-C' line of the single-photon avalanche diode of Figure 5. FIG. 7 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 8 is a cross-sectional view along the D-D' line of the single-photon avalanche diode of Figure 7. FIG. 9 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 10 is a cross-sectional view along the E-E' line of the single-photon avalanche diode of Figure 9. FIG. 11 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 12 is a cross-sectional view along the F-F' line of the single-photon avalanche diode of Figure 11. FIG. 13 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 14 is a cross-sectional view along the G-G' line of the single-photon avalanche diode of Figure 13. FIG. 15 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 16 is a cross-sectional view along the H-H' line of the single-photon avalanche diode of Figure 15. FIG. 17 is a plan view of a single-photon avalanche diode according to exemplary embodiments. FIG. 18 is a cross-sectional view along the line I-I' of the single-photon avalanche diode of FIG. 17. FIG. 19 is a plan view of a single-photon avalanche diode according to exemplary embodiments. FIG. 20 is a cross-sectional view along the J-J' line of the single-photon avalanche diode of FIG. 19. FIG. 21 is a plan view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. FIG. 22 is a plan view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. FIG. 23 is a plan view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. FIG. 24 is a plan view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. FIG. 25 is a plan view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. FIG. 26 is a plan view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. FIG. 27 is a cross-sectional view corresponding to the line H-H' of FIG. 15 of a single-photon avalanche diode according to exemplary embodiments. FIG. 28 is a cross-sectional view corresponding to the line H-H' of FIG. 15 of a single-photon avalanche diode according to exemplary embodiments. FIG. 29 is a plan view of a single-photon avalanche diode according to exemplary embodiments. FIG. 30 is a cross-sectional view along the line I-I' of the single-photon avalanche diode of FIG. 29. FIG. 31 is a plan view of a single-photon avalanche diode according to exemplary embodiments. Figure 32 is a cross-sectional view along the J-J' line of the single-photon avalanche diode of Figure 31. FIG. 33 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. FIG. 34 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. FIG. 35 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. Figure 36 is a plan view of the diffraction pattern of Figure 35. FIG. 37 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. FIG. 38 is a plan view of a single-photon detector array according to an exemplary embodiment. FIG. 39 is a cross-sectional view along the line K-K' of FIG. 38. FIG. 40 is a plan view of the output pattern, bias pattern, and shield pattern of FIG. 39. FIG. 41 is a cross-sectional view along the K-K' line of FIG. 38. FIG. 42 is a cross-sectional view along the line K-K' of FIG. 38. FIG. 43 is a cross-sectional view along the K-K' line of FIG. 38. FIG. 44 is a cross-sectional view along the line K-K' of FIG. 38. FIG. 45 is a cross-sectional view along the line K-K' of FIG. 38. Fig. 46 is a cross-sectional view along the K-K' line of Fig. 38. Figure 47 is a cross-sectional view along the K-K' line of Figure 38. FIG. 48 is a block diagram illustrating an electronic device according to an exemplary embodiment. FIGS. 49 and FIGS. 50 are conceptual diagrams showing a case where a LiDAR device according to an exemplary embodiment is applied to a vehicle. FIG. 51 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. FIG. 52 is a cross-sectional view along the line K-K' of FIG. 38. Specific details for implementing the invention

[0040] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

[0041] In the following, what is described as "above" may include not only what is directly above in contact, but also what is above without contact.

[0042] In the following, “top surface” may refer to a surface positioned on the upper side of a drawing.

[0043] A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is said to "include" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0044] In addition, terms such as “part” as described in the specification refer to a unit that processes at least one function or operation.

[0046] FIG. 1 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 2 is a cross-sectional view along line A-A' of the single-photon avalanche diode of FIG. 1.

[0047] Referring to FIGS. 1 and 2, a single-photon avalanche diode (1000) may be provided. The single-photon avalanche diode (1000) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1000) may include a buried region (110), a first well (120), a first high-concentration doping region (140), a first low-concentration doping region (141), a first guard ring (142), a first contact (121), a first relaxation region (122), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first well (120), a first high-concentration doping region (140), a first low-concentration doping region (141), a first guard ring (142), a first contact (121), and a first relaxation region (122) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the first well (120), the first high-concentration doping area (140), the first low-concentration doping area (141), the first guard ring (142), the first contact (121), and the first relaxation area (122), may be referred to as the substrate area (102).

[0048] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0049] A first well (120) may be provided within a semiconductor substrate (100). A buried region (110) may be disposed between the first well (120) and the back surface (100b). The top and side surfaces of the first well (120) may be in direct contact with the buried region (110). The conductivity type of the first well (120) may be p-type. For example, the doping concentration of the first well (120) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the first well (120) may have a uniform doping concentration. In one example, the doping concentration of the first well (120) may become smaller as it approaches the front surface (100a).

[0050] A first high-concentration doping region (140) may be provided between the first well (120) and the front surface (100a). The first high-concentration doping region (140) may be exposed on the front surface (100a). The conductivity type of the first high-concentration doping region (140) may be n-type. The first high-concentration doping region (140) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. Hereinafter, the region having an n-type conductivity type may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1000) or receive a signal from the single-photon avalanche diode (1000).

[0051] The first low-concentration doping region (141) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When a reverse bias is applied to the single-photon avalanche diode (1000), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. The first low-concentration doping region (141) may be configured to reduce or prevent short-channel effects that occur as the size of the semiconductor device decreases. For example, a short-channel effect may be current flowing even when no photon is incident on the single-photon avalanche diode (1000). The first low-concentration doping region (141) may be provided between the first high-concentration doping region (140) and the first well (120). The first low-concentration doping region (141) may be in contact with the upper and side surfaces of the first high-concentration doping region (140). The first low-concentration doping region (141) may be exposed on the front surface (100a). On the front surface (100a), the first low-concentration doping region (141) may surround the first high-concentration doping region (140). The conductivity type of the first low-concentration doping region (141) may be n-type. The first low-concentration doping region (141) may have a lower doping concentration than the first high-concentration doping region (140). For example, the doping concentration of the first low-concentration doping region (141) is 1x10 15 ~ 1x10 19 cm -3It may be possible. By forming a depletion region (106) using a first low-concentration doping region (141), tunneling noise and trap-assisted tunneling noise of the single-photon avalanche diode (1000) can be reduced, and the operating wavelength band of the single-photon avalanche diode (1000) can be widened.

[0052] A first guard ring (142) may be provided on the side of the first low-concentration doping region (141). The first guard ring (142) may surround the first low-concentration doping region (141). For example, the first guard ring (142) may have a ring shape extending along the side of the first low-concentration doping region (141). The first guard ring (142) may be in direct contact with the first low-concentration doping region (141). In another example, the first guard ring (142) may be spaced apart from the first low-concentration doping region (141). The first guard ring (142) may be exposed on the front surface (100a). On the front surface (100a), the first guard ring (142) may surround the first low-concentration doping region (141). The first guard ring (142) may extend along the direction from the front (100a) toward the rear (100b). The distance between the first guard ring (142) and the rear (100b) may be smaller than the distance between the first low-concentration doping region (141) and the rear (100b). The first guard ring (142) may be spaced apart from the buried region (110) by the first well (120). The conductivity type of the first guard ring (142) may be n-type. The doping concentration of the first guard ring (142) may be lower than the doping concentration of the first low-concentration doping region (141). For example, the doping concentration of the first guard ring (142) is 1x10 15 ~ 5x10 17 cm -3The first guard ring (142) can improve the breakdown characteristics of the single-photon avalanche diode (1000). Specifically, the first guard ring (142) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0053] A first contact (121) may be provided on the side of the first guard ring (142). A first contact (121) may be provided on the opposite side of the first low-concentration doping region (141) with the first guard ring (142) in between. A first contact (121) may be exposed on the front surface (100a). On the front surface (100a), a first contact (121) may surround the first guard ring (142). In another example, a plurality of first contacts (121) may be provided. In this case, the plurality of contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1000). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the first well (120). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0054] A first relaxation area (122) may be provided between the first contact (121) and the first well (120). The first relaxation area (122) may be electrically connected to the first contact (121) and the first well (120). The first relaxation area (122) may relax the difference between the first contact (121) and the first well (120). The first relaxation area (122) may extend along the first contact (121). The first relaxation area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relaxation area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top surface and one side of the first relaxation area (122) may be in contact with the first well (120). The other side of the first relief area (122) is exposed by the first well (120) and may come into contact with the buried area (110). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relief area (122) may surround the first guard ring (142). The first relief area (122) may be spaced apart from the first guard ring (142). The first well (120) may extend between the first relief area (122) and the first guard ring (142). For example, the area between the first relief area (122) and the first guard ring (142) may be filled with the first well (120). Between the first relief area (122) and the first guard ring (142), the first well (120) may be exposed on the front surface (100a). In one example, the first well (120) may not be provided in an area adjacent to the front surface (100a). For example, the area adjacent to the front surface (100a) between the first relaxation area (122) and the first guard ring (142) may be filled with a substrate area (102). The substrate area (102) between the first relaxation area (122) and the first guard ring (142) may be exposed on the front surface (100a). The conductivity type of the first relaxation area (122) may be p-type.The doping concentration of the first relaxation region (122) is lower than the doping concentration of the first contact (121) and may be similar to or higher than the doping concentration of the first well (120). For example, the doping concentration of the first relaxation region (122) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0055] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess area formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1000) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1000) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0056] The present disclosure can provide a single-photon avalanche diode (1000) that operates over a wide wavelength band, with improved tunneling noise characteristics and trap-assisted tunneling noise characteristics by utilizing a first low-concentration doping region (141) to form a depletion region (106).

[0059] FIG. 3 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 4 is a cross-sectional view along the line B-B' of the single-photon avalanche diode of FIG. 3.

[0060] Referring to FIGS. 3 and 4, a single-photon avalanche diode (1100) may be provided. The single-photon avalanche diode (1100) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1100) may include a buried region (110), a first well (120), a first high-concentration doping region (140), a first low-concentration doping region (141), a first guard ring (142), a first contact (121), a first relaxation region (122), a second well (123), a second low-concentration doping region (124), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first well (120), a first high-concentration doping region (140), a first low-concentration doping region (141), a first guard ring (142), a first contact (121), a first relaxation region (122), a second well (123), and a second low-concentration doping region (124) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the first well (120), the first high-concentration doping area (140), the first low-concentration doping area (141), the first guard ring (142), the first contact (121), the first relaxation area (122), the second well (123), and the second low-concentration doping area (124), may be referred to as the substrate area (102).

[0061] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It could be.

[0062] A first well (120) may be provided within a semiconductor substrate (100). A buried region (110) may be disposed between the first well (120) and the back surface (100b). The top and side surfaces of the first well (120) may be in direct contact with the buried region (110). The conductivity type of the first well (120) may be p-type. For example, the doping concentration of the first well (120) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the first well (120) may have a uniform doping concentration. In one example, the doping concentration of the first well (120) may become smaller as it approaches the front surface (100a) of the single-photon avalanche diode (1100).

[0063] A first high-concentration doping region (140) may be provided between the first well (120) and the front surface (100a). The first high-concentration doping region (140) may be exposed on the front surface (100a). The conductivity type of the first high-concentration doping region (140) may be n-type. The first high-concentration doping region (140) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. Hereinafter, the region having an n-type conductivity type may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1100) or receive a signal from the single-photon avalanche diode (1100).

[0064] The first low-concentration doping region (141) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When a reverse bias is applied to the single-photon avalanche diode (1100), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. The first low-concentration doping region (141) may be configured to reduce or prevent short-channel effects that occur as the size of the semiconductor device decreases. For example, a short-channel effect may be current flowing even when no photon is incident on the single-photon avalanche diode (1100). The first low-concentration doping region (141) may be provided between the first high-concentration doping region (140) and the first well (120). The first low-concentration doping region (141) may be in contact with the upper and side surfaces of the first high-concentration doping region (140). The first low-concentration doping region (141) may be exposed on the front surface (100a). On the front surface (100a), the first low-concentration doping region (141) may surround the first high-concentration doping region (140). The conductivity type of the first low-concentration doping region (141) may be n-type. The first low-concentration doping region (141) may have a lower doping concentration than the first high-concentration doping region (140). For example, the doping concentration of the first low-concentration doping region (141) is 1x10 15 ~ 1x10 19 cm -3 It could be.

[0065] A first guard ring (142) may be provided on the side of the first low-concentration doping region (141). The first guard ring (142) may surround the first low-concentration doping region (141). For example, the first guard ring (142) may have a ring shape extending along the side of the first low-concentration doping region (141). The first guard ring (142) may be in direct contact with the first low-concentration doping region (141). In another example, the first guard ring (142) may be spaced apart from the first low-concentration doping region (141). The first guard ring (142) may be exposed on the front surface (100a). On the front surface (100a), the first guard ring (142) may surround the first low-concentration doping region (141). The first guard ring (142) may extend along the direction from the front (100a) toward the rear (100b). The distance between the first guard ring (142) and the rear (100b) may be smaller than the distance between the first low-concentration doping region (141) and the rear (100b). The first guard ring (142) may be spaced apart from the buried region (110) by the first well (120). The conductivity type of the first guard ring (142) may be n-type. The doping concentration of the first guard ring (142) may be lower than the doping concentration of the first low-concentration doping region (141). For example, the doping concentration of the first guard ring (142) is 1x10 15 ~ 5x10 17 cm -3 The first guard ring (142) can improve the breakdown characteristics of the single-photon avalanche diode (1100). Specifically, the first guard ring (142) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as a larger electric field is concentrated in a part of the depletion region (106).

[0066] A first contact (121) may be provided on the side of the first guard ring (142). A first contact (121) may be provided on the opposite side of the first low-concentration doping region (141) with the first guard ring (142) in between. A first contact (121) may be exposed on the front surface (100a). On the front surface (100a), a first contact (121) may surround the first guard ring (142). In another example, a plurality of first contacts (121) may be provided. In this case, the plurality of contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1100). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the first well (120). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0067] A first relaxation area (122) may be provided between the first contact (121) and the first well (120). The first relaxation area (122) may be electrically connected to the first contact (121) and the first well (120). The first relaxation area (122) may relax the difference between the first contact (121) and the first well (120). The first relaxation area (122) may extend along the first contact (121). The first relaxation area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relaxation area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top surface and one side of the first relaxation area (122) may be in contact with the first well (120). The other side of the first relief area (122) is exposed by the first well (120) and may come into contact with the buried area (110). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relief area (122) may surround the first guard ring (142). The first relief area (122) may be spaced apart from the first guard ring (142). The first well (120) may extend between the first relief area (122) and the first guard ring (142). For example, the area between the first relief area (122) and the first guard ring (142) may be filled with the first well (120). Between the first relief area (122) and the first guard ring (142), the first well (120) may be exposed on the front surface (100a). In one example, the first well (120) may not be provided in an area adjacent to the front surface (100a). For example, the area adjacent to the front surface (100a) between the first relaxation area (122) and the first guard ring (142) may be filled with a substrate area (102). The substrate area (102) between the first relaxation area (122) and the first guard ring (142) may be exposed on the front surface (100a). The conductivity type of the first relaxation area (122) may be p-type.The doping concentration of the first relaxation region (122) is lower than the doping concentration of the first contact (121) and may be similar to or higher than the doping concentration of the first well (120). For example, the doping concentration of the first relaxation region (122) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0068] Unlike the single-photon avalanche diode (1000) described with reference to FIGS. 1 and 2, the single-photon avalanche diode (1100) may further include a second well (123) and a second low-concentration doping region (124). The second well (123) may be provided between the first low-concentration doping region (141) and the first well (120). The second well (123) may be in contact with the first well (120). The second well (123) may be provided in the inner region of the first guard ring (142) having a ring shape. From the perspective of looking at the front (100a), the second well (123) may be surrounded by the first guard ring (142). The conductivity type of the second well (123) may be p-type. For example, the doping concentration of the second well (123) is 1x10 15 ~ 5x10 17 cm -3 The second well (123) can enhance the avalanche effect by increasing the electric field in the depletion region. The second well (123) can enable electrons or holes in the first well (120) to move more effectively to the first high-concentration doping region (140).

[0069] A second low-concentration doping region (124) may be provided between the second well (123) and the first low-concentration doping region (141). The second low-concentration doping region (124) may be in contact with the second well (123) and the first low-concentration doping region (141). The second low-concentration doping region (124) may be provided in the inner region of the first guard ring (142) having a ring shape. From the perspective of looking at the front (100a), the second low-concentration doping region (124) may be surrounded by the first guard ring (142). The conductivity type of the second low-concentration doping region (124) may be p-type. The second low-concentration doping region (124) may have a doping concentration lower than the doping concentration of the first contact (121). For example, the doping concentration of the second low-concentration doping region (124) is 1x10 15 ~ 1x10 18 cm -3 It could be.

[0070] By forming a PN junction using the first low-concentration doping region (141) and the second low-concentration doping region (142), tunneling noise and trap-assisted tunneling noise of the single-photon avalanche diode (1100) can be reduced, and a single-photon avalanche diode (1100) operating over a wide wavelength band can be provided.

[0071] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1100) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1100) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0072] The present disclosure can provide a single-photon avalanche diode (1000) that operates over a wide wavelength band and has improved tunneling noise characteristics and trap-assisted tunneling noise characteristics by utilizing a first low-concentration doping region (141) and a second low-concentration doping region (124) to form a PN junction.

[0074] FIG. 5 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 6 is a cross-sectional view along the line C-C' of the single-photon avalanche diode of FIG. 5.

[0075] Referring to FIGS. 5 and 6, a single-photon avalanche diode (1200) may be provided. The single-photon avalanche diode (1200) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1200) may include a buried region (110), a first well (120), a first high-concentration doping region (140), a first guard ring (142), a first contact (121), a first relaxation region (122), an additional relaxation region (125), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first well (120), a first high-concentration doping region (140), a first guard ring (142), a first contact (121), a first relaxation region (122), and an additional relaxation region (125) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the first well (120), the first high-concentration doping area (140), the first guard ring (142), the first contact (121), the first relaxation area (122), and the additional relaxation area (125), may be referred to as the substrate area (102).

[0076] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0077] A first well (120) may be provided within a semiconductor substrate (100). A buried region (110) may be disposed between the first well (120) and the back surface (100b). The top and side surfaces of the first well (120) may be in direct contact with the buried region (110). The conductivity type of the first well (120) may be p-type. For example, the doping concentration of the first well (120) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the first well (120) may have a uniform doping concentration. In one example, the doping concentration of the first well (120) may become smaller as it approaches the front surface (100a).

[0078] The first high-concentration doping region (140) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When a reverse bias is applied to the single-photon avalanche diode (1200), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A first high-concentration doping region (140) may be exposed on the front surface (100a). The first high-concentration doping region (140) may be provided between the first well (120) and the front surface (100a). The first high-concentration doping region (140) and the first well (120) may be arranged along the direction from the front surface (100a) toward the rear surface (100b). The width of the first high-concentration doping region (140) may be greater than the width of the first well (120). The widths may be of a size along a direction parallel to the front surface (100a). As the first well (120) is configured to have a width smaller than that of the first high-concentration doping region (140), the electric field can be formed to have a large strength in the region adjacent to the interface between the first well (120) and the first high-concentration doping region (140) (i.e., the region adjacent to the PN junction), and the occurrence of premature breakdown due to unintended electric field concentration can be prevented, thereby improving the operational stability of the single-photon avalanche diode (1200). For example, the single-photon avalanche diode (1200) can operate stably even without including the guard ring (142) described in other embodiments.

[0079] The first high-concentration doping region (140) may protrude from the side of the first well (120). The conductivity type of the first high-concentration doping region (140) may be n-type. The first high-concentration doping region (140) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1200) or receive a signal from the single-photon avalanche diode (1200).

[0080] A first guard ring (142) may be provided on the side of the first well (120) and the first high-concentration doping area (140). The first guard ring (142) may surround the first well (120) and the first high-concentration doping area (140). For example, the first guard ring (142) may have a ring shape extending along the side of the first well (120) and the first high-concentration doping area (140). The first guard ring (142) may be in direct contact with the first well (120) and the first high-concentration doping area (140). In another example, the first guard ring (142) may be spaced apart from the first well (120) and the first high-concentration doping area (140). The first guard ring (142) may be exposed on the front surface (100a). On the front surface (100a), the first guard ring (142) may surround the first low-concentration doping region (141). The first guard ring (142) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the first guard ring (142) and the rear surface (100b) may be smaller than the distance between the first high-concentration doping region (140) and the rear surface (100b). The distance between the first guard ring (142) and the rear surface (100b) may be larger than the distance between the first well (120) and the rear surface (100b). The first guard ring (142) may be in contact with the buried region (110). The conductivity type of the first guard ring (142) may be n-type. The doping concentration of the first guard ring (142) may be lower than the doping concentration of the first high-concentration doping region (140). For example, the doping concentration of the first guard ring (142) is 1x10 15 ~ 5x10 17 cm -3The first guard ring (142) can improve the breakdown characteristics of the single-photon avalanche diode (1200). Specifically, the first guard ring (142) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0081] A polysilicon pattern (105) may be provided on the front surface (100a). The polysilicon pattern (105) may overlap with the first guard ring (142) along the direction from the front surface (100a) toward the rear surface (100b). The polysilicon pattern (105) may be in direct contact with the first guard ring (142). As the polysilicon pattern (105) is formed on the first guard ring (142), the characteristics for preventing premature breakdown of the first guard ring (142) may be improved. In one embodiment, a voltage may be applied to the polysilicon pattern (105) as needed to improve the characteristics for preventing premature breakdown of the first guard ring (142). For example, a required constant voltage, AC voltage, or pulsed DC voltage may be applied to the polysilicon pattern (105). In one embodiment, the polysilicon pattern (105) may be electrically connected to the anode or cathode of the single-photon avalanche diode (1200) to apply voltage. For example, the polysilicon pattern (105) may be electrically connected to the high-concentration doping region (140) or the first contact (121). The configuration in which the polysilicon pattern (105) is provided on the first guard ring (142) may be provided not only in this embodiment but also on other guard rings described herein or near the corners of depletion regions.

[0082] A first contact (121) may be provided on the side of the first guard ring (142). The first contact (121) may be provided on the opposite side of the first high-concentration doping region (140) with the first guard ring (142) in between. The first contact (121) may be exposed on the front surface (100a). On the front surface (100a), the first contact (121) may surround the first guard ring (142). In another example, the first contact (121) may be provided in multiple numbers. In this case, the multiple contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1200). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the first well (120). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0083] A first relief area (122) may be provided between the first contact (121) and the buried area (110). The first relief area (122) may be electrically connected to the first contact (121) and the buried area (110). The first relief area (122) may relieve the difference between the first contact (121) and the buried area (110). The first relief area (122) may extend along the first contact (121). The first relief area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relief area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top and side surfaces of the first relief area (122) may be in contact with the buried area (110). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relief area (122) may surround the first guard ring (142). The first relief area (122) may be spaced apart from the first guard ring (142). A buried area (110) may extend between the first relief area (122) and the first guard ring (142). For example, the area between the first relief area (122) and the first guard ring (142) may be filled with the buried area (110). Between the first relief area (122) and the first guard ring (142), the buried area (110) may be exposed on the front surface (100a). In one example, the first well (120) may not be provided in an area adjacent to the front surface (100a). For example, the area adjacent to the front surface (100a) between the first relaxation area (122) and the first guard ring (142) may be filled with a substrate area (102). The substrate area (102) between the first relaxation area (122) and the first guard ring (142) may be exposed on the front surface (100a). The conductivity type of the first relaxation area (122) may be p-type. The doping concentration of the first relaxation area (122) may be lower than the doping concentration of the first contact (121) and similar to or higher than the doping concentration of the first well (120).For example, the doping concentration of the first relaxation region (122) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0084] An additional relaxation area (125) may be provided on the upper surface of the relaxation area (122). The additional relaxation area (125) may be in direct contact with the relaxation area (122). The side of the additional relaxation area (125) may be aligned with the side of the relaxation area (122). The additional relaxation area (125) may extend along the direction from the front (100a) toward the rear (100b). The distance between the additional relaxation area (125) and the rear (100b) may be smaller than the distance between the first guard ring (142) and the rear (100b). The conductivity type of the additional relaxation area (125) may be p-type. For example, the doping concentration of the additional relaxation area (125) is 1x10 15 ~ 1x10 18 cm -3 The additional relaxation area (125) and the first relaxation area (122) may improve the electrical connection characteristics between the first contact (121) and the buried area (110). For example, the additional relaxation area (125) and the first relaxation area (122) may be configured to reduce or prevent voltage drop when voltage is applied to the buried area (110) through the first contact (121), and to ensure that voltage is applied uniformly to the buried area (110).

[0085] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1200) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1200) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0086] In one embodiment, a first low-concentration doping region (141 in FIGS. 1 and 2), described with reference to FIGS. 1 and 2, may be further provided between the first high-concentration doping region (140) and the first well (120). Accordingly, the single-photon avalanche diode (1200) has improved tunneling noise characteristics and trap-assisted tunneling noise characteristics and can operate over a wide wavelength band.

[0087] The present disclosure can provide a single-photon avalanche diode (1200) with improved operational stability.

[0089] FIG. 7 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 8 is a cross-sectional view along the line D-D' of the single-photon avalanche diode of FIG. 7.

[0090] Referring to FIGS. 7 and 8, a single-photon avalanche diode (1300) may be provided. The single-photon avalanche diode (1300) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1300) may include a buried region (110), a first well (120), a first high-concentration doping region (140), a first guard ring (142), a first contact (121), a first relaxation region (122), an additional relaxation region (125), a third well (126), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In other examples, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first well (120), a first high-concentration doping region (140), a first guard ring (142), a first contact (121), a first relaxation region (122), an additional relaxation region (125), and a third well (126) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the first well (120), the first high-concentration doping area (140), the first guard ring (142), the first contact (121), the first relaxation area (122), the additional relaxation area (125), and the third well (126), may be referred to as the substrate area (102).

[0091] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0092] A first well (120) may be provided within a semiconductor substrate (100). A buried region (110) may be disposed between the first well (120) and the back surface (100b). The top and side surfaces of the first well (120) may be in direct contact with the buried region (110). The conductivity type of the first well (120) may be p-type. For example, the doping concentration of the first well (120) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the first well (120) may have a uniform doping concentration. In one example, the doping concentration of the first well (120) may become smaller as it approaches the front surface (100a).

[0093] The first high-concentration doping region (140) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When a reverse bias is applied to the single-photon avalanche diode (1300), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. The first high-concentration doping region (140) may be exposed on the front surface (100a). The first high-concentration doping region (140) may be provided between the first well (120) and the front surface (100a). The first high-concentration doping region (140) and the first well (120) may be arranged along the direction from the front surface (100a) toward the rear surface (100b). The width of the first high-concentration doping region (140) may be greater than the width of the first well (120). The widths may be of a size along a direction parallel to the front surface (100a). The first high-concentration doping region (140) may protrude from the side of the first well (120). The first high-concentration doping region (140) of the first well (120) may have an n-type conductivity. The first high-concentration doping region (140) may contain Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements as impurities. In the following description, the region having an n-type conductivity may contain Group 5, Group 6, or Group 7 elements as impurities. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1300) or receive a signal from the single-photon avalanche diode (1300).

[0094] A first guard ring (142) may be provided on the side of the first well (120) and the first high-concentration doping area (140). The first guard ring (142) may surround the first well (120) and the first high-concentration doping area (140). For example, the first guard ring (142) may have a ring shape extending along the side of the first well (120) and the first high-concentration doping area (140). The first guard ring (142) may be in direct contact with the first well (120) and the first high-concentration doping area (140). In another example, the first guard ring (142) may be spaced apart from the first well (120) and the first high-concentration doping area (140). The first guard ring (142) may be exposed on the front surface (100a). On the front surface (100a), the first guard ring (142) may surround the first low-concentration doping region (141). The first guard ring (142) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the first guard ring (142) and the rear surface (100b) may be smaller than the distance between the third well (126) and the rear surface (100b). The first guard ring (142) may be in contact with the buried region (110). The conductivity type of the first guard ring (142) may be n-type. The doping concentration of the first guard ring (142) may be lower than the doping concentration of the first high-concentration doping region (140). For example, the doping concentration of the first guard ring (142) is 1x10 15 ~ 5x10 17 cm -3 The first guard ring (142) can improve the breakdown characteristics of the single-photon avalanche diode (1300). Specifically, the first guard ring (142) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0095] The first contact (121) may be provided on the side of the first guard ring (142). The first contact (121) may be provided on the opposite side of the first high-concentration doping region (140) with the first guard ring (142) in between. The first contact (121) may be exposed on the front surface (100a). On the front surface (100a), the first contact (121) may surround the first guard ring (142). In another example, the first contact (121) may be provided in multiple numbers. In this case, the multiple contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1300). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the first well (120). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0096] A first relief area (122) may be provided between the first contact (121) and the buried area (110). The first relief area (122) may be electrically connected to the first contact (121) and the buried area (110). The first relief area (122) may relieve the difference between the first contact (121) and the buried area (110). The first relief area (122) may extend along the first contact (121). The first relief area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relief area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top and side surfaces of the first relief area (122) may be in contact with the buried area (110). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relief area (122) may surround the first guard ring (142). The first relief area (122) may be spaced apart from the first guard ring (142). A buried area (110) may extend between the first relief area (122) and the first guard ring (142). For example, the area between the first relief area (122) and the first guard ring (142) may be filled with the buried area (110). Between the first relief area (122) and the first guard ring (142), the buried area (110) may be exposed on the front surface (100a). In one example, the first well (120) may not be provided in an area adjacent to the front surface (100a). For example, the area adjacent to the front surface (100a) between the first relaxation area (122) and the first guard ring (142) may be filled with a substrate area (102). The substrate area (102) between the first relaxation area (122) and the first guard ring (142) may be exposed on the front surface (100a). The conductivity type of the first relaxation area (122) may be p-type. The doping concentration of the first relaxation area (122) may be lower than the doping concentration of the first contact (121) and similar to or higher than the doping concentration of the first well (120).For example, the doping concentration of the first relaxation region (122) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0097] An additional relaxation area (125) may be provided on the upper surface of the relaxation area (122). The additional relaxation area (125) may be in direct contact with the relaxation area (122). The side of the additional relaxation area (125) may be aligned with the side of the relaxation area (122). The additional relaxation area (125) may extend along the direction from the front (100a) toward the rear (100b). The distance between the additional relaxation area (125) and the rear (100b) may be smaller than the distance between the first guard ring (142) and the rear (100b). The conductivity type of the additional relaxation area (125) may be p-type. For example, the doping concentration of the additional relaxation area (125) is 1x10 15 ~ 1x10 18 cm -3 The additional relaxation area (125) and the first relaxation area (122) may improve the electrical connection characteristics between the first contact (121) and the buried area (110). For example, the additional relaxation area (125) and the first relaxation area (122) may be configured to reduce or prevent voltage drop when voltage is applied to the buried area (110) through the first contact (121), and to ensure that voltage is applied uniformly to the buried area (110).

[0098] A third well (126) may be provided between the first high-concentration doping region (140) and the first well (120). The third well (126) may be in direct contact with the first high-concentration doping region (140) and the first well (120). The third well (126) may be placed on the upper surface of the first high-concentration doping region (140). The conductivity type of the third well (126) may be p-type. For example, the doping concentration of the third well (126) is 1x10 15 ~ 5x10 17 cm -3The third well (126) may have a width smaller than the first high-concentration doping region (140). The width may be a size that follows a direction parallel to the front surface (100a). As the third well (126) has a width smaller than the first high-concentration doping region (140), an electric field with a large strength may be formed in the region adjacent to the interface between the third well (126) and the first high-concentration doping region (140) (i.e., the region adjacent to the PN junction). Accordingly, the occurrence of premature breakdown due to unintended electric field concentration may be prevented, and the operational stability of the single-photon avalanche diode (1300) may be improved.

[0099] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1300) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1300) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0100] In one embodiment, a first low-concentration doping region (141 in FIGS. 1 and 2), described with reference to FIGS. 1 and 2, may be further provided between the first high-concentration doping region (140) and the third well (126). Accordingly, the single-photon avalanche diode (1300) has improved tunneling noise characteristics and trap-assisted tunneling noise characteristics and can operate over a wide wavelength band.

[0101] The present disclosure may provide a single-photon avalanche diode (1300) configured such that the third well (126) has a width smaller than that of the first high-concentration doping region (140), thereby forming an electric field of high strength in a region adjacent to the interface between the third well (126) and the first high-concentration doping region (140) (i.e., a region adjacent to the PN junction). Accordingly, the occurrence of premature breakdown due to unintended electric field concentration is prevented, and the single-photon avalanche diode (1300) with improved operational stability may be provided.

[0103] FIG. 9 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 10 is a cross-sectional view along the line E-E' of the single-photon avalanche diode of FIG. 9.

[0104] Referring to FIGS. 9 and 10, a single-photon avalanche diode (1400) may be provided. The single-photon avalanche diode (1400) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1400) may include a buried region (110) formed on a semiconductor substrate (100), a first high-concentration doping region (140), a second low-concentration doping region (124), a first contact (121), a first relaxation region (122), an additional relaxation region (125), and a device isolation pattern (104). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In other examples, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first high-concentration doping region (140), a second low-concentration doping region (124), a first contact (121), a first relaxation region (122), and an additional relaxation region (125) may be formed by injecting impurities into the semiconductor substrate (100). The remaining region of the semiconductor substrate (100), excluding the buried region (110), the first high-concentration doping region (140), the second low-concentration doping region (124), the first contact (121), the first relaxation region (122), and the additional relaxation region (125), may be referred to as the substrate region (102).

[0105] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be possible. The doping concentration of the landfill area (110) may decrease as it gets closer to the front (100a).

[0106] The first high-concentration doping region (140) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When a reverse bias is applied to the single-photon avalanche diode (1400), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. The first high-concentration doping region (140) may be exposed on the front surface (100a). The conductivity type of the first high-concentration doping region (140) may be n-type. The first high-concentration doping region (140) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. Hereinafter, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1400) or receive a signal from the single-photon avalanche diode (1400).

[0107] The second low-concentration doping region (124) may be configured to form a depletion region (106). The second low-concentration doping region (124) may be provided between the first high-concentration doping region (140) and the burial region (110). The second low-concentration doping region (124) may be in contact with the first high-concentration doping region (140) and the burial region (110). The second low-concentration doping region (124) may be placed on the upper surface of the first high-concentration doping region (140). The second low-concentration doping region (124) may have a width smaller than that of the first high-concentration doping region (140). The width may be a size following a direction parallel to the front surface (100a). As the second low-concentration doping region (124) has a smaller width than the first high-concentration doping region (140), an electric field with a large intensity can be formed in the region adjacent to the interface between the second low-concentration doping region (124) and the first high-concentration doping region (140) (i.e., the region adjacent to the PN junction). Accordingly, the occurrence of premature breakdown due to unintended electric field concentration can be prevented, and the operational stability of the single-photon avalanche diode (1400) can be improved. The conductivity type of the second low-concentration doping region (124) may be p-type. For example, the doping concentration of the second low-concentration doping region (124) is 1x10 15 ~ 1x10 18 cm -3 It could be.

[0108] A first contact (121) may be provided on the side of the first high-concentration doping region (140) and the second low-concentration doping region (124). The first contact (121) may be exposed on the front surface (100a). On the front surface (100a), the first contact (121) may surround the first high-concentration doping region (140) and the second low-concentration doping region (124). In another example, the first contact (121) may be provided in multiple numbers. In this case, the multiple contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1400). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the buried region (110). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0109] A first relief area (122) may be provided between the first contact (121) and the buried area (110). The first relief area (122) may be electrically connected to the first contact (121) and the buried area (110). The first relief area (122) may relieve the difference between the first contact (121) and the buried area (110). The first relief area (122) may extend along the first contact (121). The first relief area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relief area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top and side surfaces of the first relief area (122) may be in contact with the buried area (110). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relaxation area (122) may surround the first high-concentration doping area (140) and the second low-concentration doping area (124). The first relaxation area (122) may be spaced apart from the first high-concentration doping area (140) and the second low-concentration doping area (124). A filling area (110) may extend between the first relaxation area (122) and the first high-concentration doping area (140). For example, the area between the first relaxation area (122) and the first high-concentration doping area (140) and the area between the first relaxation area (122) and the second low-concentration doping area (124) may be filled with the filling area (110). Between the first relaxation area (122) and the first high-concentration doping area (140), the buried area (110) may be exposed on the front surface (100a). In one example, the buried area (110) may not be provided in an area adjacent to the front surface (100a). For example, the area adjacent to the front surface (100a) between the first relaxation area (122) and the first high-concentration doping area (140) and between the first relaxation area (122) and the second low-concentration doping area (124) may be filled with a substrate area (102).Between the first relaxation region (122) and the first high-concentration doping region (140), the substrate region (102) may be exposed on the front surface (100a). The conductivity type of the first relaxation region (122) may be p-type. The doping concentration of the first relaxation region (122) may be lower than the doping concentration of the first contact (121). For example, the doping concentration of the first relaxation region (122) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0110] An additional relaxation area (125) may be provided on the upper surface of the relaxation area (122). The additional relaxation area (125) may be in direct contact with the relaxation area (122). The side of the additional relaxation area (125) may be aligned with the side of the relaxation area (122). The additional relaxation area (125) may extend along the direction from the front (100a) toward the rear (100b). The distance between the additional relaxation area (125) and the rear (100b) may be smaller than the distance between the second low-concentration doping area (124) and the rear (100b). The conductivity type of the additional relaxation area (125) may be p-type. For example, the doping concentration of the additional relaxation area (125) is 1x10 15 ~ 1x10 18 cm -3 The additional relaxation area (125) and the first relaxation area (122) may improve the electrical connection characteristics between the first contact (121) and the buried area (110). For example, the additional relaxation area (125) and the first relaxation area (122) may be configured to reduce or prevent voltage drop when voltage is applied to the buried area (110) through the first contact (121), and to ensure that voltage is applied uniformly to the buried area (110).

[0111] As the doping concentration of the buried region (110) decreases as it approaches the front surface (100a), a virtual guard ring (210) may be formed on the side of the first high-concentration doping region (140) and the second low-concentration doping region (124). The virtual guard ring (210) may be a part of the buried region (110) or the substrate region (102) that can act as a guard ring for the first high-concentration doping region (140) and the second low-concentration doping region (124) because the doping concentration of impurities is low. Specifically, the virtual guard ring (210) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). The premature breakdown phenomenon occurs when a breakdown phenomenon occurs first in a part of the depletion region (106) before an electric field of sufficient magnitude is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106). The breakdown characteristics of the single-photon avalanche diode (1400) can be improved by the virtual guard ring (210). The virtual guard ring (210) can surround the first high-concentration doping region (140), the second low-concentration doping region (124), and the depletion region (106). For example, the virtual guard ring (210) can have a ring shape extending along the sides of the first high-concentration doping region (140), the second low-concentration doping region (124), and the depletion region (106).

[0112] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1400) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1400) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0113] The present disclosure can provide a single-photon avalanche diode (1400) that operates over a wide wavelength band and has improved tunneling noise characteristics and trap-assisted tunneling noise characteristics by utilizing a first high-concentration doping region (140) and a second low-concentration doping region (124) to form a PN junction.

[0114] The present disclosure may provide a single-photon avalanche diode (1400) configured such that a second low-concentration doping region (124) has a width smaller than that of a first high-concentration doping region (140), thereby forming an electric field of high strength in a region adjacent to the interface between the second low-concentration doping region (124) and the first high-concentration doping region (140) (i.e., a region adjacent to the PN junction). Accordingly, a single-photon avalanche diode (1400) may be provided in which the occurrence of premature breakdown due to unintended electric field concentration is prevented and operational stability is improved.

[0116] FIG. 11 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 12 is a cross-sectional view along the line F-F' of the single-photon avalanche diode of FIG. 11.

[0117] Referring to FIGS. 11 and 12, a single-photon avalanche diode (1500) may be provided. The single-photon avalanche diode (1500) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1500) may include a buried region (110), a first well (120), a first high-concentration doping region (140), a fourth well (143), a fifth well (144), a first contact (121), a first relaxation region (122), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first well (120), a first high-concentration doping region (140), a fourth well (143), a fifth well (144), a first contact (121), and a first relaxation region (122) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the first well (120), the first high-concentration doping area (140), the fourth well (143), the fifth well (144), the first contact (121), and the first relaxation area (122), may be referred to as the substrate area (102).

[0118] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0119] A first high-concentration doping region (140) may be provided between the first well (120) and the front surface (100a). The first high-concentration doping region (140) may be exposed on the front surface (100a). The conductivity type of the first high-concentration doping region (140) may be n-type. The first high-concentration doping region (140) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. Hereinafter, the region having an n-type conductivity type may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1500) or receive a signal from the single-photon avalanche diode (1500).

[0120] A fourth well (143) may be provided between the first high-concentration doping region (140) and the landfill region (110). The fourth well (143) may be in contact with the top and side surfaces of the first high-concentration doping region (140). The fourth well (143) may be exposed on the front surface (100a). On the front surface (100a), the fourth well (143) may surround the first high-concentration doping region (140). The conductivity type of the fourth well (143) may be n-type. For example, the doping concentration of the fourth well (143) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0121] The fifth well (144) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1500), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A fifth well (144) may be provided between the fourth well (143) and the buried region (110). The fifth well (144) may be in contact with the top and side surfaces of the fourth well (143). The fifth well (144) may be in contact with the buried region (110). The fifth well (144) may be exposed on the front surface (100a). On the front surface (100a), the fifth well (144) may surround the fourth well (143). The conductivity type of the fifth well (144) may be n-type. For example, the doping concentration of the fifth well (144) is 1x10 15 ~ 1x10 18 cm -3 It could be.

[0122] The depletion region (106) may be formed at a depth required by the fourth well (143) and the fifth well (144). The depth may refer to a distance from the front (100a) along the direction from the front (100a) toward the rear (100b). Depending on the depth of the depletion region (106), the detection efficiency of the single-photon avalanche diode (1500) according to the wavelength band may vary. For example, the wavelength band in which the single-photon avalanche diode (1500) has high detection efficiency may be controlled by the depth of the depletion region (106). Accordingly, the present disclosure may provide a single-photon avalanche diode (1500) having high detection efficiency for a required wavelength band.

[0123] The first well (120) may be provided on the side of the fifth well (144). The first well (120) may surround the side of the fifth well (144). For example, the first well (120) may extend along the side of the fifth well (144). The fifth well (144) may protrude from the upper surface of the first well (120). The conductivity type of the first well (120) may be p-type. For example, the doping concentration of the first well (120) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the first well (120) may have a uniform doping concentration. In one example, the doping concentration of the first well (120) may become smaller as it approaches the front surface (100a).

[0124] The first contact (121) may be provided on the side of the fifth well (144). The first contact (121) may be provided on the opposite side of the fourth well (143) with the fifth well (144) in between. The first contact (121) may be exposed on the front surface (100a). On the front surface (100a), the first contact (121) may surround the fifth well (144). In another example, the first contact (121) may be provided in multiple numbers. In this case, the multiple contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1500). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the first well (120). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0125] A first relaxation area (122) may be provided between the first contact (121) and the first well (120). The first relaxation area (122) may be electrically connected to the first contact (121) and the first well (120). The first relaxation area (122) may relax the difference between the first contact (121) and the first well (120). The first relaxation area (122) may extend along the first contact (121). The first relaxation area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relaxation area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top surface and one side of the first relaxation area (122) may be in contact with the first well (120). The other side of the first relief area (122) is exposed by the first well (120) and may come into contact with the landfill area (110). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relief area (122) may surround the fifth well (144). The first relief area (122) may be spaced apart from the fifth well (144). The first well (120) may extend between the first relief area (122) and the fifth well (144). For example, the area between the first relief area (122) and the fifth well (144) may be filled with the first well (120). Between the first relief area (122) and the fifth well (144), the first well (120) may be exposed on the front surface (100a). In one example, the first well (120) may not be provided in an area adjacent to the front (100a). For example, the portion of the area adjacent to the front (100a) between the first relief area (122) and the fifth well (144) that is close to the front (100a) may be filled with a reclaimed area (110). The reclaimed area (110) between the first relief area (122) and the fifth well (144) may be exposed on the front (100a).For example, the portion of the area adjacent to the front surface (100a) between the first relaxation region (122) and the fifth well (144) that is close to the front surface (100a) may be filled with a substrate region (102). The substrate region (102) between the first relaxation region (122) and the fifth well (144) may be exposed on the front surface (100a). The conductivity type of the first relaxation region (122) may be p-type. The doping concentration of the first relaxation region (122) may be lower than the doping concentration of the first contact (121) and may be similar to or higher than the doping concentration of the first well (120). For example, the doping concentration of the first relaxation region (122) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0126] As the doping concentration of the buried region (110) and the first well (120) decreases as it approaches the front surface (100a), a virtual guard ring (210) may be formed on the side of the fifth well (144). Specifically, the virtual guard ring (210) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown phenomenon that occurs in a part before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part. The breakdown characteristics of the single-photon avalanche diode (1500) can be improved by the virtual guard ring (210). The virtual guard ring (210) may surround the fifth well (144). For example, the virtual guard ring (210) may have a ring shape extending along the side of the fifth well (144).

[0127] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1500) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1500) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0128] The present disclosure can provide a single-photon avalanche diode (1500) having high detection efficiency for a required wavelength band.

[0130] FIG. 13 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 14 is a cross-sectional view along the line G-G' of the single-photon avalanche diode of FIG. 13.

[0131] Referring to FIGS. 13 and 14, a single-photon avalanche diode (1600) may be provided. The single-photon avalanche diode (1600) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1600) may include a buried region (110), a first well (120), a first high-concentration doping region (140), a fourth well (143), a first contact (121), a first relaxation region (122), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In other examples, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a first well (120), a first high-concentration doping region (140), a fourth well (143), a first contact (121), and a first relaxation region (122) may be formed by injecting impurities into the semiconductor substrate (100). The remaining region of the semiconductor substrate (100), excluding the buried region (110), the first well (120), the first high-concentration doping region (140), the fourth well (143), the first contact (121), and the first relaxation region (122), may be referred to as the substrate region (102).

[0132] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0133] A first high-concentration doping region (140) may be provided between the first well (120) and the front surface (100a). The first high-concentration doping region (140) may be exposed on the front surface (100a). The conductivity type of the first high-concentration doping region (140) may be n-type. The first high-concentration doping region (140) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. Hereinafter, the region having an n-type conductivity type may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the first high-concentration doping region (140) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first high-concentration doping region (140) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1600) or receive a signal from the single-photon avalanche diode (1600).

[0134] The fourth well (143) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1600), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A fourth well (143) may be provided between the first high-concentration doping region (140) and the buried region (110). The fourth well (143) may be in contact with the top and side surfaces of the first high-concentration doping region (140). The fourth well (143) may be exposed on the front surface (100a). On the front surface (100a), the fourth well (143) may surround the first high-concentration doping region (140). The conductivity type of the fourth well (143) may be n-type. For example, the doping concentration of the fourth well (143) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0135] The first well (120) may be provided on the upper surface of the fourth well (143). The first well (120) may be provided between the fourth well (143) and the landfill area (110). The first well (120) may be in contact with the fourth well (143) and the landfill area (110). The first well (120) may have a width smaller than that of the fourth well (143). The conductivity type of the first well (120) may be p-type. For example, the doping concentration of the first well (120) is 1x10 15 ~ 1x10 18 cm -3 It may be possible. As the first well (120) is configured to have a smaller width than the fourth well (143), the electric field can be formed to have a large strength in the region adjacent to the interface between the first well (120) and the fourth well (143) (i.e., the region adjacent to the PN junction), and the operation stability of the single-photon avalanche diode (1600) can be improved by preventing the occurrence of premature breakdown due to unintended electric field concentration. For example, the single-photon avalanche diode (1600) can operate stably even without including the guard ring (142) described in other embodiments.

[0136] A first contact (121) may be provided on the side of the fourth well (143). A first contact (121) may be provided on the opposite side of the first high-concentration doping region (140) with the fourth well (143) in between. A first contact (121) may be exposed on the front surface (100a). On the front surface (100a), a first contact (121) may surround the fourth well (143). In another example, a plurality of first contacts (121) may be provided. In this case, the plurality of contacts may each be electrically connected to a circuit outside the single-photon avalanche diode (1600). The conductivity type of the first contact (121) may be p-type. The doping concentration of the first contact (121) may be higher than the doping concentration of the first well (120). For example, the doping concentration of the first contact (121) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the first contact (121) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the first contact (121) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0137] A first relief area (122) may be provided between the first contact (121) and the fourth well (143). The first relief area (122) may be electrically connected to the first contact (121) and the fourth well (143). The first relief area (122) may relieve the difference between the first contact (121) and the fourth well (143). The first relief area (122) may extend along the first contact (121). The first relief area (122) may be provided on the side and top surfaces of the first contact (121). For example, the first relief area (122) may be in direct contact with the side and top surfaces of the first contact (121). The top and side surfaces of the first relief area (122) may be in contact with the first well (120). The first relief area (122) may be exposed on the front surface (100a). On the front surface (100a), the first relaxation area (122) may surround the fourth well (143). The first relaxation area (122) may be spaced apart from the fourth well (143). A filling area (110) may extend between the first relaxation area (122) and the fourth well (143). For example, the area between the first relaxation area (122) and the fourth well (143) may be filled with the filling area (110). Between the first relaxation area (122) and the fourth well (143), the filling area (110) may be exposed on the front surface (100a). In one example, the filling area (110) may not be provided in an area adjacent to the front surface (100a). For example, in the area between the first relaxation region (122) and the fourth well (143), the area adjacent to the front surface (100a) may be filled with a substrate region (102). Between the first relaxation region (122) and the fourth well (143), the substrate region (102) may be exposed on the front surface (100a). The conductivity type of the first relaxation region (122) may be p-type. The doping concentration of the first relaxation region (122) may be lower than the doping concentration of the first contact (121) and may be similar to or higher than the doping concentration of the first well (120). For example, the doping concentration of the first relaxation region (122) is 1x10 15~ 5x10 17 cm -3 It could be.

[0138] A device isolation pattern (104) may be provided on the side of the first relaxation region (122). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the first relaxation region (122). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching a semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1600) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the first relaxation region (122) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1600) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0139] The present disclosure can provide a single-photon avalanche diode (1600) with improved operational stability.

[0141] FIG. 15 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 16 is a cross-sectional view along the line H-H' of the single-photon avalanche diode of FIG. 15.

[0142] Referring to FIGS. 15 and 16, a single-photon avalanche diode (1700) may be provided. The single-photon avalanche diode (1700) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1700) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), a third low-concentration doping region (154), an eighth well (155), a second guard ring (131), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a sixth well (153), a second high-concentration doping region (130), a third low-concentration doping region (154), an eighth well (155), a second guard ring (131), a second contact (151), and a second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the filled area (110), the sixth well (153), the second high-concentration doping area (130), the third low-concentration doping area (154), the eighth well (155), the second guard ring (131), the second contact (151), and the second relaxation area (152), may be referred to as the substrate area (102).

[0143] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0144] The sixth well (153) may be provided within the semiconductor substrate (100). A buried region (110) may be disposed between the sixth well (153) and the back surface (100b). The top surface and side surface of the sixth well (153) may be in direct contact with the buried region (110). The conductivity type of the sixth well (153) may be n-type. The sixth well (153) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may become smaller as it approaches the front (100a).

[0145] The second high-concentration doping region (130) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When a reverse bias is applied to the single-photon avalanche diode (1700), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A second high-concentration doping region (130) may be provided between the sixth well (153) and the front surface (100a). The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1700) or receive a signal from the single-photon avalanche diode (1700).

[0146] A third low-concentration doping region (154) may be provided between the second high-concentration doping region (130) and the sixth well (153). The third low-concentration doping region (154) may be provided on the upper surface of the second high-concentration doping region (130). The third low-concentration doping region (154) may be configured to reduce or prevent short-channel effects that occur as the size of the semiconductor device decreases. For example, a short-channel effect may be current flowing even when no photon is incident on the single-photon avalanche diode (1700). The conductivity type of the third low-concentration doping region (154) may be n-type. For example, the doping concentration of the third low-concentration doping region (154) is 1x10 15 ~ 1x10 19 cm -3It may be possible. In one embodiment, the third low-concentration doping region (154) may be configured to expand the size of the depletion region (106). For example, the third low-concentration doping region (154) may be formed to overlap with a portion of the second high-concentration doping region (150), so that the doping concentration of the second high-concentration doping region (150) overlapping with the third low-concentration doping region (154) may be lowered. As the doping concentration of the second high-concentration doping region (150) decreases, the size of the depletion region (106) may be expanded. Accordingly, the tunneling noise and trap-assisted tunneling noise of the single-photon avalanche diode (1700) may be reduced, and the operating wavelength band of the single-photon avalanche diode (1700) may be widened. In one embodiment, the third low-concentration doping region (154) can lower the breakdown voltage of the single-photon avalanche diode (1700). For example, if the third low-concentration doping region (154) is formed so as not to overlap with the second high-concentration doping region (150) and has a higher doping concentration than the eighth well (155) described later, the breakdown voltage of the single-photon avalanche diode (1700) can be lowered.

[0147] The eighth well (155) may be provided between the third low-concentration doping region (154) and the sixth well (153). The eighth well (155) may be provided on the upper surface of the eighth well (155). The conductivity type of the eighth well (155) may be n-type. For example, the doping concentration of the eighth well (155) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0148] A second guard ring (131) may be provided on the side of the second high-concentration doping region (130), the third low-concentration doping region (154), and the eighth well (155). The second guard ring (131) may surround the second high-concentration doping region (130), the third low-concentration doping region (154), and the eighth well (155). For example, the second guard ring (131) may have a ring shape extending along the side of the second high-concentration doping region (130), the third low-concentration doping region (154), and the eighth well (155). The second guard ring (131) may be in direct contact with the second high-concentration doping region (130), the third low-concentration doping region (154), and the eighth well (155). In another example, the second guard ring (131) may be spaced apart from the second high-concentration doping region (130), the third low-concentration doping region (154), and the eighth well (155). The second guard ring (131) may be exposed on the front surface (100a). On the front surface (100a), the second guard ring (131) may surround the second high-concentration doping region (130). The second guard ring (131) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second guard ring (131) and the rear surface (100b) may be greater than the distance between the eighth well (155) and the rear surface (100b). The second guard ring (131) may be in contact with the sixth well (153). The conductivity type of the second guard ring (131) may be p-type. The doping concentration of the second guard ring (131) may be lower than the doping concentration of the second high-concentration doping region (130). For example, the doping concentration of the second guard ring (131) is 1x10 15 ~ 5x10 17 cm -3The second guard ring (131) can improve the breakdown characteristics of the single-photon avalanche diode (1700). Specifically, the second guard ring (131) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0149] A second contact (151) may be provided on the side of the second guard ring (131). The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the second guard ring (131) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the second guard ring (131). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1700). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0150] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may come into contact with the buried area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the second guard ring (131). The second relief area (152) may be spaced apart from the second guard ring (131). The sixth well (153) may extend between the second relief area (152) and the second guard ring (131). For example, the area between the second relief area (152) and the second guard ring (131) may be filled with the sixth well (153). Between the second relief area (152) and the second guard ring (131), the sixth well (153) may be exposed on the front surface (100a). In one example, the sixth well (153) may not be provided in an area adjacent to the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a buried area (110). The buried area (110) between the second relaxation area (152) and the second guard ring (131) may be exposed on the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a substrate area (102).Between the second relaxation region (152) and the second guard ring (131), the substrate region (102) may be exposed on the front surface (100a). The second relaxation region (152) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second relaxation region (152) and the rear surface (100b) may be smaller than the distance between the second guard ring (131) and the rear surface (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151) and may be similar to or higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second relaxation region (152) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0151] A device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1700) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1700) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0152] The present disclosure may provide a single-photon avalanche diode (1700) that operates over a wide wavelength band and has improved tunneling noise characteristics and trap-assisted tunneling noise characteristics by utilizing a third low-concentration doping region (154). The present disclosure may provide a single-photon avalanche diode (1700) having a low breakdown voltage by utilizing a third low-concentration doping region (154).

[0154] FIG. 17 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 18 is a cross-sectional view along the line I-I' of the single-photon avalanche diode of FIG. 17.

[0155] Referring to FIGS. 17 and 18, a single-photon avalanche diode (1800) may be provided. The single-photon avalanche diode (1800) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1800) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), a seventh well (132), an eighth well (155), a second guard ring (131), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a sixth well (153), a second high-concentration doping region (130), a seventh well (132), an eighth well (155), a second guard ring (131), a second contact (151), and a second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the sixth well (153), the second high-concentration doping area (130), the seventh well (132), the eighth well (155), the second guard ring (131), the second contact (151), and the second relaxation area (152), may be referred to as the substrate area (102).

[0156] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0157] The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1800) or receive a signal from the single-photon avalanche diode (1800).

[0158] The seventh well (132) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1800), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. The seventh well (132) may be provided between the second high-concentration doping region (130) and the buried region (110). The seventh well (132) may be in contact with the upper and side surfaces of the second high-concentration doping region (130). The seventh well (132) may be exposed on the front surface (100a). On the front surface (100a), the seventh well (132) may surround the second high-concentration doping region (130). The conductivity type of the seventh well (132) may be p-type. For example, the doping concentration of the seventh well (132) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0159] The eighth well (155) may be provided between the seventh well (132) and the landfill area (110). The eighth well (155) may be provided on the upper surface of the seventh well (132). The conductivity type of the eighth well (155) may be n-type. For example, the doping concentration of the eighth well (155) is 1x10 15 ~ 5x10 17 cm -3It may be. The eighth well (155) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having an n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. A depletion region (106) may be formed at the depth required by the seventh well (132) and the eighth well (155). The depth may refer to a distance from the front (100a) along the direction from the front (100a) toward the rear (100b). Depending on the depth of the depletion region (106), the detection efficiency according to the wavelength band of the single-photon avalanche diode (1800) may vary. For example, the wavelength band in which the single-photon avalanche diode (1800) has high detection efficiency may be controlled by the depth of the depletion region (106). Accordingly, the present disclosure can provide a single-photon avalanche diode (1800) having high detection efficiency for a required wavelength band.

[0160] A second guard ring (131) may be provided on the side of the second high-concentration doping area (130), the seventh well (132), and the eighth well (155). The second guard ring (131) may surround the second high-concentration doping area (130), the seventh well (132), and the eighth well (155). For example, the second guard ring (131) may have a ring shape extending along the side of the second high-concentration doping area (130), the seventh well (132), and the eighth well (155). The second guard ring (131) may be in direct contact with the second high-concentration doping area (130), the seventh well (132), and the eighth well (155). In another example, the second guard ring (131) may be spaced apart from the second high-concentration doping region (130), the seventh well (132), and the eighth well (155). The second guard ring (131) may be exposed on the front surface (100a). On the front surface (100a), the second guard ring (131) may surround the second high-concentration doping region (130) and the seventh well (132). The second guard ring (131) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second guard ring (131) and the rear surface (100b) may be smaller than the distance between the eighth well (155) and the rear surface (100b). The conductivity type of the second guard ring (131) may be p-type. The doping concentration of the second guard ring (131) may be lower than the doping concentration of the second high-concentration doping region (130). For example, the doping concentration of the second guard ring (131) is 1x10 15 ~ 1x10 18 cm -3The second guard ring (131) can improve the breakdown characteristics of the single-photon avalanche diode (1800). Specifically, the second guard ring (131) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0161] A sixth well (153) may be provided between the second guard ring (131) and the buried area (110). The sixth well (153) may cover the upper and side surfaces of the second guard ring (131). For example, the sixth well (153) may have a ring shape extending along the second guard ring (131). The upper surface of the eighth well (155) may be exposed on the inner side of the second guard ring (131). The upper and side surfaces of the sixth well (153) may be in direct contact with the buried area (110). The conductivity type of the sixth well (153) may be n-type. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be possible. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may be smaller as it approaches the front surface (100a). The sixth well (153) may electrically connect the eighth well (155) to the second contact (151) and the second relaxation region (152) described later. For example, a cathode voltage may be applied to the eighth well (155) through the sixth well (153).

[0162] A second contact (151) may be provided on the side of the second guard ring (131). The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the second guard ring (131) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the second guard ring (131). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1800). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0163] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may come into contact with the buried area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the second guard ring (131). The second relief area (152) may be spaced apart from the second guard ring (131). The sixth well (153) may extend between the second relief area (152) and the second guard ring (131). For example, the area between the second relief area (152) and the second guard ring (131) may be filled with the sixth well (153). Between the second relief area (152) and the second guard ring (131), the sixth well (153) may be exposed on the front surface (100a). In one example, the sixth well (153) may not be provided in an area adjacent to the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a buried area (110). The buried area (110) between the second relaxation area (152) and the second guard ring (131) may be exposed on the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a substrate area (102).Between the second relaxation region (152) and the second guard ring (131), the substrate region (102) may be exposed on the front surface (100a). The second relaxation region (152) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second relaxation region (152) and the rear surface (100b) may be greater than the distance between the second guard ring (131) and the rear surface (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151). For example, the doping concentration of the second relaxation region (152) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0164] A device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1800) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102) as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1800) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type. The present disclosure may provide a single-photon avalanche diode (1800) having high detection efficiency for a required wavelength band.

[0166] FIG. 19 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 20 is a cross-sectional view along the line J-J' of the single-photon avalanche diode of FIG. 19.

[0167] Referring to FIGS. 19 and 20, a single-photon avalanche diode (1900) may be provided. The single-photon avalanche diode (1900) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1900) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), a fourth low-concentration doping region (133), an eighth well (155), a second guard ring (131), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a sixth well (153), a second high-concentration doping region (130), a fourth low-concentration doping region (133), an eighth well (155), a second guard ring (131), a second contact (151), and a second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the filled area (110), the sixth well (153), the second high-concentration doping area (130), the fourth low-concentration doping area (133), the eighth well (155), the second guard ring (131), the second contact (151), and the second relaxation area (152), may be referred to as the substrate area (102).

[0168] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0169] The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1900) or receive a signal from the single-photon avalanche diode (1900).

[0170] The fourth low-concentration doping region (133) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1900), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. The fourth low-concentration doping region (133) may be configured to reduce or prevent short-channel effects that occur as the size of the semiconductor device decreases. For example, a short-channel effect may be current flowing even when no photon is incident on the single-photon avalanche diode (1900). The fourth low-concentration doping region (133) may be provided between the second high-concentration doping region (130) and the sixth well (153). The fourth low-concentration doping region (133) may be in contact with the upper and side surfaces of the second high-concentration doping region (130). The fourth low-concentration doping region (133) may be exposed on the front surface (100a). On the front surface (100a), the fourth low-concentration doping region (133) may surround the second high-concentration doping region (130). The conductivity type of the fourth low-concentration doping region (133) may be p-type. The fourth low-concentration doping region (133) may have a lower doping concentration than the second high-concentration doping region (130). For example, the doping concentration of the fourth low-concentration doping region (133) is 1x10 15 ~ 1x10 18 cm -3 It may be possible. By forming a depletion region (106) using a fourth low-concentration doping region (133), tunneling noise and trap-assisted tunneling noise of the single-photon avalanche diode (1900) can be reduced, and the operating wavelength band of the single-photon avalanche diode (1900) can be widened.

[0171] The eighth well (155) may be provided between the fourth low-concentration doping region (133) and the landfill region (110). The eighth well (155) may be provided on the upper surface of the fourth low-concentration doping region (133). The conductivity type of the eighth well (155) may be n-type. For example, the doping concentration of the eighth well (155) is 1x10 15 ~ 5x10 17cm -3 It may be. The eighth well (155) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following, the region having an n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements.

[0172] A second guard ring (131) may be provided on the side of the fourth low-concentration doping region (133) and the eighth well (155). The second guard ring (131) may surround the fourth low-concentration doping region (133) and the eighth well (155). For example, the second guard ring (131) may have a ring shape extending along the side of the fourth low-concentration doping region (133) and the eighth well (155). The second guard ring (131) may be in direct contact with the fourth low-concentration doping region (133) and the eighth well (155). In another example, the second guard ring (131) may be spaced apart from the fourth low-concentration doping region (133) and the eighth well (155). The second guard ring (131) may be exposed on the front surface (100a). On the front surface (100a), the second guard ring (131) may surround the fourth low-concentration doping region (133). The second guard ring (131) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second guard ring (131) and the rear surface (100b) may be smaller than the distance between the eighth well (155) and the rear surface (100b). The conductivity type of the second guard ring (131) may be p-type. The doping concentration of the second guard ring (131) may be lower than the doping concentration of the second high-concentration doping region (130). For example, the doping concentration of the second guard ring (131) is 1x10 15 ~ 1x10 18 cm -3The second guard ring (131) can improve the breakdown characteristics of the single-photon avalanche diode (1900). Specifically, the second guard ring (131) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0173] A sixth well (153) may be provided between the second guard ring (131) and the burial area (110) and between the eighth well (155) and the burial area (110). The sixth well (153) may cover the second guard ring (131) and the eighth well (155). The sixth well (153) may cover the top surface and one side of the second relaxation area (152), while leaving the other side of the second relaxation area (152) exposed. The top surface and side of the sixth well (153) may be in direct contact with the burial area (110). The conductivity type of the sixth well (153) may be n-type. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may become smaller as it approaches the front (100a).

[0174] A second contact (151) may be provided on the side of the second guard ring (131). The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the second guard ring (131) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the second guard ring (131). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1900). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0175] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may come into contact with the buried area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the second guard ring (131). The second relief area (152) may be spaced apart from the second guard ring (131). The sixth well (153) may extend between the second relief area (152) and the second guard ring (131). For example, the area between the second relief area (152) and the second guard ring (131) may be filled with the sixth well (153). Between the second relief area (152) and the second guard ring (131), the sixth well (153) may be exposed on the front surface (100a). In one example, the sixth well (153) may not be provided in an area adjacent to the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a buried area (110). The buried area (110) between the second relaxation area (152) and the second guard ring (131) may be exposed on the front (100a). For example, the area between the second relaxation area (152) and the second guard ring (131) may be filled with a substrate area (102) adjacent to the front (100a).Between the second relaxation region (152) and the second guard ring (131), the substrate region (102) may be exposed on the front surface (100a). The second relaxation region (152) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second relaxation region (152) and the rear surface (100b) may be greater than the distance between the second guard ring (131) and the rear surface (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151). For example, the doping concentration of the second relaxation region (152) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0176] A device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1900) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1900) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0177] The present disclosure can provide a single-photon avalanche diode (1900) that operates over a wide wavelength band, with improved tunneling noise characteristics and trap-assisted tunneling noise characteristics by utilizing a fourth low-concentration doping region (133) to form a depletion region (106).

[0179] FIG. 21 is a top view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. For the sake of brevity, differences from that shown in FIG. 1 are explained.

[0180] Referring to FIG. 21, a single-photon avalanche diode (1000) may be provided. Unlike that shown in FIG. 1, the single-photon avalanche diode (1000) may have a square shape. Specifically, the high-concentration doping region (140) may have a square shape, and the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have a square ring shape surrounding the high-concentration doping region (140). The first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may be arranged sequentially in a direction away from the high-concentration doping region (140). For example, the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have the same center.

[0182] FIG. 22 is a top view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. For the sake of brevity, differences from that shown in FIG. 1 are explained.

[0183] Referring to FIG. 22, a single-photon avalanche diode (1000) may be provided. Unlike that shown in FIG. 1, the single-photon avalanche diode (1000) may have a square shape with rounded corners. Specifically, the high-concentration doping region (140) may have a square shape with rounded corners, and the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have a square ring shape with rounded corners surrounding the high-concentration doping region (140). The first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may be arranged sequentially in a direction away from the high-concentration doping region (140). For example, the high-concentration doping region (140), the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have the same center.

[0185] FIG. 23 is a top view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. For the sake of brevity, differences from that shown in FIG. 1 are explained.

[0186] Referring to FIG. 23, a single-photon avalanche diode (1000) may be provided. Unlike that shown in FIG. 1, the single-photon avalanche diode (1000) may have a rectangular shape. Specifically, the high-concentration doping region (140) may have a rectangular shape, and the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have a rectangular ring shape surrounding the high-concentration doping region (140). The first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may be arranged sequentially in a direction away from the high-concentration doping region (140). For example, the high-concentration doping region (140), the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have the same center.

[0188] FIG. 24 is a top view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. For the sake of brevity, differences from that shown in FIG. 1 are explained.

[0189] Referring to FIG. 24, a single-photon avalanche diode (1000) may be provided. Unlike that shown in FIG. 1, the single-photon avalanche diode (1000) may have a rectangular shape with rounded corners. Specifically, the high-concentration doping region (140) may have a rectangular shape with rounded corners, and the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have a rectangular ring shape with rounded corners surrounding the high-concentration doping region (140). The first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may be arranged sequentially in a direction away from the high-concentration doping region (140). For example, the high-concentration doping region (140), the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have the same center.

[0191] FIG. 25 is a top view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. For the sake of brevity, differences from that shown in FIG. 1 are explained.

[0192] Referring to FIG. 25, a single-photon avalanche diode (1000) may be provided. Unlike that shown in FIG. 1, the single-photon avalanche diode (1000) may have an elliptical shape. Specifically, the high-concentration doping region (140) may have an elliptical shape, and the guard ring (142), first relaxation region (122), first well (120), first contact (121), buried region (110), and device isolation pattern (104) may have an elliptical ring shape surrounding the high-concentration doping region (140). The guard ring (142), first relaxation region (122), first well (120), first contact (121), buried region (110), and device isolation pattern (104) may be arranged sequentially in a direction away from the high-concentration doping region (140). For example, the high-concentration doping region (140), the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have the same center.

[0194] FIG. 26 is a top view of the single-photon avalanche diode of FIG. 2 according to exemplary embodiments. For the sake of brevity, differences from that shown in FIG. 1 are explained.

[0195] Referring to FIG. 26, a single-photon avalanche diode (1000) may be provided. Unlike that shown in FIG. 1, the single-photon avalanche diode (1000) may have an octagonal shape. Specifically, the high-concentration doping region (140) may have an octagonal shape, and the guard ring (142), first relaxation region (122), first well (120), first contact (121), buried region (110), and device isolation pattern (104) may have an octagonal ring shape surrounding the high-concentration doping region (140). The guard ring (142), first relaxation region (122), first well (120), first contact (121), buried region (110), and device isolation pattern (104) may be arranged sequentially in a direction away from the high-concentration doping region (140). For example, the high-concentration doping region (140), the first low-concentration doping region (141), the first guard ring (142), the first well (120), the first relaxation region (122), the first contact (121), the buried region (110), and the device isolation pattern (104) may have the same center.

[0197] FIG. 27 is a cross-sectional view corresponding to the line H-H' of FIG. 15 of a single-photon avalanche diode according to exemplary embodiments.

[0198] Referring to FIGS. 15 and 27, a single-photon avalanche diode (1710) may be provided. The single-photon avalanche diode (1710) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1710) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), a second guard ring (131), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In other examples, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, the buried region (110), the sixth well (153), the second high-concentration doping region (130), the second guard ring (131), the second contact (151), and the second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining region of the semiconductor substrate (100), excluding the buried region (110), the sixth well (153), the second high-concentration doping region (130), the second guard ring (131), the second contact (151), and the second relaxation region (152), may be referred to as the substrate region (102).

[0199] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0200] The sixth well (153) may be provided within the semiconductor substrate (100). A buried region (110) may be disposed between the sixth well (153) and the back surface (100b). The top surface and side surface of the sixth well (153) may be in direct contact with the buried region (110). The conductivity type of the sixth well (153) may be n-type. The sixth well (153) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may become smaller as it approaches the front (100a).

[0201] The second high-concentration doping region (130) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1710), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A second high-concentration doping region (130) may be provided between the sixth well (153) and the front surface (100a). The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1710) or receive a signal from the single-photon avalanche diode (1710).

[0202] A second guard ring (131) may be provided on the side of the second high-concentration doping area (130). The second guard ring (131) may surround the second high-concentration doping area (130). For example, the second guard ring (131) may have a ring shape extending along the side of the second high-concentration doping area (130). The second guard ring (131) may be in direct contact with the second high-concentration doping area (130). In another example, the second guard ring (131) may be spaced apart from the second high-concentration doping area (130). The second guard ring (131) may be exposed on the front surface (100a). On the front surface (100a), the second guard ring (131) may surround the second high-concentration doping area (130). The second guard ring (131) may extend along the direction from the front (100a) toward the rear (100b). The distance between the second guard ring (131) and the rear (100b) may be greater than the distance between the eighth well (155) and the rear (100b). The second guard ring (131) may be in contact with the sixth well (153). The conductivity type of the second guard ring (131) may be p-type. The doping concentration of the second guard ring (131) may be lower than the doping concentration of the second high-concentration doping region (130). For example, the doping concentration of the second guard ring (131) is 1x10 15 ~ 5x10 17 cm -3 The second guard ring (131) can improve the breakdown characteristics of the single-photon avalanche diode (1710). Specifically, the second guard ring (131) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0203] A second contact (151) may be provided on the side of the second guard ring (131). The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the second guard ring (131) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the second guard ring (131). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1710). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0204] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may come into contact with the buried area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the second guard ring (131). The second relief area (152) may be spaced apart from the second guard ring (131). The sixth well (153) may extend between the second relief area (152) and the second guard ring (131). For example, the area between the second relief area (152) and the second guard ring (131) may be filled with the sixth well (153). Between the second relief area (152) and the second guard ring (131), the sixth well (153) may be exposed on the front surface (100a). In one example, the sixth well (153) may not be provided in an area adjacent to the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a buried area (110). The buried area (110) between the second relaxation area (152) and the second guard ring (131) may be exposed on the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a substrate area (102).Between the second relaxation region (152) and the second guard ring (131), the substrate region (102) may be exposed on the front surface (100a). The second relaxation region (152) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second relaxation region (152) and the rear surface (100b) may be smaller than the distance between the second guard ring (131) and the rear surface (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151) and may be similar to or higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second relaxation region (152) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0205] A device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess area formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1710) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1710) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0207] FIG. 28 is a cross-sectional view corresponding to the line H-H' of FIG. 15 of a single-photon avalanche diode according to exemplary embodiments.

[0208] Referring to FIGS. 15 and 28, a single-photon avalanche diode (1720) may be provided. The single-photon avalanche diode (1720) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1720) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), an eighth well (155), a second guard ring (131), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In another example, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, a buried region (110), a sixth well (153), a second high-concentration doping region (130), an eighth well (155), a second guard ring (131), a second contact (151), and a second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining area of ​​the semiconductor substrate (100), excluding the buried area (110), the sixth well (153), the second high-concentration doping area (130), the eighth well (155), the second guard ring (131), the second contact (151), and the second relaxation area (152), may be referred to as the substrate area (102).

[0209] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0210] The sixth well (153) may be provided within the semiconductor substrate (100). A buried region (110) may be disposed between the sixth well (153) and the back surface (100b). The top surface and side surface of the sixth well (153) may be in direct contact with the buried region (110). The conductivity type of the sixth well (153) may be n-type. The sixth well (153) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may become smaller as it approaches the front (100a).

[0211] The second high-concentration doping region (130) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated by example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1720), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A second high-concentration doping region (130) may be provided between the sixth well (153) and the front surface (100a). The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1720) or receive a signal from the single-photon avalanche diode (1720).

[0212] The eighth well (155) may be provided between the second high-concentration doping region (130) and the sixth well (153). The eighth well (155) may be provided on the upper surface of the eighth well (155). The conductivity type of the eighth well (155) may be n-type. For example, the doping concentration of the eighth well (155) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0213] A second guard ring (131) may be provided on the side of the second high-concentration doping area (130) and the eighth well (155). The second guard ring (131) may surround the second high-concentration doping area (130) and the eighth well (155). For example, the second guard ring (131) may have a ring shape extending along the side of the second high-concentration doping area (130) and the eighth well (155). The second guard ring (131) may be in direct contact with the second high-concentration doping area (130) and the eighth well (155). In another example, the second guard ring (131) may be spaced apart from the second high-concentration doping area (130) and the eighth well (155). The second guard ring (131) may be exposed on the front surface (100a). On the front surface (100a), the second guard ring (131) may surround the second high-concentration doping region (130). The second guard ring (131) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second guard ring (131) and the rear surface (100b) may be greater than the distance between the eighth well (155) and the rear surface (100b). The second guard ring (131) may be in contact with the sixth well (153). The conductivity type of the second guard ring (131) may be p-type. The doping concentration of the second guard ring (131) may be lower than the doping concentration of the second high-concentration doping region (130). For example, the doping concentration of the second guard ring (131) is 1x10 15 ~ 5x10 17 cm -3 The second guard ring (131) can improve the breakdown characteristics of the single-photon avalanche diode (1720). Specifically, the second guard ring (131) can prevent premature breakdown by mitigating the concentration of the electric field in a part of the depletion region (106). Premature breakdown is a breakdown that occurs in a part of the depletion region (106) before a sufficient electric field is applied across the entire depletion region (106), and occurs as the electric field is concentrated in a part of the depletion region (106).

[0214] A second contact (151) may be provided on the side of the second guard ring (131). The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the second guard ring (131) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the second guard ring (131). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1720). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0215] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may come into contact with the buried area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the second guard ring (131). The second relief area (152) may be spaced apart from the second guard ring (131). The sixth well (153) may extend between the second relief area (152) and the second guard ring (131). For example, the area between the second relief area (152) and the second guard ring (131) may be filled with the sixth well (153). Between the second relief area (152) and the second guard ring (131), the sixth well (153) may be exposed on the front surface (100a). In one example, the sixth well (153) may not be provided in an area adjacent to the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a buried area (110). The buried area (110) between the second relaxation area (152) and the second guard ring (131) may be exposed on the front (100a). For example, the area adjacent to the front (100a) between the second relaxation area (152) and the second guard ring (131) may be filled with a substrate area (102).Between the second relaxation region (152) and the second guard ring (131), the substrate region (102) may be exposed on the front surface (100a). The second relaxation region (152) may extend along the direction from the front surface (100a) toward the rear surface (100b). The distance between the second relaxation region (152) and the rear surface (100b) may be smaller than the distance between the second guard ring (131) and the rear surface (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151) and may be similar to or higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second relaxation region (152) is 1x10. 15 ~ 5x10 17 cm -3 It could be.

[0216] A device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess area formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1720) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1720) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0218] FIG. 29 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 30 is a cross-sectional view along the line I-I' of the single-photon avalanche diode of FIG. 29.

[0219] Referring to FIGS. 29 and 30, a single-photon avalanche diode (1730) may be provided. The single-photon avalanche diode (1730) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1730) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), an eighth well (155), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In other examples, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, the buried region (110), the sixth well (153), the second high-concentration doping region (130), the eighth well (155), the second contact (151), and the second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining region of the semiconductor substrate (100), excluding the buried region (110), the sixth well (153), the second high-concentration doping region (130), the eighth well (155), the second contact (151), and the second relaxation region (152), may be referred to as the substrate region (102).

[0220] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0221] The sixth well (153) may be provided within the semiconductor substrate (100). A buried region (110) may be disposed between the sixth well (153) and the back surface (100b). The top surface and side surface of the sixth well (153) may be in direct contact with the buried region (110). The conductivity type of the sixth well (153) may be n-type. The sixth well (153) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may become smaller as it approaches the front (100a).

[0222] The second high-concentration doping region (130) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1730), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x10 5 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A second high-concentration doping region (130) may be provided between the sixth well (153) and the front surface (100a). The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1730) or receive a signal from the single-photon avalanche diode (1730).

[0223] The eighth well (155) may be provided between the second high-concentration doping region (130) and the sixth well (153). The eighth well (155) may be provided on the upper surface of the eighth well (155). The conductivity type of the eighth well (155) may be n-type. For example, the doping concentration of the eighth well (155) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0224] The landfill area (110) may be further provided on the side of the second high-concentration doping area (130) and the eighth well (155). The landfill area (110) may surround the second high-concentration doping area (130) and the eighth well (155). For example, the landfill area (110) may have a ring shape extending along the side of the second high-concentration doping area (130) and the eighth well (155). The landfill area (110) may be in direct contact with the second high-concentration doping area (130) and the eighth well (155).

[0225] The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the buried region (110) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the buried region (110). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1730). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0226] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may be in contact with the reclaimed area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the reclaimed area (110). The second relief area (152) may be spaced apart from the reclaimed area (110). The sixth well (153) may extend between the second relief area (152) and the eighth well (155). The sixth well (153) may not be provided in the area adjacent to the front surface (100a). The area adjacent to the front surface (100a) between the second relief area (152) and the eighth well (155) may be filled with the reclaimed area (110). The second relaxation region (152) may extend along the direction from the front (100a) toward the rear (100b). The distance between the second relaxation region (152) and the rear (100b) may be smaller than the distance between the buried region (110) on the side of the second high-concentration doping region (130) and the rear (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151) and similar to or higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second relaxation region (152) is 1x1015 ~ 5x10 17 cm -3 It may be. The device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess area formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1730) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1730) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0228] FIG. 31 is a top view of a single-photon avalanche diode according to exemplary embodiments. FIG. 32 is a cross-sectional view along the line J-J' of the single-photon avalanche diode of FIG. 31.

[0229] Referring to FIGS. 31 and 32, a single-photon avalanche diode (1740) may be provided. The single-photon avalanche diode (1740) may be referred to as a Geiger-mode avalanche diode (G-APD). The single-photon avalanche diode (1740) may include a buried region (110), a sixth well (153), a second high-concentration doping region (130), a seventh well (132), a second contact (151), a second relaxation region (152), and a device isolation pattern (104) formed on a semiconductor substrate (100). The semiconductor substrate (100) may be an epi layer formed by an epitaxial growth process. For example, the semiconductor substrate (100) may be a silicon substrate. The conductivity type of the semiconductor substrate (100) may be p-type. However, the conductivity type of the semiconductor substrate (100) is not limited to p-type. In other examples, the conductivity type of the semiconductor substrate (100) may be n-type. The semiconductor substrate (100) may include a front surface (100a) and a rear surface (100b) facing each other. For example, the buried region (110), the sixth well (153), the second high-concentration doping region (130), the seventh well (132), the second contact (151), and the second relaxation region (152) may be formed by injecting impurities into the semiconductor substrate (100). The remaining region of the semiconductor substrate (100), excluding the buried region (110), the sixth well (153), the second high-concentration doping region (130), the seventh well (132), the second contact (151), and the second relaxation region (152), may be referred to as the substrate region (102).

[0230] The buried region (110) may be provided to extend from the front surface (100a) to a region adjacent to the rear surface (100b). The top surface and side surface of the buried region (110) may be in contact with the substrate region (102). For example, the conductivity type of the buried region (110) may be p-type. The buried region (110) may contain Group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or Group 2 elements as impurities. In the following description, the region having a p-type conductivity type may contain Group 3 or Group 2 elements as impurities. For example, the doping concentration of the buried region (110) is 1x10 14 ~ 1x10 18 cm -3 It may be. In one example, the landfill area (110) may have a uniform doping concentration. In one example, the doping concentration of the landfill area (110) may become smaller as it gets closer to the front (100a).

[0231] The sixth well (153) may be provided within the semiconductor substrate (100). A buried region (110) may be disposed between the sixth well (153) and the back surface (100b). The top surface and side surface of the sixth well (153) may be in direct contact with the buried region (110). The conductivity type of the sixth well (153) may be n-type. The sixth well (153) may contain impurities of Group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), Group 6, or Group 7 elements. In the following description, the region having n-type conductivity may contain impurities of Group 5, Group 6, or Group 7 elements. For example, the doping concentration of the sixth well (153) is 1x10 15 ~ 1x10 18 cm -3 It may be. In one example, the sixth well (153) may have a uniform doping concentration. In one example, the doping concentration of the sixth well (153) may become smaller as it approaches the front (100a).

[0232] A second high-concentration doping region (130) may be provided between the sixth well (153) and the front surface (100a). The second high-concentration doping region (130) may be exposed on the front surface (100a). The conductivity type of the second high-concentration doping region (130) may be p-type. For example, the doping concentration of the second high-concentration doping region (130) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second high-concentration doping region (130) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits. The quenching resistor or quenching circuit may interrupt the avalanche effect and allow the single-photon avalanche diode (SPAD) to detect another photon. Other pixel circuits may include, for example, a reset or recharge circuit, a memory, an amplifier circuit, a counter, a gate circuit, a time-to-digital converter, etc. Other pixel circuits can transmit a signal to the single-photon avalanche diode (1740) or receive a signal from the single-photon avalanche diode (1740).

[0233] The seventh well (132) may be configured to form a depletion region (106). The size of the depletion region (106) is illustrated as an example and is not limited. When reverse bias is applied to the single-photon avalanche diode (1740), a strong electric field may be formed in the depletion region (106). For example, the maximum strength of the electric field is approximately 3x105 ~ 1x10 6 It may be V / cm. Since electrons can be multiplied by the electric field of the depletion region (106), the depletion region (106) may be referred to as a multiplication region. A seventh well (132) may be provided between the second high-concentration doping region (130) and the sixth well (153). The seventh well (132) may be in contact with the top and side surfaces of the second high-concentration doping region (130). The seventh well (132) may be exposed on the front surface (100a). On the front surface (100a), the seventh well (132) may surround the second high-concentration doping region (130). The conductivity type of the seventh well (132) may be p-type. For example, the doping concentration of the seventh well (132) is 1x10 15 ~ 5x10 17 cm -3 It could be.

[0234] The reclaimed area (110) may be further provided on the side of the seventh well (132). The reclaimed area (110) may surround the seventh well (132). For example, the reclaimed area (110) may have a ring shape extending along the side of the eighth well (155). The reclaimed area (110) may be in direct contact with the eighth well (155).

[0235] The second contact (151) may be provided on the opposite side of the second high-concentration doping region (130) with the buried region (110) in between. The second contact (151) may be exposed on the front surface (100a). On the front surface (100a), the second contact (151) may surround the buried region (110). In another example, the second contact (151) may be provided in multiple numbers. In this case, the multiple second contacts (151) may each be electrically connected to a circuit outside the single-photon avalanche diode (1740). The conductivity type of the second contact (151) may be n-type. The doping concentration of the second contact (151) may be higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second contact (151) is 1x10 15 ~ 2x10 20 cm -3 It may be. In one example, the second contact (151) may be electrically connected to at least one of an external power source, a DC-to-DC converter, and other power management integrated circuits. In one example, the second contact (151) may be electrically connected to at least one of a quenching resistor (or quenching circuit) and other pixel circuits.

[0236] A second relief area (152) may be provided between the second contact (151) and the sixth well (153). The second relief area (152) may be electrically connected to the second contact (151) and the sixth well (153). The second relief area (152) may relieve the difference between the second contact (151) and the sixth well (153). The second relief area (152) may extend along the second contact (151). The second relief area (152) may be provided on the side and top surfaces of the second contact (151). For example, the second relief area (152) may be in direct contact with the side and top surfaces of the second contact (151). The top surface and one side of the second relief area (152) may be in contact with the sixth well (153). The other side of the second relief area (152) is exposed by the sixth well (153) and may be in contact with the reclamation area (110). The second relief area (152) may be exposed on the front surface (100a). On the front surface (100a), the second relief area (152) may surround the reclamation area (110). The second relief area (152) may be spaced apart from the reclamation area (110). The sixth well (153) may extend between the second relief area (152) and the seventh well (132). The sixth well (153) may not be provided in the area adjacent to the front surface (100a). The area adjacent to the front surface (100a) between the second relief area (152) and the seventh well (132) may be filled with the reclamation area (110). The second relaxation region (152) may extend along the direction from the front (100a) toward the rear (100b). The distance between the second relaxation region (152) and the rear (100b) may be smaller than the distance between the buried region (110) on the side of the second high-concentration doping region (130) and the rear (100b). The conductivity type of the second relaxation region (152) may be n-type. The doping concentration of the second relaxation region (152) may be lower than the doping concentration of the second contact (151) and similar to or higher than the doping concentration of the sixth well (153). For example, the doping concentration of the second relaxation region (152) is 1x1015 ~ 5x10 17 cm -3 It may be. The device isolation pattern (104) may be provided on the side of the second relaxation region (152). The device isolation pattern (104) may be exposed on the front surface (100a). On the front surface (100a), the device isolation pattern (104) may surround the second relaxation region (152). The device isolation pattern (104) may be formed, for example, by a process of filling an insulating material into a recess area formed by etching the semiconductor substrate (100). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). The device isolation pattern (104) may electrically isolate the single-photon avalanche diode (1740) and other semiconductor devices (e.g., other single-photon avalanche diodes). Although the device isolation pattern (104) is shown to be in contact only with the buried region (110), this is exemplary. In another example, the device isolation pattern (104) may be formed to be in contact with the second relaxation region (152) and the substrate region (102), as well as the buried region (110). In another example, the device isolation pattern (104) may be formed to be in contact with the first contact (121). In another example, the single-photon avalanche diode (1740) may not include the device isolation pattern (104). Each region may have a conductivity type opposite to the conductivity type described above. For example, regions described as having n-type may have p-type, and regions described as having p-type may have n-type.

[0238] FIG. 33 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. For the sake of brevity, substantially the same details as those described with reference to FIG. 1 and FIG. 2 may not be described.

[0239] Referring to FIG. 33, a single-photon detector (SPD1) may be provided. The single-photon detector (SPD1) may include a single-photon avalanche diode (1), a control layer (200), a connection layer (300), and a lens portion (400). The single-photon detector (SPD1) may be a back-side illumination (BSI) type image sensor. The front side may be a surface where various semiconductor processes are performed during the manufacturing of the single-photon avalanche diode (1), and the back side may be a surface positioned opposite the front side. For example, the top surface and bottom surface of the single-photon avalanche diodes (1000 to 1900) of the present disclosure may be the front side (100a) and the back side (100b), respectively. The back-side illumination method may refer to light being incident on the back side (100b) of the single-photon avalanche diode (1). The front illumination method described below may refer to light being incident on the front of the single-photon avalanche diode (1). The single-photon avalanche diode (1) may be substantially the same as the single-photon avalanche diode (1000) described with reference to FIGS. 1 and FIGS. 2. However, this is exemplary. In other examples, the single-photon avalanche diode (1) may be any one of the single-photon avalanche diodes (1100 to 1900) described above. For convenience of explanation, the single-photon avalanche diode (1) is shown as having its top and bottom reversed compared to the single-photon avalanche diode (1000) shown in FIG. 2. Accordingly, the top surface and bottom surface of the single-photon avalanche diode (1) may be the rear surface (100b) and the front surface (100a), respectively.

[0240] A control layer (200) may be provided on the front surface of a single-photon avalanche diode (1). The control layer (200) may include circuits necessary for the operation of the single-photon avalanche diode (1). For example, the control layer (200) may be a chip on which circuits are formed. The circuits may be implemented by various electronic components as needed. The circuits may include a quenching resistor (or quenching circuit) and a pixel circuit. The quenching resistor (or quenching circuit) may be configured to interrupt the avalanche effect and allow the single-photon avalanche diode (1) to detect another photon. The pixel circuits may be composed of a reset or recharge circuit, memory, amplifier circuit, counter, gate circuit, time-to-digital converter, etc. Additionally, the circuit may include a DC-to-DC converter and other power management integrated circuits. The circuit may transmit a signal to a single-photon avalanche diode (1) or receive a signal from a single-photon avalanche diode (1).

[0241] A connection layer (300) may be provided between a single-photon avalanche diode (1) and a control layer (200). The connection layer (300) may include an insulating layer (306), an output pattern (302a), a bias pattern (302b), a shield pattern (302c), and a vertical connection (304). For example, the insulating layer (306) may include silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), or a combination thereof. For example, the vertical connection (304) may include a contact or a via.

[0242] The output pattern (302a) may be electrically connected to the first high-concentration doping region (140). The output pattern (302a) may include an electrically conductive material. For example, the output pattern (302a) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The output pattern (302a) may electrically connect the circuit of the first high-concentration doping region (140) and the control layer (200). For example, a vertical connection (304) may be provided between the first high-concentration doping region (140) and the output pattern (302a), and a Cu-Cu bonding may be provided between the output pattern (302a) and the control layer (200). The output pattern (302a) may be configured to extract a detection signal from the single-photon avalanche diode (1).

[0243] The bias pattern (302b) may be electrically connected to the first contact (121). The bias pattern (302b) may include an electrically conductive material. For example, the bias pattern (302b) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The bias pattern (302b) may electrically connect the circuit of the first contact (121) and the control layer (200). For example, a vertical connection (304) may be provided between the first contact (121) and the bias pattern (302b), and a Cu-Cu bonding may be provided between the bias pattern (302b) and the control layer (200). The bias pattern (302b) may be configured to apply a bias to the single-photon avalanche diode (1).

[0244] The shield pattern (302c) can electrically shield between the output pattern (302a) and the bias pattern (302b). For example, the shield pattern (302c) can be configured so that the detection signal extracted by the output pattern (302a) is not affected by the bias signal applied to the bias pattern (302b). The shield pattern (302c) can be electrically isolated from the output pattern (302a) and the bias pattern (302b). For example, the shield pattern (302c) can be spaced apart from the output pattern (302a) and the bias pattern (302b).

[0245] The output pattern (302a), bias pattern (302b), and shield pattern (302c) can serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode (1) can be reflected by the output pattern (302a), bias pattern (302b), and shield pattern (302c) and then incident back on the single-photon avalanche diode (1). Accordingly, the light absorption efficiency of the single-photon avalanche diode (1) can be improved.

[0246] A lens portion (400) may be provided on the rear surface (100b) of a single-photon avalanche diode (1). The lens portion (400) may include a lens (402). The lens (402) may focus incident light and transmit it to the single-photon avalanche diode (1). For example, the lens (402) may include a microlens, a Fresnel lens, or a metal lens. However, the type of lens (402) is not limited and may be determined as necessary. In one example, the central axis of the lens (402) may be aligned with the central axis of the single-photon avalanche diode (1). The central axis of the lens (402) and the central axis of the single-photon avalanche diode (1) may be virtual axes that pass through the center of the lens (402) and the center of the single-photon avalanche diode (1), respectively, and are parallel to the stacking direction of the single-photon avalanche diode (1) and the lens (402). In one example, the central axis of the lens (402) may be aligned offset from the central axis of the single-photon avalanche diode (1). In one embodiment, the width of the lens (402) may be about half the width of the single-photon avalanche diode (1) and implemented in a 2x2 shape. In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode (1). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0248] FIG. 34 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. For the sake of brevity, substantially the same details as those described with reference to FIG. 1 and FIG. 2 may not be described.

[0249] Referring to FIG. 34, a single-photon detector (SPD2) may be provided. The single-photon detector (SPD2) may include a single-photon avalanche diode (1), a connecting layer (300), and a lens portion (400). The single-photon detector (SPD2) may be a back-side illumination (BSI) type image sensor. The single-photon avalanche diode (1) may be substantially the same as the single-photon avalanche diode (1000) described with reference to FIG. 1 and FIG. 2. However, this is exemplary. In other examples, the single-photon avalanche diode (1) may be any one of the single-photon avalanche diodes (1100 to 1900) described above. For convenience of explanation, the single-photon avalanche diode (1) is depicted as the upper and lower inverted version of the single-photon avalanche diode (1000) shown in FIG. 2. The top and bottom surfaces of the single-photon avalanche diode (1) may be the rear surface (100b) and the front surface (100a), respectively.

[0250] The single-photon avalanche diode (1) may include circuits necessary for the operation of the single-photon avalanche diode (1) in an area adjacent to the front surface (100a). The circuits may be implemented by various electronic components as needed. The circuits may include a quenching resistor (or quenching circuit) and pixel circuits. The quenching resistor (or quenching circuit) may be configured to interrupt the avalanche effect and allow the single-photon avalanche diode (1) to detect another photon. The pixel circuits may be composed of a reset or recharge circuit, memory, amplifier circuit, counter, gate circuit, time-to-digital converter, etc. Additionally, the circuits may include a DC-to-DC converter and other power management integrated circuits. The circuit can transmit a signal to the single-photon avalanche diode (1) or receive a signal from the single-photon avalanche diode (1).

[0251] A connection layer (300) may be provided on the front surface (100a) of a single-photon avalanche diode (1). The connection layer (300) may include an insulating layer (306), an output pattern (302a), a bias pattern (302b), a shield pattern (302c), and a vertical connection (304). For example, the insulating layer (306) may include silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), or a combination thereof. For example, the vertical connection (304) may include a contact or a via.

[0252] The output pattern (302a) may be electrically connected to the first high-concentration doping region (140). The output pattern (302a) may include an electrically conductive material. For example, the output pattern (302a) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The output pattern (302a) may electrically connect the first high-concentration doping region (140) and the circuit contained in the single-photon avalanche diode (1). For example, a vertical connection (304) may be provided between the first high-concentration doping region (140) and the output pattern (302a), and between the output pattern (302a) and the circuit. The output pattern (302a) may be configured to extract a detection signal from the single-photon avalanche diode (1).

[0253] The bias pattern (302b) may be electrically connected to the first contact (121). The bias pattern (302b) may include an electrically conductive material. For example, the bias pattern (302b) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The bias pattern (302b) may electrically connect the first contact (121) and the circuit contained in the single-photon avalanche diode (1). For example, a vertical connection (304) may be provided between the first contact (121) and the bias pattern (302b) and between the bias pattern (302b) and the circuit. The bias pattern (302b) may be configured to apply a bias to the single-photon avalanche diode (1).

[0254] The shield pattern (302c) can electrically shield between the output pattern (302a) and the bias pattern (302b). For example, the shield pattern (302c) can be configured so that the detection signal extracted by the output pattern (302a) is not affected by the bias signal applied to the bias pattern (302b).

[0255] The output pattern (302a), bias pattern (302b), and shield pattern (302c) can serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode (1) can be reflected by the output pattern (302a), bias pattern (302b), and shield pattern (302c) and then incident back on the single-photon avalanche diode (1). Accordingly, the light absorption efficiency of the single-photon avalanche diode (1) can be improved.

[0256] A lens portion (400) may be provided on the rear surface (100b) of a single-photon avalanche diode (1). The lens portion (400) may include a lens (402). The lens (402) may focus incident light and transmit it to the single-photon avalanche diode (1). For example, the lens (402) may include a microlens, a Fresnel lens, or a metal lens. However, the type of lens (402) is not limited and may be determined as necessary. In one example, the central axis of the lens (402) may be aligned with the central axis of the single-photon avalanche diode (1). The central axis of the lens (402) and the central axis of the single-photon avalanche diode (1) may be virtual axes that pass through the center of the lens (402) and the center of the single-photon avalanche diode (1), respectively, and are parallel to the stacking direction of the single-photon avalanche diode (1) and the lens (402). In one example, the central axis of the lens (402) may be aligned offset from the central axis of the single-photon avalanche diode (1). In one embodiment, the width of the lens (402) may be about half the width of the single-photon avalanche diode (1) and implemented in a 2x2 shape. In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode (1). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0258] FIG. 35 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. FIG. 36 is a top view of the first diffraction pattern of FIG. 35. For brevity of description, substantially the same as that described with reference to FIG. 1 and FIG. 2 may not be described.

[0259] Referring to FIG. 35, a single-photon detector (SPD3) may be provided. The single-photon detector (SPD3) may include a single-photon avalanche diode (1), a control layer (200), a connection layer (300), and a lens portion (400). The single-photon detector (SPD3) may be a back-side illumination (BSI) type image sensor. The front side may be the surface where various semiconductor processes are performed during the manufacturing of the single-photon avalanche diode (1), and the back side may be the surface positioned opposite the front side. For example, the top surface and bottom surface of the single-photon avalanche diodes (1000 to 1900) of the present disclosure may be the front side (100a) and the back side (100b), respectively. The back-side illumination method may refer to light being incident on the back side (100b) of the single-photon avalanche diode (1). The front illumination method described below may refer to light being incident on the front of the single-photon avalanche diode (1). The single-photon avalanche diode (1) may be substantially the same as the single-photon avalanche diode (1000) described with reference to FIGS. 1 and FIGS. 2. However, this is exemplary. In other examples, the single-photon avalanche diode (1) may be any one of the single-photon avalanche diodes (1100 to 1900) described above. For convenience of explanation, the single-photon avalanche diode (1) is shown as having its top and bottom reversed compared to the single-photon avalanche diode (1000) shown in FIG. 2. Accordingly, the top surface and bottom surface of the single-photon avalanche diode (1) may be the rear surface (100b) and the front surface (100a), respectively.

[0260] A control layer (200) may be provided on the front surface of a single-photon avalanche diode (1). The control layer (200) may include circuits necessary for the operation of the single-photon avalanche diode (1). For example, the control layer (200) may be a chip on which circuits are formed. The circuits may be implemented by various electronic components as needed. The circuits may include a quenching resistor (or quenching circuit) and a pixel circuit. The quenching resistor (or quenching circuit) may be configured to interrupt the avalanche effect and allow the single-photon avalanche diode (1) to detect another photon. The pixel circuits may be composed of a reset or recharge circuit, memory, amplifier circuit, counter, gate circuit, time-to-digital converter, etc. Additionally, the circuit may include a DC-to-DC converter and other power management integrated circuits. The circuit may transmit a signal to a single-photon avalanche diode (1) or receive a signal from a single-photon avalanche diode (1).

[0261] A connection layer (300) may be provided between a single-photon avalanche diode (1) and a control layer (200). The connection layer (300) may include an insulating layer (306), an output pattern (302a), a bias pattern (302b), a shield pattern (302c), and a vertical connection (304). For example, the insulating layer (306) may include silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), or a combination thereof. For example, the vertical connection (304) may include a contact or a via.

[0262] The output pattern (302a) may be electrically connected to the first high-concentration doping region (140). The output pattern (302a) may include an electrically conductive material. For example, the output pattern (302a) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The output pattern (302a) may electrically connect the circuit of the first high-concentration doping region (140) and the control layer (200). For example, a vertical connection (304) may be provided between the first high-concentration doping region (140) and the output pattern (302a), and a Cu-Cu bonding may be provided between the output pattern (302a) and the control layer (200). The output pattern (302a) may be configured to extract a detection signal from the single-photon avalanche diode (1).

[0263] The bias pattern (302b) may be electrically connected to the first contact (121). The bias pattern (302b) may include an electrically conductive material. For example, the bias pattern (302b) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The bias pattern (302b) may electrically connect the circuit of the first contact (121) and the control layer (200). For example, a vertical connection (304) may be provided between the first contact (121) and the bias pattern (302b), and a Cu-Cu bonding may be provided between the bias pattern (302b) and the control layer (200). The bias pattern (302b) may be configured to apply a bias to the single-photon avalanche diode (1).

[0264] The shield pattern (302c) can electrically shield between the output pattern (302a) and the bias pattern (302b). For example, the shield pattern (302c) can be configured so that the detection signal extracted by the output pattern (302a) is not affected by the bias signal applied to the bias pattern (302b).

[0265] The output pattern (302a), bias pattern (302b), and shield pattern (302c) can serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode (1) can be reflected by the output pattern (302a), bias pattern (302b), and shield pattern (302c) and then incident back on the single-photon avalanche diode (1). Accordingly, the light absorption efficiency of the single-photon avalanche diode (1) can be improved.

[0266] A lens portion (400) may be provided on the rear surface (100b) of a single-photon avalanche diode (1). Referring to FIG. 36, the lens portion (400) may include first diffraction patterns (404). The first diffraction patterns (404) may diffract incident light to increase the absorption length of light within the single-photon avalanche diode (1). In another example, scattering patterns may be provided on the rear surface (100b) of the single-photon avalanche diode (1) instead of the first diffraction patterns (404). The scattering patterns may be, for example, cross or X-shaped patterns. In another example, the scattering patterns may be a combined cross and X shape or a combined cross shape. The light absorption efficiency of the single-photon avalanche diode (1) may be improved by the lens portion (400). In one embodiment, at least one optical element may be inserted between the first diffraction patterns (404) and the single-photon avalanche diode (1). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer.

[0268] FIG. 37 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. For the sake of brevity, substantially the same details as those described with reference to FIG. 1 and FIG. 2 may not be described.

[0269] Referring to FIG. 37, a single-photon detector (SPD4) may be provided. The single-photon detector (SPD4) may include a single-photon avalanche diode (1), a control layer (200), a connection layer (300), and a lens portion (400). The single-photon detector (SPD4) may be a front-side illumination (FSI) type image sensor. The single-photon avalanche diode (1) may be substantially the same as the single-photon avalanche diode (1000) described with reference to FIG. 1 and FIG. 2. However, this is exemplary. In another example, the single-photon avalanche diode (1) may be any one of the single-photon avalanche diodes (1100 to 1900) described above. The top surface and bottom surface of the single-photon avalanche diode (1) may be the front surface (100a) and the rear surface (100b), respectively.

[0270] The single-photon avalanche diode (1) may include circuits necessary for the operation of the single-photon avalanche diode (1) in an area adjacent to the front surface (100a). The circuits may be implemented by various electronic components as needed. The circuits may include a quenching resistor (or quenching circuit) and pixel circuits. The quenching resistor (or quenching circuit) may be configured to interrupt the avalanche effect and allow the single-photon avalanche diode (1) to detect another photon. The pixel circuits may be composed of a reset or recharge circuit, memory, amplifier circuit, counter, gate circuit, time-to-digital converter, etc. Additionally, the circuits may include a DC-to-DC converter and other power management integrated circuits. The circuit can transmit a signal to the single-photon avalanche diode (1) or receive a signal from the single-photon avalanche diode (1).

[0271] A connection layer (300) may be provided on the front surface (100a) of a single-photon avalanche diode (1). The connection layer (300) may include an insulating layer (306), an output conduction line (303a), a bias conduction line (303b), and a vertical connection (304). For example, the insulating layer (306) may include silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), or a combination thereof. For example, the vertical connection (304) may include a contact or a via.

[0272] The output conduction line (303a) may be electrically connected to the first high-concentration doping region (140). The output conduction line (303a) may include an electrically conductive material. For example, the output conduction line (303a) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The output conduction line (303a) may electrically connect the first high-concentration doping region (140) and the circuit contained in the single-photon avalanche diode (1). For example, a vertical connection (304) may be provided between the first high-concentration doping region (140) and the output conduction line (303a), and between the output conduction line (303a) and the circuit. The output conduction line (303a) may be configured to extract a detection signal from the single-photon avalanche diode (1).

[0273] The bias conduction line (303b) may be electrically connected to the first contact (121). The bias conduction line (303b) may include an electrically conductive material. For example, the bias conduction line (303b) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The bias conduction line (303b) may electrically connect the first contact (121) and the circuit contained in the single-photon avalanche diode (1). For example, a vertical connection (304) may be provided between the first contact (121) and the bias conduction line (303b) and between the bias conduction line (303b) and the circuit. The bias conduction line (303b) may be configured to apply a bias to the single-photon avalanche diode (1).

[0274] A lens portion (400) may be provided on a connecting layer (300). A lens portion (400) may be provided on the opposite side of a single-photon avalanche diode (1) with the connecting layer (300) in between. The lens portion (400) may include a lens (402). The lens (402) may focus incident light and transmit it to the single-photon avalanche diode (1). For example, the lens (402) may include a microlens, a Fresnel lens, or a metal lens. However, the type of lens (402) is not limited and may be determined as needed. In one example, the central axis of the lens (402) may be aligned with the central axis of the single-photon avalanche diode (1). The central axis of the lens (402) and the central axis of the single-photon avalanche diode (1) may be virtual axes that pass through the center of the lens (402) and the center of the single-photon avalanche diode (1), respectively, and are parallel to the stacking direction of the single-photon avalanche diode (1) and the lens (402). In one example, the central axis of the lens (402) may be aligned offset from the central axis of the single-photon avalanche diode (1). In one embodiment, the width of the lens (402) may be about half the width of the single-photon avalanche diode (1) and implemented in a 2x2 shape. In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode (1). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0276] FIG. 38 is a plan view of a single-photon detector array according to an exemplary embodiment. FIG. 39 is a cross-sectional view along the line K-K' of FIG. 38. FIG. 40 is a plan view of the output pattern, bias pattern, and shield pattern of FIG. 39. For brevity of description, substantially the same as that described with reference to FIG. 33 may not be described.

[0277] Referring to FIGS. 38 and 39, a single-photon detector array (SPA1(SPA)) may be provided. The single-photon detector array (SPA1(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD1 of FIG. 33) described with reference to FIG. 33. The buried regions (110), control layers (200), connection layers (300), and lens portions (400) of the pixels (PX) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD1 of FIG. 33) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA1(SPA)). The connecting layers (300) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA1(SPA)). The control layers (200) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the control layer (200a) of the single-photon detector array (SPA1(SPA)). The lens portions (400) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the lens portion (400a) of the single-photon detector array (SPA1(SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0278] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved.

[0279] A pair of first contacts (121) that are immediately adjacent to each other and are each included in different pixels (PX) may be configured to share a single bias pattern (302b). For example, a single bias pattern (302b) and a pair of first contacts (121) may each be electrically connected by a pair of vertical connections (304). A device isolation pattern (104) may be placed between immediately adjacent pixels (PX). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). For example, the vertical connections (304) may include contacts or vias.

[0281] FIG. 41 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 34 may not be described.

[0282] Referring to FIGS. 38 and FIGS. 41, a single-photon detector array (SPA2(SPA)) may be provided. The single-photon detector array (SPA2(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD2 of FIG. 34) described with reference to FIG. 34. The buried regions (110), connecting layers (300), and lens portions (400) of the single-photon detectors (SPD2 of FIG. 34) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD2 of FIG. 34) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA2(SPA)). The connecting layers (300) of the single-photon detectors (SPD2 in FIG. 34) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA2(SPA)). The lens portions (400) of the single-photon detectors (SPD2 in FIG. 34) can be connected to form the lens portion (400a) of the single-photon detector array (SPA2(SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0283] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved.

[0284] A pair of first contacts (121) that are immediately adjacent to each other and are each included in different pixels (PX) may be configured to share a single bias pattern (302b). For example, a single bias pattern (302b) and a pair of first contacts (121) may each be electrically connected by a pair of vertical connections (304). A device isolation pattern (104) may be placed between immediately adjacent pixels (PX). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). For example, the vertical connections (304) may include contacts or vias.

[0286] FIG. 42 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 35 may not be described.

[0287] Referring to FIGS. 38 and FIGS. 42, a single-photon detector array (SPA3(SPA)) may be provided. The single-photon detector array (SPA3(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD3 of FIG. 35) described with reference to FIGS. 35 and FIGS. The buried regions (110), connecting layers (300), and lens portions (400) of the single-photon detectors (SPD3 of FIG. 35) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD3 of FIG. 35) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA3(SPA)). The connecting layers (300) of the single-photon detectors (SPD3 in FIG. 35) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA3 (SPA)). The control layers (200) of the single-photon detectors (SPD3 in FIG. 35) can be connected to form the control layer (200a) of the single-photon detector array (SPA3 (SPA)). The lens portions (400) of the single-photon detectors (SPD3 in FIG. 35) can be connected to form the lens portion (400a) of the single-photon detector array (SPA3 (SPA)).

[0288] The lens portion (400a) may include diffraction patterns (404). The diffraction patterns (404) diffract incident light to increase the absorption length of light within the single-photon avalanche diode layer (1a). In another example, scattering patterns may be provided on the back surface (100b) of the single-photon avalanche diode layer (1a) instead of the diffraction patterns (404). The scattering patterns may be, for example, cross or X-shaped patterns. In another example, the scattering patterns may be a combined cross and X shape or a combined cross shape. The light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved by the lens portion (400). In one embodiment, at least one optical element may be inserted between the diffraction patterns (404) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer.

[0289] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved.

[0290] A pair of first contacts (121) that are immediately adjacent to each other and are each included in different pixels (PX) may be configured to share a single bias pattern (302b). For example, a single bias pattern (302b) and a pair of first contacts (121) may each be electrically connected by a pair of vertical connections (304). A device isolation pattern (104) may be placed between immediately adjacent pixels (PX). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). For example, a pair of vertical connections (304) may include contacts or vias.

[0292] FIG. 43 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 37 may not be described.

[0293] Referring to FIGS. 38 and FIGS. 43, a single-photon detector array (SPA4(SPA)) may be provided. The single-photon detector array (SPA4(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD4 of FIG. 37) described with reference to FIG. 37. The buried regions (110), connecting layers (300), and lens portions (400) of the single-photon detectors (SPD4 of FIG. 37) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD4 of FIG. 37) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA4(SPA)). The connecting layers (300) of the single-photon detectors (SPD4 of FIG. 37) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA4 (SPA)). The control layers (200) of the single-photon detectors (SPD4 of FIG. 37) can be connected to form the control layer (200a) of the single-photon detector array (SPA4 (SPA)). The lens portions (400) of the single-photon detectors (SPD4 of FIG. 37) can be connected to form the lens portion (400a) of the single-photon detector array (SPA4 (SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0294] The connecting layer (300) may include an insulating layer (306), an output conductive line (303a), a bias conductive line (303b), and a vertical connecting portion (304). The vertical connecting portion (304) may include a contact or a via. For example, the insulating layer (306) may include silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), or a combination thereof. Since the single-photon detector array (SPA4(SPA)) of the present disclosure is configured so that light is incident on the front surface (100a), the incident light may pass through the lens portion (400a) and the connecting layer (300a) in sequence to reach the single-photon avalanche diode layer (1a). Accordingly, unlike the single-photon detector arrays (SPA1, SPA2, SPA3) shown in FIG. 39, 41, and 42, output conduction lines (303a) and bias conduction lines (303b) may be included instead of output pattern (302a), bias pattern (302b), and shield pattern (302c) so as not to hinder incident light from reaching the single-photon avalanche diode layer (1a).

[0295] The output conduction line (303a) may be electrically connected to the first high-concentration doping region (140). The output conduction line (303a) may include an electrically conductive material. For example, the output conduction line (303a) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The output conduction line (303a) may electrically connect the first high-concentration doping region (140) and the circuit contained in the single-photon avalanche diode layer (1a). For example, a connecting portion (340) may be provided between the first high-concentration doping region (140) and the output conduction line (303a), and between the output conduction line (303a) and the circuit. The output conduction line (303a) may be configured to extract a detection signal from the single-photon avalanche diode layer (1a).

[0296] The bias conduction line (303b) may be electrically connected to the first contact (121). The bias conduction line (303b) may include an electrically conductive material. For example, the bias conduction line (303b) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The bias conduction line (303b) may electrically connect the first contact (121) and the circuit contained in the single-photon avalanche diode layer (1a). For example, a vertical connection (340) may be provided between the first contact (121) and the bias conduction line (303b) and between the bias conduction line (303b) and the circuit. The bias conduction line (303b) may be configured to apply a bias to the single-photon avalanche diode layer (1a).

[0297] A pair of first contacts (121) that are immediately adjacent to each other and are each included in different pixels (PX) may be configured to share a single bias pattern (302b). For example, a single bias pattern (302b) and a pair of first contacts (121) may each be electrically connected by a pair of vertical connections (340). A device isolation pattern (104) may be placed between immediately adjacent pixels (PX). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI).

[0299] FIG. 44 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 33 may not be described.

[0300] Referring to FIGS. 38 and FIGS. 44, a single-photon detector array (SPA5(SPA)) may be provided. The single-photon detector array (SPA5(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD1 of FIG. 33) described with reference to FIG. 33. The buried regions (110), control layers (200), connection layers (300), and lens portions (400) of the pixels (PX) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD1 of FIG. 33) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA5(SPA)). The connecting layers (300) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA5 (SPA)). The control layers (200) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the control layer (200a) of the single-photon detector array (SPA5 (SPA)). The lens portions (400) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the lens portion (400a) of the single-photon detector array (SPA5 (SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0301] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved. A pair of first contacts (121) that are each included in different pixels (PX) and are immediately adjacent to each other may be configured to share a single bias pattern (302b). For example, one bias pattern (302b) and a pair of first contacts (121) can each be electrically connected by a pair of vertical connections (340). The vertical connections (304) may include contacts or vias.

[0302] A device isolation pattern (104) may be placed between immediately adjacent pixels (PX). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). A vertical isolation pattern (107) may be provided between the device isolation pattern (104) and the back surface (100b). One end of the vertical isolation pattern (107) may be in direct contact with the device isolation pattern (104), and the other end may be exposed on the back surface (100b). For example, the upper surface of the vertical isolation pattern (107) may be located at substantially the same level as the back surface (100b). The vertical isolation pattern (107) may be formed by a process of filling an insulating material into a recessed area formed by etching a buried area (110). For example, the vertical isolation pattern (107) may be a Full Trench Isolation (FTI). In one embodiment, the vertical separation pattern (107) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or polysilicon or high-dielectric (high-k) materials such as hafnium oxide (HfO2), zirconium oxide (zirconia, ZrO2), and tantalum oxide (TaO).

[0304] FIG. 45 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 33 may not be described.

[0305] Referring to FIGS. 38 and FIGS. 45, a single-photon detector array (SPA6(SPA)) may be provided. The single-photon detector array (SPA6(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD1 of FIG. 33) described with reference to FIG. 33. The buried regions (110), control layers (200), connection layers (300), and lens portions (400) of the pixels (PX) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD1 of FIG. 33) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA6(SPA)). The connecting layers (300) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA6 (SPA)). The control layers (200) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the control layer (200a) of the single-photon detector array (SPA6 (SPA)). The lens portions (400) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the lens portion (400a) of the single-photon detector array (SPA6 (SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0306] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved. A pair of first contacts (121) that are each included in different pixels (PX) and are immediately adjacent to each other may be configured to share a single bias pattern (302b). For example, one bias pattern (302b) and a pair of first contacts (121) can each be electrically connected by a pair of vertical connections (340). The vertical connections (304) may include contacts or vias.

[0307] A vertical separation pattern (107) may be provided between immediately adjacent pixels (PX). One end of the vertical separation pattern (107) may be exposed on the front surface (100a), and the other end may be exposed on the back surface (100b). For example, the bottom surface and the top surface of the vertical separation pattern (107) may be located at substantially the same level as the front surface (100a) and the back surface (100b), respectively. The vertical separation pattern (107) may be formed by a process of filling an insulating material into a recessed area formed by etching a buried area (110). For example, the vertical separation pattern (107) may be a Full Trench Isolation (FTI). In one embodiment, the vertical separation pattern (107) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or polysilicon or high-dielectric (high-k) materials such as hafnium oxide (HfO2), zirconium oxide (zirconia, ZrO2), and tantalum oxide (TaO).

[0309] FIG. 46 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 33 may not be described.

[0310] Referring to FIGS. 38 and FIGS. 46, a single-photon detector array (SPA7(SPA)) may be provided. The single-photon detector array (SPA7(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD1 of FIG. 33) described with reference to FIG. 33. The buried regions (110), control layers (200), connection layers (300), and lens portions (400) of the pixels (PX) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD1 of FIG. 33) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA7(SPA)). The connecting layers (300) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA7 (SPA)). The control layers (200) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the control layer (200a) of the single-photon detector array (SPA7 (SPA)). The lens portions (400) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the lens portion (400a) of the single-photon detector array (SPA7 (SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0311] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved. A pair of first contacts (121) that are each included in different pixels (PX) and are immediately adjacent to each other may be configured to share a single bias pattern (302b). For example, one bias pattern (302b) and a pair of first contacts (121) can each be electrically connected by a pair of vertical connections (304). The vertical connections (304) may include contacts or vias.

[0312] A device isolation pattern (104) may be placed between immediately adjacent pixels (PX). For example, the device isolation pattern (104) may be a Shallow Trench Isolation (STI). A vertical isolation pattern (107) may be provided between the device isolation pattern (104) and the back surface (100b). One end of the vertical isolation pattern (107) may be placed adjacent to the device isolation pattern (104), and the other end may be exposed on the back surface (100b). The vertical isolation pattern (107) may be spaced apart from the device isolation pattern (104). The bottom surface of the vertical isolation pattern (107) may face the device isolation pattern (104). A buried area (110) may be provided between the vertical isolation pattern (107) and the device isolation pattern (104). For example, the top surface of the vertical isolation pattern (107) may be located at substantially the same level as the back surface (100b). The vertical separation pattern (107) can be formed by a process of filling an insulating material into a recessed area formed by etching a buried area (110). For example, the vertical separation pattern (107) may be a Deep Trench Isolation (DTI). For example, the vertical separation pattern (107) may be a Partial Deep Trench Isolation (DTI). In one embodiment, the vertical separation pattern (107) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or polysilicon or high-dielectric constant (high-k) materials such as hafnium oxide (HfO2), zirconium oxide (zirconia, ZrO2), and tantalum oxide (TaO).

[0314] FIG. 47 is a cross-sectional view along the line K-K' of FIG. 38. For the sake of brevity, substantially the same content as that described with reference to FIG. 33 may not be described.

[0315] Referring to FIGS. 38 and FIGS. 47, a single-photon detector array (SPA6(SPA)) may be provided. The single-photon detector array (SPA6(SPA)) may include pixels (PX) arranged in two dimensions. Each of the pixels (PX) may include a single-photon detector (SPD1 of FIG. 33) described with reference to FIG. 33. The buried regions (110), control layers (200), connection layers (300), and lens portions (400) of the pixels (PX) may be connected to each other. The single-photon avalanche diodes (1) of the single-photon detectors (SPD1 of FIG. 33) may be connected to form a single-photon avalanche diode layer (1a) of the single-photon detector array (SPA6(SPA)). The connecting layers (300) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the connecting layer (300a) of the single-photon detector array (SPA6 (SPA)). The control layers (200) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the control layer (200a) of the single-photon detector array (SPA6 (SPA)). The lens portions (400) of the single-photon detectors (SPD1 of FIG. 33) can be connected to form the lens portion (400a) of the single-photon detector array (SPA6 (SPA)). In one embodiment, at least one optical element may be inserted between the lens (402) and the single-photon avalanche diode layer (1a). For example, the optical element may be a color filter, a bandpass filter, a metal grid, an air grid, a grid based on a low refractive index material, an anti-reflection coating, a 2D nanomaterial layer, or an organic material layer. In one example, the anti-reflection coating may be formed on the top of the lens (402).

[0316] The connection layer (300) may include an output pattern (302a), a bias pattern (302b), and a shield pattern (302c). The output pattern (302a), the bias pattern (302b), and the shield pattern (302c) may serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode layer (1a) may be reflected by the output pattern (302a), the bias pattern (302b), and the shield pattern (302c) and may be incident back on the single-photon avalanche diode layer (1a). Accordingly, the light absorption efficiency of the single-photon avalanche diode layer (1a) may be improved. A pair of first contacts (121) that are each included in different pixels (PX) and are immediately adjacent to each other may be configured to share a single bias pattern (302b). For example, one bias pattern (302b) and a pair of first contacts (121) can each be electrically connected by a pair of vertical connections (304). The vertical connections (304) may include contacts or vias.

[0317] A vertical separation pattern (107) may be provided between immediately adjacent pixels (PX). One end of the vertical separation pattern (107) may be spaced apart from the front surface (100a). A buried area (110) may be provided between one end of the vertical separation pattern (107) and the connection layer (300a). The other end of the vertical separation pattern (107) may be exposed on the rear surface (100b). For example, the upper surface of the vertical separation pattern (107) may be located at substantially the same level as the rear surface (100b). The vertical separation pattern (107) may be formed by a process of filling an insulating material into a recessed area formed by etching the buried area (110). For example, the vertical separation pattern (107) may be a Deep Trench Isolation (DTI). For example, the vertical separation pattern (107) may be a Partial Deep Trench Isolation (Partial DTI). In one embodiment, the vertical separation pattern (107) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or polysilicon or high-dielectric (high-k) materials such as hafnium oxide (HfO2), zirconium oxide (zirconia, ZrO2), and tantalum oxide (TaO).

[0319] FIG. 48 is a block diagram illustrating an electronic device according to an exemplary embodiment.

[0320] Referring to FIG. 48, an electronic device (2000) may be provided. The electronic device (2000) may irradiate light toward a subject (not shown) and detect light reflected by the subject and returning to the electronic device (2000). The electronic device (2000) may include a beam steering device (2010). The beam steering device (2010) may control the direction of irradiation of light emitted outside the electronic device (2000). The beam steering device (2010) may be a mechanical or non-mechanical (semiconductor) beam steering device. The electronic device (2000) may include a light source unit within the beam steering device (2010) or include a light source unit provided separately from the beam steering device (2010). The beam steering device (2010) may be a scanning type light emitting device. However, the light-emitting device of the electronic device (2000) is not limited to the beam steering device (2010). In other examples, the electronic device (2000) may include a flash-type light-emitting device instead of or together with the beam steering device (2010). The flash-type light-emitting device can irradiate light at once to an area that includes the entire field of view without a scanning process.

[0321] Light steered by the beam steering device (2010) can be reflected by a subject and return to the electronic device (2000). The electronic device (2000) may include a detection unit (2030) for detecting light reflected by a subject. The detection unit (2030) may include a plurality of light detection elements and may further include other optical members. The plurality of light detection elements may include any one of the single-photon avalanche diodes (1000 to 1900) described above. Additionally, the electronic device (2000) may further include a circuit unit (2020) connected to at least one of the beam steering device (2010) and the detection unit (2030). The circuit unit (2020) may include a calculation unit that acquires and calculates data, and may further include a driving unit and a control unit, etc. Additionally, the circuit unit (2020) may further include a power supply unit and a memory, etc.

[0322] Although the electronic device (2000) is illustrated as including a beam steering device (2010) and a detector (2030) within a single device, the beam steering device (2010) and the detector (2030) may not be provided as a single device but may be provided separately in different devices. Additionally, the circuit unit (2020) may not be connected to the beam steering device (2010) or the detector (2030) via a wired connection but may be connected via wireless communication.

[0323] The electronic device (2000) according to the embodiment described above can be applied to various electronic devices. For example, the electronic device (2000) can be applied to a Light Detection And Ranging (LiDAR) device. The LiDAR device may be a phase-shift type or a time-of-flight (TOF) type device. In addition, the single-photon avalanche diodes (1000 to 1900) according to the embodiment or the electronic device (2000) including them can be mounted on electronic devices such as smartphones, wearable devices (such as glasses-type devices for implementing augmented reality and virtual reality), Internet of Things (IoT) devices, home appliances, tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), navigation systems, drones, robots, unmanned vehicles, autonomous vehicles, Advanced Driver Assistance Systems (ADAS), etc.

[0325] FIGS. 49 and FIGS. 50 are conceptual diagrams showing a case where a LiDAR device according to an exemplary embodiment is applied to a vehicle.

[0326] Referring to FIGS. 49 and 50, a LiDAR device (3010) may be applied to a vehicle (3000). Information about a subject (4000) may be obtained using the LiDAR device (3010) applied to the vehicle. The vehicle (3000) may be an automobile with autonomous driving capabilities. The LiDAR device (3010) can detect objects or people, i.e., subjects (4000), in the direction in which the vehicle (3000) is traveling. The LiDAR device (3010) can measure the distance to the subject (4000) by using information such as the time difference between a transmitted signal and a detected signal. The LiDAR device (3010) can obtain information about nearby subjects (4010) and distant subjects (4020) within the scan range. The LiDAR device (3010) may include an electronic device (2000) described with reference to FIG. 48. Although the LiDAR device (3010) is depicted as being positioned at the front of the vehicle (3000) to detect a subject (4000) in the direction in which the vehicle (3000) is traveling, this is not limited thereto. In other examples, the LiDAR device (3010) may be positioned at multiple locations on the vehicle (3000) to detect all subjects (4000) around the vehicle (3000). For example, four LiDAR devices (3010) may be positioned at the front, rear, and both sides of the vehicle (3000), respectively. In another example, a LiDAR device (3010) is positioned on the roof of a vehicle (3000) and rotates to detect all objects (4000) around the vehicle (3000).

[0328] FIG. 51 is a cross-sectional view of a single-photon detector according to an exemplary embodiment. For the sake of brevity, substantially the same details as those described with reference to FIG. 1 and FIG. 2 may not be described.

[0329] Referring to FIG. 51, a single-photon detector (SPD5) may be provided. The single-photon detector (SPD5) may include a single-photon avalanche diode (1), a control layer (200), a connection layer (300), and a lens portion (400). The single-photon detector (SPD5) may be a back-side illumination (BSI) type image sensor. The front side may be the surface where various semiconductor processes are performed during the manufacturing of the single-photon avalanche diode (1), and the back side may be the surface positioned opposite the front side. For example, the top surface and bottom surface of the single-photon avalanche diodes (1000 to 1900) of the present disclosure may be the front side (100a) and the back side (100b), respectively. The back-side illumination method may refer to light being incident on the back side (100b) of the single-photon avalanche diode (1). The front illumination method described below may refer to light being incident on the front of the single-photon avalanche diode (1). The single-photon avalanche diode (1) may be substantially the same as the single-photon avalanche diode (1000) described with reference to FIGS. 1 and FIGS. 2. However, this is exemplary. In other examples, the single-photon avalanche diode (1) may be any one of the single-photon avalanche diodes (1100 to 1900) described above. For convenience of explanation, the single-photon avalanche diode (1) is shown as having its top and bottom reversed compared to the single-photon avalanche diode (1000) shown in FIG. 2. Accordingly, the top surface and bottom surface of the single-photon avalanche diode (1) may be the rear surface (100b) and the front surface (100a), respectively.

[0330] A control layer (200) may be provided on the front surface of a single-photon avalanche diode (1). The control layer (200) may include circuits necessary for the operation of the single-photon avalanche diode (1). For example, the control layer (200) may be a chip on which circuits are formed. The circuits may be implemented by various electronic components as needed. The circuits may include a quenching resistor (or quenching circuit) and a pixel circuit. The quenching resistor (or quenching circuit) may be configured to interrupt the avalanche effect and allow the single-photon avalanche diode (1) to detect another photon. The pixel circuits may be composed of a reset or recharge circuit, memory, amplifier circuit, counter, gate circuit, time-to-digital converter, etc. Additionally, the circuit may include a DC-to-DC converter and other power management integrated circuits. The circuit may transmit a signal to a single-photon avalanche diode (1) or receive a signal from a single-photon avalanche diode (1).

[0331] A connection layer (300) may be provided between a single-photon avalanche diode (1) and a control layer (200). The connection layer (300) may include an insulating layer (306), an output pattern (302a), a bias pattern (302b), a shield pattern (302c), and a vertical connection (304). For example, the insulating layer (306) may include silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), or a combination thereof. For example, the vertical connection (304) may include a contact or a via.

[0332] The output pattern (302a) may be electrically connected to the first high-concentration doping region (140). The output pattern (302a) may include an electrically conductive material. For example, the output pattern (302a) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The output pattern (302a) may electrically connect the circuit of the first high-concentration doping region (140) and the control layer (200). For example, a vertical connection (304) may be provided between the first high-concentration doping region (140) and the output pattern (302a), and a Cu-Cu bonding may be provided between the output pattern (302a) and the control layer (200). The output pattern (302a) may be configured to extract a detection signal from the single-photon avalanche diode (1).

[0333] The bias pattern (302b) may be electrically connected to the first contact (121). The bias pattern (302b) may include an electrically conductive material. For example, the bias pattern (302b) may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof. The bias pattern (302b) may electrically connect the circuit of the first contact (121) and the control layer (200). For example, a vertical connection (304) may be provided between the first contact (121) and the bias pattern (302b), and a Cu-Cu bonding may be provided between the bias pattern (302b) and the control layer (200). The bias pattern (302b) may be configured to apply a bias to the single-photon avalanche diode (1).

[0334] The shield pattern (302c) can electrically shield between the output pattern (302a) and the bias pattern (302b). For example, the shield pattern (302c) can be configured so that the detection signal extracted by the output pattern (302a) is not affected by the bias signal applied to the bias pattern (302b).

[0335] The output pattern (302a), bias pattern (302b), and shield pattern (302c) can serve as a reflective layer. Light that is not absorbed by the single-photon avalanche diode (1) can be reflected by the output pattern (302a), bias pattern (302b), and shield pattern (302c) and then incident back on the single-photon avalanche diode (1). Accordingly, the light absorption efficiency of the single-photon avalanche diode (1) can be improved.

[0336] Second diffraction patterns (108) may be provided on the back surface (100b) of the single-photon avalanche diode (1). For example, the second diffraction patterns (108) may be formed by etching the back surface (100b) of the single-photon avalanche diode (1). The second diffraction patterns (108) may diffract incident light to increase the absorption length of light within the single-photon avalanche diode (1). In another example, scattering patterns may be formed on the back surface (100b) of the single-photon avalanche diode (1) instead of the second diffraction patterns (108). The scattering patterns may be formed by etching the back surface (100b) of the single-photon avalanche diode (1). The scattering patterns may be, for example, cross or X-shaped patterns. In another example, the scattering patterns may be in the form of a cross and an X combined, or in the form of each connected.

[0337] A lens portion (400) may be provided on the rear surface (100b) of a single-photon avalanche diode (1). The lens portion (400) may cover the second diffraction patterns (108). The lens portion (400) may include a lens (402). The lens (402) may focus incident light and transmit it to the single-photon avalanche diode (1). For example, the lens (402) may include a microlens, a Fresnel lens, or a metallens. However, the type of lens (402) is not limited and may be determined ...

Claims

Claim 1 A single-photon detector comprising: a high-concentration doping region having a first conductivity type; a buried region provided on the high-concentration doping region and having a second conductivity type different from the first conductivity type; a first well provided between the high-concentration doping region and the buried region and having the second conductivity type; a second well provided between the high-concentration doping region and the first well and having the second conductivity type; and a contact electrically connected to the buried region and having the second conductivity type, and having a first surface and a second surface facing each other; and a connection layer provided on the first surface, comprising an output pattern electrically connected to the high-concentration doping region and configured to reflect light transmitted through the single-photon avalanche diode, and a bias pattern electrically connected to the contact and configured to reflect light transmitted through the single-photon avalanche diode. Claim 2 In claim 1, the end of the high-concentration doping region is a single-photon detector protruding from the side of the second well. Claim 3 In claim 2, the first well extends laterally over the second well and is a single-photon detector in contact with the end of the high-concentration doping region. Claim 4 In claim 1, the single-photon avalanche diode further comprises a guard ring provided on the side of the high-concentration doping region, having the first conductivity type and having a doping concentration lower than that of the high-concentration doping region, and a single-photon detector. Claim 5 In claim 4, the first well is a single-photon detector extending into the region between the guard ring and the second well. Claim 6 In claim 4, a single-photon detector in which the side of the first well is exposed on the guard ring. Claim 7 In claim 4, the buried area is a single-photon detector extending between the guard ring and the contact. Claim 8 In claim 1, the single-photon avalanche diode further comprises a single-photon detector having a low-concentration doping region provided between the second well and the high-concentration doping region and having the second conductivity type. Claim 9 In claim 8, the single-photon avalanche diode further comprises a guard ring extending from the side of the high-concentration doping region onto the side of the second well, having the first conductivity type and having a doping concentration lower than that of the high-concentration doping region, a single-photon detector. Claim 10 In claim 8, the single-photon avalanche diode further comprises a relaxation region provided between the first well and the contact, having the second conductivity type and having a lower doping concentration than the contact; a single-photon detector. Claim 11 In claim 4, the first well is a single-photon detector extending between the guard ring and the contact. Claim 12 In claim 1, the output pattern and the bias pattern are a single-photon detector spaced apart from each other along a direction parallel to the first plane. Claim 13 A single-photon detector according to claim 1, further comprising a shield pattern provided between the output pattern and the bias pattern and configured to reflect light transmitted through the single-photon avalanche diode. Claim 14 In claim 13, the shield pattern, the output pattern, and the bias pattern are spaced apart from each other along a direction parallel to the first plane in a single-photon detector. Claim 15 A single-photon detector according to claim 1, wherein the single-photon avalanche diode further comprises a relaxation region provided between the buried region and the contact, having the first conductivity type and having a lower doping concentration than the contact. Claim 16 In claim 15, the single-photon avalanche diode further comprises an additional relaxation region provided between the buried region and the relaxation region, extending along a direction perpendicular to the first plane and having the second conductivity type, in a single-photon detector. Claim 17 In claim 1, the first well extends along the side of the second well and contacts the high-concentration doping region, and the end of the high-concentration doping region protrudes from the side of the first well, forming a single-photon detector. Claim 18 A single-photon detector according to claim 1, further comprising a lens provided on the second surface and configured to collect incident light and transmit it to the single-photon avalanche diode. Claim 19 A single-photon detector according to claim 1, further comprising diffraction patterns provided on the second surface and diffracting incident light to increase the absorption length of light within the single-photon avalanche diode. Claim 20 A single-photon detector according to claim 1, further comprising a control layer provided on the opposite side of the single-photon avalanche diode with respect to the connection layer, and including a circuit required for the operation of the single-photon avalanche diode.

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