Synaptic device, light sesnsing device including the same, electronic device including the same, and manufacturing method of the same

Abstract

The present invention relates to a synapse device comprising: a substrate including a gate electrode; a gate insulating layer disposed on the substrate; a first channel layer disposed on the gate insulating layer; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; and a second channel layer disposed between the first electrode and the second electrode on the first channel layer, wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated to the synapse device is disposed at the interface between the first channel layer and the second channel layer.

Description

Technology Field

[0001] The present invention relates to a synapse element, a photodetector element including the same, an electronic device including the same, and a method for manufacturing the same. Background Technology

[0002] With the advent of the Big Data era, the volume of information processed has increased exponentially, yet the computing technology required to handle it has reached its physical limits. Moore's Law has come to an end, and conventional Von Neumann-based digital computing—composed of a Central Processing Unit (CPU) for computation and memory for information storage—is still used in most designs today due to its advantage of enabling the execution of various programs solely through software replacement without the need for hardware rearrangement. However, because the computation and storage units exist structurally separated, bottlenecks occur when processing large amounts of information, leading to significant power consumption. Neuromorphic computing technology emerged as a breakthrough in this situation of limitations. Neuromorphic computing is a technology that implements the computational methods of the human brain, known as the most efficient system in existence, using both hardware and software. The human brain is composed of a super-parallel structure consisting of approximately 100 billion neurons and 100 trillion synapses connecting them, enabling it to process massive amounts of information efficiently and rapidly.

[0003] Accordingly, the inventor of this institute has developed technology for a next-generation smart sensor equipped with both light sensing and processing functions by integrating neuromorphic technology into an optical sensor.

[0004] The technology forming the background of this application is disclosed in Korean Patent Publication No. 10-1940669. The problem to be solved

[0005] The present invention aims to solve the problems of the aforementioned prior art by providing a synapse device capable of remembering and processing detection results and delaying a photocurrent signal by mimicking artificial sensory functions, and a method for manufacturing the same.

[0006] In addition, the present invention aims to provide a semiconductor device capable of inducing strengthening and inhibitory responses of synapses through optical and electrical stimulation, and a method for manufacturing the same.

[0007] However, the technical problems that the embodiments of the present invention aim to solve are not limited to those described above, and other technical problems may exist. means of solving the problem

[0008] As a technical means for achieving the above-mentioned technical problem, a synapse element according to the first aspect of the present invention comprises: a substrate including a gate electrode; a gate insulating layer disposed on the substrate; a first channel layer disposed on the gate insulating layer; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; and a second channel layer disposed between the first electrode and the second electrode on the first channel layer; wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is disposed at the interface between the first channel layer and the second channel layer.

[0009] In addition, the first channel layer is provided to absorb light of a first absorption wavelength, and the second channel layer is provided to absorb light of a second absorption wavelength.

[0010] In addition, when light of the first absorption wavelength is irradiated onto the synapse element, electrons excited in the first channel layer are trapped at the interface between the first channel layer and the second channel layer, and even after the irradiation of light of the first absorption wavelength is stopped, a signal delay of the current flowing through the synapse element is induced by the attraction between the trapped electrons and the holes in either of the channel layers, thereby enabling the mimicry of a synapse function.

[0011] In addition, if the first channel layer additionally absorbs light of the second absorption wavelength, it may be provided to absorb less than the second channel layer.

[0012] In addition, when light of the second absorption wavelength is irradiated onto the synapse element, holes excited in the second channel layer are trapped at the interface between the first channel layer and the second channel layer, and even after the irradiation of light of the second absorption wavelength is stopped, signal delay of the current flowing through the synapse element is induced by the repulsion between the trapped holes and the holes in the first channel layer, thereby enabling the mimicry of a synapse function.

[0013] Additionally, the first channel layer is formed of a material selected from the group consisting of a Si:H, Si, SiO2, and combinations thereof, and the second channel layer is formed of a material selected from the group consisting of Ga2O3, TiO2, ZnO, SnO2, In2O3, SiO2, NiO, MgO, WO3, Al2O3, CuO, MnO2, TaO3, V2O5, MoO2, Nb2O3, and combinations thereof, wherein the first channel layer and the second channel layer are formed of different materials.

[0014] In addition, the Ga2O3 included in the second channel layer comprises a phase selected from the group consisting of α phase, β phase, γ phase, δ phase, ε phase, and combinations thereof.

[0015] In addition, when a gate voltage is applied to the synapse element, the interface between the first channel layer and the gate insulating layer acquires a positive or negative interface charge, and even after the application of the gate voltage is stopped, a signal delay of the current flowing through the synapse element is induced by the repulsion between the positive interface charge and the hole in the first channel layer, or by the attraction between the negative interface charge and the hole in the first channel layer, thereby enabling the mimicry of a synapse function.

[0016] Additionally, a synapse element according to the second aspect of the present invention comprises: a substrate; a second channel layer disposed on the substrate; a first channel layer disposed on the second channel layer; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; a gate insulating layer disposed between the first electrode and the second electrode on the first channel layer; and a gate electrode disposed on the gate insulating layer; wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is disposed at the interface between the first channel layer and the second channel layer.

[0017] In addition, the photodetector according to the third aspect of the present invention includes a synapse element according to the first aspect or the second aspect.

[0018] Additionally, the electronic device according to the fourth aspect of the present invention includes a synapse element according to the first aspect or the second aspect.

[0019] In addition, the electronic device comprises a component selected from the group consisting of semiconductor devices, image sensors, vision sensors, and combinations thereof.

[0020] Additionally, the fifth aspect of the present invention is a method for manufacturing a synapse element according to the first aspect, comprising: a step of placing a gate insulating layer on a substrate including a gate electrode; a step of placing a first channel layer on the gate insulating layer; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; and a step of placing a second channel layer between the first electrode and the second electrode on the first channel layer; wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is placed at the interface between the first channel layer and the second channel layer.

[0021] Additionally, the sixth aspect of the present invention is a method for manufacturing a synapse element according to the second aspect, comprising: a step of placing a second channel layer on a substrate; a step of placing a first channel layer on the second channel layer; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; a step of placing a gate insulating layer between the first electrode and the second electrode on the first channel layer; and a step of placing a gate electrode on the gate insulating layer; wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is placed at the interface between the first channel layer and the second channel layer.

[0022] Additionally, a synapse element according to the seventh aspect of the present invention comprises: a substrate including a gate electrode; a gate insulating layer disposed on the substrate; a first channel layer disposed on the gate insulating layer; and a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is disposed at the interface between the first channel layer and the gate insulating layer.

[0023] In addition, the first channel layer comprises a material selected from the group consisting of Si:H, Si, SiO2, and combinations thereof.

[0024] In addition, the synapse element further includes a second channel layer disposed between the first electrode and the second electrode on the first channel layer.

[0025] Additionally, a synapse element according to the eighth aspect of the present invention comprises: a substrate; a first channel layer disposed on the substrate; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; a gate insulating layer disposed between the first electrode and the second electrode on the first channel layer; and a gate electrode disposed on the gate insulating layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is disposed at the interface between the first channel layer and the gate insulating layer.

[0026] In addition, the synapse element further includes a second channel layer disposed on the substrate, and the first channel layer is disposed on the second channel layer.

[0027] Additionally, the ninth aspect of the present invention is a method for manufacturing a synapse device according to the seventh aspect, comprising the steps of: placing a gate insulating layer on a substrate including a gate electrode; placing a first channel layer on the gate insulating layer; and placing a first electrode and a second electrode spaced apart from each other on the first channel layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is placed at the interface between the first channel layer and the gate insulating layer.

[0028] In addition, the method for manufacturing the synapse device further includes the step of placing a second channel layer between the first electrode and the second electrode on the first channel layer.

[0029] Additionally, the tenth aspect of the present invention is a method for manufacturing a synapse device according to the eighth aspect, comprising: a step of placing a first channel layer on a substrate; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; a step of placing a gate insulating layer between the first electrode and the second electrode on the first channel layer; and a step of placing a gate electrode on the gate insulating layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is placed at the interface between the first channel layer and the gate insulating layer.

[0030] In addition, the step of placing a first channel layer on the substrate of the method for manufacturing the synapse device further includes the step of placing a second channel layer on the substrate; and the step of placing a first channel layer on the second channel layer.

[0031] The means for solving the problem described above are merely exemplary and should not be interpreted as intended to limit the present invention. In addition to the exemplary embodiments described above, additional embodiments may exist in the drawings and the detailed description of the invention. Effects of the invention

[0032] In the case of conventional digital computing-based optical sensors, the immediate correspondence of the detection response (photocurrent) with the input optical signal was advantageous for information processing; however, for neuromorphic sensors, the ability to store and process detection results is important.

[0033] According to the means for solving the problem of the present invention described above, the synapse device according to the present invention separates the regions that absorb light by wavelength by stacking two or more different semiconductor channel layers, and can mimic the synapse function because a signal delay of current can occur when a charge generated by light stimulation or gate voltage stimulation is trapped at the interface between the channel layers.

[0034] In addition, the synapse device according to the present invention can contribute to the development of smart sensor technology capable of overcoming the computing limitations of conventional digital CMOS image sensors.

[0035] In addition, the synapse device according to the present invention realizes the implementation of a low-power, high-performance image sensor compatible with human biological motion, can serve as a medical and technological alternative for people with visual impairments, and can contribute to the implementation of an artificial smart wide-spectrum vision sensor that expands and complements the human visual range limited to the visible light region.

[0036] However, the effects obtainable from this invention are not limited to those described above, and other effects may exist. Brief explanation of the drawing

[0037] FIGS. 1a and FIGS. 1b are schematic diagrams of a synapse element according to one embodiment of the present invention. FIGS. 2a and 2b are schematic diagrams of a synapse element according to one embodiment of the present invention. FIGS. 3a and 3b are schematic diagrams illustrating the operation of a synapse element according to one embodiment of the present invention. FIGS. 4a and 4b are schematic diagrams illustrating the operation of a synapse element according to one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating the operation method of a synapse element according to one embodiment of the present invention. FIGS. 6a and 6b are schematic diagrams illustrating the operation of a synapse element according to one embodiment of the present invention. FIG. 7 is a schematic diagram of an electronic device (synapse element) according to one embodiment of the present invention. FIG. 8 is a schematic diagram of a synapse device according to one embodiment of the present invention and an enlarged view of a part thereof. FIG. 9a is a graph of drain current according to a change in gate voltage of a synapse device according to one embodiment of the present invention, and FIG. 9b is a graph of drain current according to a change in drain voltage. FIG. 10a is a transmission spectrum of a synapse device according to one embodiment of the present invention, FIG. 10b is for the extraction of the optical bandgap of a channel layer obtained through a Tauc plot of the transmission spectrum, and FIG. 10c is a graph showing the light absorption of the first channel layer and the second channel layer according to wavelength. FIG. 11 illustrates the current characteristics of a synapse element according to one embodiment of the present invention. FIG. 12a shows the sweeping delay time between two consecutive measurement points in a synapse device according to one embodiment of the present invention, FIG. 12b shows the gate voltage sweeping range, and FIG. 12c shows the charge trapping effect in the synapse device by applying a pulse. Figures 13 (a) to (f) show the relationship between the photoelectric response characteristics and time dependence of a synapse device according to the present invention. Figures 14 (a) to (f) show current modulation and weight modulation characteristics according to the photoelectric response characteristic conditions of a synapse device according to the present invention. Figures 15 (a) to (j) relate to the spike-timing-dependent plasticity (STDP) of a synapse device according to the present invention, depending on the spike stimulation conditions and spike timing. FIG. 16a shows a simulation of the optic nerve of a zebrafish, FIG. 16b shows the phototactic behavior pattern of the zebrafish, and FIG. 16c shows the result of mimicking the behavior of the zebrafish through a synapse element according to one embodiment of the present invention. FIG. 17a is a schematic diagram showing the pulse conditions of a synapse device according to one embodiment of the present invention, FIG. 17b shows the change in conductivity of the synapse device as a function of the number of pulses, FIG. 17c is a graph showing the normalized G for the number of pulses to extract nonlinearity, FIG. 17d compares the nonlinearity and asymmetry for optical and electrical stimulation, and FIG. 17e is for a CNN model trained using the synapse device. FIGS. 18a and 18b are schematic diagrams illustrating the operation of the first channel layer and the second channel layer of a synapse device. FIGS. 19a and FIGS. 19b are schematic diagrams illustrating the operation of the first channel layer and the second channel layer of a synapse device. Specific details for implementing the invention

[0038] Below, embodiments of the present invention are described in detail with reference to the attached drawings so that those skilled in the art can easily implement them.

[0039] However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the description have been omitted, and similar parts throughout the specification have been given similar reference numerals.

[0040] Throughout this specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "electrically connected" with other elements interposed between them.

[0041] Throughout the entire specification, when a component is described as being located "on," "on top," "on top," "under," "on bottom," or "on bottom" of another component, this includes not only cases where the component is in contact with the other component but also cases where another component exists between the two components.

[0042] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0043] Hereinafter, a synapse element according to one embodiment of the present invention, a UV detection element including the same, an electronic device including the same, and a method for manufacturing the same will be described.

[0044] As a technical means for achieving the above-mentioned technical problem, a synapse element according to the first aspect of the present invention comprises: a substrate including a gate electrode; a gate insulating layer disposed on the substrate; a first channel layer disposed on the gate insulating layer; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; and a second channel layer disposed between the first electrode and the second electrode on the first channel layer; wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is disposed at the interface between the first channel layer and the second channel layer.

[0045] Additionally, a synapse element according to the second aspect of the present invention comprises: a substrate; a second channel layer disposed on the substrate; a first channel layer disposed on the second channel layer; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; a gate insulating layer disposed between the first electrode and the second electrode on the first channel layer; and a gate electrode disposed on the gate insulating layer; wherein the first channel layer and the second channel layer are provided such that an interface charge that induces a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is disposed at the interface between the first channel layer and the second channel layer.

[0046] The synapse element according to the first aspect and the synapse element according to the second aspect may operate with the same mechanism, even though the position of the gate insulating layer is different.

[0047] Additionally, a synapse element according to the seventh aspect of the present invention comprises: a substrate including a gate electrode; a gate insulating layer disposed on the substrate; a first channel layer disposed on the gate insulating layer; and a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is disposed at the interface between the first channel layer and the gate insulating layer.

[0048] Additionally, a synapse element according to the eighth aspect of the present invention comprises: a substrate; a first channel layer disposed on the substrate; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; a gate insulating layer disposed between the first electrode and the second electrode on the first channel layer; and a gate electrode disposed on the gate insulating layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is disposed at the interface between the first channel layer and the gate insulating layer.

[0049] At this time, the synapse element according to the seventh aspect may additionally include a second channel layer disposed between the first electrode and the second electrode on the first channel layer, and the synapse element according to the eighth aspect may additionally include a second channel layer disposed on the substrate, but is not limited thereto. If the synapse element according to the eighth aspect additionally includes a second channel layer, the first channel layer is disposed on the second channel layer.

[0050] The synapse device according to the present invention has the characteristic of being able to mimic synaptic function in an optical stimulation mode and an electrical stimulation mode (gate voltage), and is capable of implementing synaptic strengthening (current increase) and inhibition (current decrease) functions in both optical and electrical stimulation modes.

[0051] FIGS. 1a, FIGS. 1b, FIGS. 2a, and FIGS. 2b are schematic diagrams of a synapse device according to one embodiment of the present invention. Specifically, FIGS. 1a and FIGS. 1b are schematic diagrams of a synapse device according to the first aspect, FIGS. 2a and FIGS. 2b are schematic diagrams of a synapse device according to the second aspect, and in FIGS. 1a to 2b, the source electrode may be referred to as the first electrode, and the drain electrode may be referred to as the second electrode. Furthermore, even if a portion of the first channel layer is etched as in FIGS. 1b and FIGS. 2b, the operating mechanism of the synapse device is the same.

[0052] With reference to FIG. 1a and FIG. 1b, the thickness of a portion of the first channel layer located at the bottom between the source electrode and the drain electrode may be thinner than the thickness of the channel layer bonded to the source electrode and the drain electrode. With reference to FIG. 1b, the thickness t1 of the first channel layer below the source electrode and the drain electrode may be greater than the thickness t2 of the first channel layer below the region between the source electrode and the drain electrode.

[0053] According to one embodiment of the present invention, the gap (L) between the first electrode and the second electrode c ) may be 1 nm to 10 nm, and t1 and t2 may each independently be 1 nm to 5 μm, and the gap (L) between the first electrode and the second channel layer g ) may be 0 mm to 3 mm, but is not limited thereto.

[0054] In addition, with respect to FIG. 2a and FIG. 2b, the device structure may include a structure in which a source electrode and a drain electrode are disposed on a first channel layer on which a gate electrode and a gate insulating layer are disposed, and the gate insulating layer is disposed between the source electrode and the drain electrode. Also in FIG. 2b, the thickness t1 of the first channel layer below the source electrode and the drain electrode may be greater than the thickness t2 of the first channel layer below the region between the source electrode and the drain electrode.

[0055] In relation to FIGS. 1a to 2b, the substrate of the synapse device may also be utilized as a gate electrode as needed. Additionally, to achieve a suitable driving mode (e.g., depletion mode or enhancement mode) according to the purpose of use of the synapse device, some or all regions of the first channel layer may be doped to provide semi-insulating properties.

[0056] Additionally, the first channel layer is formed of a material selected from the group consisting of a Si:H, Si, SiO2, and combinations thereof, and the second channel layer is formed of a material selected from the group consisting of Ga2O3, TiO2, ZnO, SnO2, In2O3, SiO2, NiO, MgO, WO3, Al2O3, CuO, MnO2, TaO3, V2O5, MoO2, Nb2O3, and combinations thereof, wherein the first channel layer and the second channel layer are formed of different materials.

[0057] As will be described later, the first channel layer may be formed to absorb light of a longer wavelength than the second channel layer.

[0058] In addition, the Ga2O3 included in the second channel layer comprises a phase selected from the group consisting of α phase, β phase, γ phase, δ phase, ε phase, and combinations thereof.

[0059] Preferably, the first channel layer may include a-Si:H and the second channel layer may include α-Ga2O3, but is not limited thereto.

[0060] The above-mentioned first channel layer may be doped in a portion of the vertical depth direction over the entire area of ​​the layer, or only in a portion of the lower part of the two electrodes in contact with the first electrode (source electrode) and the second electrode (drain electrode) to ensure conductivity and improve contact resistance, but is not limited thereto.

[0061] When the second channel layer is gallium oxide, it may be amorphous, polycrystalline, or single-crystalline depending on the crystal structure, may be in an intrinsic state, and may be unintentionally doped or doped.

[0062] Throughout the entire specification, the description of "a-Ga2O3" may mean "α-Ga2O3".

[0063] Additionally, FIGS. 3a and 4b are schematic diagrams illustrating the operation of a synapse element according to one embodiment of the present invention. Specifically, FIGS. 3a and 4b illustrate the operation when light is irradiated onto the synapse element, where FIGS. 3a and 4a illustrate the operation when light of a first absorption wavelength is irradiated onto the synapse element, and FIGS. 3b and 4b illustrate the operation when light of a second absorption wavelength is irradiated onto the synapse element.

[0064] Referring to FIGS. 3a to 4b, when light is irradiated or a gate voltage is applied to the synapse element, a current is generated, but depending on the type of light or the direction of the gate voltage, the process from the state of current flow to recovery to the original state may differ.

[0065] First, referring to FIGS. 3a to 4b, the operation method when light is irradiated onto the synapse element will be explained.

[0066] The first channel layer is provided to absorb light of a first absorption wavelength, and the second channel layer is provided to absorb light of a second absorption wavelength.

[0067] Additionally, the first channel layer may be provided to absorb only light of a first absorption wavelength, or may be provided to additionally absorb light of a second absorption wavelength along with the absorption of light of the first absorption wavelength. If the first channel layer additionally absorbs light of the second absorption wavelength, it may be provided to absorb less than the second channel layer.

[0068] Additionally, the second channel layer may be provided to absorb only light of the second absorption wavelength, or it may be provided to additionally absorb light of the first absorption wavelength along with the absorption of light of the second absorption wavelength. When the second channel layer additionally absorbs light of the first absorption wavelength, it may be provided to absorb less light than the first channel layer.

[0069] According to one embodiment of the present invention, the light of the first absorption wavelength and the light of the second absorption wavelength may each independently include light with a wavelength of 200 nm to 1200 nm, but are not limited thereto. In this case, the light of the first absorption wavelength may be absorbed only in the first channel layer, and the light of the second absorption wavelength may be absorbed in both the first channel layer and the second channel layer, provided that the second channel layer absorbs more.

[0070] Specifically, when any light having a very long wavelength (e.g., greater than 1200 nm) is irradiated onto the synapse element, it is not absorbed in both the first channel layer and the second channel layer; however, when the wavelength of the said any light is reduced, it may not be absorbed in the second channel layer but may be absorbed only in the first channel layer. At this time, if the wavelength of the said any light is further reduced, it may be absorbed in both the first channel layer and the second channel layer; however, if it is absorbed in both channel layers, the said any light is absorbed more in the second channel layer, and the degree of absorption in the second channel layer may increase as the wavelength decreases.

[0071] More specifically, to induce a synaptic 'strengthening' response, most of the light must be absorbed by the first channel layer so that electrons are trapped at the interface, and to induce a synaptic 'inhibition' response, most of the light must be absorbed by the second channel layer so that holes are trapped at the interface.

[0072] At this time, there may be some overlap between the absorption curve of the first channel layer and the absorption curve of the second channel layer, but to create 'enhancement' and 'suppression', light in the non-overlapping region can be selected as the first absorption wavelength and the second absorption wavelength.

[0073] At this time, the first absorption wavelength may refer to a wavelength mainly absorbed in the first channel layer, and the second absorption wavelength may refer to a wavelength mainly absorbed in the second channel layer.

[0074] Referring to FIGS. 3a and 3b for example, the light of the first absorption wavelength may be 455 nm and the light of the second absorption wavelength may be 245 nm or less, but the wavelength band of the light of the first absorption wavelength and the wavelength band of the light of the second absorption wavelength are not limited thereto. If light of 200 nm or less is used as the second absorption wavelength, the second absorption wavelength may not be absorbed by the first channel layer and may be fully absorbed by the second channel layer.

[0075] In this way, the smaller the overlap region between the wavelength of light absorbed by the first channel layer and the wavelength of light absorbed by the second channel layer, the easier it is for synaptic 'strengthening' and synaptic 'inhibition' responses to occur.

[0076] In addition, when light of the first absorption wavelength is irradiated onto the synapse element, electrons excited in the first channel layer are trapped at the interface between the first channel layer and the second channel layer, and even after the irradiation of light of the first absorption wavelength is stopped, a signal delay of the current flowing through the synapse element is induced by the attraction between the trapped electrons and the holes in the first channel layer, thereby enabling the mimicry of a synapse function.

[0077] When input light of a first absorption wavelength is irradiated onto the first channel layer, photoexcited electrons and holes are generated in the first channel layer, and the generated electrons are trapped at the interface between the first channel layer and the second channel layer. Subsequently, when the light input is removed, the electrons trapped at the interface between the first channel layer and the second channel layer attract and exert an influence (attraction) on the holes present within the first channel layer. Due to the attraction of the holes, the resistance of the first channel layer decreases, causing an increase in synaptic current, and by delaying the recovery of the synaptic current until it returns to an initial state where the interface charge does not exist, it enables the mimicry of synaptic function.

[0078] Referring to Fig. 4a, when pulsed blue light stimulation is applied once, the synaptic current rises and then recovers with a delay, following the generation of the photocurrent. Thus, this rise followed by delayed recovery implies that the characteristics of the excitatory postsynaptic current (EPSC) among synaptic functions are mimicked.

[0079] Referring to FIGS. 3a and 4a, light of the first absorption wavelength (455 nm) passes through the second channel layer (a-Ga2O3) and is absorbed by the first channel layer (a-Si:H) to generate photoexcited electrons and holes. At this time, most of the charge carriers generated are |I D The synaptic current increases in L mode by contributing to the increase of |. Some of the photoexcited electrons generated during light irradiation accumulate at trap sites located at the interface between the first channel layer and the second channel layer, and are slowly detrapped over time when the light irradiation ends. At this time, electrons trapped at the interface between the first channel layer and the second channel layer can flow in from the source electrode through the first channel layer (a-Si:H), which is part of the charge transport channel, and attract holes located in the first channel layer. Even after light is irradiated, |I continues until the trapped electrons attract all the holes and the synaptic element is restored to its initial steady state. D The increased state of | can be maintained, which means that delayed recovery after EPSC occurs due to interfacial trapping.

[0080] Specifically, when light of a first absorption wavelength (455 nm) is irradiated onto the synapse element, the second channel layer does not absorb the light of the first absorption wavelength, and the light of the first absorption wavelength is absorbed only in the first channel layer. Charges (electrons and holes) having levels below the valence band of the first channel layer are excited to have levels above the conduction band by the energy of the light of the first absorption wavelength, and |I D As | increases, the synaptic current increases.

[0081] In this regard, when interfacial bonding occurs between different materials, atoms that are not chemically bonded may exist at the interface due to the mismatch in the lattices constituting the two materials, and trap sites may exist at the interface due to these unbonded atoms. These trap sites can act as spaces where electrons or holes can enter and remain, thereby trapping electrons or holes.

[0082] In this case, on the energy band diagram, 'electrons' find it easier to move downward along the band structure, while 'holes' find it easier to move upward along the band structure.

[0083] Considering these points, electrons of the first channel layer (e.g., a-Si:H) that have absorbed light of the first absorption wavelength (e.g., light of 455 nm wavelength) may be excited to an energy level above the conduction band and then move to the conduction band of the second channel layer through the energy band diagram formed by the contact between the first channel layer and the second channel layer (e.g., a-Ga2O3), and may be placed at a trap site at the interface. The electrons placed at the trap site change the resistance of the synapse element, and the changed resistance may change slowly over time until all the electrons are discharged from the trap site.

[0084] In addition, when light of the second absorption wavelength (e.g., light of 245 nm wavelength) is irradiated onto the synapse element, holes excited in the second channel layer are trapped at the interface between the first channel layer and the second channel layer, and even after the irradiation of the light of the second absorption wavelength is stopped, signal delay of the current flowing through the synapse element is induced by the repulsion between the trapped holes and the holes in the first channel layer, thereby enabling the mimicry of a synapse function.

[0085] When input light of a second absorption wavelength absorbed by the second channel layer is irradiated onto the synapse element, photoexcited electrons and holes are generated in the second channel layer. The generated holes are trapped at the interface between the first channel layer and the second channel layer. Subsequently, when the light input is removed, the holes trapped at the interface between the first and second channel layers repel holes present within the first channel layer, exerting an influence (repulsion). Due to this repulsion between the holes, the resistance of the first channel layer increases, causing a decrease in the synaptic current. Furthermore, by delaying the recovery of the synaptic current until it returns to an initial state where the interface charge does not exist, it is possible to mimic the function of the synapse.

[0086] In addition, as shown in Fig. 4b, when ultraviolet (UV) stimulation is applied once, it can be observed that the synaptic current rises with the generation of photocurrent, then decreases further than the initial value, and then recovers with a delay. This delayed recovery after decrease implies that it mimics the characteristics of the inhibitory postsynaptic current (IPSC) among synaptic functions.

[0087] Referring to FIGS. 3b and 4b, in the mode (L' mode) in which light of a second absorption wavelength (245 nm) is irradiated, most of the light is absorbed by the second channel layer (a-Ga2O3), and only a portion of the second absorption wavelength is absorbed by the first channel layer. Since the second channel layer, like the first channel layer, is also part of the charge transport channel, the charge generated by the light irradiated in the second channel layer is also |I at the time of light irradiation. D| contributes to the increase. However, holes generated by light move slowly in the second channel layer and are not trapped at the interface between the first and second channel layers, although it was confirmed that some holes are trapped at said interface (left side of Fig. 3b). Holes trapped at said interface lower the energy bands of the first and second channel layers and repel holes placed in the first channel layer, which functions as charge transport channels. That is, until the repulsion between the trapped holes and the holes in the first channel layer ends, |I D | decreases below the initial value. This is shown in Fig. 4b, when light is irradiated, |I D It refers to the IPSC characteristic where | temporarily spikes, then decreases below the initial value at a very rapid rate, and then slowly recovers after the light irradiation ends.

[0088] Specifically, when light of a second absorption wavelength is irradiated onto the synapse element, electrons in the valence band of the second channel layer are excited by the light of the second absorption wavelength and transition to the conduction band, while holes are simultaneously generated in the valence band. The current may increase due to the transitioned electrons. However, the holes located in the valence band of the second channel layer, formed by absorbing the light of the second absorption wavelength, may move slowly through the second channel layer and be placed at a trap site at the interface between the first channel layer and the second channel layer. The holes placed at the trap site change the resistance of the synapse element, and the changed resistance may change slowly over time until all the electrons flow out of the trap site.

[0089] The light irradiated to the first channel layer and the second channel layer and used for optical stimulation is light in a wavelength band suitable for the optical absorption range of each of the first channel layer and the second channel layer. When the synapse element according to the present invention has a plurality of channel structures including multiple first channel layers and second channel layers, the use of light of different wavelengths for stimulation is fundamental, but the use of light in an overlapping wavelength range may also be included.

[0090] The light receiving direction of the synapse device according to the present invention may be a vertical downward direction traveling straight from the top to the bottom of the synapse device, or a vertical upward direction traveling straight from the bottom to the top depending on the optical transparency of the substrate (gate electrode) and the gate insulating layer. That is, the light irradiated onto the synapse device may be from 12 o'clock (upper direction) to 6 o'clock (lower direction) based on FIGS. 1a and 1b, and may be irradiated from 6 o'clock (lower direction) to 12 o'clock (upper direction) if the substrate, the gate electrode, and the gate insulating layer are transparent.

[0091] The synapse device according to the present invention is such that the lattice of the first channel layer and the lattice of the second channel layer are mismatched and a synapse strengthening response or a synapse inhibition response is induced through the difference in wavelength of light mainly absorbed, but the first channel layer and the second channel layer may additionally satisfy the following physical conditions regarding energy band gap, doping, and band level at junction.

[0092] For example, the energy band gap of a channel layer positioned closer to the direction in which light is irradiated on the synapse element needs to be larger than the energy band gap of a channel layer positioned further away from the direction in which light is irradiated. In this case, either the first channel layer or the second channel layer may be a channel layer with a large energy band gap and the other may be a channel layer with a small energy band gap, and either one (the channel layer with the large energy band gap among the two channel layers) may be positioned closer to the direction in which light is irradiated compared to the other one (the channel layer with the small energy band gap among the two channel layers).

[0093] Additionally, the two channel layers may have different doping types. For example, if one of the channel layers is doped with type n, the other channel layer may be doped with type p.

[0094] At this time, when the channel layer with the larger energy band gap among the two channel layers is doped with n-type and joined with the channel layer with the smaller energy band gap, it is desirable that the conduction band level at joining is lower than the conduction band level of the channel with the smaller energy band gap, and the valence band level at joining is lower than the valence band level of the channel with the smaller energy band gap.

[0095] In addition, when the channel layer with the larger energy band gap among the two channel layers is doped with p-type and joined with the channel layer with the smaller energy band gap, it is desirable that the conduction band level at joining is higher than the conduction band level of the channel with the smaller energy band gap, and the valence band level at joining is higher than the valence band level of the channel with the smaller energy band gap.

[0096] FIGS. 18a to 19b are schematic diagrams illustrating the operation of the first channel layer and the second channel layer of a synapse device. In this regard, the synapse device according to FIGS. 18a to 19b does not operate in the same manner as the synapse device according to FIGS. 3a to 4b even when irradiated with light, and thus corresponds to a comparative example of the synapse device according to one embodiment of the present invention.

[0097] For example, as shown in FIG. 18a and FIG. 18b, the second channel layer is doped with n-type and the first channel layer is doped with p-type, and the conduction band level of the second channel layer is higher than the conduction band level of the first channel layer, but the valence band level of the second channel layer is lower than the valence band level of the first channel layer, the second channel layer absorbs a second absorption wavelength, and electron-hole pairs are formed by the absorbed second wavelength, and the formed holes are trapped at the interface between the first channel layer and the second channel layer, and the hole may have a junction structure in which the hole can flow toward the higher valence band level. In contrast, referring to FIG. 18b, when the first channel layer absorbs light of the first absorption wavelength to form electron-hole pairs, the level of the conduction band is higher on the second channel layer side, so the formed electrons are not trapped between the interface of the first channel layer and the second channel layer, and this is not a junction structure in which electrons can flow toward the side with the lower level of the conduction / valence band.

[0098] In addition, as shown in FIG. 19a and FIG. 19b, the second channel layer is doped with p-type and the first channel layer is doped with n-type, and the conduction band level of the second channel layer is higher than the conduction band level of the first channel layer, but the valence band level of the second channel layer is lower than the valence band level of the first channel layer, the second channel layer absorbs a second absorption wavelength, and electron-hole pairs are formed by the absorbed second wavelength, and the formed holes are trapped at the interface between the first channel layer and the second channel layer, and the hole can flow toward the higher valence band level. In contrast, referring to FIG. 19b, when the first channel layer absorbs light of the first absorption wavelength to form electron-hole pairs, the level of the conduction band is higher on the second channel layer side, so the formed electrons are not trapped between the interface of the first channel layer and the second channel layer, and this is not a junction structure in which electrons can flow toward the side with the lower level of the conduction / valence band.

[0099] As such, the synapse device of FIGS. 18a to 19b can induce a synapse inhibitory response through light (Figs. 18a and 19a), but cannot induce a synapse strengthening response through light.

[0100] That is, the synapse device according to FIGS. 18a to 19b cannot simultaneously induce a synapse strengthening response and a synapse inhibition response by light, but the synapse device according to the embodiment of the present invention of FIGS. 3a to 4b can simultaneously induce a synapse strengthening response and a synapse inhibition response by light alone, thereby enabling synapse operation.

[0101] According to one embodiment of the present invention, the synapse device may additionally include a passivation layer covering a part or all of the channel layer, but is not limited thereto. The synapse device may include a form in which a part or all of the channel layer is covered by a passivation layer to protect the exposed channel layer depending on the operating environment of the synapse device, and the passivation layer may have a structure that is in contact with or not in contact with the source and drain electrodes, and is made of Si, SiO2, Al2O3, Si3N4, SiN x :H, AlN, TiO x It may include those selected from the group consisting of , ITZO, and combinations thereof.

[0102] According to one embodiment of the present invention, the substrate may comprise, but is not limited to, an insulator, a conductor, Si, and combinations thereof, selected from the group consisting of insulators, conductors, Si, and combinations thereof.

[0103] According to one embodiment of the present invention, the gate electrode may comprise, but is not limited to, a conductive metal material, Si, and combinations thereof selected from the group consisting of,

[0104] In this case, if the substrate and the gate electrode comprise the same material (e.g., Si), the substrate may serve as the gate electrode.

[0105] According to one embodiment of the present invention, the gate insulating layer comprises an insulating material, and the thickness of the gate insulating layer may be 1 nm to 1000 nm, but is not limited thereto.

[0106] Meanwhile, FIGS. 5 to 6b are schematic diagrams illustrating the operation method of a synapse device according to one embodiment of the present invention. Specifically, FIG. 5 illustrates the case where a positive gate voltage is applied to the gate electrode and the case where a negative gate voltage is applied, and illustrates the operation method of a synapse device according to the seventh aspect and the eighth aspect.

[0107] When a gate voltage is applied to the synapse element, the interface between the first channel layer and the gate insulating layer acquires a positive or negative interface charge, and even after the application of the gate voltage is stopped, a signal delay of the current flowing through the synapse element is induced by the repulsion between the positive interface charge and the hole in the first channel layer, or by the attraction between the negative interface charge and the hole in the first channel layer, thereby enabling the mimicry of a synapse function.

[0108] Additionally, the direction of the gate voltage pulse applied to the synapse element may be related to the interface charge between the gate insulating layer and the first channel layer. For example, when a positive gate voltage pulse is applied (E + In an electrical stimulation mode, the drain current decreases, the band of the p-type first channel layer (a-Si:H) bends downward toward the gate insulating layer (SiO2), and the interface between the first channel layer and the gate insulating layer is charged with electrons (negative interface charge). The electrons located at the interface can attract holes in the first channel layer, and when the positive gate voltage pulse ends, the conductivity of the first channel layer increases, causing the drain current to increase, and the increased conductivity can affect the first channel layer even after the pulse ends, thereby delaying recovery to the initial current state.

[0109] Figure 6a shows the synaptic current behavior when a positive gate voltage pulse is applied to the synaptic device. Referring to Figure 6a, when a positive gate voltage pulse is applied to the synaptic device, a channel is formed and the synaptic current decreases instantaneously. When the duration of the positive gate voltage pulse ends, the synaptic current increases to a level exceeding the initial value and then slowly recovers to the original synaptic current. In other words, when a positive gate voltage is applied to the synaptic device, it can be seen that EPSC characteristics, which are a phenomenon of current increase followed by delayed recovery, appear.

[0110] Also, when a negative gate voltage pulse is applied (E - In an electrical stimulation mode, the drain current decreases, the band of the p-type first channel layer (a-Si:H) bends upward toward the gate insulating layer (SiO2), and the interface between the first channel layer and the gate insulating layer is charged with holes (positive interface charge). The holes located at the interface can repel the holes in the first channel layer, and when the negative gate voltage pulse ends, the conductivity of the first channel layer decreases, causing the drain current to decrease. The reduced conductivity can affect the first channel layer even after the pulse ends, thereby delaying recovery to the initial current state.

[0111] Figure 6b shows the application of a negative gate voltage pulse to a synapse device. When a negative gate voltage pulse is applied, channel formation is suppressed, causing the synapse current to increase instantaneously. When the pulse ends, the synapse current drops below the initial value and then slowly recovers to the original synapse current. Therefore, it can be seen that the IPSC characteristic, which is a delayed recovery phenomenon after current reduction, appears.

[0112] In addition, the photodetector according to the third aspect of the present invention includes a synapse element according to the first aspect or the second aspect.

[0113] Additionally, the electronic device according to the fourth aspect of the present invention includes a synapse element according to the first aspect or the second aspect.

[0114] In addition, the electronic device comprises a component selected from the group consisting of semiconductor devices, image sensors, vision sensors, and combinations thereof.

[0115] Additionally, the fifth aspect of the present invention is a method for manufacturing a synapse element according to the first aspect, comprising: a step of placing a gate insulating layer on a substrate including a gate electrode; a step of placing a first channel layer on the gate insulating layer; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; and a step of placing a second channel layer between the first electrode and the second electrode on the first channel layer; wherein the first channel layer and the second channel layer are provided such that an interface charge inducing a signal delay of a current generated by light (photostimulation) irradiated on the synapse element is placed at the interface between the first channel layer and the second channel layer, and / or an interface charge inducing a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulation) is placed at the interface between the first channel layer and the gate insulating layer.

[0116] Additionally, the sixth aspect of the present invention is a method for manufacturing a synapse element according to the second aspect, comprising: a step of placing a second channel layer on a substrate; a step of placing a first channel layer on the second channel layer; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; a step of placing a gate insulating layer between the first electrode and the second electrode on the first channel layer; and a step of placing a gate electrode on the gate insulating layer; wherein the first channel layer and the second channel layer are provided such that an interface charge inducing a signal delay of a current generated by light (photostimulation) irradiated to the synapse element is placed at the interface between the first channel layer and the second channel layer, and / or an interface charge inducing a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulation) is placed at the interface between the first channel layer and the gate insulating layer.

[0117] The method for manufacturing a synapse device according to the fifth aspect above is a method for manufacturing a synapse device according to the first aspect above, and the method for manufacturing a synapse device according to the sixth aspect above is for manufacturing a synapse device according to the second aspect above.

[0118] Hereinafter, a method for manufacturing a synapse device according to the fifth aspect is described, and the method for manufacturing a synapse device according to the sixth aspect may be substantially the same as the method for manufacturing a synapse device according to the fifth aspect.

[0119] First, a gate electrode is formed on a substrate. At this time, if the substrate functions as a gate electrode, the substrate and the gate electrode may be identical.

[0120] Next, a gate insulating layer is formed on a substrate. Next, a first channel layer is formed on the gate insulating layer. Next, a source electrode and a drain electrode are formed on the first channel layer. Next, a second channel layer is formed between the source electrode and the drain electrode on the first channel layer.

[0121] At this time, the source electrode, the second channel layer, and the drain electrode are disposed on the first channel layer in a spaced-apart state.

[0122] According to one embodiment of the present invention, the method for manufacturing the synapse device may additionally include a heat treatment process for improving contact between the first channel layer and the electrode, but is not limited thereto.

[0123] Additionally, the ninth aspect of the present invention is a method for manufacturing a synapse device according to the seventh aspect, comprising the steps of: placing a gate insulating layer on a substrate including a gate electrode; placing a first channel layer on the gate insulating layer; and placing a first electrode and a second electrode spaced apart from each other on the first channel layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is placed at the interface between the first channel layer and the gate insulating layer. At this time, the method for manufacturing a synapse device according to the ninth aspect may additionally include the step of placing a second channel layer between the first electrode and the second electrode on the first channel layer.

[0124] Additionally, the tenth aspect of the present invention is a method for manufacturing a synapse device according to the eighth aspect, comprising: a step of placing a first channel layer on a substrate; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; a step of placing a gate insulating layer between the first electrode and the second electrode on the first channel layer; and a step of placing a gate electrode on the gate insulating layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is placed at the interface between the first channel layer and the gate insulating layer.

[0125] At this time, the method for manufacturing a synapse element according to the 10th aspect above may additionally include the step of placing a second channel layer on a substrate, and if the step of placing a second channel layer on a substrate is additionally included, the first channel layer is placed on the second channel layer.

[0126] The present invention is to be explained in more detail through the following examples, but the following examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0127] [Example]

[0128] First, for the back gate electrode and gate insulator, p + Si and SiO2 were prepared. Subsequently, to deposit a first channel layer (charge transfer layer) on the gate insulator, a-Si:H was deposited to a thickness of 50 nm via plasma-enhanced chemical vapor deposition (PE-CVD). At this time, the formation of the a-Si:H film was performed at 50 W (operating power), 600 mTorr (operating pressure), 250°C, and gas ratios of H2 / SiH4 = 15, B2H6 / SiH4 = 0.3, and CO2 / SiH4 = 0.6. The a-Si:H is porous, approximately 10 17 cm -3 It has a doping concentration of.

[0129] Next, Ti / TiN (5 / 150 nm) source / drain electrodes were formed on the a-Si:H through photolithography and lift-off processes. Subsequently, an amorphous gallium oxide (a-Ga2O3) thin film (second channel layer) with a thickness of 100 nm was deposited by radio frequency magnetized cathode deposition using a Ga2O3 target with 99.99% purity. At this time, the a-Ga2O3 deposition was performed at 1.3 mTorr (pressure) and 70 W power in an inert atmosphere of Ar gas.

[0130] Subsequently, photoresist masking and tetramethylammonium hydroxide (TMAH, C4H 13 A synapse device was fabricated by selectively wet-etching a-Ga2O3 using NO (diluted to water <3 wt%). The synapse device comprises a-Si:H as a first channel layer and a-Ga2O3 as a second channel layer, and various equipment can be used to detect the characteristics of the synapse device.

[0131] First, the thickness and crystal structure of the synapse device can be investigated using a 300 keV electron microscope (TEM, EM-ARM200F, JEOL, Ltd., Japan). To analyze the crystal structure of the synapse device, an FFT pattern was acquired using a Gatan DigitalMicrograph® (AMETEK, Inc., USA). Additionally, to obtain cross-sectional information, sampling can be performed using a focused ion beam (FIB) milling system (Helios 5 UX, Thermo Fisher, USA).

[0132] Meanwhile, the transmittance of the a-Si:H and a-Ga2O3 layers can be characterized using an ultraviolet-visible-near-infrared (UV-VIS-NIR) spectrometer (UV-3600, Shimadzu, Japan), and the postsynaptic current (PSC) of the synapse device can be measured using a semiconductor parameter analyzer (Keithley 4200-SCS, Tektronix, USA). To irradiate light onto the synapse device, an LED light source (M455L3, Thorlabs, USA), a monochromatic light (lamp (6269, Newport, USA), lamp housing (66921, Newport, USA), a monochromator (CS130B-1-MC, Newport, USA), and an arc lamp power supply (69920, Newport, USA)) were used. At this time, the stimulation pulses from the LED light source were controlled via TTL using a function generator (AFG-2225, GW Instek, Taiwan) connected to an LED driver (T-Cube LED Driver, Thorlabs, USA), and the stimulation pulses from the monochromatic lamp were controlled by the diaphragm shutter by inputting TTL to a controller (SHB025T, Thorlabs, USA) mounted on the monochromator output section.

[0133] [Experimental Example 1]

[0134] FIG. 7 is a schematic diagram of an electronic device (synapse element) according to one embodiment of the present invention, FIG. 8 is a schematic diagram of a synapse element according to one embodiment of the present invention and an enlarged view of a part thereof, FIG. 9a is a graph of drain current according to a change in gate voltage of a synapse element according to one embodiment of the present invention, and FIG. 9b is a graph of drain current according to a change in drain voltage.

[0135] The synapse device according to the above embodiment is a field-effect transistor (FET) comprising a dual channel of amorphous Si and amorphous gallium oxide (a-Si:H / a-Ga2O3), and can be represented as shown in FIG. 7. FIG. 7 schematically illustrates the operation of the synapse device, wherein a biological synapse is a connection at a contact point that transmits signals between neurons, and a neuron stimulated by a signal transmits a neural signal in the form of an electrical spike through the synapse to another neuron, and the signal transmission proceeds from the axon of the synaptic progenitor neuron to the dendrite or cell body of the synaptic postsynaptic neuron. At this time, when a spike occurs, it operates as if a neurotransmitter is emitted to a receptor on the opposite side of the synapse to transmit a signal.

[0136] The behavior of the biological synapse described above can be mimicked by optical pulse input and / or electrical pulse input in the synapse device according to the embodiment. Specifically, the synapse device can generate EPSC (positive potential synaptic current) and IPSC (negative potential synaptic current) based on optical signals and / or electrical signals.

[0137] Referring to Fig. 8, cross-sectional image analysis confirmed that the thicknesses of the a-Si:H and a-Ga2O3 films were 50 nm and 100 nm, respectively. Fast Fourier Transform (FFT) diffraction patterns were obtained from each film, and the obtained ring-shaped diffraction patterns indicate that the Ga2O3 and Si:H films have an amorphous crystal structure.

[0138] The electrical characteristics of the above synapse device were investigated using a current-voltage (IV) curve. Figure 9a shows the gate voltage (V G ) and drain voltage (V D Drain current (I) measured while varying ) D Showing the transfer characteristic curve of ) (at room temperature at 300 K), V D = Approximately 10 at -10 V 4 It shows the gate control of. In this case, the figure inserted inside Fig. 9a is the optical microstructure of the device. The synapse element corresponding to the device inserted inside Fig. 9a is designed as an interdigitated electrode in which a-Ga2O3 is selectively etched along the source and drain electrodes, thereby providing an advantageous result for receiving light. Additionally, in Fig. 9a, if the first channel layer is a p-type semiconductor, a p-type conduction characteristic in which the channel layer turns on according to a negative direction gate voltage sweep may appear, and if the first channel layer is an n-type semiconductor, an n-type conduction characteristic in which the channel turns on according to a positive direction gate voltage sweep may appear.

[0139] In addition, the characteristic output curve of Fig. 9b shows typical transistor characteristics consisting of linear and saturation regions. Since the first channel layer, which is the main charge transfer layer, uses p-type a-Si:H, the drain current decreases as the gate-source voltage decreases, and this negative characteristic is consistent with the conductivity of p-type a-Si:H of 50 nm.

[0140] [Experimental Example 2]

[0141] FIG. 10a is a transmission spectrum of a synapse device according to one embodiment of the present invention, FIG. 10b is for the extraction of the optical bandgap of a channel layer obtained through a Tauc plot of the transmission spectrum, FIG. 10c is a graph showing the light absorption of a first channel layer and a second channel layer according to wavelength, and FIG. 11 is for the current characteristics of a synapse device according to one embodiment of the present invention.

[0142] FIGS. 10a to 11 relate to the synaptic operating principles of the synapse device of the above embodiment in response to optical and electrical stimulation. First, FIGS. 10a to 10c relate to the synaptic response of the synapse device in response to optical stimulation, where FIG. 10a relates to a-Si:H (50 nm) and aG a This concerns the measured transmittance of a 2O3 (100 nm) sample. Referring to Fig. 10b, based on the measured transmittance and the Tauc plot method, it can be confirmed that the optical band gaps of a-Si:H and a-Ga2O3 are 2.0 eV and 4.92 eV, respectively. Subsequently, finite difference time domain (FDTD) simulations were performed to analyze the absorption in each layer of a-Si:H / a-Ga2O3, and the measured refractive index (n) and extinction coefficient (k) were applied to reflect the optical properties.

[0143] Referring to Fig. 10c, α-Ga2O3 and α-Si:H can absorb incident light near the boundary wavelength (about ~257 nm) and generate holes and electrons as minority charge carriers, respectively, and in the boundary wavelength region (250 nm to 300 nm), mechanisms for synaptic strengthening and synaptic inhibition may occur together, but a mechanism in which the type of charge carrier (electron or hole) with a higher concentration, higher trap capture rate, and longer lifetime at the trap site is determined to be dominant.

[0144] Referring to Fig. 11, since inhibitory behavior in which the current decreases after the pulse is observed at wavelengths below 290 nm and excitatory behavior in which the current increases after the pulse is observed at wavelengths above 290 nm, it can be confirmed that the dominant mechanism gradually changes from inhibition to activation as the wavelength of light irradiated on the synaptic device increases. Since the second channel layer, α-Ga2O3, and the first channel layer, α-Si:H, have the same light absorption rate at 257 nm, and based on the trap capture rate and lifetime in the trap, the inhibitory effect of holes (i.e., synaptic inhibition response) is stronger than the activation effect of electrons (i.e., synaptic strengthening response) based on the wavelength of light irradiated on 290 nm, the synaptic device can mimic synaptic behavior according to the wavelength of the irradiated light.

[0145] Meanwhile, the above-mentioned synaptic device can also mimic synaptic behavior through electrical stimulation.

[0146] FIG. 12a shows the sweeping delay time between two consecutive measurement points in a synapse device according to one embodiment of the present invention, FIG. 12b shows the gate voltage sweeping range, and FIG. 12c shows the charge trapping effect in the synapse device by applying a pulse.

[0147] First, to verify the interface effect, the hysteresis of the transfer characteristic curve according to the sweeping delay was measured. Referring to Fig. 12a, the first channel layer (a-Si:H) of the synapse device is very thin, so the movement of charge carriers within the first channel layer is influenced by charges captured from the surrounding medium, and as a result, carrier mobility is generally reduced and large hysteresis of the transfer characteristic is observed. In the synapse device, counterclockwise hysteresis due to electron capture and emission in donor traps of the Si / SiO2 structure can be observed.

[0148] Specifically, sweeping the gate with a negative voltage increases the occupancy of electron traps, thereby lowering the threshold voltage (V T Shift ) to the negative side (negative shift), and the same V G Increases channel conductivity for. Interface trap density (N) between the first channel layer and the second channel layer. trap ) can be expressed as in the following mathematical formula 1:

[0149] [Mathematical Formula 1]

[0150]

[0151] (At this time, C OX is 4X10 -8 F / cm 2 As, it refers to the oxide capacitance of the SiO2 back gate, and V T-fwd represents the threshold voltage of forward sweeping, and V T-rev represents the threshold voltage for backward sweeping, and q represents the atomic charge constant).

[0152] For the sweeping range corresponding to FIG. 12a above, N of the a-Si:H / a-Ga2O3 transistor trap It is approximately 7.49 x 10 12 cm -2 It is estimated that... Additionally, Fig. 12b, which shows the hysteresis of the device according to the sweeping range, indicates that the magnitude of the hysteresis loop is at maximum V G It indicates that it is determined by.

[0153] Additionally, the graph inserted in FIG. 12a shows the gate voltage V without sweep delay. G Transconductance (|g m This relates to the representative operating characteristics of |), specifically the drain current (I D Due to the counterclockwise hysteresis of ), the transconductance may exhibit a hysteresis loop with a vertex.

[0154] Before adjusting the PSC of the synapse device using gate voltage pulses, V before and after applying 50 pulses T The change in was observed. The captured charge density per pulse (N) calculated using Fig. 12c and the above Equation 1. trap ) average 3.5 X 10 10 cm -2 It was confirmed. The captured charge density means that the conduction state can be controlled repeatedly and in reverse by applying an appropriate pulse to the gate of the synapse element.

[0155] Electronic devices can be controlled by implementing synaptic behavior through voltage pulses applied to the above synaptic device. Generally, since most devices using a semiconductor-gate oxide interface utilize resistance hysteresis in response to voltage input in electrical mode, it is necessary to analyze lattice mismatch, oxide fixed charge, crystal structure of each layer, and the location of interface traps for precise control of synaptic current.

[0156] [Experimental Example 3]

[0157] Through Experimental Examples 1 and 2 above, it can be confirmed that the synapse device according to the above embodiment generates PSCs bidirectionally through optical stimulation and electrical stimulation. At this time, optical stimulation and electrical stimulation can be controlled by changing the intensity and duration of the optical pulse and electrical pulse. At this time, the stimulation intensity of the system is P in optical mode. in As, in electrical mode, V G It can be expressed as.

[0158] Figures 13 (a) to (f) show the relationship between the photoelectric response characteristics and time dependence of a synapse device according to the present invention.

[0159] Specifically, (a) and (b) of FIG. 13 show P in L and L' modes. in and as a result of changing the duration. In L mode, Pin As the duration increases, the PSC and delay time increase, but in L' mode, they decrease (top of (e) and (f) in Fig. 13). Meanwhile, Figs. 13 (c) and (d) are E + and E - Pulse V in mode G As a result of changing the duration, E + Pulse V in mode G and as the duration increases, PSC and delay time increase, but E - In mode, it can be confirmed that it decreases (bottom of (e) and (f) of Fig. 13). That is, by controlling the total amount of stimulation under a single pulse input, the synaptic strength appearing in the synaptic element can be controlled.

[0160] [Experimental Example 4]

[0161] Figures 14 (a) to (f) show current modulation and weight modulation characteristics according to the photoelectric response characteristic conditions of a synapse device according to the present invention.

[0162] Paired-Pulse Facilitation (PPF) refers to a neurological phenomenon in which the induced postsynaptic potential increases when one stimulus is closely followed by another stimulus. Figures 14 (a) to (d) illustrate the PPF characteristics of a synaptic phototransistor stimulated by two consecutive optical and electrical pulses. In this case, the pulse duration and interval (Δt) are both 0.25 seconds.

[0163] In all stimulation modes, the PSC after the second pulse was confirmed to be greater than the PSC after the first pulse. Additionally, Figure 14 (e) shows the correlation between the PPF index ((PSC2 / PSC1) × 100) and Δt, and the PPF index can be expressed as Equation 2 below:

[0164] [Mathematical Formula 2]

[0165]

[0166] (In the above Equation 2, τ1 and τ2 represent decay time).

[0167] τ1 and τ2 are related to the PPF indices of the optical and electrical pulses. For example, for optical stimulation irradiating 455 nm, τ1 and τ2 are 0.07 sec and 4.62 sec, respectively, and for optical stimulation irradiating 245 nm, they are 0.08 sec and 1.96 sec, respectively. In addition, positive V G When a pulse is applied, τ1 and τ2 are 0.18 sec and 5.06 sec, respectively, and negative V G When a pulse is applied, τ1 and τ2 are 0.04 seconds and 0.92 seconds, respectively. The decay time is similar to the time scale of biological synapses and can consist of a fast phase (lasting for tens of milliseconds) and a slow phase (lasting for hundreds of milliseconds).

[0168] Meanwhile, since the energy consumption of typical biological synapses is very small, ranging from approximately 1 fJ to 10 fJ per synaptic event, it is advantageous for the energy consumption of artificial synapse devices to also be as low as possible. Energy consumption (E) due to electrical stimulation in the above synapse device elec ) or energy consumption due to optical stimulation (E opt ) can be calculated according to the following mathematical formulas 3 and 4.

[0169] [Mathematical Formula 3]

[0170]

[0171] [Mathematical Formula 4]

[0172]

[0173] (In the above mathematical formulas 3 and 4, V D , I PSC , t d , S, and P inrepresents the magnitude of the drain voltage, the magnitude of the PSC current, the pulse duration, the device area, and the optical power density, respectively).

[0174] The energy consumption of the synapse device according to the above embodiment is L, L', E + , and E - The energy consumption in the optical mode was found to be 1.09 nJ, 20.13 pJ, 199.58 nJ, and 58.65 nJ, respectively, and it can be confirmed that the energy consumption in the optical mode is very low compared to the energy consumption in the electrical mode.

[0175] Subsequently, the short-term and long-term memory switching characteristics in the aforementioned synaptic devices were examined following repetitive stimulation. Long-term potentiation (LTP) and long-term depression (LTD) refer to long-term plasticity characteristics associated with the increase and decrease of synaptic weights, respectively. To this end, L / L', L / L', L / E + , E + / L, L / E - , E - / L, L' / E + , E + / L', L' / E - , E - / L', and E + / E - Combinations of stimulation modes were investigated, and (f) of FIG. 14 represents the change in absolute postsynaptic current (|W|) according to the number of spikes, where |W| can be calculated as shown in Equation 5 below:

[0176] [Mathematical Formula 5]

[0177]

[0178] (In the above Equation 5, PSC0 represents the initial synaptic current, and PSC represents the value obtained by subtracting the first spike current from the second spike current).

[0179] Referring to (f) of FIG. 14 above, |W| can be adjusted according to the number of spikes resulting from optical or electrical stimulation, and as the number of spikes increases, |W| is L, L', E + , and E - For each mode, it can be adjusted from 11% to 38%, 2% to 55%, 33% to 67%, and 10% to 24%, respectively. Additionally, |W| corresponding to the spike frequency increases from 1% to 16%, 3% to 38%, 0.5% to 11%, and 0.6% to 11% for each measurement frequency range, which corresponds to light of a wavelength of 455 nm and +V G LTP of synaptic elements induced by spike stimulation and 245 nm wavelength light and -V G The LTD of the synaptic device is verified by spike stimulation. That is, the operation of the synaptic device means that it mimics the transition from short-term memory to long-term memory through repetitive stimulation and interval control.

[0180] [Experimental Example 5]

[0181] STDP (spike-timing-dependent plasticity) is the time interval (firing time difference; Δt) between a presynaptic neuron and a postsynaptic neuron. pre-post It refers to the mechanism by which synaptic strength changes depending on ). The shorter the elapsed time between two spikes, the greater the change in synaptic weight, and since this mechanism can induce LTP and LTD, it contributes to learning and information storage in the brain, similar to other forms of synaptic plasticity. Generally, the STDP of biological synapses can be expressed by symmetric Hebbian learning rules and asymmetric Hebbian learning rules, which are given by Equations 6 and 7 below:

[0182] [Mathematical Equation 6] : Symmetric Hebbian learning rule

[0183]

[0184] [Mathematical Equation 7] : Antisymmetric Hebbian learning rule

[0185]

[0186] (In the above mathematical equations 6 and 7, A and τ represent the synaptic scaling constant and the time constant, respectively, and ΔW represents the relative change in synaptic weights.

[0187] Different waveforms and interval times were applied to the two associated spikes, and the results are shown in Fig. 15.

[0188] FIGS. 15 (a) through (j) relate to the spike-timing-dependent plasticity (STDP) of a synaptic device according to the present invention, depending on the spike stimulation conditions and spike timing. Specifically, FIGS. 15 (a) through (j) relate to optical stimulation (L or L') or electrical stimulation (E + or E - The STDP of the synapse device is shown in ), where (a) to (j) of FIG. 15 are L / L, L' / L', and E, respectively. + / E + , E - / E - , L / L', L / E + , L / E - , L' / E + , L' / E - , and E + / E - It was stimulated.

[0189] When both the presynaptic spike and the postsynaptic spike are L or E+, or when an L presynaptic spike and an E+ postsynaptic spike are applied (Fig. 15 (a), (c), and (f)), Δt pre-postAt = 0, a positive ΔW always appears, which shows that a symmetric Hebbian learning rule appears in the synaptic element.

[0190] When both the presynaptic spike and the postsynaptic spike are E- or L' (Fig. 15 (b) and (d)), Δt pre-post At = 0, a negative ΔW always appears, which shows that a symmetric anti-Hebbian learning rule appears in the synaptic element.

[0191] L' / E as in (h) and (j) of Fig. 15 + or E + / E - In the case of combinations, Δt pre-post When > 0, a positive ΔW appears and Δt pre-post It is shown that when < 0, a negative ΔW appears, indicating an asymmetric anti-Hebbian learning rule.

[0192] Meanwhile, L / L', L / E - , and L' / E - In combinations, learning rules are not observed due to differences in the weight modulation range between combinations (Fig. 15 (e), (g), and (i)). In such cases, the Hebbian rule can be achieved by matching the weight modulation range between stimulus pairs by optimizing the composition of light intensity, voltage magnitude, and / or pulses.

[0193] As a result of calculating the STDP time window (τ) of the synapse device according to the embodiment by fitting the experimental data to the above mathematical formulas 6 and 7, it was confirmed that τ varies from 0.11 seconds to 2.28 seconds depending on the configuration of the presynapse spike and the postsynapse spike. That is, since optical stimulation and electrical stimulation can coexist in the synapse device, homeostatic feedback control is possible, synaptic plasticity is easy to implement, and ΔW can be programmed by applying appropriate stimulation to the synapse device.

[0194] [Experimental Example 6]

[0195] FIG. 16a shows a simulation of the optic nerve of a zebrafish, FIG. 16b shows the phototactic behavior pattern of the zebrafish, and FIG. 16c shows the result of mimicking the behavior of the zebrafish through a synapse element according to one embodiment of the present invention.

[0196] The synapse device according to the present invention can mimic the light-sensing response of a living organism by utilizing all optical synapse modes.

[0197] For example, phototaxis is the property of organisms to move toward (positive phototaxis) or away from (negative phototaxis) light stimuli, and the wavelength-differential response of organisms to phototaxis is an essential element in the behavior and evolutionary ecology of various species.

[0198] Zebrafish are organisms that avoid ultraviolet rays and exhibit positive phototaxis behavioral patterns toward visible light; as light intensity increases, these positive phototaxis patterns become more pronounced. This implies that zebrafish living at shallow depths adapt to their environment to find food, avoid predators, and escape harmful ultraviolet rays. Zebrafish were selected as the subject for behavioral mimicry because they are vertebrates with a nervous system similar to humans and are widely used as neurological models due to their short generation cycles.

[0199] Referring to FIGS. 16a to 16c, for the visual perception of the zebrafish, stimulus signals are transmitted to the optic nerve through the optic ganglion, which is a neuronal pathway. Referring to FIG. 16b, the positive phototactic response and negative phototactic response of the zebrafish are observed. Specifically, referring to FIG. 16b, when blue light is shone on the side of a zebrafish moving in a straight line, the zebrafish exhibits a positive phototactic response of rotating in the direction of the blue light, and conversely, when ultraviolet light is shone on the side, the zebrafish exhibits a negative phototactic response of rotating in the direction opposite to the ultraviolet light and performs avoidance movements against the ultraviolet light.

[0200] The photo-directed response of a zebrafish as shown in FIG. 16b can be mimicked through the optical modulation function of a synapse element according to one embodiment of the present invention, specifically, the photo-directed response to visible light (blue light) corresponds to the L mode, and the photo-directed response to ultraviolet light corresponds to the L' mode.

[0201] When blue light and ultraviolet light are alternately irradiated onto the above synapse device, the synapse device generates EPSC in response to blue light to mimic a positive photoreflex response, and generates IPSC in response to ultraviolet light to mimic a negative photoreflex response. That is, the synapse device according to the above embodiment can mimic wavelength-dependent biological reflections involved in the formation of visual memory.

[0202] [Experimental Example 7]

[0203] FIG. 17a is a schematic diagram showing the pulse conditions of a synapse device according to one embodiment of the present invention, FIG. 17b shows the change in conductivity of the synapse device as a function of the number of pulses, FIG. 17c is a graph showing the normalized G for the number of pulses to extract nonlinearity, FIG. 17d compares the nonlinearity and asymmetry for optical and electrical stimulation, and FIG. 17e is for a CNN model trained using the synapse device.

[0204] The synapse device according to the above embodiment can be applied to neuromorphic computing. Specifically, the synapse device can be applied to a deep neural network (DNN).

[0205] In the above DNN, artificial synaptic currents (synaptic weights) can be strengthened or suppressed through a backpropagation algorithm, and artificial synapses need to exhibit linear or symmetric weight update characteristics for high learning accuracy.

[0206] FIG. 17a discloses an excitatory or inhibitory stimulus for evaluating the amplification and inhibition characteristics of the synaptic device. Additionally, FIG. 17b shows the conductance extracted from the potentialistatic current (PSC) defined as a function of the number of pulses applied to the synaptic device, specifically L / L', L / E - , L / E + , and E + Amplification / suppression was confirmed for a total of four cases / L'. Figure 17c shows the nonlinearity (α) obtained by fitting an exponential function to determine the optimal combination. p,d It is the extraction of ). In this case, complete linearity is α p,d As = 0, the asymmetry is |α p,d| is defined as such, and the ideal value is 0. A graph comparing nonlinearity and asymmetry is Fig. 17d, and it was confirmed that the L / L' combination is most suitable for using the synapse element as an artificial synapse in a DNN.

[0207] Next, the above-mentioned synapse device was applied to a learning model for classifying the MNIST (Modified National Institute of Standards and Technology) dataset of handwritten digits. In this case, the learning model is based on a CNN (convolutional neural network). Referring to Fig. 17e, a learning model consisting of convolutional and pooling layers for feature extraction and dense layers for classification can be observed. After the training was completed, the weight values ​​of the two dense layers were quantized. The normalized conductivity (G) value of the above-mentioned synapse device was measured from 100 iterations of amplification (L stimulus) and inhibition (L' stimulus) light stimulation pulses and quantized for CNN training. The quantized weights were re-inserted into the learning model, and as a result of performing an MNIST classification test, it was confirmed that the average accuracy was 98.46%.

[0208] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0209] The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and the concept of equivalents thereof should be interpreted as being included within the scope of the present invention.

Claims

Claim 1 A synapse device comprises: a substrate including a gate electrode; a gate insulating layer disposed on the substrate; and a first channel layer disposed on the gate insulating layer. and a first electrode and a second electrode spaced apart from each other and disposed on the first channel layer; wherein the first channel layer is provided such that an interface charge inducing a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is disposed at the interface between the first channel layer and the gate insulating layer, the first channel layer comprises a material selected from the group consisting of Si:H, Si, SiO2, and combinations thereof, and the first channel layer and the gate insulating layer are provided with different materials such that a trap site capable of trapping charge is formed at the interface between the first channel layer and the gate insulating layer, and the synapse element, when a positive gate voltage is applied to the gate electrode, the band of the first channel layer bends downward toward the gate insulating layer, and the interface between the first channel layer and the gate insulating layer is charged with a negative interface charge, and after the application of the positive gate voltage is stopped, the resistance of the first channel layer decreases due to the attraction between the negative interface charge and the hole of the first channel layer, and the synapse A synapse device capable of mimicking a synapse function in which a signal delay of the current flowing through the device is induced, wherein when a negative gate voltage is applied to the gate electrode, the band of the first channel layer bends upward toward the gate insulating layer, and the interface between the first channel layer and the gate insulating layer is charged with a positive interface charge, and after the application of the negative gate voltage is stopped, the resistance of the first channel layer increases due to the repulsion between the positive interface charge and the hole in the first channel layer, thereby enabling the mimicking of a synapse function in which a signal delay of the current flowing through the synapse device is induced. Claim 2 delete Claim 3 A synapse device according to claim 1, further comprising a second channel layer disposed between the first electrode and the second electrode on the first channel layer. Claim 4 A synapse device comprises: a substrate; a first channel layer disposed on the substrate; a first electrode and a second electrode disposed spaced apart from each other on the first channel layer; and a gate insulating layer disposed between the first electrode and the second electrode on the first channel layer. The synapse element comprises: a gate electrode disposed on the gate insulating layer; wherein the first channel layer is provided such that an interface charge inducing a signal delay of the current generated by a voltage applied to the gate electrode (gate voltage stimulus) is disposed at the interface between the first channel layer and the gate insulating layer; wherein the first channel layer comprises a material selected from the group consisting of Si:H, Si, SiO2, and combinations thereof; wherein the first channel layer and the gate insulating layer are provided with different materials such that a trap site capable of trapping a charge is formed at the interface between the first channel layer and the gate insulating layer; wherein, when a positive gate voltage is applied to the gate electrode, the band of the first channel layer bends downward toward the gate insulating layer, and the interface between the first channel layer and the gate insulating layer is charged with a negative interface charge; and after the application of the positive gate voltage is stopped, the resistance of the first channel layer decreases due to the attraction between the negative interface charge and the hole of the first channel layer, thereby inducing a signal delay of the current flowing through the synapse element. A synapse element configured to enable synapse function mimicry, wherein when a negative gate voltage is applied to the gate electrode, the band of the first channel layer bends upward in the direction of the gate insulating layer, the interface between the first channel layer and the gate insulating layer is charged with a positive interface charge, and after the application of the negative gate voltage is stopped, the resistance of the first channel layer increases due to the repulsion between the positive interface charge and the hole in the first channel layer, thereby inducing a signal delay of the current flowing through the synapse element. Claim 5 A synapse element according to claim 4, further comprising a second channel layer disposed on the substrate, wherein the first channel layer is disposed on the second channel layer. Claim 6 A method for manufacturing a synapse device according to claim 1, comprising: a step of placing a gate insulating layer on a substrate including a gate electrode; a step of placing a first channel layer on the gate insulating layer; and a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is placed at the interface between the first channel layer and the gate insulating layer. Claim 7 A method for manufacturing a synapse device according to claim 6, further comprising the step of placing a second channel layer between the first electrode and the second electrode on the first channel layer. Claim 8 A method for manufacturing a synapse device according to claim 4, comprising: a step of placing a first channel layer on a substrate; a step of placing a first electrode and a second electrode spaced apart from each other on the first channel layer; a step of placing a gate insulating layer between the first electrode and the second electrode on the first channel layer; and a step of placing a gate electrode on the gate insulating layer; wherein the first channel layer is provided such that an interface charge that induces a signal delay of a current generated by a voltage applied to the gate electrode (gate voltage stimulus) is placed at the interface between the first channel layer and the gate insulating layer. Claim 9 A method for manufacturing a synapse device according to claim 8, wherein the step of placing a first channel layer on the substrate further comprises: a step of placing a second channel layer on the substrate; and a step of placing a first channel layer on the second channel layer.

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